11th week of 2014 patent applcation highlights part 15 |
Patent application number | Title | Published |
20140070228 | SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE - An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. | 2014-03-13 |
20140070229 | SYSTEMS AND METHODS FOR TERMINATING JUNCTIONS IN WIDE BANDGAP SEMICONDUCTOR DEVICES - An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction. | 2014-03-13 |
20140070230 | USING A CARBON VACANCY REDUCTION MATERIAL TO INCREASE AVERAGE CARRIER LIFETIME IN A SILICON CARBIDE SEMICONDUCTOR DEVICE - A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure. | 2014-03-13 |
20140070231 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented. | 2014-03-13 |
20140070232 | Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core - A composite wafer including a carrier substrate having a graphite core and a monocrystalline semiconductor substrate or layer attached to the carrier substrate and a corresponding method for manufacturing such a composite wafer is provided. | 2014-03-13 |
20140070233 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained. | 2014-03-13 |
20140070234 | HIGH VOLTAGE POWER SEMICONDUCTOR DEVICES ON SIC - 4H SiC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm | 2014-03-13 |
20140070235 | WIRE BONDS AND LIGHT EMITTER DEVICES AND RELATED METHODS - Improved wire bonds and light emitting devices and related methods are disclosed. In one aspect, an improved wire bond can include a shaped wire bond, where at least a portion of the wire bond includes a negative kink and/or a concave shape with respect to an underlying substrate. | 2014-03-13 |
20140070236 | DEVICE AND METHOD FOR TOP EMITTING AMOLED - Embodiments of the present disclosure relate to devices and methods for reducing the resistance level of top electrodes in top emission AMOLED displays. By way of example, one embodiment includes disposing a metal frame between the top electrode and an insulating layer. The present disclosure also relates to methods for making such a display in reduced number of process steps, including certain techniques for combining certain steps into one process step. | 2014-03-13 |
20140070237 | DISPLAY APPARATUS - A display apparatus includes a display panel, a light guide plate, point light sources, a passivation layer and a first light adjusting layer. The light guide plate is disposed above the display panel and has an upper surface, an opposite lower surface, a light incident surface, a first and a second light guiding blocks. The display panel is disposed corresponding to the first light guiding block, and the second light guiding block extends outside the display panel. A portion of the upper surface located on the first light guiding block is an even surface. The first light guiding block is located between the passivation layer and the display panel. The first light adjusting layer is disposed on the second light guiding block and located on the upper surface or the lower surface. There is a first rough interface between the first light adjusting layer and the light guide plate. | 2014-03-13 |
20140070238 | LIGHT EMITTING DEVICE PACKAGE FOR CONTROLLING LIGHT EMISSION FROM A SIDE SURFACE AND METHOD OF MANUFACTURING THE SAME - A light emitting device package includes a base including at least one recess, at least one light emitting device disposed within the recess, and a reflective wall filling a space between the light emitting device and the recess so as to surround lateral surfaces of the light emitting device. The recess is formed to have a depth ranging from 80% to 120% of a height of the light emitting device. | 2014-03-13 |
20140070239 | Array Substrate And Method For Fabricating The Same - An array substrate and a method for fabricating the same are disclosed. The method for fabricating the array substrate comprises: forming a pattern of a gate electrode ( | 2014-03-13 |
20140070240 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises: a base substrate; a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a source electrode, a drain electrode and a pixel electrode formed on the gate insulating layer, wherein the pixel electrode is directly connected to the drain electrode; and an active layer formed on the gate insulating layer, the source electrode and the drain electrode. | 2014-03-13 |
20140070241 | SOLID STATE LIGHT SOURCE ARRAY - A solid state light source array including a transparent substrate and N rows of solid state light emitting element series is provided. Each row of the solid state light emitting element series includes M solid state light emitting elements connected in series, wherein N, M are integers and N≧1, M≧2. Each of the solid state emitting elements includes a first type electrode pad and a second type electrode pad. The first and the M | 2014-03-13 |
20140070242 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND LIQUID CRYSTAL DISPLAY - The disclosed technology relates to an array substrate and a method of manufacturing the same, and a liquid crystal display. The array substrate comprises a base substrate. The base substrate comprises a pixel region and a peripheral region; data lines and gate lines are formed to transversely and longitudinally cross each other on the base substrate to form a plurality of pixel units, and each of the pixel units comprises a switching element, a pixel electrode and a common electrode above the pixel electrode; the common electrode has slits in each pixel unit and is a plate-shaped electrode in the pixel region, when powered on, the common electrode forms a horizontal electric field together with the pixel electrode of the pixel unit; and a common electrode line fouled in the pixel region and connected with the common electrode. | 2014-03-13 |
20140070243 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a light-emitting device including a light-emitting cell formed on one surface of a substrate, wherein the light-emitting cell comprises a plurality of semiconductor layers and emits light of a certain wavelength; and a wavelength conversion layer formed on the other surface of the substrate and to a certain height of the side of the substrate, wherein the wavelength conversion layer converts a wavelength of light emitted from the light-emitting cell. | 2014-03-13 |
20140070244 | SEMICONDUCTOR LIGHT EMITTING DEVICE HAVING MULTI-CELL ARRAY AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material. | 2014-03-13 |
20140070245 | HIGH VOLTAGE MONOLITHIC LED CHIP - Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament. | 2014-03-13 |
20140070246 | LIGHT-EMITTING SEMICONDUCTOR COMPONENT - The invention relates to a light-emitting semiconductor component, comprising—a first semiconductor body ( | 2014-03-13 |
20140070247 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATING METHOD THEREOF - A semiconductor light-emitting device comprises a light-emitting epitaxial structure, a first electrode structure, a light reflective layer and an resistivity-enhancing structure. The light-emitting epitaxial structure has a first surface and a second surface opposite to the first surface. The first electrode structure is electrically connected to the first surface. The light reflective layer is disposed adjacent to the second surface. The resistivity-enhancing structure is disposed adjacent to the light reflective layer and away from the second surface corresponding to a position of the first electrode structure. | 2014-03-13 |
20140070248 | LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE - According to one embodiment, a semiconductor light-emitting device includes a semiconductor light-emitting layer, a pair of electrodes, a fluorescent material layer and a chromaticity adjusting layer. The semiconductor light-emitting layer emits first light. The pair of electrodes is connected to the semiconductor light-emitting layer. The fluorescent material layer covers at least a center portion of the semiconductor light-emitting layer, and contains a fluorescent material to absorb the first light and radiate second light. The chromaticity adjusting layer covers at least a peripheral portion of the semiconductor light-emitting layer, is exposed to outside, and contains a fluorescent material with a concentration lower than a concentration of the fluorescent material in the fluorescent material layer. | 2014-03-13 |
20140070249 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM INCLUDING THE SAME - A light emitting device according to the embodiment includes a body; a first lead electrode having a first bonding part and a second bonding part; a second lead electrode having a third bonding part and a fourth bonding part; a gap part between the first and second lead electrodes; a third lead electrode on a bottom surface of the body; a fourth lead electrode on the bottom surface of the body; a first connection electrode; a second connection electrode; a light emitting chip; and a first bonding member, wherein the gap part includes a first gap part disposed between the first and third bonding parts, and the first gap part includes first and second regions spaced apart from each other corresponding to a width of the third bonding part, and a third region connected to the first and second regions and disposed perpendicularly to the first and second regions. | 2014-03-13 |
20140070250 | LIGHT-EMITTING DEVICE - A light-emitting device of an embodiment of the present application comprises a substrate; a first semiconductor light-emitting structure formed on the substrate, wherein the first semiconductor light-emitting structure comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and a first active layer formed between the first semiconductor layer and the second semiconductor layer, wherein the first active layer is capable of emitting a first light having a first dominant wavelength; and a first thermal-sensitive layer formed on a path of the first light, wherein the first thermal-sensitive layer comprises a material characteristic which varies with a temperature change. | 2014-03-13 |
20140070251 | REFLECTIVE PHASE RETARDER AND SEMICONDUCTOR LIGHT-EMITTING DEVICE INCLUDING SUCH REFLECTING PHASE RETARDER - The invention provides a reflective phase retarder and a semiconductor light-emitting device including such reflective phase retarder. The reflective phase retarder of the invention converts an incident light beam with a first type polarization into the light with a second type polarization, and reflects the converted light beam with the second type polarization out. | 2014-03-13 |
20140070252 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer sequentially stacked on a substrate. A first electrode is disposed on a portion of the first conductivity-type semiconductor layer. A current diffusion layer is disposed on the second conductivity-type semiconductor layer and includes an opening exposing a portion of the second conductivity-type semiconductor layer. A second electrode covers a portion of the current diffusion layer and the exposed portion of the second conductivity-type semiconductor layer, wherein the portion of the current diffusion layer is near the opening. | 2014-03-13 |
20140070253 | SEMICONDUCTOR LIGHT EMITTING DEVICE - The semiconductor device includes a substrate, a semiconductor layer which is formed on the substrate and includes a light emitting layer, and a diffraction/scattering film for diffracting or scattering light generated at the light emitting layer. The diffraction/scattering film is formed between the light emitting layer and the substrate, has a side surface slanted with respect to a film thickness direction thereof, and has a composition gradient in the film thickness direction. | 2014-03-13 |
20140070254 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a semiconductor lamination including a p-type semiconductor layer, an active semiconductor layer, and an n-type semiconductor layer; opposing electrode structure including a first electrode structure formed above the p-type semiconductor layer, and a second electrode structure formed above the n-type semiconductor layer; and brightness grade producing structure including a surface layer of at least one of the p-type semiconductor layer and the n-type semiconductor layer and producing brightness grade gradually changing from one edge to opposite edge of light output plane. | 2014-03-13 |
20140070255 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device includes: a semiconductor light-emitting chip held on a mounting surface of a mounting substrate, having a growth surface that is a nonpolar or semipolar plane, and emitting polarized light; a reflector surrounding the semiconductor light-emitting chip when viewed in plan and having a reflective surface off which the polarized light is reflected; and a coupler held on the mounting surface of the mounting substrate and holding the reflector such that the reflector is rotatable around the semiconductor light-emitting chip. | 2014-03-13 |
20140070256 | LIGHT EMITTING DEVICE, METHOD FOR FABRICATING THE LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Provided is a light emitting device. The light emitting device includes a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode electrically connected to the first conductive type semiconductor layer, an insulating support member under the light emitting structure layer, and a plurality of conductive layers between the light emitting structure layer and the insulating support member. At least one of the plurality of conductive layers has a width greater than that of the light emitting structure layer and includes a contact part disposed further outward from a sidewall of the light emitting structure layer. | 2014-03-13 |
20140070257 | LIGHT EMITTING DIODE - A light emitting diode includes a second electrode, a first semiconductor layer, an active layer, a second semiconductor layer, a reflector, and a first electrode. The second electrode, the first semiconductor layer, the active layer, the second semiconductor layer, and the reflector are stacked on the first electrode in that order. The first semiconductor layer defines a number of grooves on a surface contacting the second electrode. The grooves form a patterned surface used as the light extraction surface. | 2014-03-13 |
20140070258 | LIGHT-EMITTING DEVICE - A light-emitting device is disclosed and comprises: a substrate; a light-emitting stack comprising a first conductivity type semiconductor layer, an active layer over the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer over the active layer; a transparent conductive layer over the a light-emitting stack; a first trench dividing the transparent conductive layer into a first block and a second block; a connecting layer electrically connecting the two blocks of the transparent conductive layer; a first conductivity type contact layer between the substrate and the first conductivity type semiconductor layer, wherein the conductivity of the first conductivity type contact layer is greater than the conductivity of the first conductivity type semiconductor layer. | 2014-03-13 |
20140070259 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM HAVING THE SAME - Disclosed are a light emitting device and a lighting system having the same. The light emitting device includes a body including first and second lateral side parts, third and fourth lateral side parts, and a cavity, a first lead frame extending in a direction of the first lateral side part of the body, a second lead frame extending in a direction of the second lateral side part of the body, a gap part between the first and second lead frames, and a molding member in the cavity. The first lead frame includes a first recess part having a first depth, and a second recess part recessed at a second depth in a region adjacent to the first lateral side part of the body, and the first depth of the first recess part is different from the second depth of the second recess part. | 2014-03-13 |
20140070260 | PIXEL UNIT, ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE - According to embodiments the invention, there are provided a pixel unit, an array substrate and a liquid crystal display device. The pixel unit comprises: a first electrode, an insulating layer located on the first electrode, and a second electrode located on the insulating layer. The first electrode includes a plurality of first electrode strips which are parallel to each other and are spaced at an interval, the second electrode includes a plurality of second electrode strips which are parallel to each other and are spaced at an interval; and an angle between the first electrode strips and the second electrode strips located above the first electrode strips is larger than 0 degree and smaller than or equal to 90 degrees. | 2014-03-13 |
20140070261 | STACKED LED DEVICE WITH POSTS IN ADHESIVE LAYER - A semiconductor light emitting device includes a substrate and a first epitaxial structure over the substrate. The first epitaxial structure includes a first doped layer, a first light emitting layer, and a second doped layer. The first doped layer includes a first dopant type and the second doped layer includes a second dopant type. A second epitaxial structure includes a third doped layer, a second light emitting layer, and a fourth doped layer. An adhesive layer is between the first epitaxial structure and the second epitaxial structure. One or more posts are located in the adhesive layer. An electrode pattern is located on an upper surface of the second epitaxial structure, wherein the posts are located under electrodes in the electrode pattern. | 2014-03-13 |
20140070262 | LIGHT EMITTING DEVICE - A light emitting device includes a package equipped on a front face with a window for installing a light emitting element, and outer lead electrodes. The package has a back face opposed to the front face and a bottom face that is located between the back face and the front face. The bottom face is adjacent to the front face. The outer lead electrodes protrude from the bottom face of the package. An end of each of the outer lead electrodes branches in at least two distal end parts on the bottom face. One of the distal end parts of each of the outer lead electrodes extends toward one of side faces of the package and is bent along the side face, and other one of the distal end parts of each of the outer lead electrodes extends toward the back face of the package. | 2014-03-13 |
20140070263 | SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved. | 2014-03-13 |
20140070264 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode. | 2014-03-13 |
20140070265 | FAST SWITCHING IGBT WITH EMBEDDED EMITTER SHORTING CONTACTS AND METHOD FOR MAKING SAME - Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed. | 2014-03-13 |
20140070266 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer. | 2014-03-13 |
20140070267 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer. | 2014-03-13 |
20140070268 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n | 2014-03-13 |
20140070269 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device such that it is possible to average the temperatures of a plurality of semiconductor chips simply by providing gate resistors. The semiconductor device includes a semiconductor module wherein a plurality of circuit substrates on which are mounted one or more semiconductor chips having a gate terminal and a gate resistor connected to the gate terminal are disposed in parallel, wherein the disposition distance of the gate resistor from the semiconductor chip is set based on the temperature of the semiconductor chip. | 2014-03-13 |
20140070270 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n | 2014-03-13 |
20140070271 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR - A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer. | 2014-03-13 |
20140070272 | PHOTODETECTOR FOR ULTRAVIOLET RADIATION, HAVING A HIGH SENSITIVITY AND A LOW DARK CURRENT - The present invention relates to a UV photodetector having a high sensitivity and a low dark current. The object of the present invention is to specify a UV photodetector that has a high sensitivity and a low dark current. According to the invention, the fingers of the first electrode structure and the fingers of the second electrode structure have a cover layer made of a second semiconducting material, wherein the cover layer is arranged on the absorber layer and directly contacts the absorber layer in the region of the fingers, and the first semiconducting material and the second semiconducting material are designed in such a manner that a two-dimensional electron gas (2DEG) is formed at the boundary layer between the absorber layer and the cover layer in the region of the fingers. | 2014-03-13 |
20140070273 | Non-Planar Device Having Uniaxially Strained Semiconductor Body and Method of Making Same - A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom. | 2014-03-13 |
20140070274 | POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION - Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches. | 2014-03-13 |
20140070275 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and third and fourth semiconductor layers of the first conductivity type formed between the first and second semiconductor layer. The first, the third, the fourth, and the second semiconductor layers are coupled in this order. A band gap of the third semiconductor layer is narrower than that of the first semiconductor layer, and a band gap of the fourth semiconductor layer is narrower than that of the third semiconductor layer. | 2014-03-13 |
20140070276 | Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer. | 2014-03-13 |
20140070277 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350 C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 2014-03-13 |
20140070278 | Active Area Shaping of III-Nitride Devices Utilizing Multiple Dielectric Materials - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a dielectric body situated over the III-nitride heterojunction and including a first dielectric layer of a first dielectric material and a second dielectric layer of a second dielectric material different than the first dielectric material. A gate well of a first width is defined by the first dielectric layer, and is of a second width defined by the second dielectric layer, where the second width is greater than the first width. The III-nitride semiconductor device further includes a gate arrangement situated in the gate well and including a gate electrode integrated with a field plate. | 2014-03-13 |
20140070279 | Active Area Shaping of III-Nitride Devices Utilizing a Source-Side Field Plate and a Wider Drain-Side Field Plate - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include steps, and the drain-side field plate is wider than the source-side field plate. | 2014-03-13 |
20140070280 | Active Area Shaping of III-Nitride Devices Utilizing Steps of Source-Side and Drain-Side Field Plates - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. A gate arrangement is situated in the gate well and includes a gate electrode, a source-side field plate, and a drain-side field plate. The source-side field plate and the drain-side field plate each include one or more steps, where the drain-side field plate has a different number of the one or more steps than the source-side field plate. | 2014-03-13 |
20140070281 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel. | 2014-03-13 |
20140070282 | SELF-ALIGNED CONTACTS - Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure. | 2014-03-13 |
20140070283 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION - An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor. | 2014-03-13 |
20140070284 | SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION - Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer. | 2014-03-13 |
20140070285 | METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES - One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity. | 2014-03-13 |
20140070286 | NANO-PILLAR TRANSISTOR FABRICATION AND USE - A field effect nano-pillar transistor has a pillar shaped gate element incorporating a biomimitec portion that provides various advantages over prior art devices. The small size of the nano-pillar transistor allows for advantageous insertion into cellular membranes, and the biomimitec character of the gate element operates as an advantageous interface for sensing small amplitude voltages such as transmembrane cell potentials. The nano-pillar transistor can be used in various embodiments to stimulate cells, to measure cell response, or to perform a combination of both actions. | 2014-03-13 |
20140070287 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device and a manufacturing method thereof achieving both reduction in ON resistance and increase in breakdown voltage and suppressing a short circuit. The semiconductor device has, in its semiconductor substrate having a main surface, a p | 2014-03-13 |
20140070288 | IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall. | 2014-03-13 |
20140070289 | FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a ferroelectric memory includes a gate insulation film formed on a semiconductor substrate, a ferroelectric film formed on the gate insulation film, and a control electrode formed on the ferroelectric film. The ferroelectric film is a film containing a metal, which is hafnium or zirconium, and oxygen, and contains an element other than the metal at a concentration lower than a concentration of the metal. | 2014-03-13 |
20140070290 | FERROELECTRIC MEMORY AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a ferroelectric memory includes a semiconductor layer, an interfacial insulating film formed on the semiconductor layer, a ferroelectric film formed on the interfacial insulating film, and a gate electrode formed on the ferroelectric film, wherein the ferroelectric film is a film which includes a metal that is hafnium (Hf) or zirconium (Zr) and oxygen as the main components and to which an element selected from the group consisting of silicon (Si), magnesium (Mg), aluminum (Al). | 2014-03-13 |
20140070291 | SEMICONDUCTOR DEVICES INCLUDING A GATE STRUCTURE BETWEEN ACTIVE REGIONS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A GATE STRUCTURE BETWEEN ACTIVE REGIONS - Semiconductor devices are provided. The semiconductor devices may include an isolation pattern and first, second, and third active regions of a substrate. The first active region may be spaced apart from the second active region by a first width of the isolation pattern in a direction. A gate structure may be between the first and second active regions and may include a second width wider than the first width of the isolation pattern in the direction. Related methods of forming semiconductor devices are also provided. | 2014-03-13 |
20140070292 | DEEP TRENCH CAPACITOR - A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer. | 2014-03-13 |
20140070293 | SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY - A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor. | 2014-03-13 |
20140070294 | FINFET TRENCH CIRCUIT - A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon. | 2014-03-13 |
20140070295 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a capacitor. | 2014-03-13 |
20140070296 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A memory cell array includes a plurality of memory cells provided on the semiconductor substrate in an array direction. A selection gate transistor is provided on an end of the memory cell array, and is used to select the memory cells from the memory cell arrays. A dummy cell is provided between a gate electrode of one of the memory cells on the end of the memory cell array and a gate electrode of the selection gate transistor. The width of a gate electrode of the dummy cell in the array direction of the memory cells and the dummy cell is twice or more as large as the width of the gate electrode of one of the memory cells. | 2014-03-13 |
20140070297 | SEMICONDUCTOR STORAGE DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, the semiconductor storage device includes a semiconductor substrate, a first pair of selection-gate electrodes including a first conductor layer and a second conductor layer, a second pair of selection-gate electrodes, a memory cell region formed in the area sandwiched by the first pair of selection-gate electrodes and the second pair of selection-gate electrodes, an interlayer-insulating film, a first contact provided between the first pair of selection gates and penetrates through the interlayer-insulating film and the first conductive film layer and is connected on the surface of the semiconductor substrate, and a second contact provided between the second pair of selection gates, in which first contact is connected to the first conductive film layer via an insulating film on the side surface thereof. | 2014-03-13 |
20140070298 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween. | 2014-03-13 |
20140070299 | SONOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer later of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention. | 2014-03-13 |
20140070300 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern. | 2014-03-13 |
20140070301 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A plurality of memory cells are provided on the semiconductor substrate. Peripheral circuits are provided on a periphery of the memory cells. A first barrier film includes a first nitride film provided on a first gate electrode of a transistor included in the peripheral circuits. A second barrier film includes a second nitride film different from the first nitride film. The second nitride film is provided on a second gate electrode of the memory cells, respectively. Metal layers are provided on the first and second barrier films, respectively. | 2014-03-13 |
20140070302 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures. | 2014-03-13 |
20140070303 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to the present embodiment includes a semiconductor substrate. Each of memory cell arrays includes a plurality of memory cells on the semiconductor substrate. Select gate transistors are provided on ends of the memory cell arrays and brought into conduction when the memory cells are connected to a corresponding line. An embedded impurity layer is embedded in active areas between the select gate transistors respectively corresponding to the memory cell arrays adjacent to each other. Contact plugs connect the embedded impurity layer and the lines. | 2014-03-13 |
20140070304 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film. | 2014-03-13 |
20140070305 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer. | 2014-03-13 |
20140070306 | VERTICAL MEMORY DEVICES AND APPARATUSES - Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods. | 2014-03-13 |
20140070307 | MULTI-LAYER WORK FUNCTION METAL REPLACEMENT GATE - Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride. | 2014-03-13 |
20140070308 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type. | 2014-03-13 |
20140070309 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is provided with a semiconductor substrate including a drain layer of a first conductivity type, a base layer of a second conductivity type, and a source layer of the first conductivity type, a gate insulating film, a gate electrode, an insulating section, a source electrode, and a drain electrode. Gate trenches are formed on an upper surface of the semiconductor substrate. A curved section is formed on the upper surface of the semiconductor substrate between the gate trenches in the semiconductor substrate. The base layer is disposed between the gate trenches, and the source layer is formed above the base layer at both ends of the curved section. | 2014-03-13 |
20140070310 | INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS - A high voltage trench MOS and its integration with low voltage integrated circuits. Embodiments include forming a first trench in a substrate, the first trench having a first width; forming a first oxide layer on side surfaces of the first trench; forming a second trench in the substrate, below the first trench, the second trench having a second width less than the first width; forming a second oxide layer on side and bottom surfaces of the second trench; forming spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on the side surfaces and a top surface of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region. | 2014-03-13 |
20140070311 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region. | 2014-03-13 |
20140070312 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions. | 2014-03-13 |
20140070313 | POWER MOSFET CURRENT SENSE STRUCTURE AND METHOD - A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET ( | 2014-03-13 |
20140070314 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING THE SAME - There is provided an MOSFET having a large current density, which can be mixed with a logic circuit, and is used in a circuit that conducts the operation of applying a negative voltage to a drain electrode. An electrode surrounded by an insulating film is formed, at an intermediate position of a gate electrode and a drain of the MOSFET formed on an SOI substrate having a drain electrode applied with a negative voltage, and the electrode is connected to the ground to prevent a withstand voltage from being lowered which is caused by an increase in impurity concentration of a drift region. A drift resistance is lowered to improve the current density. | 2014-03-13 |
20140070315 | Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure - A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V. | 2014-03-13 |
20140070316 | REPLACEMENT SOURCE/DRAIN FOR 3D CMOS TRANSISTORS - A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions. | 2014-03-13 |
20140070317 | METHOD FOR MANUFACTURING A SUSPENDED MEMBRANE AND DUAL-GATE MOS TRANSISTOR - A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring. | 2014-03-13 |
20140070318 | Reducing Resistance in Source and Drain Regions of FinFETs - A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer. | 2014-03-13 |
20140070319 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto. | 2014-03-13 |
20140070320 | INTEGRATED CIRCUITS WITH SELECTIVE GATE ELECTRODE RECESS - Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit. | 2014-03-13 |
20140070321 | INTEGRATED CIRCUITS HAVING BORON-DOPED SILICON GERMANIUM CHANNELS AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. One method includes recessing a PFET active region to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region. | 2014-03-13 |
20140070322 | METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES - One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material. | 2014-03-13 |
20140070323 | Semiconductor Arrangement with a Load, a Sense and a Start-Up Transistor - A semiconductor arrangement includes a semiconductor body with a first active region, a second active region and an isolation region arranged between the first and the second active regions. At least one source region and at least one body region of a first transistor are integrated in the first active region. At least one source region and at least one body region of a second transistor are integrated in the second active region. Source and body regions of a third transistor are integrated in the second active region. The second transistor and the third transistor have a common source electrode. The first transistor, the second transistor and the third transistor have a common drain electrode. | 2014-03-13 |
20140070324 | SEMICONDUCTOR DEVICE WITH CONTACT HOLE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first barrier layer disposed on the substrate, a first dielectric layer disposed on the first barrier layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device further includes a third barrier layer and a first metal gate each being disposed between a first portion of the second barrier layer and a second portion of the second barrier layer. The first metal gate is disposed between the third barrier layer and the substrate. The semiconductor device further includes a second dielectric layer. The third barrier layer is disposed between the first metal gate and the second dielectric layer. The semiconductor device further includes a second metal gate. The semiconductor device further includes a contact hole positioned between the first metal gate and the second metal gate. | 2014-03-13 |
20140070325 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first interface film on a first area of a substrate, the first interface film including a first growth interface film and a second growth interface film on a lower portion of the first growth interface film, a first dielectric film on the first interface film, and a first gate electrode on the first dielectric film. | 2014-03-13 |
20140070326 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 2014-03-13 |
20140070327 | Replacement Metal Gate Process for CMOS Integrated Circuits - A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal. | 2014-03-13 |