11th week of 2009 patent applcation highlights part 45 |
Patent application number | Title | Published |
20090068791 | Method For Fabricating Stacked Semiconductor Components - A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer member for protecting the semiconductor substrates. A method for fabricating the component includes the steps of providing the carrier with the conductive members, and providing the semiconductor substrates with the conductive openings. The method also includes the step of aligning and placing the conductive openings on the conductive members, and then bonding the conductive members to the conductive openings. A system includes the carrier having the conductive members, the semiconductor substrates having the conductive openings, an aligning and placing system for aligning and placing the semiconductor substrates on the carrier, and a bonding system for bonding the conductive members to the conductive openings. | 2009-03-12 |
20090068792 | MANUFACTURING PROCESS FOR A CHIP PACKAGE STRUCTURE - A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated. | 2009-03-12 |
20090068793 | MANUFACTURING PROCESS FOR A CHIP PACKAGE STRUCTURE - A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated. | 2009-03-12 |
20090068794 | MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated. | 2009-03-12 |
20090068795 | Production methods of electronic devices - A method of producing an electronic device having mounted thereon a microelectromechanical system element. The method includes forming a micromachine component and electronic component for operation of the micromachine component on a substrate to form the system element, and bonding to the substrate a lid covering an active surface of the substrate and provided with wiring patterns to define an operating space for the micromachine component and electrically connecting the electronic component and the wiring patterns of the lid at a bonded part of the substrate and the lid. | 2009-03-12 |
20090068796 | SEMICONDUCTOR CONNECTION COMPONENT - There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire | 2009-03-12 |
20090068797 | MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated. | 2009-03-12 |
20090068798 | IMAGER DIE PACKAGE AND METHODS OF PACKAGING AN IMAGER DIE ON A TEMPORARY CARRIER - Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication substrate comprising a plurality of imager die. Thereafter, known good die (KGD) qualified from the imager die are repopulated, face down on a high temperature-compatible temporary carrier, the KGD on the temporary carrier are encapsulated and thereafter removed as a reconstructed wafer from the temporary carrier. Furthermore, a first plurality of discrete conductive elements on a back side of the reconstructed wafer may be partially exposed and, optionally, a second plurality of discrete conductive elements may be applied to the first plurality of discrete conductive elements. The encapsulated KGD are then singulated. | 2009-03-12 |
20090068799 | MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer exposed by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated. | 2009-03-12 |
20090068800 | Method and/or system for forming a thin film - Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film are described. | 2009-03-12 |
20090068801 | METHOD OF MANUFACTURING ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY DEVICE - The embodiment of the invention discloses an exemplary method, in which a gate line, a gate electrode, and a pixel electrode are formed in a first step; a multilayer structure is formed on the gate line and the gate electrode in a second step; and a data line and source/drain electrodes are formed in a third step. | 2009-03-12 |
20090068802 | BEAM HOMOGENIZER AND LASER IRRADIATION APPARATUS - The present invention provides a beam homogenizer for homogenizing energy distribution by making the distance between lenses small to shorten the optical path length with the use of an array lens of an optical path shortened type, and a laser irradiation apparatus using the beam homogenizer. The beam homogenizer is equipped with a front side array lens of an optical path shortened type whose second principal point is positioned ahead on a beam incidence side, a back side array lens of an optical path shortened type whose first principal point is positioned behind on a beam emission side, and a condensing lens, wherein the distance between the second principal point of the front side array lens and the first principal point of the back side array lens is equal to the focal length of the back side array lens. | 2009-03-12 |
20090068803 | METHOD FOR MAKING AN INTEGRATED CIRCUIT INCLUDING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS - A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur. | 2009-03-12 |
20090068804 | DRAIN EXTENDED PMOS TRANSISTORS AND METHODS FOR MAKING THE SAME - Semiconductor devices ( | 2009-03-12 |
20090068805 | METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTORS - A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer. | 2009-03-12 |
20090068806 | FIELD EFFECT TRANSISTOR - A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material. | 2009-03-12 |
20090068807 | DUAL GATE OXIDE DEVICE INTEGRATION - A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon. | 2009-03-12 |
20090068808 | Method of manufacturing a nonvolatile semiconductor memory device having a gate stack - A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si | 2009-03-12 |
20090068809 | SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL ETCH STOPPER AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region. | 2009-03-12 |
20090068810 | METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved. | 2009-03-12 |
20090068811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having a greater film thickness than the gate insulation film and formed adjacent to the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film. | 2009-03-12 |
20090068812 | Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 2009-03-12 |
20090068813 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity. | 2009-03-12 |
20090068814 | Semiconductor Devices Including Capacitor Support Pads and Related Methods - A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed. | 2009-03-12 |
20090068815 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions. | 2009-03-12 |
20090068816 | METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - Provided is a method for forming an isolation layer in a semiconductor device. In the method, a trench is formed in a semiconductor substrate, and a liner layer is formed on an exposed surface of the trench. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buffer layer is formed on a portion of the liner layer that is formed on a sidewall of the trench and exposed after the flowable insulation layer is recessed. The buffer layer is etched to smoothen a rough portion of the liner layer that is formed when the flowable insulation layer is recessed. A buried insulation layer is deposited in the trench. | 2009-03-12 |
20090068817 | METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE - A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buried insulation layer is deposited on the flowable insulation layer while keeping a deposition sputtering rate (DSR) below about 22 so as to fill the trench with the buried insulation layer while restraining the buried insulation layer from growing on a lateral portion of the trench. | 2009-03-12 |
20090068818 | METHOD OF FORMING AN ISOLATION LAYER OF A SEMICONDUCTOR DEVICE - In a method of forming an isolation layer of a semiconductor device, a gate insulating layer, a first conductive layer, and a hard mask are formed in an active region of a semiconductor substrate and a trench is formed in an isolation region. The trench is partially gap-filled by forming a first insulating layer in the trench. The trench is fully gap-filled by forming a second insulating layer on the first insulating layer. A polishing process is performed on the first insulating layer and the second insulating layer formed over the hard mask. An etchback process is performed to lower a height of the second insulating layer in the trench. The trench is gap-filled by forming a third insulating layer over the first insulating layer and the second insulating layer, thereby forming an isolation layer in the trench. Accordingly, the occurrence of a void within the isolation layer is prevented. | 2009-03-12 |
20090068819 | Tape structures, and methods and apparatuses for separating a wafer using the same - Example embodiments provide tape structures including a base layer, a neutralizing layer and an adhesive layer. The base layer may support an object. The neutralizing layer may be arranged on the base layer. The neutralizing layer may be grounded to neutralize charges between the base layer and the object. The adhesive layer may be arranged on the neutralizing layer. The object may be attached to the adhesive layer. Example embodiments also provide methods of manufacturing the tape structures, methods of separating a wafer, and apparatuses for separating a wafer. | 2009-03-12 |
20090068820 | Microspheres including nanoparticles - A microparticle can include a central region and a peripheral region. The peripheral region can include a nanoparticle, such as a metal nanoparticle, a metal oxide nanoparticle, or a semiconductor nanocrystal. The microparticle can be a member of a monodisperse population of particles. | 2009-03-12 |
20090068821 | Charge-free low-temperature method of forming thin film-based nanoscale materials and structures on a substrate - A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the plasma have an average kinetic energy in a range from about 1 eV to about 5 eV. | 2009-03-12 |
20090068822 | METHOD FOR PREPARING SUBSTRATE FOR GROWING GALLIUM NITRIDE AND METHOD FOR PREPARING GALLIUM NITRIDE SUBSTRATE - Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si | 2009-03-12 |
20090068823 | Plasma Ion Doping Method and Apparatus - In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described. | 2009-03-12 |
20090068824 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor substrate is provided. A substrate having a region adjacent to a surface of the substrate as a channel region is provided. An ion implantation process is performed to form an amorphized silicon layer in the substrate below the channel region. A thermal treatment process is performed to re-crystallize the amorphized silicon layer so as to form an epitaxial material layer. The epitaxial material layer may enhance the stress on the channel region in the substrate. | 2009-03-12 |
20090068825 | IMPLEMENTATION OF TEMPERATURE-DEPENDENT PHASE SWITCH LAYER FOR IMPROVED TEMPERATURE UNIFORMITY DURING ANNEALING - The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process. | 2009-03-12 |
20090068826 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The present invention includes the steps of: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 2009-03-12 |
20090068827 | Method for fabricating semiconductor device - A semiconductor device provided with: a channel region formed in a surface of a semiconductor substrate in a predetermined depth range, a trench being formed in the surface as penetrating the channel region in a depthwise direction; a gate insulating film formed on an inside wall of the trench, the gate insulating film being in contact with the channel region; and a gate electrode including: a polysilicon layer opposing the channel region with the gate insulating film interposed therebetween, the polysilicon layer being embedded in an internal space of the trench at least in the predetermined depth range; and a low-resistance layer essentially formed from a metal element and disposed in the trench above the polysilicon layer that opposes the channel region. | 2009-03-12 |
20090068828 | DUAL WORK FUNCTION CMOS DEVICES UTILIZING CARBIDE BASED ELECTRODES - Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region. | 2009-03-12 |
20090068829 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising forming a conductive layer on a semiconductor substrate; forming a metal layer on the conductive layer; performing a first etching process for patterning the metal layer on a first area to form first metal layer patterns at relatively wide intervals until the conductive layer of the first area is exposed; performing a second etching process for forming an etching-obstructing layer on the first area and patterning the metal layer on a second area to form second metal layer patterns at relatively narrow intervals until the conductive layer of the second area is exposed; removing the etching-obstructing layer; and removing an exposed area of the conductive layer to form a conductive pattern. | 2009-03-12 |
20090068830 | Microelectronic package interconnect and method of fabrication thereof - A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles. | 2009-03-12 |
20090068831 | 3D IC METHOD AND DEVICE - A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding. | 2009-03-12 |
20090068832 | THIN FILMS - Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO | 2009-03-12 |
20090068833 | METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a contact hole of a semiconductor device. According to the method of forming a contact hole of a semiconductor device, a semiconductor substrate in which gates and junctions are formed is provided. A self-aligned contact (SAC) nitride layer is formed on a surface of the gates. A pre-metal dielectric layer is formed on the SAC nitride layer. A contact hole is formed to thereby expose the junction between the gates. A passivation layer is formed on sidewalls of the contact hole. A contact plug is formed, thus gap-filling the contact hole. | 2009-03-12 |
20090068834 | METHOD OF FORMING A CONTACT PLUG OF A SEMICONDUCTOR DEVICE - In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed. | 2009-03-12 |
20090068835 | METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS - A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer. | 2009-03-12 |
20090068836 | METHOD OF FORMING CONTACT PLUG OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming contact plugs of a semiconductor device. According to the method, a first insulating layer is formed over a semiconductor substrate in which a cell region and a peri region are defined and a first contact plug is formed in the peri region. The first insulating layer is etched using an etch process, thus forming contact holes through which junctions are exposed in the cell region and the first contact plug is exposed in the peri region. Second contact plugs are formed in the contact holes. The second contact plug formed within the contact hole of the peri region are removed using an etch process. A spacer is formed on sidewalls of the contact holes. Third contact plugs are formed within the contact holes. | 2009-03-12 |
20090068837 | LINE ENDS FORMING - Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element. | 2009-03-12 |
20090068838 | METHOD FOR FORMING MICROPATTERNS IN SEMICONDUCTOR DEVICE - A method for forming micropatterns in a semiconductor device includes forming a first etch stop layer over a etch target layer, forming a second etch stop layer over the first etch stop layer, forming a first sacrificial layer over the second etch stop layer, etching portions of the first sacrificial layer and second etch stop layer to form first sacrificial patterns, forming an insulation layer along an upper surface of the first etch stop layer, forming a second sacrificial layer over the insulation layer to cover the insulation layer, planarizing the second sacrificial layer and the insulation layer to expose the first sacrificial patterns, removing the first sacrificial patterns and the second sacrificial layer, etching the second etch stop layer and insulation layer to thereby form second sacrificial patterns, etching the first etch stop layer, and etching the etch target layer. | 2009-03-12 |
20090068839 | Slurry, chemical mechanical polishing method using the slurry, and method of forming metal wiring using the slurry - A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor. | 2009-03-12 |
20090068840 | POLISHING LIQUID AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A polishing liquid is provided, which includes abrasive grains and a surfactant. The abrasive grains contain a first colloidal silica having an average primary particle diameter of 45-80 nm and a second colloidal silica having an average primary particle diameter of 10-25 nm. The weight w | 2009-03-12 |
20090068841 | Chemical mechanical polishing method of organic film and method of manufacturing semiconductor device - There is disclosed a chemical mechanical polishing method of an organic film comprising forming the organic film above a semiconductor substrate, contacting the organic film formed above the semiconductor substrate with a polishing pad attached to a turntable, and dropping a slurry onto the polishing pad to polish the organic film, the slurry being selected from the group consisting of a first slurry and a second slurry, the first slurry comprising a resin particle having a functional group selected from the group consisting of an anionic functional group, a cationic functional group, an amphoteric functional group and a nonionic functional group, and having a primary particle diameter ranging from 0.05 to 5 μm, the first slurry having a pH ranging from 2 to 8, and the second slurry comprising a resin particle having a primary particle diameter ranging from 0.05 to 5 μm, and a surfactant having a hydrophilic moiety. | 2009-03-12 |
20090068842 | METHOD FOR FORMING MICROPATTERNS IN SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes forming an etch target layer over a substrate, forming a first etch stop layer over the etch target layer, forming a second etch stop layer over the first etch stop layer, forming a first sacrificial layer over the second etch stop layer, forming first sacrificial patterns by selectively etching the first sacrificial layer, forming second sacrificial layer over the second etch stop layer and the first sacrificial patterns, etching the second sacrificial layer and the second etch stop layer until the first sacrificial patterns are exposed and the second sacrificial layer remain only on sidewalls of the first sacrificial patterns, removing the exposed first sacrificial patterns, etching the exposed second etch stop layer mask to define a plurality of first structures, etching the first etch stop layer, and etching the etch target layer. | 2009-03-12 |
20090068843 | METHOD OF FORMING MARK IN IC-FABRICATING PROCESS - A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps. | 2009-03-12 |
20090068844 | Etching Process - Mixtures of fluorine and inert gases like nitrogen and/or argon can be used for etching of semiconductors, solar panels and flat panels (TFTs and LCDs), and for cleaning of semiconductor surfaces and plasma chambers. Preferably, fluorine is comprised in an amount of 15 to 25 vol.-% in binary mixtures. The gas mixtures can be used as substitute or drop-in for respective mixtures comprising NF | 2009-03-12 |
20090068845 | Low contamination components for semiconductor processing apparatus and methods for making components - Components of semiconductor processing apparatus are formed at least partially of erosion, corrosion and/or corrosion-erosion resistant ceramic materials. Exemplary ceramic materials can include at least one oxide, nitride, boride, carbide and/or fluoride of hafnium, strontium, lanthanum oxide and/or dysprosium. The ceramic materials can be applied as coatings over substrates to form composite components, or formed into monolithic bodies. The coatings can protect substrates from physical and/or chemical attack. The ceramic materials can be used to form plasma exposed components of semiconductor processing apparatus to provide extended service lives. | 2009-03-12 |
20090068846 | COMPOSITIONS AND METHOD FOR TREATING A COPPER SURFACE - The present invention is directed to compositions for copper passivation and methods of use of such compositions. | 2009-03-12 |
20090068847 | METHODS FOR REMOVING CONTAMINANTS FROM ALUMINUM-COMPRISING BOND PADS AND INTEGRATED CIRCUITS THEREFROM - Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface. | 2009-03-12 |
20090068848 | SYSTEMS AND METHODS FOR MANIPULATING LIQUID FILMS ON SEMICONDUCTOR SUBSTRATES - A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed. | 2009-03-12 |
20090068849 | MULTI-REGION PROCESSING SYSTEM AND HEADS - The various embodiments of the invention provide for relative movement of the substrate and a process head to access the entire wafer in a minimal space to conduct combinatorial processing on various regions of the substrate. The heads enable site isolated processing within the chamber described and method of using the same are described. | 2009-03-12 |
20090068850 | Method of Fabricating Flash Memory Device - The present invention relates generally to a method of fabricating a flash memory device. The method includes forming a tunnel dielectric layer on a semiconductor substrate using a plasma oxidization process. The tunnel dielectric layer is formed using the plasma oxidation process employing Ar and O | 2009-03-12 |
20090068851 | SUSCEPTOR, MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A susceptor of the present invention includes an inner susceptor having a diameter smaller than a diameter of a wafer w and a protruding part for placing the wafer w on a surface thereof, and an outer susceptor having an opening in the central portion thereof, a first step section for placing the inner susceptor so as to block the opening and a second step section provided above the first step section for placing the wafer. | 2009-03-12 |
20090068852 | METHOD OF FORMING A CARBON POLYMER FILM USING PLASMA CVD - A method forms a hydrocarbon-containing polymer film on a semiconductor substrate by a capacitively-coupled plasma CVD apparatus. The method includes the steps of: vaporizing a hydrocarbon-containing liquid monomer (C | 2009-03-12 |
20090068853 | IMPURITY CONTROL IN HDP-CVD DEP/ETCH/DEP PROCESSES - Methods are disclosed of depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A first portion of the silicon oxide film is deposited over the substrate and within the gap using a high-density plasma process. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched back. This includes flowing a halogen precursor through a first conduit from a halogen-precursor source to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the portion has been etched back. Thereafter, a halogen scavenger is flowed to the substrate processing chamber to react with residual halogen in the substrate processing chamber. Thereafter, a second portion of the silicon oxide film is deposited over the first portion of the silicon oxide film and within the gap using a high-density plasma process. | 2009-03-12 |
20090068854 | SILICON NITRIDE GAP-FILLING LAYER AND METHOD OF FABRICATING THE SAME - A method for fabricating a silicon nitride gap-filling layer is provided. A pre-multi-step formation process is performed to form a stacked layer constituting as a dense film on a substrate. Then, a post-single step deposition process is conducted to form a cap layer constituting as a sparse film on the stacked layer, wherein the cap layer has a thickness of at least 10% of the total film thickness. | 2009-03-12 |
20090068855 | MODULAR BOARD TO BOARD CONNECTOR - A connector assembly has a receptacle module and a pin module that interconnect. Stiffener engagement projections and recesses are provided along the sides of the receptacle and pin modules in an alternating fashion. The recesses are sized and shaped to receive the stiffener engagement projections of a respective neighboring module. Stainless steel elongated stiffener plates removably engage the pin and receptacle modules in both an X-direction and/or a Y-direction. The stiffener plates have slots that extend partly through the plates and align with the stiffener engagement projections and receiving recesses. The slots receive respective ones of the projections of the neighboring pin and receptacle modules. | 2009-03-12 |
20090068856 | LED light source module, manufacturing method thereof and LED backlight module using the same - A LED light source module includes a printed circuit board and a plurality of LEDs. The printed circuit board has a plurality of through holes arranged in intervals. Each of the LEDs includes at least one LED chip and at least one metal board. The metal board has a supporting surface. The LED chip is arranged on the supporting surface. At least one of the LED chip and the metal board is contained in each through hole of the printed circuit board corresponding to the LED including the at least one of the LED chip and the metal board. Each of the LEDs electrically is connected with printed circuit board through the supporting surface of the metal board to make the LED chip be connected with the printed circuit board electrically. | 2009-03-12 |
20090068857 | Electrically conducting contact and method for production thereof - A contact element for the intermittent contacting of conductor tracks on a circuit board, in particular, for flexible touchpads, for example for flexible input devices in the automobile industry, is made from a metal foam. The metal foam may be at least partly infiltrated by an elastomeric material which can also be the material of construction of the touchpad. The contact element has a very reliable construction which is particularly suitable for high voltage application. A method for production of the contact element, touchpads/input devices with such contact pads and the use of the contact pads is also provided. | 2009-03-12 |
20090068858 | MINIATURE ELECTRICAL BALL AND TUBE SOCKET ASSEMBLY WITH SELF-CAPTURING MULTIPLE-CONTACT-POINT COUPLING - A socket assembly for connecting an array of bulbous terminals such as balls wherein the female element is a miniature tube that has resilient prongs that grip the corresponding terminals with varying force during insertion and deletion. The tube is of resilient conductive material that has been sliced or helically partitioned into opposing prongs forming slots of a width that increases with axial distance from the end of the tube so as to allow the prongs of the connector to grip around the ball-like bulbous terminal and mechanically retain the terminal within the connector. The tubular element of the connector may be made by forming prongs in one or both ends of a tube by cuts of a width that increases with distance from the end of the tube. | 2009-03-12 |
20090068859 | Fail-Safe Lockout for Blind Mate Card - A lockout mechanism for a card assembly having a blind connection to an electronic component includes a card disposed in a housing and articulable in the housing in a direction substantially perpendicular to a direction of insertion of the card assembly into the electronic component, the card including a connector having connection fingers extending substantially in said direction. A lockout is disposed in the housing, the lockout movable in a direction perpendicular to the card between a first or locked position and a second or unlocked position, and preventing articulation of the card unless the one or more connection fingers are aligned with one or more corresponding component fingers in the electronic component. An alignment feature is included, that when brought into contact with a corresponding portion of the electronic component ensures proper alignment between the one or more connection fingers and one or more corresponding component fingers. | 2009-03-12 |
20090068860 | CONNECTOR DEVICE - A connector device to be used with a flexible printed circuit board including a connector. The flexible printed circuit board has on its front and rear surfaces ground patterns, signal patterns and phase inversion signal patterns arranged such that the signal pattern and the phase inversion signal pattern are arranged between the two ground patterns, and has a ground layer between the front and rear surfaces and exposed portions located at predetermined positions and reaching the ground layer. The connector has first and second contacts of two kinds. The first and second contacts are arranged in one and the same inserting hole of the housing such that their contact portions are opposite to each other. When a pivoting member has been pivotally moved, the first and second contacts come into contact with the corresponding ground, signal and phase inversion signal patterns on the flexible printed circuit board and the members at the predetermined positions enter the exposed portions so as to contact the ground layer, thereby achieving a miniaturization of the connector and high speed transmission of signals. | 2009-03-12 |
20090068861 | Apparatus and method for adjusting position of electronic component - An apparatus, includes a plurality of pins which include a longitudinal axis, each of the pins to be respectively electronically contacted with each of a plurality of terminals of an electronic component by pressing each of the terminals onto each of the pins from a direction corresponding to the longitudinal axis, and an adjusting unit which adjusts a position of the electronic component so that each of the terminals corresponds to each of the pins respectively. | 2009-03-12 |
20090068862 | Electronic device including printed circuit board, connector and casing - An electronic device includes a printed circuit board, a connector mounted on the printed circuit board, a casing, and a sealing member. The casing houses the printed circuit board and a part of the connector in such a manner that the other part of the connector protrudes to an outside of the casing. The casing has a casing-side recess portion and a casing-side protruding portion that are connected each other to have a loop shape. The housing has a connector-side protruding portion and a connector-side recess portion that are connected to each other to have a loop shape. The connector-side protruding portion is fitted into the casing-side recess portion through the sealing member and the casing-side protruding portion is fitted into the connector-side recess portion through the sealing member. | 2009-03-12 |
20090068863 | Connecting terminal - The invention relates to a connecting terminal with an insulating housing and a clamping contact positioned in the connecting terminal housing for the purpose of connecting an electrical conductor, such that a contact spring, which is electrically connected to the clamping contact in the housing, is guided through an initial hole in the housing of connecting terminal to the outside of the housing, and where the contact spring is so designed that it presses against the contact surface of the circuit board when the connecting terminal is mounted on a circuit board, to thereby produce an electrical contact between the circuit board and the clamping contact. | 2009-03-12 |
20090068864 | Electronic device including printed circuit board and electronic element mounted on the printed circuit board - An electronic device includes a printed circuit board and an electronic element having a terminal. The terminal has a surface section and an insertion section. The printed circuit board includes a through hole extending from a first surface to a second surface of the printed circuit board, a surface land disposed on the first surface, and an insertion land integrally disposed on a sidewall of the through hole and on a periphery around the through hole. The surface section is coupled with the surface land through a solder. The insertion section is disposed in the through hole and is coupled with the insertion land through the solder. The surface section has a recess part and a portion of recess part is disposed so as to be axially aligned with a portion of the through hole. | 2009-03-12 |
20090068865 | Case with Connector and Manufacturing Method Thereof - A case with a connector integrally formed with a resin connector, and can be manufactured with a small number of processes is provided. The connector case includes a housing, a resin connector, and a ground terminal extending along an outer periphery of the connector. A terminal-side fixing portion extending backward from the ground terminal is crimped to or pressed over a housing-side fixing portion. When molds are closed after the housing and the ground terminal are placed in the molds for injection molding of the resin connector, a pressing portion formed on the mold presses the terminal-side fixing portion against the housing-side fixing portion to crimp or press the terminal-side fixing portion to or over the housing-side fixing portion. As a result, in the process for the injection molding of the connector, the ground terminal is fixed to the housing at the same time. The connector case with the ground terminal fixed to the housing can be manufactured in a small number of processes. | 2009-03-12 |
20090068866 | Elongate Electrical Conductor That is Adapted for Electrically Connecting With an Electrical Contact - An elongate electrical conductor ( | 2009-03-12 |
20090068867 | CONNECTOR SYSTEM - A portable computer is disclosed. The portable computer comprises a chassis and a connection system. The connection system has a plurality of different connector receptacles. The connection system is configured to swing relative to the chassis between an open position where the connector receptacles are exposed for use and, closed position where the connector receptacles are hidden and stored within the chassis. | 2009-03-12 |
20090068868 | Card connector - A card connector ( | 2009-03-12 |
20090068869 | Flourescent lamp socket with enhanced contact reliability - The lamp socket according to the invention demonstrates a housing ( | 2009-03-12 |
20090068870 | FLOATING SELF-CENTERING CONNECTOR - A self-centering connection is provided. This self-centering connection includes a first substrate, a first connector assembly, a first number of alignment guides, a second substrate, a second connector assembly, a second number of alignment guides, and a number of free-floating compression fastener systems. The first connecting assembly is mounted on the first substrate. The first alignment guides are amounted on both the first and second substrate. The second connector assembly is mounted on the second substrate. The free-floating compression fastener system mechanically couples the first substrate to the second substrate wherein tolerances of the free-floating compression fastener system allow the first substrate to float relative to the second substrate in an XY in a first plane. The compression load of the compression fastener system allows the first substrate to float in a Z axis relative to the second substrate. | 2009-03-12 |
20090068871 | SUBMERSIBLE ELECTRICAL CABLE CONNECTOR - The present invention is embodied in a submersible electrical cable connector having a cable-side connector assembly and a receptacle-side connector assembly. In a preferred embodiment, the cable-side connector assembly includes a generally circular printed circuit board having individual pin assemblies, each pin assembly having its own spring-loaded mechanism. The pin assemblies provide for an electrical connection between the cable-side connector assembly and the receptacle-side connector assembly. The printed circuit board also includes an oil valve that allows oil to flow between the cable-side connector assembly and the receptacle-side connector assembly when the two connector assemblies are coupled together. The cable-side connector assembly additionally includes a cap having a bleed valve that allows a user to remove air trapped within the submersible electrical cable connector when it is filled with oil. | 2009-03-12 |
20090068872 | Electrical system - An electrical system ( | 2009-03-12 |
20090068873 | Electrical connector - An electrical connector including a pair of connector bars and a pair of biting pads. The connecting bars are configured to be located on opposite sides of a plate section of a first member. The connector bars include holes to receive a bolt for clamping the connector bars directly against each other. The pair of biting pads are connected to the connector bars. The biting pads include surfaces which are configured to contact the opposite sides of the plate section and bite onto the opposite sides as the connector bars are clamped against each other. | 2009-03-12 |
20090068874 | MOBILE PHONE AND MEMORY CARD FIXING DEVICE THEREOF - A memory card fixing device including a base and two resilient fastening structures is disclosed. The resilient fastening structures are provided at the two opposite sides of the base. Each fastening structure has a guiding portion and a recess. A memory card slides into the recess along the guiding portion and can be fixed in the recess by the resilience of the fastening structures. | 2009-03-12 |
20090068875 | Socket connector assembly with a heat sink detachably attached thereon - An electrical connector assembly includes a frame ( | 2009-03-12 |
20090068876 | Zero insertion force connector with improved driving device - An electrical connector of the present invention includes a base unit ( | 2009-03-12 |
20090068877 | Apparatus for making electrical contact with luminous means in spotlights - An apparatus for making electrical contact with luminous means in spotlights, which contain a glass vessel, a luminous means base and contact pins for the power supply is provided. The apparatus comprising a luminous means holder with at least two socket pairs for accommodating the contact pins of different luminous means. The socket pairs are arranged in clamping pieces, whose mutually opposite connecting faces can be removed from one another in order to accommodate the contact pins of the luminous means and can be guided towards one another in order to make electrical contact with the contact pins of the luminous means. | 2009-03-12 |
20090068878 | Wire containment cap - A wire containment cap includes a first side having a plurality of retainers for retaining wires, and a second side opposite the first side. Two sidewalls extend between the first side and the second side, and a support rib extends between the two sidewalls. The support rib includes two pair separators for separating wire pairs. In one embodiment, a plurality of sloped pair splitters is located between two of the retainers and includes a sharp point for cutting through insulation material on a pair of bonded wires. A communication jack assembly including a front portion and the wire containment cap is also described. | 2009-03-12 |
20090068879 | Connector structure - A connector structure is composed of a base, a cover plate, and terminals. A location of the base is installed with the terminals, and the other location of the base is installed with the cover plate. A location of the cover plate is extended with a shaft, and the base is provided with a groove. Therefore, when a user inserts a cable into the connector, he or she can inspect that whether the cable has been positioned through the groove, so as to facilitate the user to install the cable, and to assure accuracy of positions of the cable and the terminals, at a same time. | 2009-03-12 |
20090068880 | STRUCTURES OF TERMINALS AND COMPONENT-TO-BE-LOADED - Terminal structures for electric connection between a battery pack and a video camera. The video camera has a main body side terminal and the battery pack has a battery side terminal for joining with the main body side terminal. Terminal pieces of the main body side terminal are insert-molded on an upper frame body having integrally molded guide pieces to sandwich the terminal pieces. Terminal members are insert-molded on a terminal case having guide grooves that correspond to the guide pieces. By engaging the guide pieces with the guide grooves, the main body side terminal and the battery side terminal are properly positioned. | 2009-03-12 |
20090068881 | TELECOMMUNICATION PATCH PANEL - A telecommunications patch panel, including a frame member including a plurality of connector module mounts; and a plurality of connector modules, each being coupled to one of said mounts in one of a plurality of positions about an axis of rotation, wherein a first side of each connector module of said modules includes a plurality first of connector jacks in electrical communication with a second connector jack coupled to an opposite facing second side of the module | 2009-03-12 |
20090068882 | Card connector - A card connector comprises an insulating housing comprising a base and a plurality of tongue portions extending from the base; a shell covering the insulating housing; a plurality of contacts arranged in upper and lower line each retained on the housing; the contacts each comprising a contacting portion extending into the mating portion, a containing portion secured in the housing, and a soldering portion extending behind the housing; a spacer and a PCB each mounted on the insulating housing and the soldering portion of the contacts each receiving in the spacer and the PCB; the distance between the soldering portions of the upper and the lower contacts is smaller than that of the containing portions. | 2009-03-12 |
20090068883 | BOARD EDGE TERMINATION BACK-END CONNECTION ASSEMBLIES AND COMMUNICATIONS JACKS INCLUDING SUCH ASSEMBLIES - A communications jack includes a housing having a plug aperture, a printed circuit board that is disposed at least partly within the housing, and eight jackwire contacts that are mounted on the printed circuit board and extend into the plug aperture. A first side of the printed circuit board further includes four output contacts and an opposed second side of the printed circuit board further includes another four output contacts. A board edge termination assembly is mounted on an edge of the printed circuit board. The board edge termination assembly includes a body and eight contact members that are disposed at least partly within the body. Each contact member is configured to mate with a respective one of the output contacts. | 2009-03-12 |
20090068884 | Connecting structure of printed circuit board for coaxial cable - The present invention relates to a coaxial cable structure for connecting to a printed circuit board including: a coaxial cable part having a plurality of signal lines, an inner insulator, a shield wire covered along the outer periphery of the inner insulator, and an outer insulator covered along the outer periphery of the shield wire; a pattern part formed on one surface of the printed circuit board, and serving as a conductor adapted to abut against the signal lines exposed to the outside of the coaxial cable part, the pattern part having the corresponding the plurality of signal lines; number of signal patterns to and a ground pattern adapted and a soldering part adapted to directly solder each the coaxial cable part portions thereof to the pattern part of signal line and exposed to the each shield wire of outside at the end the printed circuit board. | 2009-03-12 |
20090068885 | MOUNTING ASSEMBLY FOR SHIELDING APPARATUS - A mounting assembly for shielding EMI, the mounting assembly includes a drive bracket ( | 2009-03-12 |
20090068886 | ASSEMBLED ELECTRICAL CONNECTOR - The invention discloses an assembled electrical connector, which comprises an insulating housing and at least two sets of electrical conducting terminals. The insulating housing has a main body, a first tongue and a second tongue extending from the main body and perpendicular to the main body, wherein the first tongue is longer than the second tongue, and the second tongue is located at a side of the first tongue in a lengthwise direction. The at least two sets of electrical conducting terminals comprise a first terminal set and a second terminal set, wherein the first terminal set is arranged at a side of the first tongue, and the second terminal set is arranged at a side of the second tongue. Compared with prior art, such a structure can miniaturize the volume of the electrical connector apparently and further miniaturize the volume of an electronic product utilizing the electrical connector. | 2009-03-12 |
20090068887 | High speed transmission connector - Each of the ground contact terminals of a contact unit has a pair of bifurcated terminals located on opposite sides of a pair of transmission contact terminals formed adjacent to each other. | 2009-03-12 |
20090068888 | Socket connector - A socket connector is disclosed that includes a housing, multiple contact modules fixed to the housing, and multiple shield members coupled and fixed to the corresponding contact modules. The contact modules and the shield members are alternately arranged in alignment in a longitudinal direction of the housing. The shield members are fixed to the housing. | 2009-03-12 |
20090068889 | Electrical connector with reduced noise - An electrical connector includes a carrier having opposite first and second sides. A plurality of contacts are held in the carrier. Each contact includes a first conductive element and a second conductive element. The first conductive element defines a conductive path configured to electrically connect an electrical component on the first side of the carrier to an electrical component on the second side of the carrier. The second conductive element provides an electrostatic shield for the first conductive element. | 2009-03-12 |
20090068890 | Electric connector assembly kit and shielded cable harness - The electric connector assembly kit is structured that the inner wire of the end of the shielded cable is fitted and held in the wire holding part of the wire holder and the outer conductor is crimped by the barrel, the connector body is set on the lower side of the wire holder, the inner conductor of the inner wire is connected to the contact and the barrel is press-fitted in the U-shaped slot, the plug cover shell is set on the higher side of the wire holder and made to contact the barrel, and the top end of the coupling piece extending toward the lower side between the U-shaped slots is bent toward the back side in the depth direction and hooked on the plug shell from the lower side to assemble onto the end of the shielded cable. | 2009-03-12 |