11th week of 2009 patent applcation highlights part 16 |
Patent application number | Title | Published |
20090065886 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a solid-state image pickup device, a thickness of an insulating film, a width and a thickness of wirings, a length of the wirings, or a diameter of bump portions formed on the wirings is formed so that a capacitance of a capacitor structure generated between a solid-state image sensor chip, and the wirings and the bump portions is not more than a desired value. Thereby, sensitivity of the solid-state image pickup device is not lowered at high-frequency driving. | 2009-03-12 |
20090065887 | Image Sensor and Method for Manufacturing the Same - Provided is an image sensor and a method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline semiconductor layer and electrically connected with the lower metal line. A pixel isolation layer is formed in regions of the photodiode. | 2009-03-12 |
20090065888 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a main surface of a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region in circular form, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other. | 2009-03-12 |
20090065889 | Semiconductor integrated circuit device and method for designing the same - A semiconductor integrated circuit device has a basic cell structure which allows avoidance of wiring congestion of signal lines or the like. The semiconductor integrated circuit device comprises a plurality of basic cells having predetermined functions, respectively, which are configured by connecting semiconductor elements via wirings. Each of the basic cells has a polygonal shape when viewed from the top. Moreover, a power source line is provided in an inner portion of the basic cell. | 2009-03-12 |
20090065890 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to the lowered reliability of a device due to deterioration caused by the concentration of an electric field in the top corner of an STI. To solve the reliability problem, the STI top corners have a local oxidation of silicon, the top corners of the STI are rounded, and the STI steps are increased in a semiconductor device fabricated according to embodiments. Embodiments relate to an STI in high and low voltage regions of a semiconductor device which can be fabricated by providing a semiconductor substrate having a shallow trench isolation structure, a high voltage region and a low voltage region. A capping layer is formed over the entire surface of the top of the high voltage region and the low voltage region, including the shallow trench isolation structure. A photoresist pattern is formed over the top of the capping layer to expose the high voltage region, including a portion of the shallow trench isolation structure formed within the high voltage region. The capping layer of the high voltage region is removed by performing an etching process using the photoresist pattern as a mask. An oxidation process is performed on the shallow trench isolation structure top corners of the high voltage region from which the capping layer is removed. An ion implantation is then carried out. The ion implantation may be carried out by implanting boron using a tilt method. | 2009-03-12 |
20090065891 | Semiconductor Substrate And Process For Producing It - A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: | 2009-03-12 |
20090065892 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same that reduces a process defect caused by pattern dependency in chemical mechanical polarization (CMP) or etching is excellent. The semiconductor device includes a device pattern formed on or in a substrate; and a plurality of dummy patterns having different longitudinal-sectional areas formed at one side of the device pattern. The dummy patterns, which have the same planar size but have different longitudinal-sectional areas from the three-dimensional structural point of view, include first dummy pattern having a first thickness and second dummy pattern having a second thickness larger than the first thickness. | 2009-03-12 |
20090065893 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device and fabrication method thereof is disclosed. The method includes the steps of providing a substrate with a trench and a stacked layer thereon, performing an epitaxy process to form an epitaxial layer in the trench, conformably depositing an oxide layer on the epitaxial layer, and removing a portion of the oxide layer and the epitaxial layer on the bottom of the trench. | 2009-03-12 |
20090065894 | Electronic circuit device having silicon substrate - An electronic circuit device comprises a silicon substrate having front and rear surfaces, a semiconductor element formed on the front surface, and at least one through-hole penetrating through the front surface and the rear surface. At least one passive element is supported by the silicon substrate. At least one connecting element is disposed in the through-hole of the silicon substrate for electrically connecting the semiconductor element to the passive element. | 2009-03-12 |
20090065895 | MIM capacitor high-k dielectric for increased capacitance density - According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlN | 2009-03-12 |
20090065896 | CAPACITOR HAVING Ru ELECTRODE AND TiO2 DIELECTRIC LAYER FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a capacitor of a semiconductor device using a TiO | 2009-03-12 |
20090065897 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A M-I-M capacitor semiconductor device capable of enhancing the reliability and capacitance of a capacitor and maximizing the integration density of the device, and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate, a capacitor lower metal layer formed over the semiconductor substrate, a SiN capacitor dielectric layer having a thickness of approximately 30 nm or less formed over the capacitor lower metal layer, and a capacitor upper metal layer formed over a portion of the capacitor dielectric layer and overlapping with the capacitor lower metal layer. | 2009-03-12 |
20090065898 | INTEGRATED BEOL THIN FILM RESISTOR - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 2009-03-12 |
20090065899 | SEMICONDUCTOR DEVICE - The invention is directed to providing a technique for increasing a hold voltage of an electrostatic breakdown protection device having a bipolar transistor structure more than conventional and reducing the size of the device. A base region (a P impurity layer) is formed on a front surface of an epitaxial layer, an emitter region (an N+ impurity layer) is formed on the front surface of the P impurity layer, and the epitaxial layer and an N+ impurity layer form a collector region. A connected portion of a base electrode and the base region (the P impurity layer) is located between the end of the base region (the P impurity layer) on a collector electrode side and the emitter region (the N+ impurity layer). It means that the electrodes for the collector, the base and the emitter are formed in this order. The base electrode and the emitter electrode are connected through a wiring (not shown). A P+ isolation layer for dividing the epitaxial layer into a plurality of island regions is further formed. | 2009-03-12 |
20090065900 | Group III nitride-based compound semiconductor device - A characteristic feature of the invention is to form, in a Group III nitride-based compound semiconductor device, a negative electrode on a surface other than a Ga-polar C-plane. In a Group III nitride-based compound semiconductor light-emitting device, there are formed, on an R-plane sapphire substrate, an n-contact layer, a layer for improving static breakdown voltage, an n-cladding layer made of a multi-layer structure having ten stacked sets of an undoped In | 2009-03-12 |
20090065901 | Semiconductor Element and Manufacturing Method Thereof - A semiconductor element and a manufacturing method of the semiconductor element are provided. A ridge waveguide type semiconductor integrated element includes: an electrode of an EA portion and an electrode of an LD portion which are arranged so as to be away from each other; a contact layer of the EA portion and a contact layer of the LD portion which are arranged so as to be away from each other and in each of which the electrode is formed on an upper surface and an edge of at least a part of the upper surface is set to the same electric potential as that of the electrode; a passivation film as an insulative concave/convex structure extending from an edge of one of the two contact layers to an edge of the other contact layer; and a polyimide resin for embedding the passivation film. | 2009-03-12 |
20090065902 | METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECEIVING AN ELECTRICAL CONNECTOR - A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package. | 2009-03-12 |
20090065903 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening. | 2009-03-12 |
20090065904 | SUBSTRATE HAVING THROUGH-WAFER VIAS AND METHOD OF FORMING - An annular trench region is formed at a semiconductor substrate of an electronic device that defines a conductive plug of the through-wafer via, wherein the conductive plug includes an undisturbed portion of the semiconductor substrate. | 2009-03-12 |
20090065905 | Conductive metal structure applied to a module IC and method of manufacturing the same - A conductive metal structure applied to a module IC includes a wafer, a first insulating unit, and a first conductive unit. The wafer has a main body and a through hole passing through the main body. The first insulating unit has a first inner insulating layer formed on an inner surface of the through hole and a first outer insulating layer that is extended from the first inner insulating layer and is formed on a first bottom surface of the main body. The first conductive unit has a first inner conductive layer formed on the first inner insulating layer and at least one first conductive pad formed on the first outer insulating layer. The present invention integrates semiconductor technologies of etching and deposition and combines them with the development of the module IC in order to provide a conductive metal structure that has lower cost and is manufactured easily. | 2009-03-12 |
20090065906 | SEMICONDUCTOR DEVICE AND PRODUCING METHOD OF THE SAME - A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening. | 2009-03-12 |
20090065907 | Semiconductor packaging process using through silicon vias - A microelectronic unit | 2009-03-12 |
20090065908 | METHODS OF FABRICATING A MICROMECHANICAL STRUCTURE - Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate. | 2009-03-12 |
20090065909 | Segmented magnetic shielding elements - A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields. | 2009-03-12 |
20090065910 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - While a semiconductor device is provided with a plurality of element electrodes | 2009-03-12 |
20090065911 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a carrier, at least one chip, an encapsulation, and a patterned conductive film. The carrier has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the carrier and electrically connected to the carrier. The encapsulation encapsulates the chip and at least a portion of the first surface of the carrier. The patterned conductive film is disposed on the encapsulation to electrically connect to the carrier. A manufacturing method of the semiconductor package is also disclosed. | 2009-03-12 |
20090065912 | Semiconductor Package and Method of Assembling a Semiconductor Package - A semiconductor package includes a semiconductor component including a circuit carrier with a plurality of inner contact pads, a semiconductor chip, and a plurality of electrical connections. An adhesion promotion layer is disposed on at least areas of the semiconductor component and a plastic encapsulation material encapsulates at least the semiconductor chip, the plurality of electrical connections and the plurality of the inner contact pads. Surface regions of the semiconductor component are selectively activated. | 2009-03-12 |
20090065913 | CHIP PACKAGE WITH ASYMMETRIC MOLDING - A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate. | 2009-03-12 |
20090065914 | SEMICONDUCTOR DEVICE WITH LEADERFRAME INCLUDING A DIFFUSION BARRIER - A semiconductor device includes a leadframe having a first face and an opposing second face, a portion of the first face defining a die pad, a diffusion barrier deposited on at least a portion of the die pad, and at least one chip coupled to the diffusion barrier. | 2009-03-12 |
20090065915 | SINGULATED SEMICONDUCTOR PACKAGE - A semiconductor device includes a singulated semiconductor package having a leadframe, a chip electrically coupled to the leadframe, encapsulating material covering the chip and a portion of the leadframe, and a material layer disposed over opposing ends of the leadframe. The leadframe includes a first face and an opposing second face, the first and second faces extending between opposing ends of the leadframe, where the second face configured to electrically couple with a circuit board. The chip is electrically coupled to the first face. The encapsulating material covers the chip and the first face of the leadframe. The material layer is configured to improve solderability of the singulated semiconductor package to the circuit board. | 2009-03-12 |
20090065916 | SEMICONDUCTOR DIE MOUNT BY CONFORMAL DIE COATING - A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support. | 2009-03-12 |
20090065917 | Multi-Standards Compliant Card Body - A card body comprises a module-receiving part ( | 2009-03-12 |
20090065918 | INTERCONNECTING ELECTRICAL DEVICES - An intercoupling component includes first male contacts, each first male contact received within a corresponding aperture of a first array of apertures and extending beyond a second surface of a first insulative support member toward a second insulative support member, each first male contact having a first axis; second contacts, each second contact received within a corresponding aperture of a second array of apertures, each second contact having a second axis; and an alignment member configured to establish a specified position of the first insulative support member relative to the second insulative support member. The first axis of each male contact is offset from the second axis of a corresponding second contact when the first insulative support member is in the specified position relative to the second insulative support member. | 2009-03-12 |
20090065919 | SEMICONDUCTOR PACKAGE HAVING RESIN SUBSTRATE WITH RECESS AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection. | 2009-03-12 |
20090065920 | Semiconductor package embedded in substrate, system including the same and associated methods - A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package. | 2009-03-12 |
20090065921 | Electronic Package Device, Module, and Electronic Apparatus - There is provided an electronic device package and the like in which it is not likely that damage occurs in a wiring pattern of an interposer substrate in a gap section formed, for example, between an electronic device and an insertion substrate. The semiconductor package in accordance with the present invention is a package of fan-out type including an interposer substrate | 2009-03-12 |
20090065922 | SEMICONDUCTOR DEVICE PACKAGE STRUCTURE - A semiconductor chip mounted interposer ( | 2009-03-12 |
20090065923 | SEMICONDUCTOR PACKAGE WITH IMPROVED SIZE, RELIABILITY, WARPAGE PREVENTION, AND HEAD DISSIPATION AND METHOD FOR MANUFACTURING THE SAME - The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on the upper portion of the semiconductor package module, and a penetration electrode penetrates the semiconductor package. The penetration electrode is electrically connected to the circuit patterns. The described semiconductor package improves upon important characteristics such as size, reliability, warpage prevention, and heat dissipation. | 2009-03-12 |
20090065924 | SEMICONDUCTOR PACKAGE WITH REDUCED VOLUME AND SIGNAL TRANSFER PATH - A semiconductor package includes a first semiconductor chip having a first semiconductor chip body including a first circuit region and peripheral regions arranged around the first circuit region. A first bonding pad group is arranged within the first circuit region and includes a plurality of bonding pads. A first redistribution group including a plurality of redistributions is electrically connected to the respective bonding pads and extends towards the peripheral regions. The package further includes a second semiconductor chip having a second semiconductor chip body including a second circuit region opposing the first circuit region. A second bonding pad group is arranged within the second circuit region and corresponds to the first bonding pad group. A second redistribution group is electrically connected to the respective bonding pads of the second bonding pad group. Redistribution connection members are used to electrically connect the first redistribution group to the second redistribution group. | 2009-03-12 |
20090065925 | DUAL-SIDED CHIP ATTACHED MODULES - An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate. | 2009-03-12 |
20090065926 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a base plate made of a material including at least a thermosetting resin, and having an opening, a vertical conductor filled and provided in the opening of the base plate, at least one semiconductor construct having a semiconductor substrate and a plurality of external connection electrodes provided on one side of the semiconductor substrate, and an insulating layer secured to and provided on a periphery of the semiconductor construct. The insulating layer is secured to the base plate, and the external connection electrodes of the semiconductor construct are bonded to the vertical conductor. | 2009-03-12 |
20090065927 | Semiconductor Device and Methods of Manufacturing Semiconductor Devices - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip wherein the molded body comprises an array of recesses in a first surface of the molded body, first contact elements, and elastic elements in the recesses that connect the first contact elements with the molded body. | 2009-03-12 |
20090065928 | Anti-stiction technique for electromechanical systems and electromechanical device employing same - A mechanical structure is disposed in a chamber, at least a portion of which is defined by the encapsulation structure. A first method provides a channel cap having at least one preform portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. A second method provides a channel cap having at least one portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. The at least one portion is fabricated apart from the electromechanical device and thereafter affixed to the electromechanical device. A third method provides a channel cap having at least one portion disposed over or in at least a portion of the anti-stiction channel to seal an anti-stiction channel, at least in part. The at least one portion may comprise a wire ball, a stud, metal foil or a solder preform. A device includes a substrate, an encapsulation structure and a mechanical structure. An anti-stiction layer is disposed on at least a portion of the mechanical structure. An anti-stiction channel is formed in at least one of the substrate and the encapsulation structure. A cap has at least one preform portion disposed over or in at least a portion of the anti-stiction channel to seal the anti-stiction channel, at least in part. | 2009-03-12 |
20090065929 | MULTI-CHIP SEMICONDUCTOR DEVICE - A semiconductor device includes semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module. The semiconductor device includes first and second semiconductor chips mounted over a package substrate which has bonding pads arranged along the edges. The first semiconductor chip includes bonding pads for analog signals, and the second semiconductor chip includes bonding pads for high-voltage signals. The edges along which the bonding pads for analog signals are arranged and the edges along which the bonding pads for high-voltage signals are arranged are disposed along mutually different edges of the package substrate. Adjoining of electrodes or wirings for high voltage signals and those for analog signals over the package substrate can be easily avoided, and SI deterioration can be thereby restrained. | 2009-03-12 |
20090065930 | Package Substrate Including Surface Mount Component Mounted on a Peripheral Surface thereof and Microelectronic Package Including Same - A microelectronic combination and a method of making the combination. The combination includes a package substrate including a substrate body having a peripheral surface and contacts disposed at the peripheral surface; and a surface mount component electrically and mechanically bonded to the contacts. | 2009-03-12 |
20090065931 | PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF - Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps has a height of about 40 micrometers (μm) to about 65 μm. Further, the plurality of copper bumps are configured on the semiconductor die. Each of the plurality of copper bumps has a height of about 10 μm to about 25 μm. The semiconductor die is disposed above the substrate such that the plurality of copper bumps are coupled to the plurality of solder bumps, which in turn, couples the semiconductor die to the substrate. | 2009-03-12 |
20090065932 | Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby - Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure. | 2009-03-12 |
20090065933 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps. | 2009-03-12 |
20090065934 | Wiring substrate, tape package having the same, display device having the tape package, method of manufacturing the wiring substrate, method of manufacturing a tape package having the same and method of manufacturing a display device having the tape package - A wiring substrate may include a base film, a plurality of wires, a first insulation member and a second insulation member. The base film may have a chip-mounting region where a semiconductor chip may be mounted thereon. The wires may extend from the chip-mounting region and the wires may include adhesive end portions that may be electrically connected to the semiconductor chip. The first insulation member may cover portions of the wires outside the chip-mounting region thereof. The second insulation member may cover portions of the wire inside the chip-mounting region, the adhesive end portion of the wire being exposed by the second insulation member. | 2009-03-12 |
20090065935 | SYSTEMS AND METHODS FOR BALL GRID ARRAY (BGA) ESCAPE ROUTING - A ball grid array (BGA) package and its corresponding printed circuit board incorporate an improved escape routing scheme. The substrate includes a plurality of conductive pads having a periphery defined by a predetermined edge pattern forming routing channels therebetween. A plurality of signal lines connected to a subset of the conductive pads extends beyond the periphery through the routing channels. The predetermined pattern may, for example, be a right triangle repeating with a periodicity along the periphery of the array, wherein the right triangle has a first side defined by a number of rows in the array, and a second side, perpendicular to the first, defined by a number of layers in the array. | 2009-03-12 |
20090065936 | SUBSTRATE, ELECTRONIC COMPONENT, ELECTRONIC CONFIGURATION AND METHODS OF PRODUCING THE SAME - A substrate for an electronic component comprises a dielectric body having an upper surface including a plurality of inner contact pads and a lower surface including a plurality of outer contact pads. Each outer contact pad has an inner face and an outer face. An insulating layer covers the lower surface of the dielectric body and the peripheral regions of the plurality of outer contact pads. A depression is located in the approximate lateral centre of the outer face of each of the plurality of outer contact. | 2009-03-12 |
20090065937 | STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD - A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump. | 2009-03-12 |
20090065938 | Semiconductor Element and Method for Manufacturing Same - The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with the semiconductor. | 2009-03-12 |
20090065939 | METHOD FOR INTEGRATING SELECTIVE RUTHENIUM DEPOSITION INTO MANUFACTURING OF A SEMICONDUCTIOR DEVICE - A method for integrating selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu. The method includes selectively depositing a Ru metal film on a metallization layer or on bulk Cu using a process gas containing Ru | 2009-03-12 |
20090065940 | METAL WIRING OF A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - According to a method of forming a metal wiring of a semiconductor device, a contact plug is formed at height lower than the contact hole, which is formed on an interlayer insulation layer, and then a metal wiring is formed over the contact plug and interlayer insulation layer to completely fill inside of the contact hole, decreasing process difficulty, ensuring reproducibility, and improving electrical property. | 2009-03-12 |
20090065941 | METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS - A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer. | 2009-03-12 |
20090065942 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a film containing silicon as the main ingredient, and an aluminum alloy film, such as a source electrode and a drain electrode, that is directly connected to the film containing silicon as the main ingredient, such as an ohmic low-resistance Si film, and contains at least Al, Ni, and N in the vicinity of the bonding interface. The Aluminum alloy film has a good contact characteristic when directly connected to the film containing silicon as the main ingredient without having a barrier layer formed of high melting point metal. | 2009-03-12 |
20090065943 | Microelectronic Assembly Having Second Level Interconnects Including Solder Joints Reinforced with Crack Arrester Elements and Method of Forming Same - A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint. | 2009-03-12 |
20090065944 | REWORKED INTEGRATED CIRCUIT DEVICE AND REWORKING METHOD THEREOF - Reworking method for removing defects on integrated circuit device is disclosed. An integrated circuit is provided, which has a substrate, a conductive material layer formed in the substrate, a dielectric layer formed on the substrate, at least a contact plug embedded in the dielectric layer, and a conductive layer contacting to the contact plug formed on the dielectric layer. A defect is found in the conductive layer and the reworking method is performed, including an etch back process, a chemical mechanical polishing process, and a deposition process. The reworking method removes the prior formed conductive layer and reform a conductive layer to prevent the integrated circuit from being scraped. | 2009-03-12 |
20090065945 | SEMICONDUCTOR DEVICE FOR PREVENTING INFLOW OF HIGH CURRENT FROM AN INPUT/OUTPUT PAD AND A CIRCUIT FOR PREVENTING INFLOW OF HIGH CURRENT THEREOF - A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a portion of the plurality of metal lines included in the buffer area forms protective resistance interconnecting the input/output pad to the input line. | 2009-03-12 |
20090065946 | Method for fabricating semiconductor device and semiconductor device - A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive material in the first opening. Then form a second thin film made of a porous material above the first thin film with the conductive material being deposited in the first opening. Next, define in the second thin film a second opening extending therethrough, followed by deposition of a conductive material in the second opening. The first thin film is removed through voids in the second thin film after having deposited the conductive material in the second opening. An integrated semiconductor device as manufactured thereby is also disclosed. | 2009-03-12 |
20090065947 | Semiconductor device having circularly connected plural pads via through holes and method of evaluating the same - A semiconductor device includes a plurality of wiring layers, a plurality of via layers, and a plurality of electrode pads. The electrode pads are circularly connected to each other through the wiring layers and the via layers. | 2009-03-12 |
20090065948 | Package structure for multiple die stack - A die module and method for assembling such a die module is provided. For example, present embodiments include providing a substrate and coupling a first sub-stack to the substrate, wherein the first sub-stack includes two or more die arranged in a first shingle stack configuration relative to one another such that an upper portion of each die in the first sub-stack is accessible, the first shingle stack configuration having a first skew. Further, present embodiments include stacking a second sub-stack on top of the first sub-stack, wherein the second sub-stack includes two or more die arranged in a second shingle stack configuration relative to one another such that an upper portion of each die in the second sub-stack is accessible, the second shingle stack configuration having a second skew that is different than the first skew. | 2009-03-12 |
20090065949 | Semiconductor package and semiconductor module having the same - A semiconductor package can include a semiconductor chip, an insulating substrate, first bond fingers, and pads. The insulating substrate can be attached to edge portions of the semiconductor chip. The first bond fingers can be arranged on edge portions of an upper surface of the insulating substrate. Further, the first bond fingers can be electrically connected to the semiconductor chip. The pads can be arranged on a central portion of the upper surface of the insulating substrate. Further, the pads can be electrically connected to the first bond fingers. Thus, types of stackable devices that can be mounted on or in the semiconductor package need not be restricted. | 2009-03-12 |
20090065950 | STACK CHIP AND STACK CHIP PACKAGE HAVING THE SAME - Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip. | 2009-03-12 |
20090065951 | STACKED DIE PACKAGE - The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed. | 2009-03-12 |
20090065952 | Semiconductor Chip with Crack Stop - Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner. | 2009-03-12 |
20090065953 | Chip module and a fabrication method thereof - A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure. | 2009-03-12 |
20090065954 | Packaging Method For Wideband Power Using Transmission Lines - Embodiments of the invention relate to a package design incorporating an ultra-low characteristic impedance transmission line (T-line) bundle. The T-line bundle can extend from inside the package to outside the package in order to provide power delivery and power interconnect for a chip. In one embodiment, the T-line bundle can be attached at the die. In another embodiment, the T-line bundle can be attached to the package substrate. The T-line bundle can be a stack of parallel planar transmission line strips in a periodic pattern where the dielectric material of the strips can be a high-k dielectric and can be flexible, semi-rigid, or precision rigid. | 2009-03-12 |
20090065955 | METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING - An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms. | 2009-03-12 |
20090065956 | MEMORY CELL - Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over an isolation region adjacent to the first active region; and a second device having a second conductive line extending over one of a second active region and a contact element and having a second line end of the second conductive line positioned over the isolation region adjacent to the one of the second active region and the contact element, wherein the first line end and the second line end each include a bulbous end that is distanced from a respective active region or contact element. | 2009-03-12 |
20090065957 | INTEGRATED FUEL INJECTION AND MIXING SYSTEMS FOR FUEL REFORMERS AND METHODS OF USING THE SAME - Systems and methods for injecting and mixing a liquid hydrocarbon fuel to provide a uniform, homogenous fuel vapor mixture for introduction into a fuel reformer for use with a fuel cell are disclosed. Preferably, the system comprises a fuel injector that generates and aspirate a liquid fuel in the presence of an atomizing gas stream; a diverging-converging mixing chamber, into which the atomized fuel and a secondary fluid stream are introduced, to enhance the mixing of the fuel and the added heated gas or steam; and a mixer/swirler, which can be centrally located in the mixing chamber between the upper and lower chambers, to stabilize the fuel vapor mixture further for greater uniformity and homogeneity. More preferably, grooves and/or brazed wires can be provided on the surfaces of the mixing chamber and/or mixer/swirler to channel any accumulated fuel so as to provide sufficient time to evaporate the accumulated fuel. | 2009-03-12 |
20090065958 | EVAPORATIVE HUMIDIFIER PAD MADE OF RIGIDIFYING LAYER LAMINATED TO PAPER LAYER AND METHOD OF CONSTRUCTING - A humidifier pad made of a plurality of laminated sheets connected together in a stack. Each of the sheets is made of a two layer laminate material made of a first layer of a rigidifying material, such as aluminum, and a second layer made of an absorbent layer, such as paper. The layers of each of the sheets are first laminated together, and then each sheet is slit and expanded in a conventional manner. Subsequently, each sheet is bonded to a next adjacent sheet to form a pad. | 2009-03-12 |
20090065959 | Method of Fabricating Optical Fiber - A method of making an optical fiber article can include providing an optical fiber including at least a core; providing a preform; and subsequent to the foregoing providing of the optical fiber and the preform, drawing the preform so as to dispose a region about the optical fiber. An optical fiber article can include a core; a pump cladding disposed about the core, the pump cladding for propagating pump light; and a second cladding disposed about the pump cladding, where the second cladding can provide a photonic bandgap for tending to confine pump light to a region about which the second cladding is disposed. The second cladding can comprise a plurality of layers including a first layer having a different optical property than a second layer, and the plurality of layers can be arranged as to provide the photonic bandgap effect. | 2009-03-12 |
20090065960 | PROCESS FOR PRODUCING POLYSTYRENE FOAM PARTICLES HAVING A HIGH DENSITY - A process for producing polystyrene foam particles having a bulk density in the range from 40 to 400 g/l by extrusion of a polystyrene melt comprising carbon dioxide and/or water as blowing agent through a nozzle and underwater pelletization, wherein the underwater pelletization is carried out at a pressure in the range 1-30 bar. | 2009-03-12 |
20090065961 | Fibre Reinforced Composite and Method of Forming the Same - A method for forming an orthodontic device having a fibre reinforced composite is provided. The fibre reinforced composite has a fibre material within a matrix phase material. The fibre material comprises braided fibre material having a braid angle in the range from about 3° to about 87°, and more particularly in the range from about 10° to about 45°. The fibre reinforced composite is formed from a method which includes the steps of impregnating the fibre material with a monomer resin, shaping the fibre that is impregnated with the resin into a defined cross sectional shape suitable for use in the orthodontic device, and polymerising the monomer resin in the impregnated fibre to form the fibre-reinforced composite. | 2009-03-12 |
20090065962 | Injection Device of an Injection Molding Machine and Method for the Operation Thereof - There is described a device and a method for operating an injection device for an injection molding machine which is provided with an extruder screw that is driven by an electric machine. Acceleration values and/or values depending on an operating point of the electric machine are used for calculating an injection pressure and/or a ram pressure, thus dispensing with the need for a pressure sensor. | 2009-03-12 |
20090065963 | METHOD AND APPARATUS FOR TENSIONING COMPOSITE MATERIAL - An apparatus and method for tensioning material ( | 2009-03-12 |
20090065964 | Method of Manufacturing an Encapsulated Package for a Magnetic Device - A method of manufacturing an encapsulated package for a magnetic device on a substrate. In one embodiment, the method includes providing a magnetic core on the substrate and placing a shielding structure over the magnetic core to create a chamber thereabout. The method also includes depositing an encapsulant about a portion of the magnetic core within the chamber. The shielding structure limits the encapsulant entering the chamber. | 2009-03-12 |
20090065965 | REINFORCED THERMOPLASTIC RESIN AND DEVICE AND METHOD FOR PRODUCING VERY LONG FIBER REINFORCED THERMOPLASTIC RESINS - Improved reinforced thermoplastic resin, and devices and methods for producing the improved reinforced thermoplastic resin. The invention comprises complete fiber strand dispersion and wet out without breaking fiber filaments after cutting the fiber to a designated length. Certain embodiments of the present invention may comprise a zero-shear down screw which rotates very slowly. Thus, the resin and glass fiber bundles are slowly kneaded and the individual filaments unbundled from the fiber bundles resulting in complete wet-out of each filament without creating a pressure flow path for the substrate material and the entrained glass fibers and unbundled filaments. Optimized geometrically-controlled openings may be provided at the end of the down screw, providing further breakage-free kneading of the individual filaments. Certain embodiments may comprise an extended length cutting chamber which allow cutting very long individual fiber lengths. Temperature reduction mechanisms may be provided which provide a thermal block between the down screw assembly and the main frame assembly. | 2009-03-12 |
20090065966 | Press molding tool and method for production of a component by press molding - The invention relates to a press moulding tool for the production of a component from at least one first material layer ( | 2009-03-12 |
20090065967 | Molding Apparatus and Related Methods - The invention relates to molding systems and related methods. In one aspect of the invention, a molding apparatus includes a first cylindrical roll that is rotatably coupled to a frame arid an adjacent pressure device, the frame is configured so that a substrate can pass through a nip formed between the first cylindrical roll and the pressure device while a portion of the substrate extends laterally beyond at least the frame and the first cylindrical roll. | 2009-03-12 |
20090065968 | PERMANENTLY LUBRICATED FILM GASKET AND METHOD OF MANUFACTURE - A permanently lubricated film gasket for providing a fluid-tight seal between a corrugated pipe and a smooth annular section of an outer pipe or section when the corrugated pipe and the outer pipe or section are in a relative surrounded and surrounding relationship. A first portion of the gasket is shaped to fit within a groove or recess of the corrugated pipe. A second portion of the gasket extends from the first portion. The second portion is at least partially comprised of permanently lubricated film for facilitating in the connection of the pipes along a single direction. | 2009-03-12 |
20090065969 | Multicomponent textile fibers, methods for their production, and products made using them - A fiber is produced comprising polymers of differing types which are not admixed during production. The differing polymer types are heated to the point of softening in a vertically-oriented crucible and a fiber comprising the polymers in positions corresponding to their positions in the crucible is drawn from an orifice at the lower end of the crucible. | 2009-03-12 |
20090065970 | Novel fibers, high airtightness fabrics and a fabrication method thereof - The present invention provides a new tetragon fiber and a method for fabricating the same. The present invention includes: heating a thermoplastic material, extruding it from a tetragon-shaped nozzle, passing it through an airless zone, then cooling and solidifying to form threadlike substances, rolling up then processing the threadlike substances to form fibers with tetragon cross sections. The fabrics of present invention comprises a property of fine air-tightness. | 2009-03-12 |
20090065971 | Manufacturing of Shaped Coolant Hoses - The present invention relates to a process for manufacturing a shaped article such as tubes, and hoses comprising processing a fiber-reinforced thermoplastic polymer in an extruder apparatus. | 2009-03-12 |
20090065972 | METHOD FOR MANUFACTURING A CONSTRUCTION BOARD - A method for manufacturing a construction board includes mixing a first cement mixture comprising magnesium oxide and magnesium chloride, mixing a second cement mixture comprising magnesium oxide, magnesium chloride, a binding agent, and at least one filler, the second cement mixture being thicker in consistency than the first cement mixture, dispensing a first layer of the first cement mixture onto a mold, and dispensing a first layer of reinforcing mesh onto the first layer of the first cement mixture, the reinforcing mesh being sized to allow the first cement mixture to at least partially pass through the reinforcing mesh layer. The method may further include dispensing a layer of the second cement mixture over the first layer of the first cement mixture, dispensing a second layer of the first cement mixture onto the layer of the second cement mixture, dispensing a second layer of reinforcing mesh onto the second layer of the first cement mixture and allowing at least a portion of the second layer of the first cement to flow through the mesh, drying the cement based board. | 2009-03-12 |
20090065973 | APPARATUS AND METHOD FOR MANUFACTURING MULTI-COMPONENT PLASTIC MOLDED PARTS - In a method of making multi-component plastic molded parts, using an apparatus which includes two outer platens with first half-molds, and a middle platen with second half-molds interacting with the first half-molds such as to define cavities in two parting planes for injection of a plastic melt and/or a PUR mixture, one of the first and second half-molds can move in increments relative to the other one of the first and second half-molds, thereby forming different cavities in the parting planes from cycle to cycle. In a first cycle preforms are produced in respective cavities and then held in one of the first and second half-molds as the other one of the first and second half-molds moves in increments. Further components can then be injected into cavities formed in the parting planes from cycle to cycle, while another process step can be executed from cycle to cycle in free half-molds. | 2009-03-12 |
20090065974 | MANUFACTURING METHOD OF PRODUCTS ATTACHED WITH RFID LABEL IN A MOLD - A manufacturing method of products attached with a RFID label in a mold includes a first step of forming a thin substratum by injecting molding, pushing molding, vacuum molding, blowing molding or sword molding in a first mold, a second step of making a substratum label composed of the substratum and an RFID label adhered with the substratum, and a third step of placing the substratum label in a second mold, in which a plastic product is to be formed and also to be attached with the substratum label inside the product during molding process. Thus, protected by the substratum and the plastic product. The RFID cannot be broken or damaged to always maintain its capacity to be identified, with the plastic product enhanced in its value. | 2009-03-12 |
20090065975 | MANUFACTURING PROCESS FOR HIGH PERFORMANCE LIGNOCELLULOSIC FIBRE COMPOSITE MATERIALS - The present invention relates to a process for the manufacture of composite materials having lignocellulosic fibres dispersed in a thermoplastic matrix, while generally maintaining an average fibre length not below 0.2 mm. The process comprises defibrillation of the lignocellulosic fibres using a mixer and at a temperature less than the decomposition temperature of the fibres in order to separate the fibres and generate microfibres, crofÊbres, followed by dispersion of the fibres in the thermoplastic matrix by mechanical mixing to get the moldable thermoplastic composition, followed by injection, compression, extrusion or compression injection molding of said composition. The process produces high performance composite materials having a tensile strength not less than about 55 MPa, a flexural strength not less than about 80 MPa, a stiffness not less than about 2 GPa, notched impact strength not less than about 20 J/m, and un-notched impact strength not less than about 100 J/m. The composite materials of the present invention are well-suited for use in automotive, aerospace, electronic, furniture, sports articles, upholstery and other structural applications. | 2009-03-12 |
20090065976 | COMPONENT PART WITH INTEGRATED SEAL - A lid component part of an internal combustion engine with integrated elastic seal, such as, for example, is provided to a cylinder head gasket or oil pan and a process for its manufacture. The component part exhibits a circumferential flange area for the arranging of the integrated seal. The component part is based on a plastic-material, while the seal essentially comprises an organic elastomer material. The component part and the seal are chemically bonded with one another. The seal is applied by injection molding onto the component part. | 2009-03-12 |
20090065977 | PROCESS, AND APPARATUS, FOR PRODUCING REINFORCING FIBER MOLDING - A method of forming, on a strip-shaped laminate of multiple reinforcing fiber sheets superimposed one upon another, two flexures with respect to the cross-section configuration thereof, wherein in the forming of the two flexures with the use of two flexure forming dies independent from each other, respectively, the two flexure forming dies are arranged so that the relative distance of the two flexure forming dies is changeable in the direction perpendicular to the longitudinal direction of the strip-shaped laminate. This method can be effectively utilized in the production of a reinforcing fiber molding with changing of the distance between the two flexures namely, width of web portion or gauge between two flange portions from the strip-shaped laminate, or the production of fiber reinforced resin (FRP) molding therefrom. | 2009-03-12 |
20090065978 | LOAD BEARING INSULATION AND METHOD OF MANUFACTURE AND USE - A building material which comprises cement, cellulose fibers and admixtures is used in the fabrication of bricks, panels or other building products. The manufacture of this building material is accomplished by adding water, paper, a water repellant composed of calcium stearate, and a sodium silicate to act as a fire retardant material. The mixture is then thickened with cement and a second batch of concrete admixtures including a superplasticizer composed of a polyester polyacrylic polyol and an air entraining resin or surfactant to create an air entrained, viscous material for inserting in a mold or extruding through a press to form load bearing and insulating building materials. The resulting product can be formed into blocks or panels and the panels can be coated with polyurethane/polyurea coating to be bullet and blast resistant. | 2009-03-12 |
20090065979 | Process for Producing Polyamide-Based Resin Film Roll - The present invention provides a process for production of a polyamide based resin film roll comprising a step of melt-extruding and cooling wherein polyamide based resin is melt-extruded and cooled in a sheet form onto a mobile cooling material surface to obtain an unstretched sheet; a step of biaxial stretching wherein an unstretched sheet is stretched biaxially in the longitudinal direction and the transverse direction; and a step of winding up the biaxially stretched film that is biaxially stretched in a form of roll. Then, in the step of melt-extruding and cooling polyamide based resin onto a mobile cooling material surface, corona discharge in a streamer corona state is performed between an electrode applied with high DC voltage and the polyamide based resin sheet in the melted state, and sufficient electric charges that enable the polyamide based resin sheet in the melted state to come in close contact with the mobile cooling material surface are imparted. | 2009-03-12 |
20090065980 | Method and Device for Blow-Molding Containers - The invention relates to a method and a device for blow-moulding containers from preforms which have been previously heated in a heating section and consist of a thermoplastic material. After being heated, said preforms are transferred to a blowing device in which they are deformed in order to form containers under the action of a blowing pressure inside blow moulds. The blow moulds respectively consist of at least two blow-moulding segments. The preforms are transported together with the blow moulds at least along part of a path of a rotating blow wheel. The blow-moulding segments are braced in relation to each other during at least part of the blow-moulding process. At least one of the blow-moulding segments is pivoted about a rotational axis in order to perform opening and closing movements. Once a blowing station holding the blow-moulding segments is closed, at least one of the blow-moulding segments is then supported, at a distance from the rotational axis and independently from the other blow-moulding segment, in relation to a counter-bearing connected to the blow wheel. The supported blow-moulding segment is at least partially braced in relation to both the counter-bearing and the other blow-moulding segment. | 2009-03-12 |
20090065981 | METHOD OF PREPARING A MOLDED ARTICLE - The present invention relates to a method of preparing a molded article, and more particularly to a method of forming a shaped thermoplastic sheet (e.g., a fluid management structure). The method includes providing a mold apparatus ( | 2009-03-12 |
20090065982 | METHOD OF MANUFACTURING A POROUS MATERIAL - According to the present invention, a porous material comprising a connected structure formed by combining silicon carbide which is in the form of aggregate particles with cordierite which is a combining material in a state to hold a large number of pores, and having a porosity of 52 to 70% and a median pore diameter of 15 to 30 μm, and is a porous material having a high porosity and a high strength and having a remarkably low possibility of including defective portions such as cuts and the like causing liquid leakage in a case where the material is used as a filter. | 2009-03-12 |
20090065983 | A METHOD AND APPARATUS FOR LIMITING THE VIBRATION OF STEEL OR ALUMINUM STRIPS IN BLOWN-GAS OR -AIR COOLING ZONES - The invention relates to a method of improving the cooling of a blown-gas cooling chamber or of a blown-air cooling section in a line for heat treating steel and/or aluminum, and/or of improving the quality of products for treatment by reducing the vibration generated by the cooling, in which jets of gas or air are projected against each of the faces of the strip traveling through said section or chamber. In accordance with the invention, the jets ( | 2009-03-12 |
20090065984 | SMELTING APPARATUS - A metallurgical vessel ( | 2009-03-12 |
20090065985 | MOLTEN METAL REACTOR UTILIZING MOLTEN METAL FLOW FOR FEED MATERIAL AND REACTION PRODUCT ENTRAPMENT - A molten metal reactor quickly entrains a feed material in the molten reactant metal and provides the necessary contact between the molten reactant metal and the feed material to effect the desired chemical reduction of the feed material. The reactor includes a unique feed structure adapted to quickly entrain the feed material into the molten reactant metal and then transfer the molten reactant metal, feed material, and initial reaction products into a treatment chamber. A majority of the desired reactions occur in the treatment chamber. Reaction products and unspent reactant metal are directed from the treatment chamber to an output chamber where reaction products are removed from the reactor. Unspent reactant metal is then transferred to a heating chamber where it is reheated for recycling through the system. | 2009-03-12 |