10th week of 2022 patent applcation highlights part 61 |
Patent application number | Title | Published |
20220077096 | PACKAGING METHOD FOR FAN-OUT WAFER-LEVEL PACKAGING STRUCTURE - The present disclosure provides a packaging method for a fan-out wafer-level packaging structure, including: providing two or more semiconductor chips, and bonding the semiconductor chips to a bonding layer; packaging the semiconductor chips by a plastic packaging layer; removing the bonding layer, and forming a redistribution layer on the semiconductor chips, so as to achieve interconnection between the semiconductor chips, where the redistribution layer includes one or more redistribution sublayers stacked in sequence, and a method for forming each redistribution sublayer includes: forming a dielectric layer on the semiconductor chips; forming vias in the dielectric layer by photolithography; baking the dielectric layer having the vias formed therein, wherein the warpage of the dielectric layer around the vias is mitigated; curing the dielectric layer; and forming on the dielectric layer a patterned metal distribution layer corresponding to the vias; and forming metal bumps on the redistribution layer. | 2022-03-10 |
20220077097 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10. | 2022-03-10 |
20220077098 | ANISOTROPIC CONDUCTIVE FILM WITH CARBON-BASED CONDUCTIVE REGIONS AND RELATED SEMICONDUCTOR DEVICE ASSEMBLIES AND METHODS - An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF. | 2022-03-10 |
20220077099 | COMPOSITION FOR CONDUCTIVE ADHESIVE, SEMICONDUCTOR PACKAGE COMPRISING CURED PRODUCT THEREOF, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - Provided is a composition for conductive adhesive. The composition for conductive adhesive includes a heterocyclic compound containing oxygen and including at least one of an epoxy group or oxetane group, a reductive curing agent including an amine group and a carboxyl group, and a photoinitiator, wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 below. | 2022-03-10 |
20220077100 | HYBRID BONDING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - A hybrid bonding structure and a semiconductor including the hybrid bonding structure are provided. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste may include solder particles including at least one of In, Zn, SnBiAg alloy, or SnBi alloy, and ceramic particles. The solder paste may include a flux. The solder particles may include Sn(42.0 wt %)-Ag(0.4 wt %)-Bi(57.5−X) wt %, and the ceramic particles include CeO | 2022-03-10 |
20220077101 | DICING DIE ATTACH FILM, AND SEMICONDUCTOR PACKAGE USING THE SAME AND METHOD OF PRODUCING SEMICONDUCTOR PACKAGE - A dicing die attach film, including an adhesive layer and a temporary-adhesive layer, the adhesive layer and the temporary-adhesive layer being laminated,
| 2022-03-10 |
20220077102 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors. | 2022-03-10 |
20220077103 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor chip; a plurality of insulating substrates mounted with the semiconductor chip; a printed circuit board facing the plurality of insulating substrates; and a conductive member for electrically connecting the plurality of insulating substrates and the printed circuit board is provided. The printed circuit board has a first through part arranged between the plurality of insulating substrates being adjacent to each other in a top view, and a second through part different from the first through part in shape in the top view. | 2022-03-10 |
20220077104 | METHODS OF FORMING STACKED INTEGRATED CIRCUITS USING SELECTIVE THERMAL ATOMIC LAYER DEPOSITION ON CONDUCTIVE CONTACTS AND STRUCTURES FORMED USING THE SAME - Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact. | 2022-03-10 |
20220077105 | HYBRID BONDING STRUCTURE AND HYBRID BONDING METHOD - Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and a first gap area exists between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric. | 2022-03-10 |
20220077106 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device is provided. The manufacturing method includes removing a portion of an edge region from a front surface of a first substrate to form a notch in the edge region; bonding the front surface of the first substrate and a front surface of a second substrate together to forma stacked substrate, wherein the stack substrate includes an opening at a position corresponding to the notch; and filling the opening with an embedding member. | 2022-03-10 |
20220077107 | FAN-OUT WAFER-LEVEL PACKAGING STRUCTURE AND METHOD PACKAGING THE SAME - The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer. | 2022-03-10 |
20220077108 | SHIFT CONTROL METHOD IN MANUFACTURE OF SEMICONDUCTOR DEVICE - A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies. | 2022-03-10 |
20220077109 | STACKED DIE INTEGRATED WITH PACKAGE VOLTAGE REGULATORS - An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package. | 2022-03-10 |
20220077110 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate, first and second semiconductor chip structures on the substrate and spaced apart from each other in a first horizontal direction, a mold layer on the substrate and covering both the first and second semiconductor chip structures, and a supporting structure on the mold layer and distal from the upper surface of the substrate than both the first and second semiconductor chip structures in a vertical direction. The supporting structure includes first and second supporting portions, spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction and the vertical direction. Each of the first and second supporting portions has a bar shape or a linear shape extending in the first horizontal direction. At least one of the first supporting portion or the second supporting portion overlaps the first and second semiconductor chips in the vertical direction. | 2022-03-10 |
20220077111 | TILED DISPLAY DEVICE - Provided is a tiled display device. The tiled display device includes adjacent first and second display devices including a display area having pixels, a bonding area between the display areas of the first and second display devices, data lines extending in a first direction, first gate lines extending in the first direction, and configured to transmit a gate signal, and off voltage lines extending in the first direction, and configured to transmit an off voltage, wherein one of the off voltage lines is between a first pixel at an outermost side of the first display device and a second pixel located more inwardly than first pixel, and wherein the off voltage lines are not between a third pixel at an outermost side of the second display device and the first pixel. | 2022-03-10 |
20220077112 | REDUNDANT THROUGH-SILICON VIAS - A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV. | 2022-03-10 |
20220077113 | 3D STACKED DIE PACKAGE WITH MOLDED INTEGRATED HEAT SPREADER - A chip package includes a substrate; a first chip including thermal VIAs, wherein the first chip is coupled to the substrate; a conductive frame at least partially surrounding the first chip and coupled to the substrate, wherein the first chip and the conductive frame have a height that is substantially the same, wherein an exposed substrate surface is covered in a layer of encapsulation material having the same height; a second chip positioned on a first portion the first chip surface in such a way to expose at least a portion of the first chip surface, wherein the at least one exposed portion includes thermal VIAs; and at least one conductive plate positioned on the at least one exposed portion, wherein the conductive plate is coupled to the conductive frame and the thermal VIAs of the first chip. | 2022-03-10 |
20220077114 | STACK PACKAGES INCLUDING PASSIVE DEVICES - A stack package includes a package substrate; a lower stack including lower dies stacked on the package substrate to form a zigzag shape in a vertical direction; an upper stack including upper dies that are sequentially offset stacked in an offset direction while providing a first upper side of a down staircase shape, a first end of an uppermost upper die among the upper dies protruding, in a horizontal direction, further than a first lower side of the lower stack; and a first passive device disposed on the package substrate and spaced apart from the first lower side, and disposed between a first portion of the package substrate and the first upper side. | 2022-03-10 |
20220077115 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels. | 2022-03-10 |
20220077116 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures. | 2022-03-10 |
20220077117 | System Formed Through Package-In-Package Formation - A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package. | 2022-03-10 |
20220077118 | SEMICONDUCTOR DEVICE WITH CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a method for fabricating a semiconductor device with a connection structure. The method includes providing a first semiconductor structure comprising a plurality of first conductive features adjacent to a top surface of the first semiconductor structure; forming a connection structure comprising a connection insulating layer on the top surface of the first semiconductor structure, a connection layer in the connection insulating layer, and a plurality of first porous interlayers on the plurality of first conductive features and in the connection insulating layer; and forming a second semiconductor structure comprising a plurality of second conductive features on the plurality of first porous interlayers | 2022-03-10 |
20220077119 | SEMICONDUCTOR POWER MODULE - A semiconductor power module including first and second power transistors situated in parallel between first collector and first emitter strip conductors. A first connection surface of each of the power transistors is electroconductively connected to the first collector strip conductor, and a second connection surface of each of the power transistors is electroconductively connected to the first emitter strip conductor, so that a current flowing between the first collector strip conductor and the first emitter strip conductor is divided between the power transistors when the power transistors are each conductively connected via an applied control voltage. A first external power contact is directly contacted with the first collector strip conductor at a first contact area, a second external power contact is contacted with the first emitter strip conductor at a second contact area via a first connecting element, and the second contact area is positioned asymmetrically between the power transistors. | 2022-03-10 |
20220077120 | MICRO-LIGHT-EMITTING DIODE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a micro-light-emitting diode display apparatus and a method of manufacturing the same. Provided is a micro-light-emitting diode (LED) display apparatus including a plurality of pixels, the micro-LED display apparatus including a driving circuit substrate, a first electrode provided on the driving circuit substrate, one or more micro-light-emitting diodes (LEDs) provided on the first electrode, an insulating layer provided on the one or more micro-LEDs, a via pattern provided in the insulating layer, electrical contacts provided in the via pattern, and a second electrode provided on the electrical contacts, wherein the via pattern exposes a portion of the one or more micro-LEDs. | 2022-03-10 |
20220077121 | DISPLAY DEVICE - A display device includes a base layer including a display area, a first pixel, a second pixel, and a third pixel disposed in the display area and including light-emitting elements disposed in light-emitting areas, a first light conversion layer, a second light conversion layer, and a third light conversion layer on the light-emitting areas of the first pixel, the second pixel, and the third pixel, respectively, a light blocking layer between the first, second and third light conversion layers, and having a height lower than the first, second, and third light conversion layers, the light blocking layer surrounding a portion of side surfaces of the first, second and third light conversion layers, and a first reflective layer disposed on the light blocking layer and surrounding the first, second and third light conversion layers. | 2022-03-10 |
20220077122 | METHOD FOR MANUFACTURING DISPLAY DEVICE AND SUBSTRATE FOR MANUFACTURING DISPLAY DEVICE - Discussed is an assembly substrate used for a display device manufacturing method of mounting semiconductor light-emitting diodes on the assembly substrate at preset positions using electric field and magnetic field. The assembly substrate includes a base portion, a plurality of assembly electrodes on the base portion, a dielectric layer on the base portion to cover the assembly electrodes, a barrier wall on the base portion, and a metal shielding layer on the base portion, wherein the metal shielding layer overlaps the barrier wall. | 2022-03-10 |
20220077123 | Chip Package Structure and Chip Packaging Method - A chip package structure includes a first chip, a second chip, and a carrier board. The first chip is disposed between the second chip and the carrier board. An active layer of the first chip is opposite to an active layer of the second chip. A first interconnection structure is disposed between the first chip and the second chip and is configured to couple the active layer of the first chip to the active layer of the second chip. A first conductor pillar is disposed in the first chip. One end of the first conductor pillar is coupled to the active layer of the first chip, and the other end of the first conductor passes through the first chip to be coupled to a circuit in the carrier board. | 2022-03-10 |
20220077124 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a main surface, a plurality of first wirings, each having a first embedded part embedded in the substrate and exposed from the main surface, and a mounted part which is in contact with the main surface and is connected to the first embedded part, a semiconductor element having an element rear surface and a plurality of electrodes bonded to the mounted parts, a plurality of second wirings, each having a second embedded part embedded in the substrate and exposed from the main surface and a columnar part protruding from the second embedded part in the thickness direction, and being located outward from the semiconductor element as viewed in the thickness direction; and a passive element located on the side facing the main surface in the thickness direction more than the semiconductor element, and electrically connected to the plurality of second wirings. | 2022-03-10 |
20220077125 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a substrate, a data conductive layer on the substrate and including a first voltage line, a via layer on the data conductive layer, a light emitting element on the via layer, a first contact electrode on the light emitting element and contacting a first end of the light emitting element, and a second contact electrode on the light emitting element and contacting a second end of the light emitting element, wherein the second contact electrode is electrically connected to the first voltage line through a first contact hole penetrating the via layer. | 2022-03-10 |
20220077126 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device may include a cell wafer including a source plate, a plurality of first word lines stacked to be spaced apart from one another along a plurality of first vertical channels projecting from a bottom surface of the source plate in a vertical direction, and a plurality of second word lines stacked to be spaced apart from one another along a plurality of second vertical channels projecting from a top surface of the source plate in a vertical direction; a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first row decoder unit which transfers an operating voltage to the plurality of first word lines; and a second peripheral wafer bonded to a top surface of the cell wafer, and including a second row decoder unit which transfers an operating voltage to the plurality of second word lines. | 2022-03-10 |
20220077127 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes: a second semiconductor chip including a second through electrode that penetrates a second body portion and a second connection electrode that is connected to one end of the second through electrode; a first semiconductor chip stack disposed over the second semiconductor chip and including a plurality of first semiconductor chips, each of the plurality of first semiconductor chips includes a first through electrode and a first connection electrode connected to one end of the first through electrode; a molding layer; a third semiconductor chip disposed over the molding layer and the first semiconductor chip stack; and an external connection electrode electrically connected to an other end of the second through electrode, wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes. | 2022-03-10 |
20220077128 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface. | 2022-03-10 |
20220077129 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - Disclosed are three-dimensional semiconductor memory devices and electronic systems including the same. The three-dimensional semiconductor memory device comprises a first structure and a second structure in contact with the first structure. Each of the first and second structures includes a substrate, a peripheral circuit region on the substrate, and a cell array region including a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures. The stack structure is between the peripheral circuit region and the common source region. The common source regions of the first and second structures are connected with each other. | 2022-03-10 |
20220077130 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, first and second bumps on a lower surface of the package substrate, a semiconductor chip on an upper surface of the package substrate, first and second connection patterns on the upper surface of the package substrate, a molding on the upper surface of the package substrate and covering the semiconductor chip, a warpage control layer on the molding, an upper insulating layer on the warpage control layer, a first opening passing through the upper insulating layer and exposing an upper surface of the warpage control layer, a second opening overlapping the first opening in a top view, the second opening passing through the warpage control layer and exposing the first connection pattern, and a third opening passing through the upper insulating layer and exposing the second connection pattern. | 2022-03-10 |
20220077131 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; and a first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer. | 2022-03-10 |
20220077132 | SYSTEM-LEVEL PACKAGING STRUCTURE AND METHOD FOR LED CHIP - The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system. | 2022-03-10 |
20220077133 | SEMICONDUCTOR DEVICE, CAPACITOR DEVICE AND MANUFACTURE METHOD OF CAPACITOR DEVICE - The present disclosure provides a semiconductor device, and a capacitor device and its manufacture method, and relates to the field of semiconductor technologies. The manufacture method includes: forming, on a substrate, a plurality of storage node contact plugs distributed in an array and an insulation layer separating each of the storage node contact plugs; forming an electrode supporting structure on a side of the insulation layer away from the substrate, the electrode supporting structure having a plurality of through holes exposing each of the storage node contact plugs respectively, the through hole comprising a plurality of hole segments end-to-end jointing successively, the hole segment located on a side close to the substrate having an aperture greater than the hole segment located on a side away from the substrate; forming a dielectric layer; forming a second electrode layer. | 2022-03-10 |
20220077134 | Cell Architecture - Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break. | 2022-03-10 |
20220077135 | SEMICONDUCTOR DEVICE - A semiconductor device includes first, second, third, and fourth active regions provided in an substrate, each of which includes a central portion, first and second portions provided at opposite sides of the central portion in a first direction, and third and fourth portions provided at opposite sides of the central portion in a second direction orthogonal to the first direction. An end portion of the first portion of the first active region faces a side portion of the fourth portion of the fourth active region, an end portion of which faces aside portion of the second portion of the second active region. An end portion of the second portion of the second active region faces a side portion of the third portion of the third active region, an end portion of which faces a side portion of the first portion of the first active region. | 2022-03-10 |
20220077136 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH STRENGTHENED PATTERNS - The disclosure provides a method for fabricating a semiconductor structure with strengthened patterns. The method includes forming a masking layer on the substrate, the masking layer including a peripheral region and an array region adjacent to the peripheral region; forming a first etched peripheral pattern in the peripheral region and a first etched array pattern in the array region, wherein the first etched peripheral pattern and the first etched array pattern have a top surface, a sidewall and a bottom surface, the sidewall connecting the top surface to the bottom surface; forming a second peripheral pattern on the first etched peripheral pattern and forming a second array pattern on the first etched array pattern; and etching the masking layer using the first etched peripheral pattern and the second peripheral pattern as an etching mask to form an etched masking layer in the peripheral region. | 2022-03-10 |
20220077137 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pad portion, a protection circuit, N wiring layers, and conductive vias connecting adjacent wiring layers, wherein, in a plan view, the semiconductor device includes a first area, a second area, and a third area, wherein the N wiring layers are provided to extend over the first area, the second area, and the third area, wherein a first wiring layer on a side of the pad portion is connected to the pad portion in the first area, and wherein an N-th wiring layer on a side of the protection circuit is connected to the protection circuit in the second area, and in the second area and the third area, where a total cross-sectional area of i-th conductive vias connecting an i-th wiring layer and an (i+1)-th wiring layer is denoted as S | 2022-03-10 |
20220077138 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first wiring; a first circuit region provided with a first power supply wiring and a first ground wiring; a second circuit region provided with a second power supply wiring and a second ground wiring; and a bidirectional diode connected between the first and second ground wirings, and provided with first and second diodes. The first diode includes a first impurity region of a first conductive type, connected to the second ground wiring, and a second impurity region of a second conductive type, connected to the first ground wiring. The second diode includes a third impurity region of the second conductive type connected to the second ground wiring, and a fourth impurity region of the first conductive type connected to the first ground wiring. Any of the first to fourth impurity regions, or any combination of the impurity regions is connected to the first wiring. | 2022-03-10 |
20220077139 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device including a substrate, a first PNP element, a second PNP element, and an isolation region is provided. The substrate has a P-type conductivity. The first and second PNP elements are formed in the substrate. The isolation region isolates the first and second PNP elements. | 2022-03-10 |
20220077140 | INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS - Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway. | 2022-03-10 |
20220077141 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate. | 2022-03-10 |
20220077142 | Method of Packaging a Rectifying Device and a Rectifying Device - A rectifying device includes a semiconductor die having first and second opposing surfaces and a first terminal and a second terminal. A power transistor has a source terminal connected to one of the first terminal or the second terminal of the rectifying device. A drain terminal is connected to the other one of the first terminal or the second terminal of the rectifying device and a gate. A gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal. A capacitor structure is provided wherein the power transistor, the gate control circuit and the capacitor structure are arranged in the semiconductor die forming a monolithic structure and the first and second opposing surfaces are at least in part metallised. | 2022-03-10 |
20220077143 | INTEGRATED CIRCUIT DEVICE INCLUDING METAL-OXIDE SEMICONDUCTOR TRANSISTORS - An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region. | 2022-03-10 |
20220077144 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate and concurrently forming a first semiconductor unit, a second semiconductor unit, and a third semiconductor unit in the substrate. The first semiconductor unit has a first insulating stack, the second semiconductor unit has a second insulating stack, and the third semiconductor unit has a third insulating stack; and thicknesses of the first insulating stack, the second insulating stack, and the third insulating stack are all different. | 2022-03-10 |
20220077145 | UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ORTHOGONAL WALLS - Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins. | 2022-03-10 |
20220077146 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND MEMORY, AND SEMICONDUCTOR STRUCTURE - The embodiments of the present application relate to the field of semiconductor technologies, and disclose a semiconductor structure manufacturing method. The method includes: forming a hard mask on a semiconductor substrate; forming a photoresist film on the hard mask; patterning the photoresist film to form a patterned photoresist layer having first openings and second openings, wherein the second openings are disposed at intervals between the first openings; etching the hard mask by taking the patterned photoresist layer as a mask to form a patterned hard mask layer having a plurality of third openings, wherein the third openings correspond to the first openings and the second openings; and etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form holes along the third openings. According to this method, the manufacturing efficiency and the quality of the holes are improved simultaneously. | 2022-03-10 |
20220077147 | SEMICONDUCTOR STRUCTURE WITH BURIED POWER LINE AND BURIED SIGNAL LINE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer. | 2022-03-10 |
20220077148 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH BURIED POWER LINE AND BURIED SIGNAL LINE - The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer. | 2022-03-10 |
20220077149 | Memory Cells, Arrays of Two Transistor-One Capacitor Memory Cells, Methods of Forming an Array of Two Transistor-One Capacitor Memory Cells, and Methods Used in Fabricating Integrated Circuitry - A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods. | 2022-03-10 |
20220077150 | BOTTOM ELECTRODE CONTACT FOR A VERTICAL THREE-DIMENSIONAL MEMORY - Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region. | 2022-03-10 |
20220077151 | MEMORY DEVICE - A memory cell comprising a substrate, a bit line vertically oriented from the substrate along a first direction, a nanosheet transistor including at least one nanosheet horizontally oriented from the bit line along a second direction perpendicular to the first direction, and a capacitor horizontally oriented from the nanosheet transistor along the second direction. | 2022-03-10 |
20220077152 | SEMICONDUCTOR DEVICES - A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall. | 2022-03-10 |
20220077153 | SEMICONDUCTOR DEVICE WITH CAPACITOR CONTACT SURROUNDED BY CONDUCTIVE RING AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring. | 2022-03-10 |
20220077154 | SEMICONDUCTOR DEVICES HAVING BURIED GATES - A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer. | 2022-03-10 |
20220077155 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH TAPERING IMPURITY REGION - The present application discloses a method for fabricating a semiconductor device with a tapering impurity region. The method includes providing a substrate; forming a word line structure in the substrate; performing an isotropicetch process to form a first recess in the substrate, wherein the first recess comprises tapering sidewalls; performing an anisotropic etch process to expand the first recess and form a second recess below the first recess; and forming an impurity region in the first recess and in the second recess and adjacent to the word line structure. | 2022-03-10 |
20220077156 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - The disclosure relates to a highly integrated memory device and a method for manufacturing the same. According to the disclosure, a memory device comprises a lower structure, an active layer horizontally oriented parallel to a surface of the lower structure, a bit line connected to a first end of the active layer and vertically oriented from the surface of the lower structure, a capacitor connected to a second end of the active layer, a word line horizontally oriented to be parallel with the active layer along a side surface of the active layer, and a fin channel layer horizontally extending from one side surface of the active layer, wherein the word line includes a protrusion covering the fin channel layer. | 2022-03-10 |
20220077157 | METHOD FOR FORMING CAPACITOR HOLES - A method for forming capacitor holes is provided. By forming a first material layer and a second material layer which are thinner and are different in materials on a supporting layer as an over-etching depth adjusting layer, when etching holes are formed in a hard mask layer and the hard mask layer is over-etched, a certain over-etching depth may be formed in the second material layer, and the etching holes terminate in the first material layer, so that the etching depth of the etching holes can be corrected and adjusted. Accordingly, the etching holes formed after the hard mask layer is over-etched can have the same depth or have a small depth difference. Therefore, time points at which the plurality of capacitors holes formed expose the corresponding connecting pads are substantially the same or differ very little, improving the performance of the DRAM. | 2022-03-10 |
20220077158 | SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD AND CONTROL METHOD THEREOF - A semiconductor structure includes: a base substrate; an insulator, located on one side of the base substrate; bit lines, arranged in the insulator, the bit lines being distributed at intervals along first direction and extending along second direction; active bodies, located in the insulator, the active bodies being located on sides of respective bit lines facing away from the base substrate, orthographic projection of each active body on the base substrate at least partially coinciding with the orthographic projection of a respective bit line on the base substrate, and the active bodies being distributed at intervals along second direction; and word lines, located in the insulator and located on sides of respective bit lines facing away from the base substrate, the word lines being distributed at intervals along second direction and extending along first direction, and only one word line being arranged between two adjacent active bodies in second direction. | 2022-03-10 |
20220077159 | MEMORY AND METHOD FOR FORMING MEMORY - Embodiments of the present application provide a memory and a method for forming the memory. The method includes: providing a substrate, and forming a bit line structure on the substrate and a first protective layer; forming a dielectric layer with which a gap between the adjacent bit line structures is filled; forming a second protective layer to cover a top surface of the first protective layer and a top surface of the dielectric layer; removing part of the dielectric layer and part of the second protective layer to form a capacitor contact hole, and exposing the first protective layer between two adjacent ones of the capacitor contact holes; forming a conductive layer with which the capacitor contact hole is filled and the top surface of the exposed first protective layer is covered, and etching part of the conductive layer to form a separate capacitor contact structure. | 2022-03-10 |
20220077160 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The disclosure provides a method for manufacturing a semiconductor device. The method includes the following operations. A substrate on which an active region and a shallow trench isolation structure are formed, is provided. A first isolation layer is formed in the active region by an ion-doping technique. The active region surrounded by the first isolation layer is ion-implanted to form a first wordline structure. A second wordline structure is formed in the shallow trench isolation structure, and the first wordline structure and the second wordline structure are connected to form a buried wordline structure extending along a surface of the substrate. | 2022-03-10 |
20220077161 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a plurality of memory cell groups and a plurality of sense amplification unit groups, and at least two memory cell groups share a same sense amplification unit group. | 2022-03-10 |
20220077162 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor. | 2022-03-10 |
20220077163 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer. | 2022-03-10 |
20220077164 | VARIABLE LOW RESISTANCE LINE NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING SAME - A variable low-resistance line memory device and an operating method thereof are provided. The memory device includes: a base including a spontaneous polarizable material; a gate arranged adjacent to the base; at least two polarization regions formed in the base by applying an electric field to the base through the gate, the at least two polarization regions having polarization in different directions from each other; a variable low-resistance line corresponding to a boundary between the at least two polarization regions selectively having polarization in different directions from each other; a source located to contact the variable low-resistance line; and a drain located to contact the variable low-resistance line, wherein the variable low-resistance line is formed in a region of the base, the region having a lower electrical resistance than other regions of the base adjacent to the variable low-resistance line. | 2022-03-10 |
20220077165 | INTEGRATION METHOD FOR MEMORY CELL - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode. | 2022-03-10 |
20220077166 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate. | 2022-03-10 |
20220077167 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers. | 2022-03-10 |
20220077168 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described. | 2022-03-10 |
20220077169 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed. | 2022-03-10 |
20220077170 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region. | 2022-03-10 |
20220077171 | THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME - Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers, a plurality of channel structures extending in the memory stack, and a source structure extending in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. Two adjacent source contacts are conductively connected to one another by a connection layer, the connection layer includes a pair of first portions being over the two adjacent ones of the plurality of source contacts and a second portion between the pair of first portions. A support structure is between the two adjacent source contacts. The support structure includes a cut structure over interleaved a plurality of conductor portions and a plurality of insulating portions. | 2022-03-10 |
20220077172 | MEMORY DEVICE INCLUDING ROW DECODER - A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers. | 2022-03-10 |
20220077173 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a plurality of first conductive layers disposed in a first direction; a structure that includes a first semiconductor layer extending in the first direction and being opposed to the plurality of first conductive layers, agate insulating layer being disposed between the first semiconductor layer and the plurality of first conductive layers, and a second semiconductor layer being contact to one end portion of the first semiconductor layer; a contact connected to the second semiconductor layer; an insulating portion that separates a part of the plurality of first conductive layers in a second direction and is in contact with the structure and the contact from one side in the second direction; and a first insulating layer in contact with the contact from the other side in the second direction. The insulating portion includes an insulating material different from a material of the first insulating layer. | 2022-03-10 |
20220077174 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a conductive layer and a second conductive layer that are arranged in a first direction; a plurality of first semiconductor layers facing the first conductive layer between the first conductive layer and the second conductive layer, the plurality of first semiconductor layers being arranged in a second direction that intersects the first direction; a first charge storage layer that is provided between the plurality of first semiconductor layers and the first conductive layer in the first direction, and extends in the second direction over a plurality of regions between the plurality of first semiconductor layers and the first conductive layer; and a first insulating layer provided between the plurality of first semiconductor layers and the first charge storage layer in the first direction. The first insulating layer includes a first region that faces one end of each of the first semiconductor layers in the second direction, in the first direction, a second region that faces the other end of each of the first semiconductor layers in the second direction, in the first direction, and a third region provided between the first region and the second region in the second direction. A nitrogen concentration in the first region and the second region is lower than a nitrogen concentration in the third region. | 2022-03-10 |
20220077175 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line. | 2022-03-10 |
20220077176 | ELECTRONIC DEVICES COMPRISING ADJOINING OXIDE MATERIALS AND RELATED METHODS AND SYSTEMS - An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems. | 2022-03-10 |
20220077177 | MICROELECTRONIC DEVICES WITH TIERED DECKS OF DIFFERING PILLAR DENSITY AND RELATED METHODS AND SYSTEMS - Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed. | 2022-03-10 |
20220077178 | MICROELECTRONIC DEVICES WITH TIERED BLOCKS SEPARATED BY PROGRESSIVELY SPACED SLITS, AND RELATED METHODS AND SYSTEMS - Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and devices the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending the through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed. | 2022-03-10 |
20220077179 | THREE-DIMENSIONAL MEMORY DEVICE - A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrO | 2022-03-10 |
20220077180 | THREE-DIMENSIONAL MEMORY DEVICES HAVING DUMMY CHANNEL STRUCTURES AND METHODS FOR FORMING THE SAME - Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer. | 2022-03-10 |
20220077181 | THREE-DIMENSIONAL MEMORY DEVICES HAVING ISOLATION STRUCTURE FOR SOURCE SELECT GATE LINE AND METHODS FOR FORMING THE SAME - Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure. | 2022-03-10 |
20220077182 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack including interlayer insulating layers and word lines alternately stacked in a first direction, channel pillars passing through the gate stack and tapering toward the first direction, source select lines surrounding the channel pillars and extending to overlap the gate stack, and a source isolation insulating layer overlapping the gate stack between the source select lines and tapering toward a direction opposite to the first direction. | 2022-03-10 |
20220077183 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a semiconductor device includes a substrate, and a plurality of electrode layers provided separately from each other in a first direction perpendicular to a surface of the substrate. The device further includes a first insulator, a charge storage layer, a second insulator, a first semiconductor region including silicon, and a second semiconductor region including silicon and carbon, which are provided in order on side faces of the electrode layers, wherein an interface between the first semiconductor region and the second insulator includes fluorine. | 2022-03-10 |
20220077184 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to one embodiment includes a substrate, a wiring layer provided on the substrate and including source lines, a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked on the wiring layer, a cell film provided in the stacked body, a semiconductor film facing the cell film in the stacked body, and a diffusion film being in contact with the source lines in the wiring layer and being in contact with the semiconductor film in the stacked body. The diffusion film includes impurities and a top end portion of the diffusion film is at a higher position than a lowermost conductive layer among the conductive layers. | 2022-03-10 |
20220077185 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a stacked body including a plurality of conductive layers and a plurality of first insulation layers alternately stacked in a first direction. The conductive layers each include a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that is chemically reactive with a material gas containing the first metal element. The second metal layer contains the first metal element and has a lower content of the substance than the first metal layer. The first metal layer is disposed between the first insulation layers and the second metal layer. | 2022-03-10 |
20220077186 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed. | 2022-03-10 |
20220077187 | METHOD FOR FABRICATING MEMORY DEVICE - A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer. | 2022-03-10 |
20220077188 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A semiconductor device includes one or more units of strings of cells, and dielectric structures extending in a vertical direction and a first direction perpendicular to the vertical direction and separating adjacent units of strings of cells. Each unit of strings of cells includes a first string of cells each including first cells, and a second string of cells each including second cells. | 2022-03-10 |
20220077189 | Method for in situ Preparation of Antimony-doped Silicon and Silicon Germanium films - A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane. | 2022-03-10 |
20220077190 | SEMICONDUCTOR DEVICE AND APPARATUS OF MANUFACTURING THE SAME - A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region. | 2022-03-10 |
20220077191 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE - To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other. | 2022-03-10 |
20220077192 | SELF-LUMINOUS DISPLAY PANEL - A self-luminous display panel is provided. The self-luminous display panel includes a power supply film layer. The power supply film layer is divided into a plurality of mutually insulated power supply blocks, and each power supply block is electrically connected to a plurality of pixel circuits located in the power supply block. A high grayscale display is independently provided for the corresponding pixel circuits by dividing the power supply film into power supply blocks, thereby easily achieving the partition display of the self-luminous display panel. | 2022-03-10 |
20220077193 | DISPLAY MODULE AND MOBILE TERMINAL - A display device comprises: a display panel including a display area in which TFT wiring is formed and a non-display area in which the TFT wiring is omitted; a touch panel including touch wiring and positioned on the front surface of the display panel; bypass wiring formed in a portion corresponding to the non-display area on the touch panel; and a via of which one end is connected to the end of the TFT wiring, and of which the other end is connected to the bypass wiring, the via being formed in the thickness direction on the display panel and the touch panel, wherein the size of the non-display area in which an optical device is disposed on a display unit can be reduced. | 2022-03-10 |
20220077194 | DISPLAY PANEL - A display panel includes: a first gate line extending in a first direction; a second gate line extending in the first direction and spaced apart from the first gate line in a second direction crossing the first direction; a first connection line extending in the second direction; and a second connection line extending in the second direction and spaced apart from the first connection line in the first direction, wherein a distal end of the first connection line overlaps the first gate line and is electrically connected to the first gate line, and wherein a distal end of the second connection line overlaps the second gate line and is electrically connected to the second gate line. | 2022-03-10 |
20220077195 | DISPLAY DEVICE AND TILED DISPLAY DEVICE INCLUDING THE SAME - A display device includes a display layer comprising pixels, each of the pixels having at least one thin-film transistor, a connection line electrically connected to the at least one thin-film transistor, the connection line being exposed on a lower surface of the display layer through a first contact hole formed in the display layer, a barrier layer disposed on the lower surface of the display layer and including a second contact hole connected to the first contact hole, a lead line disposed on a lower surface of the barrier layer and electrically connected to the connection line through the second contact hole, a pad part disposed on the lower surface of the barrier layer and electrically connected to the lead line, and a lower film overlapping the lower surface of the barrier layer and the lead line. | 2022-03-10 |