| 10th week of 2022 patent applcation highlights part 60 |
| Patent application number | Title | Published |
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| 20220076994 | SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING SAME, AND STORAGE APPARATUS - A method for preparing method semiconductor device includes: providing a wafer on which a semiconductor structure is formed; forming a stacked film layer structure on a side of the semiconductor structure away from the wafer, a film layer in the stacked film layer structure farthest from the semiconductor structure being a first film layer; reducing a thickness of the first film layer so that the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates at an edge of the wafer is less than the thickness of the first film layer at where orthographic projection of the first film layer on the wafer locates in middle of the wafer; and patterning the stacked film layer structure to form through holes which communicate to the semiconductor structure. | 2022-03-10 |
| 20220076995 | INTEGRATED CIRCUITS WITH LINE BREAKS AND LINE BRIDGES WITHIN A SINGLE INTERCONNECT LEVEL - Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines. | 2022-03-10 |
| 20220076996 | METHODS FOR DEPOSITING GAP FILING FLUIDS AND RELATED SYSTEMS AND DEVICES - Methods and systems for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses. The recesses are at least partially filled with a gap filling fluid. The gap filling fluid comprises boron, nitrogen, and hydrogen. | 2022-03-10 |
| 20220076997 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method of the semiconductor device are provided. The semiconductor device includes a substrate, a source-drain plug layer in the substrate, a gate structure in the substrate, and a dielectric layer disposed over the substrate and covering the gate structure and the source-drain plug layer. The dielectric layer contains a first through-hole having a bottom exposing a top surface of the source-drain plug layer, and a second through-hole having a bottom exposing a top surface of the gate structure. Further, the semiconductor device includes an interface layer disposed on each of the top surface of the source-drain plug layer exposed by the first through-hole and the top surface of the gate structure exposed by the second through-hole. | 2022-03-10 |
| 20220076998 | SEMICONDUCTOR DEVICE HAVING A LANDING PAD WITH SPACERS - The present application discloses a semiconductor device having a landing pad with spacers. The semiconductor device includes a first insulating layer, a second insulating layer, a conductive pillar and spacers. The first insulating layer is disposed on a substrate. The second insulating layer is disposed on the first insulating layer. The conductive pillars are disposed in the first insulating layer and penetrates through the second insulating layer. The spacers are disposed on sidewalls of the conductive pillars. | 2022-03-10 |
| 20220076999 | METHOD OF PROCESSING WAFER - A method of processing a wafer includes a groove forming step of forming grooves in the wafer to a depth equal to or larger than a thickness of chips to be produced from the wafer from a face side of the wafer along projected dicing lines, a separation initiating point forming step of positioning a focused spot of a laser beam having a wavelength transmittable through the wafer, at a depth in the wafer corresponding to a thickness of the chips from a reverse side of the wafer that is opposite the face side thereof, applying the laser beam to the wafer while moving the focused spot and the wafer relatively to each other, thereby forming separation initiating points in the wafer that are parallel to the face side of the wafer and made up of modified layers and cracks extending from the modified layers in the wafer, and a chip peeling step of peeling off the chips from the wafer at the separation initiating points. | 2022-03-10 |
| 20220077000 | Assemblies Containing PMOS Decks Vertically-Integrated with NMOS Decks, and Methods of Forming Integrated Assemblies - Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers. | 2022-03-10 |
| 20220077001 | PROFILE CONTROL OF A GAP FILL STRUCTURE - The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure. | 2022-03-10 |
| 20220077002 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a bit line contact hole in a substrate; forming a first spacer on a sidewall of the bit line contact hole; forming a sacrificial spacer over the first spacer; forming a first conductive material that fills the bit line contact hole over the sacrificial spacer; forming a second conductive material over the first conductive material; forming a bit line by etching the second conductive material; and forming a bit line contact plug and a gap between the bit line contact plug and the first spacer by partially etching the first conductive material and the sacrificial spacer to be aligned with the bit line. | 2022-03-10 |
| 20220077003 | METHOD FOR FABRICATING A 3D SEMICONDUCTOR APPARATUS HAVING TWO VERTICALLY DISPOSED SEMINCONDUCTOR DEVICES - Aspects of the present disclosure provide a method for fabricating a 3D semiconductor apparatus. The method can include forming a multilayer stack including a plurality of dielectric layers. The dielectric layers can include three or four dielectric materials that can be etched selectively with respect to one another. The method can also include forming opening(s) in the multilayer stack, and filling the opening(s) with first and second channel materials to form first and second channels that interface at a transition dielectric layer the multilayer stack. The method can also include removing second and first source/drain (S/D) dielectric layers of the multilayer stack and replacing with second and first S/D materials to form second and first S/D regions, respectively. The method can also include removing gate dielectric layers of the multilayer stack and replacing with a gate material to form gate regions of the 3D semiconductor apparatus. | 2022-03-10 |
| 20220077004 | SEMICONDUCTOR DEVICE MEASUREMENT METHOD - The present disclosure relates to a semiconductor device measure method, which can reduce measurement errors during the critical dimension measurement of a semiconductor device. The semiconductor device measurement method for using an OCD ellipsometer to measure critical dimensions of a semiconductor device includes the following steps: obtaining at least two minimum repeating units on a surface of the semiconductor device according to surface morphological features of a standard product of the semiconductor device; performing critical dimension measurement on the at least two minimum repeating units to obtain critical dimension data of the at least two minimum repeating units; constructing, in the OCD ellipsometer, a measurement model for the semiconductor device according to the critical dimension data of the at least two minimum repeating units; and performing critical dimension measurement on the semiconductor device by using the measure model. | 2022-03-10 |
| 20220077005 | DATA ANALYSIS METHOD AND ELECTRONIC DEVICE, AND STORAGE MEDIUM - A data analysis method includes: a target yield problem stacked graph corresponding to a wafer list is obtained, and measurement data stacked graphs of the wafer list under different types of tests are obtained; graph matching is performed on the target yield problem stacked graph and each of the measurement data stacked graphs to obtain matching degree data corresponding to the target yield problem stacked graph and each of the measurement data stacked graphs; correlation data corresponding to each of the measurement data stacked graphs and the target yield problem stacked graph is calculated; and weighted calculation is performed on the matching degree data and the correlation data, and a target measurement parameter causing a target yield problem is determined according to a result of the weighted calculation. | 2022-03-10 |
| 20220077006 | ENDPOINT DETECTION FOR CHEMICAL MECHANICAL POLISHING BASED ON SPECTROMETRY - A method of detecting a polishing endpoint includes storing a plurality of library spectra, measuring a sequence of spectra from the substrate in-situ during polishing, and for each measured spectrum of the sequence of spectra, finding a best matching library spectrum from the plurality of library spectra to generate a sequence of best matching library spectra. Each library spectrum has a stored associated value representing a degree of progress through a polishing process, and the stored associated value for the best matching library spectrum is determined for each best matching library spectrum to generate a sequence of values representing a progression of polishing of the substrate. The sequence of values is compared to a target value, and a polishing endpoint is triggered when the sequence of values reaches the target value. | 2022-03-10 |
| 20220077007 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns. | 2022-03-10 |
| 20220077008 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes multiple chip regions and a strip line for separating the chip regions. A test key is formed in the strip line and is used for a bit line contact (BLC) resistance test. The test key includes active regions and connecting structures. The active regions are formed in the semiconductor substrate. The connecting structures are located at ends of the active regions. The multiple active regions located on the same column are sequentially connected end to end by the connecting structures. | 2022-03-10 |
| 20220077009 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path. | 2022-03-10 |
| 20220077010 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element and resin. The semiconductor element includes a semiconductor part, first and second electrodes. The semiconductor part includes a back surface, a front surface at a side opposite to the back surface, and a side surface linking the back front surfaces. The semiconductor part includes a groove in the side surface. The groove surrounds the semiconductor part. The first electrode is provided on the back surface of the semiconductor part. The second electrode is provided on the front surface of the semiconductor part. The resin hermetically seals the semiconductor element. The resin includes a portion embedded in the groove. | 2022-03-10 |
| 20220077011 | PACKAGE, AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR MODULE - A first frame is supported by a heat sink plate, surrounds an unmounted region of the heat sink plate, contains a resin, and has a first surface. A second frame contains a resin, and has a second surface opposing the first surface. An external terminal electrode passes between the first surface and the second surface. An adhesive layer contains a resin, and includes a lower portion, an upper portion, and an intermediate portion. The lower portion connects the external terminal electrode and the first surface to each other. The upper portion connects the external terminal electrode and the second surface to each other. The intermediate portion is disposed within a through hole of the external terminal electrode, and connects the lower portion and the upper portion to each other. | 2022-03-10 |
| 20220077012 | ELECTRONIC ELEMENT MOUNTING SUBSTRATE AND ELECTRONIC DEVICE - An electronic element mounting substrate according to the present disclosure includes a base body having a recessed portion including a mounting region on which an electronic element is mounted and a cutout section located on an outer periphery of the base body in a plane perspective, and a channel having an inner end portion located on an inner wall of the base body and an outer end portion located on the outer periphery of the base body. The inner end portion of the channel is open to the recessed portion, and the outer end portion of the channel is continuous with the cutout section. | 2022-03-10 |
| 20220077013 | SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF - A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate. | 2022-03-10 |
| 20220077014 | PACKAGED DEVICE WITH DIE WRAPPED BY A SUBSTRATE - A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads. | 2022-03-10 |
| 20220077015 | RECONSTITUTED WAFER INCLUDING MOLD MATERIAL WITH RECESSED CONDUCTIVE FEATURE - A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A a surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die. | 2022-03-10 |
| 20220077016 | RECONSTITUTED WAFER INCLUDING INTEGRATED CIRCUIT DIE MECHANICALLY INTERLOCKED WITH MOLD MATERIAL - A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material. | 2022-03-10 |
| 20220077017 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE MANUFACTURING METHOD - A semiconductor module includes a semiconductor element made of a wide-bandgap semiconductor, the semiconductor element having an upper surface with an edge, a buffer member that covers the edge of the upper surface of the semiconductor element, and a sealing resin that seals the semiconductor element and the buffer member. The buffer member has a thickness equal to or larger than 50 μm. | 2022-03-10 |
| 20220077018 | CHIP PACKAGING APPARATUS AND PREPARATION METHOD THEREOF - A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip. | 2022-03-10 |
| 20220077019 | Semiconductor Device and Method of Forming Protective Layer Around Cavity of Semiconductor Die - A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant. | 2022-03-10 |
| 20220077020 | Compression-Loaded Printed Circuit Assembly For Solder Defect Mitigation - The present disclosure provides systems for applying a compression load on at least part of an application specific integrated circuit (“ASIC”) ball grid array (“BGA”) package during the rework or secondary reflow process. The compression-loading assembly may include a top plate and a compression plate. The compression plate may exert a compression load on at least part of the ASIC using one or more compression mechanisms. The compression mechanisms may each include a bolt and a spring. The bolt may releasably couple the top plate to the compression plate and allow for adjustments to the compression load. The spring may be positioned on the bolt between the top plate and the compression plate and, therefore, may exert a force in a direction away from the top plate and toward the compression plate. The compression load may retain the solder joint and may prevent the solder separation defect during the reflow process. | 2022-03-10 |
| 20220077021 | POWER ELECTRONICS SYSTEM - The disclosure relates to an electronic system including a plurality of adjacent, elementary power electronics modules and connected to one another by an electrical module connection. Each elementary module including at least one power component integrated on a printed circuit inserted between two electrically conductive heat sinks. The electrical module connection is made by heat sinks at the side and/or central connection surfaces thereof. | 2022-03-10 |
| 20220077022 | SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit substrate having a first metal layer on a first side, a second metal later on a second side, and an insulating layer between the first and second metal layers. A semiconductor chip is on the first side of the circuit substrate. A metal plate is on the second side. A solder layer is between the metal plate and the second metal layer. The second metal layer includes a protruding region which extends to a first thickness towards the metal plate, a first recessed region, and a second recessed region, each adjacent to the protruding region. The first recessed region extends to a second thickness that is less than the first thickness, and the second recessed region extends to a third thickness that is less than the first thickness. | 2022-03-10 |
| 20220077023 | TUNABLE STACK-UP DIMM FORM FACTOR COLD PLATE WITH EMBEDDED PELTIER DEVICES FOR ENHANCED COOLING CAPABILITY - An apparatus is described. The apparatus includes a metallic chamber having a first outer surface with first Peltier devices and a second outer surface with second Peltier devices. The first and second outer surfaces face in opposite directions such that the first Peltier devices are to cool first semiconductor chips that face the first outer surface and the second Peltier devices are to cool second semiconductor chips that face the second outer surface. | 2022-03-10 |
| 20220077024 | SEMICONDUCTOR DEVICE INCLUDING HEAT DISSIPATION STRUCTURE AND FABRICATING METHOD OF THE SAME - A semiconductor device includes a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface; and a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern. | 2022-03-10 |
| 20220077025 | SEMICONDUCTOR DEVICE WITH PROTECTION LAYERS AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a second mask layer positioned on the first mask layer, a conductive filler layer positioned penetrating the second mask layer, the first mask layer, and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die, between the conductive filler layer and the second die, and between the conductive filler layer and the first mask layer, and protection layers positioned between the conductive filler layer and the second mask layer and between the conductive filler layer and the first mask layer, and covering upper portions of the isolation layers. | 2022-03-10 |
| 20220077026 | Diode and semiconductor structure thereof - A diode, which is implemented in a semiconductor structure, includes a substrate, and first, second, third and fourth conductors. The substrate contains first and second doped regions. The first and second doped regions are used respectively as a first electrode and a second electrode of the diode. The first and third conductors are in a first conductor layer of the semiconductor structure and are connected to the first and second doped regions, respectively. The second and fourth conductors are in a second conductor layer of the semiconductor structure and are connected to the first and third conductors, respectively. In a side view of the semiconductor structure, an overlapping area between the first conductor and the third conductor is larger than an overlapping between of the second conductor and the fourth conductor. | 2022-03-10 |
| 20220077027 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface. | 2022-03-10 |
| 20220077028 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF LEAD FRAME - A lead frame includes: a die pad having a mounting surface for a semiconductor element; a recess included on the mounting surface; and a lead disposed around the die pad. The recess includes: a bottom surface positioned at a depth less than a thickness of the die pad from an opening plane of the recess; a plurality of protrusions protruding from the bottom surface; and a concavity recessed from the bottom surface. | 2022-03-10 |
| 20220077029 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed. | 2022-03-10 |
| 20220077030 | MULTI-LEAD ADAPTER - In some examples, a device comprises an electronic component having multiple electrical connectors, the multiple electrical connectors configured to couple to a printed circuit board (PCB) and having a first footprint. The device also comprises a multi-lead adapter comprising multiple rows of leads arranged in parallel, the leads in the rows configured to couple to the electrical connectors of the electronic component and having a second footprint that has a different size than the first footprint. | 2022-03-10 |
| 20220077031 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In one example, an electronic device includes a substrate with a conductive structure and a substrate encapsulant. The conductive structure has a lead with a lead via and a lead protrusion. The lead via can include via lateral sides defined by first concave portions and the lead protrusion can include protrusion lateral sides defined by second concave portions. The substrate encapsulant covers the first concave portions at a first side of the substrate but not the second concave portions so that the lead protrusion protrudes from the substrate encapsulant at a second side of the substrate. An electronic component can be adjacent to the first side of the substrate and electrically coupled to the conductive structure. A body encapsulant encapsulates portions of the electronic component and the substrate. In some examples, the lead can further include a lead trace at the second side of the substrate. In some examples, the substrate can include a redistribution structure at the first side of the substrate. Other examples and related methods are also disclosed herein. | 2022-03-10 |
| 20220077032 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements. | 2022-03-10 |
| 20220077033 | PACKAGE, AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR MODULE - An external terminal electrode is attached to a frame, and the frame contains a first resin, and has a first adhered surface. A heat sink plate supports the frame, has an unmounted region where a power semiconductor element is to be mounted within the frame in plan view, is made of metal, and has a second adhered surface. An adhesive layer contains a second resin different from the first resin, and adheres the first adhered surface of the frame and the second adhered surface of the heat sink plate to each other. One of the first and second adhered surfaces includes a flat portion and a protruding portion. The protruding portion protrudes from the flat portion and opposes the other one of the first adhered surface and the second adhered surface with the adhesive layer therebetween. | 2022-03-10 |
| 20220077034 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a first side surface located on one side of a first direction, a second side surface located on the other side of the first direction, and third and fourth side surfaces that are separated from each other in a second direction orthogonal to both a thickness direction and the first direction and are connected to the first and second side surfaces. A first gate mark having a surface roughness larger than the other regions of the third side surface is formed on the third side surface. When viewed along the second direction, the first gate mark overlaps a pad gap provided between the first die pad and the second die pad in the first direction. | 2022-03-10 |
| 20220077035 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a top surface, a bottom surface, and first to third side surfaces. The first terminals include a first edge terminal located closest to the third side surface. The second terminals include a second edge terminal located closest to the third side surface. A first creepage distance, which is a shortest distance from the first edge terminal to the second edge terminal along the first side surface, the third side surface, and the second side surface, is shorter than a second creepage distance, which is a shortest distance from the first edge terminal to the second edge terminal along the first side surface, the bottom surface, and the second side surface. | 2022-03-10 |
| 20220077036 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a top surface, a bottom surface, and a first side surface connected to the top surface and the bottom surface. The first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region, the plurality of first terminals being exposed to the third region. A surface roughness of each of the top surface, the bottom surface, the first region, and the second region is larger than a surface roughness of the third region. | 2022-03-10 |
| 20220077037 | SEMICONDUCTOR DEVICE - A semiconductor device includes a conductive support member, a first semiconductor element, and a second semiconductor element. The conductive support member includes a first die pad and a second die pad separated from each other in a first direction. The first die pad and the second die pad overlap each other when viewed along the first direction. The first die pad has a first main surface mounting the first semiconductor element, and a first back surface opposing the first main surface. The second die pad has a second main surface mounting the second semiconductor element, and a second back surface opposing the second main surface. When viewed along a second direction, a distance in the first direction between the first back surface and the second back surface is larger than a distance in the first direction between the first main surface and the second main surface. | 2022-03-10 |
| 20220077038 | LEADFRAME CAPACITORS - An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate. | 2022-03-10 |
| 20220077039 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region. | 2022-03-10 |
| 20220077040 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern. | 2022-03-10 |
| 20220077041 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer. | 2022-03-10 |
| 20220077042 | ELECTRONIC APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An electronic apparatus includes an integrated circuit board on, over, or in which a USB circuit block is provided; a first USB interface; a second USB interface; a printed circuit board on which a source clock circuit configured to output a source clock is provided; and a ball grid array that includes first, second, and third ball grids for electric coupling between the integrated circuit board and the printed circuit board. The first ball grid electrically couples the USB circuit block and the first USB interface to each other. The second ball grid electrically couples the USB circuit block and the second USB interface to each other. The third ball grid electrically couples the source clock circuit and the USB circuit block to each other. The third ball grid is located between the first ball grid and the second ball grid. | 2022-03-10 |
| 20220077043 | SEMICONDUCTOR PACKAGE - A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern. | 2022-03-10 |
| 20220077044 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring board that includes a first insulating layer, a first conductive layer arranged over the first insulating layer, a second conductive layer arranged under the first insulating layer, the wiring board further including a magnetic layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher specific magnetic permeability than the first and second conductive layers, and a carbon layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher thermal conductivity in a planary direction than the first and second conductive layers; a semiconductor chip electrically connected to the first and second conductive layers; and an insulating circuit board arranged separately from the wiring board and that has the semiconductor chip mounted thereon. | 2022-03-10 |
| 20220077045 | WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE - A wiring substrate includes a substrate, a first metal and a second metal. The substrate has a first surface, a second surface opposite the first surface, and a side surface connected to the first surface and the second surface. The first metal film is disposed so as to extend from the first surface to the side surface. The second metal film is disposed so as to extend from the second surface to the first metal film disposed on the side surface. | 2022-03-10 |
| 20220077046 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a first conductor layer, an insulating layer on the first layer such that the insulating layer is covering the first layer, a second conductor layer on the insulating layer such that the insulating layer is formed between the first and second layers, the connection conductors penetrating through the insulating layer and connecting the first and second layers, and a coating film formed at least partially on surface of the first layer such that the film improves adhesion between the first layer and insulating layer. The first layer includes pads and wiring patterns such that the pads are in contact with the connection conductors and that the patterns have surfaces facing the insulating layer and covered by the film, and the pads have roughened surfaces facing the insulating layer and having first surface roughness that is higher than second surface roughness of the surfaces of the patterns. | 2022-03-10 |
| 20220077047 | ORGANIC MOLD INTERCONNECTS IN SHIELDED INTERCONNECTS FRAMES FOR INTEGRATED-CIRCUIT PACKAGES - A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer. | 2022-03-10 |
| 20220077048 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns. | 2022-03-10 |
| 20220077049 | WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE - A wiring substrate includes: an insulating substrate being shaped in a quadrangle in a plan view, including a mounting portion where an electronic component is mounted on a side of a principal surface of the insulating substrate, and having a recess on a side surface thereof; an inner surface electrode which is located on an inner surface of the recess; a via conductor which is located on a corner side of the insulating substrate in a perspective plan view and has both ends located in a thickness direction of the insulating substrate; and a wiring conductor, on the side of the principal surface of the insulating substrate, connecting the mounting portion, the inner surface electrode, and the via conductor, wherein, in a perspective plan view, the wiring conductor has a wiring conductor absent region which surrounds a region located between the mounting portion and the via conductor. | 2022-03-10 |
| 20220077050 | ELECTRONIC APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An electronic apparatus includes an integrated circuit board; a printed circuit board electrically coupled to first and second external circuits; and a ball grid array that couples the integrated circuit board and the printed circuit board, includes a first group including pieces of first ball grid, and includes a second group including pieces of second ball grid. The first group couples the first circuit block and the first external circuit. The second group couples the second circuit block and the second external circuit. The number of the pieces of first ball grid is larger than the number of the pieces of second ball grid. The minimum distance between the first group and the first side is shorter than the minimum distance between the group and the first side and is shorter than the minimum distance between the second group and the second side. | 2022-03-10 |
| 20220077051 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure including a lead frame structure, a die, an adhesive layer, and at least one three-dimensional (3D) printing conductive wire is provided. The lead frame structure includes a carrier and a lead frame. The carrier has a recess. The lead frame is disposed on the carrier. The die is disposed in the recess. The die includes at least one pad. The adhesive layer is disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier. The 3D printing conductive wire is disposed on the lead frame, the adhesive layer, and the pad, and is electrically connected between the lead frame and the pad. | 2022-03-10 |
| 20220077052 | QFN SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE AND LEAD FRAME - A Quad Flat No-Lead (QFN) package comprises a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat. | 2022-03-10 |
| 20220077053 | INTEGRATED CIRCUIT PACKAGE STRUCTURE, INTEGRATED CIRCUIT PACKAGE UNIT AND ASSOCIATED PACKAGING METHOD - An IC package structure including an array of package units formed into a panel-shaped package units array. Each package unit has a continuous and closed metal wall surrounding the periphery of the package unit and at least one IC chip/IC die disposed in the package unit, and wherein each IC chip/IC die has a top surface and a back surface opposite to the top surface. A panel-shaped metal layer corresponding to the panel-shaped package units array can be formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing. | 2022-03-10 |
| 20220077054 | INTEGRATED CIRCUIT PACKAGE STRUCTURE, INTEGRATED CIRCUIT PACKAGE UNIT AND ASSOCIATED PACKAGING METHOD - An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads. | 2022-03-10 |
| 20220077055 | INTERNAL NODE JUMPER FOR MEMORY BIT CELLS - Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell. | 2022-03-10 |
| 20220077056 | SEMICONDUCTOR DEVICE WITH COMPOSITE PASSIVATION STRUCTURE AND METHOD FOR PREPARING THE SAME - A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern | 2022-03-10 |
| 20220077058 | SEMICONDUCTOR DEVICE HAVING INTER-METAL DIELECTRIC PATTERNS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view. | 2022-03-10 |
| 20220077059 | INTERCONNECT STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail. | 2022-03-10 |
| 20220077061 | SEMICONDUCTOR DEVICE WITH COMPOSITE LANDING PAD FOR METAL PLUG - The present disclosure relates to a semiconductor device with a composite landing pad. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed over the lower metal plug, and an outer silicide portion disposed over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion. | 2022-03-10 |
| 20220077062 | INTEGRATED CHIP HAVING A BURIED POWER RAIL - The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a gate structure overlying a front-side surface of a first substrate. The first substrate has a back-side surface opposite the front-side surface. A first source/drain structure overlies the first substrate and is laterally adjacent to the grate structure. A power rail is embedded in the first substrate and directly underlies the first source/drain structure. A first source/drain contact continuously extends from the first source/drain structure to the power rail. The first source/drain contact electrically couples the first source/drain structure to the power rail. | 2022-03-10 |
| 20220077063 | BONDED STRUCTURE WITH INTERCONNECT STRUCTURE - A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element. | 2022-03-10 |
| 20220077064 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package. | 2022-03-10 |
| 20220077065 | INTERPOSER FOR 2.5D PACKAGING ARCHITECTURE - A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer. | 2022-03-10 |
| 20220077066 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection. | 2022-03-10 |
| 20220077067 | Method for Producing A Component, and Component - In an embodiment a component includes a semiconductor chip, a connection member and a carrier, wherein the semiconductor chip is mechanically and electrically connected to the carrier via the connection member, wherein the connection member includes a contiguous metallic connecting layer and a plurality of metallic through-vias extending vertically through the connecting layer and being laterally spaced from the connecting layer by insulating regions, wherein the insulating regions are filled with a gaseous medium and are hermetically sealed, and wherein the gaseous medium contains an insulating gas having a higher breakdown field strength compared to nitrogen, or wherein a gas pressure is less than 1 mbar in the hermetically sealed insulating regions. | 2022-03-10 |
| 20220077068 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING VIA THROUGH BONDED WAFERS - A method of manufacturing a semiconductor structure includes steps of providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer over the second substrate, and a second conductive pad surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; forming a first opening extending through the second substrate and partially through the second dielectric layer; disposing a dielectric liner conformal to the first opening; forming a second opening extending through the second dielectric layer and the second conductive pad to at least partially expose the first conductive pad; and disposing a conductive material within the first opening and the second opening to form a conductive via over the first conductive pad. | 2022-03-10 |
| 20220077069 | PACKAGE COMPRISING AN INTEGRATED DEVICE COUPLED TO A SUBSTRATE THROUGH A CAVITY - A package that includes a substrate and an integrated device. The substrate includes a core portion, a first substrate portion and a second substrate portion. The core portion includes a core layer and core interconnects. The first substrate portion is coupled to the core portion. The first substrate portion includes at least one first dielectric layer coupled to the core layer, and a first plurality of interconnects located in the at least one first dielectric layer. The second substrate portion is coupled to the core portion. The second substrate includes at least one second dielectric layer coupled to the core layer, and a second plurality of interconnects located in the at least one second dielectric layer. The core portion and the second substrate portion include a cavity. The integrated device is coupled to the first substrate portion through the cavity of the second substrate portion and the core portion. | 2022-03-10 |
| 20220077070 | STACKED SEMICONDUCTOR PACKAGE WITH FLYOVER BRIDGE - According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate. | 2022-03-10 |
| 20220077071 | SEMICONDUCTOR DEVICE HAVING THROUGH SILICON VIAS - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween. | 2022-03-10 |
| 20220077072 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material. | 2022-03-10 |
| 20220077073 | SEMICONDUCTOR DEVICES - Disclosed is a semiconductor device comprising a substrate, a first lower pattern group on the substrate and including a first key pattern and first lower test patterns horizontally spaced apart from the first key pattern, and a first upper pattern group on the first lower pattern group and including first pads horizontally spaced apart from each other and first upper test patterns between adjacent ones of the first pads. The first key pattern is configured to be used for a photography process associated with fabrication of the semiconductor device. The first pads are electrically connected to the first upper test patterns. One of the first pads vertically overlaps with the first key pattern. | 2022-03-10 |
| 20220077074 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof. | 2022-03-10 |
| 20220077075 | PANEL LEVEL METAL WALL GRIDS ARRAY FOR INTEGRATED CIRCUIT PACKAGING AND ASSOCIATED MANUFACTURING METHOD - A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid, | 2022-03-10 |
| 20220077076 | SEMICONDUCTOR DEVICES WITH REINFORCED SUBSTRATES - Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure. | 2022-03-10 |
| 20220077077 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via. The multi-stage terminal includes a pad base within the first opening having a pad base top side recessed below an upper surface the first dielectric and a pad head coupled to the pad base within the first opening, the pad head having a pad head top side with a micro dimple. Other examples and related methods are also disclosed herein. | 2022-03-10 |
| 20220077078 | SEMICONDUCTOR PACKAGE - A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm | 2022-03-10 |
| 20220077079 | CHIP AND MEMORY - Provided are a chip and a memory, relating to the technical field of semiconductors, and intended to solve the technical problem of low qualification rate of chips. The chip includes a base in which a through hole penetrating through the base is provided. A conductive column is provided in the through hole. A first surface of the base is provided with a first annular groove which surrounds the conductive column. A first isolator is provided in the first annular groove, and a first air gap extending along a circumferential direction of the first annular groove is formed in the first isolator. | 2022-03-10 |
| 20220077080 | SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor package, comprising: a support part; a semiconductor chip provided on the support part and including a plurality of signal pads; a buffer layer provided on the semiconductor chip; an adhesive layer provided on the buffer layer; a pressure-reducing layer provided on the adhesive layer; and a mold layer provided on the pressure-reducing layer. | 2022-03-10 |
| 20220077081 | ELECTRONIC DEVICE - An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively. | 2022-03-10 |
| 20220077082 | SEMICONDUCTOR DEVICE - A semiconductor device includes a conductive support member, a first semiconductor element, a second semiconductor element, an insulating element, and a sealing resin. The conductive support member includes a first die pad and a second die pad, which are separated from each other in a first direction. The first die pad and the second die pad overlap each other when viewed along the first direction. When viewed along a thickness direction, a peripheral edge of the first die pad has a first near-angle portion including a first end portion in a second direction orthogonal to both the thickness direction and the first direction. The first near-angle portion is separated from the second die pad in the first direction toward the first end portion in the second direction. | 2022-03-10 |
| 20220077083 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction. | 2022-03-10 |
| 20220077084 | INTEGRATED DECOUPLING CAPACITORS - Embodiments herein describe providing a decoupling capacitor on a first wafer (or substrate) that is then bonded to a second wafer to form an integrated decoupling capacitor. Using wafer bonding means that the decoupling capacitor can be added to the second wafer without having to take up space in the second wafer. In one embodiment, after bonding the first and second wafers, one or more vias are formed through the second wafer to establish an electrical connection between the decoupling capacitor and bond pads on a first surface of the second wafer. An electrical IC can then be flip chipped bonded to the first surface. As part of coupling the decoupling capacitor to the electrical IC, the decoupling capacitor is connected between the rails of a power source (e.g., VDD and VSS) that provides power to the electrical IC. | 2022-03-10 |
| 20220077085 | ELECTRONIC PACKAGE AND IMPLANTABLE MEDICAL DEVICE INCLUDING SAME - Various embodiments of an electronic package and an implantable medical device that includes such package are disclosed. The electronic package includes a monolithic package substrate having a first major surface and a second major surface, an integrated circuit disposed in an active region of the package substrate, and a conductive via disposed through an inactive region of the package substrate and extending between the first major surface and the second major surface of the package substrate. The conductive via is separated from the active region by a portion of the inactive region of the substrate. | 2022-03-10 |
| 20220077086 | SIDE WETTABLE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality. | 2022-03-10 |
| 20220077087 | BONDED STRUCTURE WITH INTERCONNECT STRUCTURE - A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die. | 2022-03-10 |
| 20220077088 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction. | 2022-03-10 |
| 20220077089 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a first chip and a second chip. The first chip includes a first substrate, a transistor, and a first pad. The second chip includes a second pad, a memory cell array, and a second substrate. The second pad is on the first pad. The second chip is bonded to the first chip. The first chip and the second chip includes, when viewed in a first direction orthogonal to the first substrate, a first region and a second region. The first region includes the memory cell array. The second region surrounds an area around the first region and includes a wall extending from the first substrate to the second substrate. The second substrate includes a first opening passing through the second substrate in the second region. | 2022-03-10 |
| 20220077090 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region. | 2022-03-10 |
| 20220077091 | SEMICONDUCTOR PACKAGE WITH AIR GAP - The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package. | 2022-03-10 |
| 20220077092 | SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device. | 2022-03-10 |
| 20220077093 | CORE MATERIAL, ELECTRONIC COMPONENT AND METHOD FOR FORMING BUMP ELECTRODE - A core material has a core; a solder layer provided outside the core and being a solder alloy containing Sn and at least any one element of Ag, Cu, Sb, Ni, Co, Ge, Ga, Fe, Al, In, Cd, Zn, Pb, Au, P, S, Si, Ti, Mg, Pd, and Pt; and a Sn layer provided outside the solder layer. The solder layer has a thickness of 1 μm or more on one side. The Sn layer has a thickness of 0.1 μm or more on one side. A thickness of the Sn layer is 0.215% or more and 36% or less of the thickness of the solder layer. | 2022-03-10 |
| 20220077094 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap. | 2022-03-10 |
| 20220077095 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE - A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer. | 2022-03-10 |
