| 10th week of 2022 patent applcation highlights part 59 |
| Patent application number | Title | Published |
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| 20220076894 | CAPACITOR COMPONENT - A capacitor component includes a body including a dielectric layer, a first electrode and a second internal electrode, laminated in a first direction, opposing each other, and a first cover portion and a second cover portion, disposed on outermost surfaces of the first and second internal electrodes, each having a thickness of 25 μm or less, a first electrode layer and a second electrode layer, respectively disposed on both external surfaces of the body in a second direction perpendicular to the first direction and respectively, and plating layers, respectively disposed on the first and second electrode layers. A metal oxide is disposed on a boundary between the first electrode layer and the plating layer and a boundary between the second electrode layer and the plating layer. | 2022-03-10 |
| 20220076895 | Solid Electrolytic Capacitor Containing A Sequential Vapor-Deposited Dielectric Film - A capacitor comprising a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric film that is formed by sequential vapor deposition and overlies the anode body, and a solid electrolyte that overlies the dielectric film is provided. | 2022-03-10 |
| 20220076896 | Method of Manufacturing a Polymer Capacitor and Polymer Capacitor - A method for manufacturing a polymer capacitor and a polymer capacitor are disclosed. In an embodiment a polymer capacitor includes an anode foil, a cathode foil and separator foils wound to a winding, wherein the anode foil is covered by a polymer, wherein one or more additives are distributed in the polymer, and wherein at least one of the additives has a boiling point below 130° C. | 2022-03-10 |
| 20220076897 | PEROVSKITE SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - Provided is a perovskite solar cell including a substrate, a lower transparent electrode provided on the substrate, an upper transparent electrode provided on the lower transparent electrode, and a light absorption layer interposed between the lower transparent electrode and the upper transparent electrode, wherein the light absorption layer includes a perovskite material, and at least one of the lower transparent electrode or the upper transparent electrode includes a first color implementation layer, an intermediate layer, and a second color implementation layer, which are sequentially stacked, the first color implementation layer and the second color implementation layer each being a metal oxide layer containing a dopant. | 2022-03-10 |
| 20220076898 | CARBON-TITANIA NANOCOMPOSITE THIN FILMS AND APPLICATIONS OF THE SAME - In one aspect of the invention, a dye sensitized solar cell has a counter-electrode including carbon-titania nanocomposite thin films made by forming a carbon-based ink; forming a titania (TiO | 2022-03-10 |
| 20220076899 | ELECTRODE MATERIAL FOR CAPACITOR - An ink includes a boron-doped nanodiamond having a specific surface area of 110 m | 2022-03-10 |
| 20220076900 | Switching Element Guide - An improved switching device includes a guide configured to reduce undesired movement of the switching element. The guide includes an upper portion configured to receive the switching element and a lower portion configured to receive a spring. The upper portion defines a seat to receive the switching element and includes at least one resilient tab to retain the switching element within the guide. The lower portion defines an opening in which the spring is positioned, where the spring is seated, in part, against the switching element and against the guide. The guide includes guide portions configured to engage a housing on the switching device to prevent rotation of the switching element within the switching device. The switching element further includes protrusions configured to engage each side of the guide and to prevent longitudinal movement of the switching element within the housing. | 2022-03-10 |
| 20220076901 | Remote Control for a Wireless Load Control System - A remote control for a wireless load control system, the remote control comprising: a housing having a front surface and an outer periphery defined by a length and a width; an actuator provided at the front surface of the housing; a wireless transmitter contained within the housing; and a controller contained within the housing and coupled to the wireless transmitter for causing transmission of a wireless signal in response to an actuation of the actuator, the wireless transmitter and the controller adapted to be powered by a battery contained within the housing; wherein the length and the width of the housing are slightly smaller than a length and a width of a standard opening of a faceplate, respectively, such that the outer periphery of the housing is adapted to be received within the standard opening of the faceplate when the housing and the faceplate are mounted to a vertical surface. | 2022-03-10 |
| 20220076902 | PUSH SWITCH - The push switch | 2022-03-10 |
| 20220076903 | MULTI-LAYERED CONDUCTIVE SPRING - A mechanical component is provided. The component can have a core, a sheath circumferentially surrounding the core, and an insulator between the core and the sheath. The core can include a shape memory material that is arranged to move from an initial form to an activated form upon a temperature of the core warming past a transition temperature of the shape memory material. A distal portion of the sheath can be in electrical communication with a distal portion of the core, while the insulator blocks a flow of electrical current between a proximal portion of the sheath and a proximal portion of the core. | 2022-03-10 |
| 20220076904 | KEY STRUCTURE AND ELECTRONIC APPARATUS - A key structure comprises at least one key switch mounted on a surface of a substrate disposed inside a case of an electronic apparatus; at least one key top inserted in a key through-hole bored in the case, the at least one key top being designed to press the at least one key switch upon undergoing a displacement from outside the case toward inside the case; and a key stopper abutting, inside the case, the at least one key top that has undergone the displacement, to restrict a further outward-to-inward displacement of the at least one key top. | 2022-03-10 |
| 20220076905 | BUTTON SWITCH - The present disclosure belongs to the technical field of switches, and particularly relates to a button switch. The button switch comprises a base, an upper cover plate and a lower cover plate are arranged on the upper side and the lower side of the base respectively, a circuit board is arranged in the base, input wiring terminals and output insertion pieces are connected to the circuit board, a switch assembly for controlling the communication of the input wiring terminals and the output insertion pieces is arranged between the input wiring terminals and the output insertion pieces The button switch is stable in use process, stable in contact, long in service life, not prone to damage and convenient to maintain, and can be widely applied to various handheld electric tools. | 2022-03-10 |
| 20220076906 | KEY ASSEMBLY AND KEYBOARD MODULE - A key assembly includes a bottom plate, a keycap disposed on the bottom plate, an elastic member disposed between the bottom plate and the keycap, a link member, and a protruding member. The keycap has an inner surface facing the bottom plate and includes a link member pivoting portion protruding from the inner surface. The link member pivoting portion has a pivot hole and an opening communicating with the pivot hole and away from the inner surface. A size of the opening is smaller than a size of the pivot hole. The link member is rotatably disposed in the pivot hole. The protruding member is disposed between the inner surface of the keycap and the link member. The link member is supported by the protruding member and contacts a part of the link member pivoting portion near the opening on a wall surface surrounding the pivot hole. | 2022-03-10 |
| 20220076907 | MEMBRANE CIRCUIT BOARD OF KEYBOARD AND KEYBOARD STRUCTURE - The present disclosure provides a membrane circuit board of keyboard and a keyboard structure. The membrane circuit board of keyboard includes a first film, a first air channel, a second film, a second air channel, and a third film. The first film includes a first circuit pattern. The first air channel is disposed on the first film. The second film is disposed on the first air channel, and the second film includes an air hole. The second air channel is disposed on the second film, and the second air channel is in fluid communication with the air hole and the first air channel. The third film is disposed on the second air channel, and the third film includes a second circuit pattern. | 2022-03-10 |
| 20220076908 | ELECTRODE DRIVING DEVICE FOR GAS INSULATED SWITCHGEAR - A movable electrode driving device for a gas insulated switchgear is proposed. A movable electrode may be installed at one of conductors installed in an enclosure inner space of an enclosure. The movable electrode may move into and out of the conductor. Power for driving the movable electrode may be transmitted from a manipulator. A rotation manipulation lever may be installed at the outside of the enclosure, and an insulated shaft may be located inside the enclosure, the insulated shaft being connected to the rotation manipulation lever and extending into the conductor. A rotary lever may be located inside the conductor by being connected to the insulated shaft, and a transmission lever driven by the rotary lever so as to move the movable electrode may be provided. | 2022-03-10 |
| 20220076909 | Electromagnetic Inertial Switch - The technology relates to techniques for an electromagnetic inertial switch. An electromagnetic inertial switch can include an electrically conductive and magnetic mass located within a cavity, where portions of the cavity are electrically conductive and are electrically coupled to terminals of the electromagnetic inertial switch. A first magnetic field can be configured to apply a first force on the mass to attract the mass towards a first location, and a second magnetic field can be configured to apply a second force on the mass to attract the mass towards a second location. The electromagnetic inertial switch can be in a first electrical state when the mass is in the first location, and in response to an acceleration event greater than a threshold acceleration, the mass can move to the second location, thereby changing the electromagnetic inertial switch to a second electrical state. | 2022-03-10 |
| 20220076910 | SWITCHING APPARATUS WITH ELECTRICALLY ISOLATED USER INTERFACE - An apparatus includes: a high-voltage module including: a current interrupter; an actuation system coupled to the current interrupter; a sensor system; and a terminal configured to electrically connect to an external electrical device. The apparatus also includes: a user interface; and an electrically insulating assembly between the user interface and the high-voltage module. In operational use, the user interface is grounded and the high-voltage module is at a system voltage. | 2022-03-10 |
| 20220076911 | Switch Module In A Moulded Casing For A Circuit Breaker And Circuit Breaker In A Modular Moulded Casing - A unipolar switching module made of insulating material and including an incorporated thermomagnetic tripping set, and/or a current measurer and power supply set for an electronic controller A multipolar low-voltage molded case circuit breaker can include unipolar switching modules, which interact with the tripping set and/or the current measurer and power supply set. | 2022-03-10 |
| 20220076912 | BI-STABLE TRIP UNIT WITH TRIP SOLENOID AND FLUX TRANSFER RESET - A trip unit for a circuit breaker includes a magnetic flux transfer system that employs a permanent magnet(s) and solenoid(s) with a ferromagnetic core. The system generates an attractive force using a solenoid to counter the force of a reset spring and latch friction force when a tripping condition is detected. The generated attractive force together with an attractive force from the magnet attracts a yoke which in turn moves the yoke together with an armature to the tripped position. The system also retains the yoke and armature in the tripped position using the attractive force of the magnet when the generated attractive force is no longer being generated. The system further generates a repulsive force using a solenoid when a resettable condition is satisfied to counter the | 2022-03-10 |
| 20220076913 | HIGH BREAKING CAPACITY CHIP FUSE - A high breaking capacity chip fuse including a bottom insulative layer, a first intermediate insulative layer, a second intermediate insulative layer, and a top insulative layer disposed in a stacked arrangement in the aforementioned order, a fusible element disposed between the first and second intermediate insulative layers and extending between electrically conductive first and second terminals at opposing longitudinal ends of the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer, wherein the first and second intermediate insulative layers are formed of porous ceramic. | 2022-03-10 |
| 20220076914 | MAGNETIC IMMERSION ELECTRON GUN - The present disclosure provides a magnetic immersion electron gun and a method of generating an electron beam using a magnetic immersion electron gun. The electron gun includes a magnetic lens forming a magnetic field, a cathode tip disposed in the magnetic field, and a multi-filament heater configured to directly heat the cathode tip to emit electrons through the magnetic lens. The multi-filament heater includes a first filament connected at each end to first and second positive terminals of a power source and a second filament connected at each end to first and second negative terminals of the power source. The first positive terminal, the second positive terminal, the first negative terminal, and the second negative terminal are arranged alternately around the cathode tip such that the first filament and the second filament intersect at the cathode tip and a resultant magnetic force applied to the cathode tip is reduced. | 2022-03-10 |
| 20220076915 | System And Technique For Profile Modulation Using High Tilt Angles - A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 μm or more using larger tilt angles. | 2022-03-10 |
| 20220076916 | THETA STAGE MECHANISM AND ELECTRON BEAM INSPECTION APPARATUS - According to one aspect of the present invention, a 8 stage mechanism includes a fixed shaft; a plurality of bearings in which outer rings roll on an outer peripheral surface of the fixed shaft; a plurality of cylindrical members supported in a state of being inserted inside inner rings of the plurality of bearings; and a table that is arranged on the plurality of cylindrical members and moves in a rotational direction about a center of the fixed shaft by the plurality of bearings rolling on an outer peripheral surface of the fixed shaft. | 2022-03-10 |
| 20220076917 | METHOD AND SYSTEM FOR AUTOMATIC ZONE AXIS ALIGNMENT - Automatic alignment of the zone axis of a sample and a charged particle beam is achieved based on a diffraction pattern of the sample. An area corresponding to the Laue circle is segmented using a trained network. The sample is aligned with the charged particle beam by tilting the sample with a zone axis tilt determined based on the segmented area. | 2022-03-10 |
| 20220076918 | Semiconductor Processing Apparatus - A semiconductor processing apparatus according to the present invention includes a main body cover that covers a main body device and a control device. The main body cover has a transfer opening for transferring a semiconductor, and the main body cover further has an intake port that generates an air flow in a horizontal direction inside the main body cover. | 2022-03-10 |
| 20220076919 | SEMICONDUCTOR PROCESSING CHAMBERS FOR DEPOSITION AND ETCH - Exemplary semiconductor substrate supports may include a pedestal having a shaft and a platen. The semiconductor substrate supports may include a cover plate. The cover plate may be coupled with the platen along a first surface of the cover plate. The cover plate may define a recessed channel in a second surface of the cover plate opposite the first surface. The semiconductor substrate supports may include a puck coupled with the second surface of the cover plate. The puck may incorporate an electrode. The puck may define a plurality of apertures extending vertically through the puck to fluidly access the recessed channel defined in the cover plate. | 2022-03-10 |
| 20220076920 | SEMICONDUCTOR PROCESSING CHAMBERS FOR DEPOSITION AND ETCH - Exemplary semiconductor substrate supports may include a pedestal shaft. The semiconductor substrate supports may include a platen. The platen may define a fluid channel across a first surface of the platen. The semiconductor substrate supports may include a platen insulator positioned between the platen and the pedestal shaft. The semiconductor substrate supports may include a conductive puck coupled with the first surface of the platen and configured to contact a substrate supported on the semiconductor substrate support. The semiconductor substrate supports may include a conductive shield extending along a backside of the platen insulator and coupled between a portion of the platen insulator and the pedestal shaft. | 2022-03-10 |
| 20220076921 | PLASMA PROCESSING APPARATUS AND CONTROL METHOD - A plasma processing apparatus includes: a processing container; an electrode that places a substrate thereon within the processing container; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies bias power to the electrode; a part exposed to the plasma in the processing container; a DC power supply that supplies a DC voltage to the part; a controller that executes a process including a first control procedure in which a first state in which the DC voltage has a first voltage value and a second state in which the DC voltage has a second voltage value higher than the first voltage value are periodically repeated, and the first voltage value is applied in a partial period in each cycle of a potential of the electrode, and the second voltage value is applied such that the first state and the second state are continuous. | 2022-03-10 |
| 20220076922 | SINGLE CHAMBER FLOWABLE FILM FORMATION AND TREATMENTS - Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The semiconductor substrate may be housed in a processing region of a semiconductor processing chamber. The processing region may be defined between a faceplate and a substrate support on which the semiconductor substrate is seated. The methods may include forming a treatment plasma within the processing region of the semiconductor processing chamber. The treatment plasma may be formed at a first power level from a first power source. A second power may be applied to the substrate support from a second power source at a second power level. The methods may include densifying the flowable film within the feature defined within the semiconductor substrate with plasma effluents of the treatment plasma. | 2022-03-10 |
| 20220076923 | Impedance Matching Apparatus and Control Method - A system includes a plasma chamber coupled to a power source, and an impedance matching network coupled between the power source and the plasma chamber, wherein the impedance matching network comprises an L-shaped network and a first adjustable inductor coupled between an input of the plasma chamber and ground, and wherein the impedance matching network is configured such that, in a predetermined frequency range, an impedance of the impedance matching network and the plasma chamber is substantially equal to an impedance of the power source. | 2022-03-10 |
| 20220076924 | SUBSTRATE PROCESSING SYSTEM INCLUDING DUAL ION FILTER FOR DOWNSTREAM PLASMA - A substrate processing system includes an upper chamber and a gas delivery system to supply a gas mixture to the upper chamber. An RF generator generates plasma in the upper chamber. A lower chamber includes a substrate support. A dual ion filter is arranged between the upper chamber and the lower chamber. The dual ion filter includes an upper filter including a first plurality of through holes configured to filter ions. A lower filter includes a second plurality of through holes configured to control plasma uniformity. | 2022-03-10 |
| 20220076925 | APPARATUS AND METHOD FOR PROCESSING SUBSTRATE USING PLASMA - A substrate processing apparatus and a substrate processing method using plasma capable of controlling an etch rate and/or uniformity according to a position of a substrate are provided. The substrate processing apparatus includes a first space disposed between an electrode and an ion blocker; a second space disposed between the ion blocker and a shower head; a processing space for processing a substrate under the shower head; a first gas supply module for providing a first gas for generating plasma in the first space; a second gas supply module for providing a second gas to be mixed with the effluent of the plasma in the processing space; and a third gas supply module for providing a third gas to be mixed with the effluent of the plasma in the processing space. | 2022-03-10 |
| 20220076926 | DEPOSITION DEVICE APPARATUS - A deposition device includes a chamber, a support member, a ground member, and a first fixing member. The chamber includes a lower portion and a side wall. The support member is located in a space defined by the lower portion and the side wall of the chamber, and includes a side surface. The ground member is disposed between the support member and the lower portion of the chamber. The first fixing member includes a first body and a first blocking part. The first body is located under a first end portion of the ground member, and includes a side surface. The first blocking part is located on the side surface of the first body and the side surface of the support member, and extends along the side surface of the support member. The first blocking part shields the first end portion of the ground member from view. | 2022-03-10 |
| 20220076927 | PART WITH CORROSION-RESISTANT LAYER - Proposed is a part with a corrosion-resistant layer capable of preventing the exposure of pores attributable to corrosion and preventing the discharge of internal moisture and particles through the pores. | 2022-03-10 |
| 20220076928 | PLASMA PROCESSING APPARATUS AND HIGH-FREQUENCY POWER APPLICATION METHOD OF PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a vacuum-exhaustible processing container, an electrode installed in the processing container, a plurality of power feeding portions connected to a peripheral portion of a back surface of the electrode, a high-frequency power supply configured to supply high-frequency power to the electrode through the plurality of power feeding portions, and a control unit. The control unit is configured to control the plasma processing apparatus to periodically apply the high-frequency power to each of the plurality of power feeding portions. | 2022-03-10 |
| 20220076929 | SUBSTRATE TREATING APPARATUS AND COVER RING THEREOF - Disclosed is a substrate treating apparatus. The substrate treating apparatus includes a process chamber that provides a treatment space in an interior thereof, a support unit that supports a substrate in the treatment space, a gas supply unit that supplies a process gas into the treatment space, and a plasma source that generates plasma from the process gas, the support unit includes a support plate, on which the substrate is positioned, and an edge ring assembly that surrounds the substrate supported on the support plate, and that forms the plasma in the substrate, and the edge ring assembly includes a focusing ring formed of a first material, and that forms distribution of the plasma in the substrate, and a cover ring provided in an area of the substrate, and including a reinforced surface layer provided by injecting a network modifier into an empty site of the network structure. | 2022-03-10 |
| 20220076930 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - In a plasma processing apparatus, a controller specifies a time point when a current starts to flow between an edge ring and a DC power supply after beginning an application of a negative DC voltage to the edge ring from the DC power supply. The controller specifies, from a voltage measurement value indicating a voltage of the edge ring at the time point, an estimate of a self-bias voltage of the edge ring generated by a supply of a radio frequency power. The controller sets a sum of an absolute value of the estimate of the self-bias voltage and a set value as an absolute value of the negative DC voltage to be applied to the edge ring by the DC power supply. | 2022-03-10 |
| 20220076931 | PLASMA PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A plasma processing apparatus includes a process chamber, a substrate support chuck configured to support a substrate in the process chamber, the substrate support chuck including an upper cooling channel and a lower cooling channel that are symmetrically separated from each other, and a support chuck temperature controller configured to supply a first coolant to the upper cooling channel and to supply a second coolant to the lower cooling channel. | 2022-03-10 |
| 20220076932 | PLASMA FILM FORMING APPARATUS AND PLASMA FILM FORMING METHOD - A plasma film forming apparatus | 2022-03-10 |
| 20220076933 | APPARATUS FOR ION ENERGY ANALYSIS OF PLASMA PROCESSES - An apparatus for obtaining ion energy distribution, TED, measurements in a plasma processing system, in one example, comprising a substrate for placement in the plasma processing system and exposed to the plasma, an ion energy analyser disposed in the substrate for measuring the ion energy distribution at the substrate surface during plasma processing, the analyser comprising a first conductive grid, a second conductive grid, a third conductive grid, a fourth conductive grid, and a collection electrode, each grid separated by an insulation layer, a battery power supply and control circuitry, integrated in the substrate, for supplying and controlling voltage to each of the grids and the collector of the ion energy analyser; wherein at least one insulation layer includes a peripheral portion which is of reduced thickness with respect to the remaining portion of the insulation layer. | 2022-03-10 |
| 20220076934 | SEMICONDUCTOR MANUFACTURING APPARATUS AND EARTH SHIELD - A semiconductor manufacturing apparatus according to an embodiment includes a stage, a backing plate and an earth shield. The stage is configured to hold a substrate that a film is to be deposited on. The backing plate faces the stage and is configured such that a target containing a film deposition material is to be joined. The earth shield has an opening configured to enclose the target, and a plurality of through holes provided over a whole circumference of a circumferential part of the opening. | 2022-03-10 |
| 20220076935 | METHOD AND DEVICE FOR ANALYSING SIMS MASS SPECTRUM DATA - A method for analyzing secondary ion mass spectrum data representing respective secondary ion counts for a range of masses at a given mass resolution. The mass spectrum data is obtained by Secondary Ion Mass Spectrometry, SIMS. Automatic quantification of the ion species and/or cluster ions detected in the analyzed spectrum data is provided. | 2022-03-10 |
| 20220076936 | METHODS AND APPARATUSES FOR DETERMINING THE INTACT MASS OF LARGE MOLECULES FROM MASS SPECTROGRAPHIC DATA - Methods and apparatuses for the identification and/or characterization of properties of a sample using mass spectrometry. The method involves using a measured spectrum of data from a sample taken with a mass spectrometer, deconvoluting the measured spectrum of data by applying parsimony weighting to minimize the number of charge states based on one or more of: the number of intense peaks in the mass spectrum; the number of harmonic relationships (e.g., masses in small integer ratios); and the number of off-by-one relationships (e.g., m/z bins with high probability for two adjacent charges). Thus, the underlying m/z spectrum may be inferred from the family of plausible deconvoluted spectra determined by applying parsimony and the inferred m/z spectrum may be used to identify and/or characterize the sample. | 2022-03-10 |
| 20220076937 | SPECTROMETRIC ANALYSIS OF MICROBES - A method of analysis using mass spectrometry and/or ion mobility spectrometry is disclosed. The method comprises: using a first device to generate smoke, aerosol or vapour from a target comprising or consisting of a microbial population; mass analysing and/or ion mobility analysing said smoke, aerosol or vapour, or ions derived therefrom, in order to obtain spectrometric data; and analysing said spectrometric data in order to analyse said microbial population. | 2022-03-10 |
| 20220076938 | VACUUM ULTRAVIOLET EXCIMER LAMP WITH A THIN WIRE INNER ELECTRODE - A VUV excimer lamp has a dielectric tube for holding an excimer-forming gas, a first electrode disposed within the dielectric tube, and a second electrode arranged outside of the dielectric tube. The first electrode has an outer diameter less than 0.5 mm, is elongated, and includes at least one thin wire with an outer diameter between 0.02 mm and 0.4 mm. The thin wire is an elongated thin wire, and is substantially straight and defines a straight axis of elongation. A photochemical system has the VUV excimer lamp. An excimer lamp system has the VUV excimer lamp, and also has a power supply to supply AC electric power to the first electrode and the second electrode. | 2022-03-10 |
| 20220076939 | VACUUM ULTRAVIOLET EXCIMER LAMP WITH AN INNER AXIALLY SYMMETRIC WIRE ELECTRODE - A dielectric barrier VUV excimer lamp has an elongated dielectric tube for holding an excimer-forming gas, a first electrode disposed within the dielectric tube, and a second electrode arranged outside of the dielectric tube. The first electrode is a wire electrode disposed along a centre axis of the dielectric tube, axially symmetric with respect to the centre axis, and physically connected to each end of the dielectric tube. The dielectric barrier VUV excimer lamp is an AC dielectric barrier discharge VUV excimer lamp or the dielectric barrier VUV excimer lamp is a pulsed DC dielectric barrier discharge VUV excimer lamp. A photochemical system has the dielectric barrier VUV excimer lamp. An excimer lamp system has the dielectric barrier VUV excimer lamp, and also has a power supply to supply electric power to the first electrode and the second electrode. | 2022-03-10 |
| 20220076940 | A PHOSPHOR FOR A UV EMITTING DEVICE AND A UV GENERATING DEVICE UTILIZING SUCH A PHOSPHOR - The invention relates to a phosphor for a UV emitting device, having the formula Na | 2022-03-10 |
| 20220076941 | SUBSTRATE PROCESSING METHOD - A substrate processing method includes a processing liquid supplying step of supplying a processing liquid to a patterned surface of a substrate having the patterned surface with projections and recesses, a processing film forming step of solidifying or curing the processing liquid supplied to the patterned surface to form, so as to follow the projections and the recesses of the patterned surface, a processing film which holds a removal object present on the patterned surface and a removing step of supplying a peeling liquid to the patterned surface to peel the processing film from the patterned surface together with the removal object, thereby removing the processing film from the substrate, while such a state is kept that the removal object is held by the processing film. | 2022-03-10 |
| 20220076942 | METHOD FOR CRITICAL DIMENSION (CD) TRIM OF AN ORGANIC PATTERN USED FOR MULTI-PATTERNING PURPOSES - Improved process flows and methods are provided herein for trimming structures formed on a patterned substrate. In the disclosed process flows and methods, a self-aligned multiple patterning (SAMP) process is utilized for patterning structures, such as mandrels, on a substrate. After the structures are patterned, an atomic layer deposition (ALD) process is used to form a spacer layer on the patterned structures. In the SAMP process disclosed herein, a critical dimension (CD) of the patterned structures is trimmed concurrently with, and as a result of, the formation of the spacer layer by controlling various ALD process parameters and conditions. By trimming the patterned structures in situ of the ALD chamber used to form the spacer layer on the patterned structures, the improved process flows and methods described herein provide a CD trim method that does not adversely affect the pattern profile or process throughput. | 2022-03-10 |
| 20220076943 | SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - The present disclosure provides a semiconductor structure and a method preparing it. After planarization of the Cu layer, a Si substrate is dry etched, so that a first height difference is configured in between the top surfaces of the the Si substrate and an insulating layer. By means of a wet etch process, Cu residues near an edge of a Cu post may be effectively removed. A second height difference is configured in between the top surfaces of the Cu post and the insulating layer. The first height difference is arranged to be greater than the second height difference. Channeling of Cu trace residues through the insulating layer are thereby avoided, effectively mitigating electrical leakage. Further, the Si substrate may be covered by a passivation layer, to prevent a conductive channel from being formed on the Si substrate, thereby further avoiding negative impact on the electrical properties of the device. | 2022-03-10 |
| 20220076944 | WATER SOLUBLE ORGANIC-INORGANIC HYBRID MASK FORMULATIONS AND THEIR APPLICATIONS - Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix. | 2022-03-10 |
| 20220076945 | AMORPHOUS CARBON FOR GAP FILL - Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition rate of greater than 200 nm/hr; and purging the processing chamber. | 2022-03-10 |
| 20220076946 | FORMATION OF SiOCN THIN FILMS - Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance. | 2022-03-10 |
| 20220076947 | PRECURSORS AND PROCESSES FOR DEPOSITION OF SI-CONTAINING FILMS USING ALD AT TEMPERATURE OF 550.degree.C OR HIGHER - Methods for forming a Si-containing film on a substrate comprise heating the substrate to a temperature higher than S50° C., exposing the substrate to a vapor including a Si-containing film forming composition containing a Si-containing precursor having the formula: SiR | 2022-03-10 |
| 20220076948 | VAPOR PHASE TRANSPORT SYSTEM AND METHOD FOR DEPOSITING PEROVSKITE SEMICONDUCTORS - Vapor phase transport systems and methods of depositing perovskite films are described. In an embodiment, a deposition method includes feeding a perovskite solution or constituent powder to a vaporizer, followed by vaporization and depositing the constituent vapor as a perovskite film. In an embodiment, a deposition system and method includes vaporizing different perovskite precursors in different vaporization zones at different temperatures, followed by mixing the vaporized precursors to form a constituent vapor, and depositing the constituent vapor as a perovskite film. | 2022-03-10 |
| 20220076949 | SELECTIVE PEALD OF OXIDE ON DIELECTRIC - Methods for selectively depositing oxide thin films on a dielectric surface of a substrate relative to a metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a first precursor comprising oxygen and a species to be included in the oxide, such as a metal or silicon, and a second plasma reactant. In some embodiments the second plasma reactant comprises a plasma formed in a reactant gas that does not comprise oxygen. In some embodiments the second plasma reactant comprises plasma generated in a gas comprising hydrogen. | 2022-03-10 |
| 20220076950 | SEMICONDUCTOR DEVICE WITH A GROUP-III OXIDE ACTIVE LAYER - A method for forming a semiconductor device with a group-III oxide active layer including at least two group-III materials is provided. A group-III oxide substrate is provided and a group-III oxide active layer including at least one group-III material on the group-III oxide substrate is formed on the group-III oxide substrate. A group-III material in the group-III oxide substrate is different from the at least one group-III material in the group-III oxide active layer. The group-III oxide active layer including at least one group-III material and the group-III oxide substrate are annealed at a temperature greater than or equal to 1,000° C. so that the group-III material in the group-III oxide substrate diffuses into the group-III oxide active layer to form the group-III oxide active layer including the at least two group-III materials. | 2022-03-10 |
| 20220076951 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - The present disclosure provides a semiconductor structure and a method for manufacturing the same. The method at least includes: applying a first wet etching to remove a Ti metal seed layer to expose a dielectric layer; performing a first pretreatment on the dielectric layer; forming a first groove in the dielectric layer to expose an interfacial Ti metal seed layer in the dielectric layer; applying a second wet etching to remove the interfacial Ti metal seed layer; and performing a second pretreatment on the dielectric layer to form a second groove with a depth greater than that of the interfacial Ti metal seed layer, which can effectively remove the interfacial Ti metal seed layer, and results in a depth difference between the bottom of the second groove and the interfacial Ti metal seed layer, thereby avoiding short circuits caused by the interfacial Ti metal seed layer, and improving device reliability. | 2022-03-10 |
| 20220076952 | METHOD FOR PATTERNING A SURFACE OF A SUBSTRATE - A method for patterning a surface of a substrate includes applying a liquid on the surface of the substrate, wherein an apparent viscosity of the liquid depends on a field strength applied to the liquid; applying a field to the liquid, wherein a field strength of the applied field is spatially varied in the liquid in a direction parallel to the surface of the substrate, thereby generating a spatially varied apparent viscosity distribution in the liquid in response to the applied field; and patterning the surface of the substrate by subjecting the surface to a surface modifying process, while maintaining the field and using portions of the liquid having apparent viscosities higher than a predetermined value as a mask; wherein the surface modifying process comprises removing material of the surface of the substrate and/or depositing material on the surface of the substrate. | 2022-03-10 |
| 20220076953 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Embodiments of the present application provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a first mask layer positioned on the substrate, wherein the first mask layer has a plurality of discrete first mask patterns; and a second mask layer positioned on the first mask layer, wherein the second mask layer has a second mask pattern, and at least a part of sidewalls of the second mask pattern is positioned on tops of the first mask patterns. | 2022-03-10 |
| 20220076954 | CONTACT SLOTS FORMING METHOD APPLYING PHOTORESISTS - Contact slots forming method applying photoresists include the following steps. A dielectric layer and a hard mask layer are formed on a substrate sequentially. A first patterned photoresist layer is formed over the hard mask layer, wherein the first patterned photoresist layer includes island patterns connecting to each other by connecting dummy parts. The hard mask layer is etched using the first patterned photoresist layer to form a patterned hard mask layer including island patterns connecting to each other by connecting dummy parts. A second patterned photoresist layer is formed over the patterned hard mask layer. The dielectric layer is etched using the second patterned photoresist layer and the patterned hard mask layer as a mask to form contact holes in the dielectric layer. | 2022-03-10 |
| 20220076955 | MANUFACTURING METHOD OF AN ELEMENT OF AN ELECTRONIC DEVICE HAVING IMPROVED RELIABILITY, AND RELATED ELEMENT, ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body. | 2022-03-10 |
| 20220076956 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate. | 2022-03-10 |
| 20220076957 | MONITORING DEVICE, MONITORING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a monitoring device and method. A monitoring device includes a laser processor configured to emit a processing laser beam to perform a melting annealing process on a wafer; a laser monitor configured to emit a monitoring laser beam onto the wafer while the laser processor performs the melting annealing process, the laser monitor configured to measure reflectivity of the wafer; and a data processor configured to process data on the reflectivity measured by the laser monitor, and monitor one or more characteristics of the wafer based on the data on the reflectivity. | 2022-03-10 |
| 20220076958 | Method for Ion Implantation That Adjusts a Targets Tilt Angle Based on a Distribution of Ejected Ions From a Target - The present disclosure describes a system and a method for an ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions. | 2022-03-10 |
| 20220076959 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING TILTED ETCH PROCESS - The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method for fabricating the semiconductor device includes providing a target layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers. The first tilted etch process and the second tilted etch process use the second hard mask layers as pattern guides and the first hard mask layer is turned into a patterned first hard mask layer by the first openings and the second openings. | 2022-03-10 |
| 20220076960 | METHODS FOR SELECTIVE DRY ETCHING GALLIUM OXIDE - Exemplary methods of etching gallium oxide from a semiconductor substrate may include selectively etching gallium oxide relative to gallium nitride. The method may include flowing a reagent in a substrate processing region housing the semiconductor substrate. The reagent may include at least one of chloride and bromide. The method may further include contacting an exposed region of gallium oxide with the at least one of chloride and bromide from the reagent to form a gallium-containing gas. The gallium-containing gas may be removed by purging the substrate processing region with an inert gas. The method includes recessing a surface of the gallium oxide. The method may include repeated cycles to achieve a desired depth. | 2022-03-10 |
| 20220076961 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes etching the first film with first gas including carbon and fluorine to form a concave portion in the first film and form a second film in the concave portion. The method further includes treating the second film by using the second film to second gas or second liquid, wherein the second film is treated without plasma. | 2022-03-10 |
| 20220076962 | SEMICONDUCTOR MASK RESHAPING USING A SACRIFICIAL LAYER - Provided herein are methods and related apparatus for mask reconstruction in an etch process. The methods involve depositing a sacrificial layer on the mask layer. The sacrificial layer may be used to protect position on the mask layer. Following mask reshaping, the sacrificial layer may be removed using the same etch process that is used to etch the target material. | 2022-03-10 |
| 20220076963 | SUBSTRATE PROCESSING APPARATUS AND OPERATION METHOD FOR SUBSTRATE PROCESSING APPARATUS - In one embodiment, a method for operating a substrate processing apparatus comprising a chamber in which a fluorine/silicon-containing substance is deposited on an inner wall through an oxide film removal process for a substrate placed therein, and an antenna installed outside the chamber to which RF power is applied, the method comprising: decomposing thermally the fluorine/silicon-containing substance through heating the inner wall of the chamber to 75° C. or more by supplying an inert gas to the inside of the chamber and applying RF power to the antenna. | 2022-03-10 |
| 20220076964 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure includes the steps of providing a substrate having a first region and a second region, forming a plurality of semiconductor devices on the first region of the substrate, forming a planarization layer on the substrate and covering the semiconductor devices, wherein the planarization layer on the first region and the planarization layer on the second region have a step-height, performing a first CMP process to remove the step height of the planarization layer, and after the first CMP process, performing a curing process to convert the planarization layer into a porous low-k dielectric layer. | 2022-03-10 |
| 20220076965 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a stacked body including a plurality of conductive layers insulated from each other, a semiconductor layer extending into the stacked body, and a charge storage layer located between one of the conductive layers and the semiconductor layer. The conductive layer contains tungsten and an auxiliary material. An amount of the auxiliary material is smaller than an amount of tungsten, and an oxide free energy of the auxiliary material is smaller than an oxide free energy of tungsten. | 2022-03-10 |
| 20220076966 | METHOD AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR LAYER - The present disclosure provides a method and system for manufacturing a semiconductor layer. The method includes: placing a first wafer in a cavity to form a metal film on the first wafer; before forming the metal film, the temperature inside the cavity is a first temperature; transferring the first wafer on which the metal film has been formed out of the cavity; the temperature in the cavity is a second temperature, and the second temperature is greater than the first temperature; introducing an inert gas into the cavity to cool the cavity, such that the temperature in the cavity is equal to the first temperature; after the temperature in the cavity is equal to the first temperature, placing a second wafer in the cavity to form the metal film on the second wafer. The manufacturing method can reduce the defects on the surface of the metal film. | 2022-03-10 |
| 20220076967 | WET ETCHING CONTROL SYSTEM, WET ETCHING MACHINE AND WET ETCHING CONTROL METHOD - A wet etching control system includes a liquid level detector, an etching agent spraying component, a cleaning agent spraying component and controller. The liquid level detector is configured to detect a liquid level of leakage liquid in a leakage liquid collection tank, and the controller is configured to control the etching agent spraying component to stop a spraying of an etching agent onto a surface of a wafer, and control the cleaning agent spraying component to spray a cleaning agent onto the surface of the wafer when the liquid level of the leakage liquid is greater than a first preset value. | 2022-03-10 |
| 20220076968 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes performing a liquid processing, detecting a temperature, generating temperature distribution information and determining whether a result of the liquid processing is good or bad. The liquid processing is performed on a substrate by using a processing unit. A temperature of a central portion of the substrate and a temperature of an edge portion of the substrate in the liquid processing are detected by using multiple sensors provided in the processing unit. The temperature distribution information indicating an in-surface temperature distribution of the substrate in the liquid processing is generated based on one or more parameter values defining a processing condition for the liquid processing and the temperature of the central portion of the substrate and the temperature of the edge portion of the substrate. Whether the result of the liquid processing is good or bad is determined based on the temperature distribution information. | 2022-03-10 |
| 20220076969 | SEMICONDUCTOR EQUIPMENT REGULATION METHOD AND SEMICONDUCTOR DEVICE FABRICATION METHOD - The present application relates to a semiconductor equipment regulation method, including: providing a simulated wafer; placing the simulated wafer in an etching chamber, and conditioning a temperature in the chamber by using a temperature control device while the simulated wafer is etched by using an etching gas; during the etching process, forming a polymer layer on a surface of each etch hole; acquiring a thickness distribution map of the polymer layer in the entire simulated wafer; comparing the acquired thickness distribution map with a target thickness distribution map; and adjusting a temperature control effect through using the temperature control device on each region of the simulated wafer according to a result of the comparison, so as to adjust thickness uniformity of the polymer layer in the entire wafer. | 2022-03-10 |
| 20220076970 | LIGHT IRRADIATION TYPE HEAT TREATMENT APPARATUS - A light diffusion plate is placed on an upper surface of an upper chamber window. A blasting process is applied to a lower surface of the light diffusion plate to provide the lower surface in the form of frosted glass. When the light diffusion plate is placed on the upper surface of the upper chamber window, the light diffusion plate and the upper chamber window do not closely adhere to each other. The frosted glass releases a mass of air entering between contact surfaces of the light diffusion plate and the upper chamber window to the outside even if the mass of air thermally expands during heat treatment. This restrains the occurrence of a phenomenon in which a thin layer of air is trapped between the light diffusion plate and the upper chamber window to prevent the sliding of the light diffusion plate resulting from the air layer. | 2022-03-10 |
| 20220076971 | SELF ALIGNING WAFER CARRIER PEDESTAL ELEMENT WITH POWER CONTACTS - Embodiments disclosed herein relate to an apparatus for aligning and securing a transferable substrate support. In one embodiment, a substrate support assembly includes a transferable substrate support. The transferable substrate support includes one or more first separable contact terminals disposed on a surface of the transferable substrate support. Each of the first separable contact terminals includes a detachable connection region and an electrical connection region, and the electrical connection region is coupled to an electrical element disposed within the transferable substrate support. The detachable connection region of each of the one or more first separable contact terminals is configured to detachably connect and disconnect with a corresponding pin of one or more pins of a supporting pedestal by repositioning the supporting pedestal relative to the transferable substrate support in a first direction. | 2022-03-10 |
| 20220076972 | IN-SITU SEMICONDUCTOR PROCESSING CHAMBER TEMPERATURE APPARATUS - Methods and systems for in-situ temperature control are provided. The method includes delivering a temperature-sensing disc into a processing region of a processing chamber without breaking vacuum. The temperature-sensing disc includes one or more cameras configured to perform IR-based imaging. The method further includes measuring a temperature of at least one region of at least one chamber surface in the processing region of the processing chamber by imaging the at least one surface using the temperature-sensing disc. The method further includes comparing the measured temperature to a desired temperature to determine a temperature difference. The method further includes adjusting a temperature of the at least one chamber surface to compensate for the temperature difference. | 2022-03-10 |
| 20220076973 | BINNING-ENHANCED DEFECT DETECTION METHOD FOR THREE-DIMENSIONAL WAFER STRUCTURES - Location-based binning can separate defects on different rows of channel holes in a 3D NAND structure to corresponding bins. A one-dimensional projection of an image is generated and a one-dimensional curve is formed. A mask is generated from the one-dimensional curve. Defects in the image are detected using the mask and location-based binning is performed. | 2022-03-10 |
| 20220076974 | APPARATUS OF STORING CARRIERS AND METHOD OF STORING CARRIERS - An apparatus of storing container includes a stocker including shelves being configured to support containers, respectively, a purging unit being configured to provide a purge gas for each of the shelves to purge the containers when the stocker is in a purge mode, and to provide the purge gas only for each of the shelves when the stocker is in a normal mode, an inspection unit being configured to inspect a purge quality of the purge gas provided to each of the shelves while the stocker is in the normal mode, and a control unit being configured to change the stocker between in the purge mode and in the normal mode, and being configured to control the purging unit according to a switch between the purge mode and the normal mode. Thus, the apparatus has improved operation efficiency. | 2022-03-10 |
| 20220076975 | SYSTEM FOR A SEMICONDUCTOR FABRICATION FACILITY AND METHOD FOR OPERATING THE SAME - An automatic cleaning unit for AMHS includes a plurality of sensors disposed on OHT rails. The sensors are configured to define a cleaning zone and to detect a location of an OHT vehicle. The automatic cleaning unit further includes a vacuum generator and a top cleaning part installed over the OHT rails in the cleaning zone. The top cleaning part is coupled to the vacuum generator. The vacuum generator is turned on to perform a vacuum cleaning operation when the sensors detect the OHT vehicle entering the cleaning zone. | 2022-03-10 |
| 20220076976 | Automated Batch Production Thin Film Deposition Systems and Methods of Using the Same - Fully automated batch production thin film deposition systems configured to deliver uniformity combined with high throughput at a low cost-per-wafer. In some examples, systems of the present disclosure include automated safe wafer handling via low-impact batch transfer via transportable wafer racks loaded with a plurality of wafers. In some examples, systems include a modular pre-heat & cool-down architecture that enables a flexible thermal management solution tailored around particular specifications. | 2022-03-10 |
| 20220076977 | TRANSFER APPARATUS AND TRANSFER METHOD - A transfer apparatus transfers a first substrate and a second substrate while holding the first substrate and the second substrate to overlap each other in a plan view. The transfer apparatus includes: a first holding arm configured to hold the first substrate in a horizontal direction; a second holding arm configured to hold the second substrate in the horizontal direction; a first detection sensor configured to detect presence/absence of the first substrate held by the first holding arm; and a second detection sensor configured to detect presence/absence of the second substrate held by the second holding arm, wherein the first detection sensor includes a sensor configured to detect the presence/absence of the first substrate, and wherein the first holding arm includes a notch formed at least at an inner end portion of a tip of the first holding arm and configured to allow the optical axis to pass therethrough. | 2022-03-10 |
| 20220076978 | ALIGNMENT OF AN ELECTROSTATIC CHUCK WITH A SUBSTRATE SUPPORT - In one example, a substrate support for a processing chamber comprises a plurality of pins and a plurality of alignment elements. The plurality of pins are configured to mate with terminals of an electrostatic chuck. The plurality of pins are configured to be coupled to one or more power sources. The plurality of alignment elements are configured to interface with a plurality of centering elements of the electrostatic chuck to center the electrostatic chuck with the substrate support. Each of the plurality of alignment elements is configured to interface with a slot of a corresponding one of the plurality of centering elements. | 2022-03-10 |
| 20220076979 | PEDESTAL ASSEMBLY FOR A SUBSTRATE PROCESSING CHAMBER - A pedestal assembly for a processing region and comprising first pins coupled to a substrate support, configured to mate with first terminals of an electrostatic chuck, and are configured to be coupled to a first power source. Each of the first pins comprises an interface element, and a compliance element supporting the interface element. Second pins are coupled to the substrate support, configured to mate with second terminals of the electrostatic chuck, and configured to couple to a second power source. Alignment elements are coupled to the substrate support and are configured to interface with centering elements of the electrostatic chuck. The flexible element is coupled to the substrate support, configured to interface with a passageway of the electrostatic chuck, and configured to be coupled to a gas source. | 2022-03-10 |
| 20220076980 | SUBSTRATE BONDING APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a substrate bonding apparatus including a first chuck stage and a second chuck stage. The first chuck stage includes a first electromagnetic force generation unit. The first chuck stage is chuckable for a first substrate. The second chuck stage includes a second electromagnetic force generation unit. The second electromagnetic force generation unit faces the first electromagnetic force generation unit. The second chuck stage is chuckable for a second substrate. | 2022-03-10 |
| 20220076981 | SEALING DEVICE FOR A PEDESTAL ASSEMBLY - A substrate support for a processing region comprises a compliant sealing device comprising. The compliant sealing device comprises a coupling mechanism, a sealing device body, and a bellows. The coupling mechanism comprises a mating surface configured to interface with an opposing surface of an electrostatic chuck. The mating surface is configured to form a separable seal when disposed against the opposing surface of the electrostatic chuck. The sealing device body is connected to the coupling mechanism and comprises a passageway. The bellows surrounds the sealing device body. | 2022-03-10 |
| 20220076982 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided. | 2022-03-10 |
| 20220076983 | PARALLEL ASSEMBLY OF DISCRETE COMPONENTS ONTO A SUBSTRATE - A method includes transferring multiple discrete components from a first substrate to a second substrate, including illuminating multiple regions on a top surface of a dynamic release layer, the dynamic release layer adhering the multiple discrete components to the first substrate, each of the irradiated regions being aligned with a corresponding one of the discrete components. The illuminating induces a plastic deformation in each of the irradiated regions of the dynamic release layer. The plastic deformation causes at least some of the discrete components to be concurrently released from the first substrate. | 2022-03-10 |
| 20220076984 | Multi-Axis Motion System with Decoupled Wafer Chuck Support and Methods of Use and Manufacture - The present application discloses a multi-axis motion system and methods of use, using an air bearing configured to position a semiconductor wafer chuck support relative to an inspection device. The air bearing includes a vacuum clamping function operative to secure the wafer chuck support to a surface formed on the underside of a structure that houses the inspection device. In one embodiment, the system includes a first positioner operative to position a carriage assembly in a first direction, the carriage assembly including a second positioner and a third positioner operative to selectively and independently travel in a second direction orthogonal to the first direction. The chuck support is secured to the positioners by one or more pivoting decoupling systems configured to transmit actuation forces from the positioners in the first and second directions, allowing the chuck support to be decoupled from the positioners when the chuck support is vacuum clamped to the underside of the structure. | 2022-03-10 |
| 20220076985 | WAFER SUPPORT, WAFER PROCESSING DEVICE AND WAFER PROCESSING METHOD - Disclosed are a wafer support, a wafer processing device and a wafer processing method. The wafer support includes a cylinder, a sidewall of the cylinder including a first wall surface facing a wafer, a second wall surface facing away from the wafer and two third wall surfaces connected to the first wall surface and the second wall surface, the first wall surface being arranged opposite to the second wall surface, the two third wall surfaces being arranged opposite to each other, the two third wall surfaces being arranged at an angle, and a distance between the two third wall surfaces gradually decreasing in a direction close to the first wall surface; and one or more supporting blocks sequentially spaced apart on the first wall surface from top to bottom, the supporting block being configured to support the wafer. | 2022-03-10 |
| 20220076986 | REPLACING END EFFECTORS IN SEMICONDUCTOR PROCESSING SYSTEMS - A method of replacing an end effector for wafer handling in a semiconductor processing system includes fixing a first end effector jig to a first stage and a second end effector jig to a second stage of the load lock module; positioning a first end effector at the first end effector jig and a second end effector at the second end effector jig, the second end effector fixed relative to the first end effector; and fixing the second end effector to the second end effector jig. The first end effector is replaced with a replacement end effector and the semiconductor processing system returned to production without re-teaching placement of the replacement end effector in a processing module connected to a wafer handling module mounting the end effectors. Semiconductor processing systems and end effector jigs for replacing end effectors in semiconductor processing systems are also described. | 2022-03-10 |
| 20220076987 | PIN-LIFTING DEVICE HAVING STATE MONITORING - Disclosed is a pin lifting device which is designed for moving and positioning a substrate to be processed, in particular a wafer, in a process atmosphere region which can be provided by a vacuum process chamber. The pin lifting device includes a coupling designed to receive a support pin adapted to contact and support the substrate, and a drive unit designed and interacting with the coupling such that the coupling is linearly adjustable along an axis of adjustment from a lowered normal position to an extended support position and back. The pin lifting device has at least one sensor unit which is designed and arranged in such a way that force-dependent and/or acceleration-dependent condition information can be generated by means of the sensor unit with reference to at least part of the pin lifting device. | 2022-03-10 |
| 20220076988 | BACK SIDE DESIGN FOR FLAT SILICON CARBIDE SUSCEPTOR - A susceptor for use in a processing chamber for supporting a wafer includes a susceptor substrate having a front side and a back side opposite the front side, and a coating layer deposited on the susceptor substrate. The front side has a pocket configured to hold a wafer to be processed in a processing chamber, the pocket being textured with a first pattern. The back side is textured with a second pattern. | 2022-03-10 |
| 20220076989 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME - A semiconductor structure and a method for forming the same are provided. The method for forming a semiconductor structure includes the following operations. A substrate is provided. A dielectric layer having a first trench is formed on the substrate. A first filling layer is formed for partially filling the first trench. A first mask layer having a first opening is formed on the dielectric layer. The first opening exposes the first filling layer and part of the dielectric layer. The dielectric is etched by taking the first mask layer as a mask to form a second trench. The first filling layer is removed. And, conductive materials are formed in the first trench and the second trench. | 2022-03-10 |
| 20220076990 | ISOLATOR - An isolator includes a first insulating portion, a first electrode provided in the first insulating portion, a second insulating portion provided on the first insulating portion and the first electrode, a third insulating portion provided on the second insulating portion, and a second electrode provided in the third insulating portion. The second insulating portion includes a plurality of first voids and a second void. The plurality of first voids are arranged in a first direction parallel to an interface between the first insulating portion and the second insulating portion. At least one of the first voids is provided under the second void. | 2022-03-10 |
| 20220076991 | SUBSTRATE OF THE SEMI-CONDUCTOR-ON-INSULATOR TYPE FOR RADIOFREQUENCY APPLICATIONS - A semiconductor-on-insulator substrate for radio-frequency applications, comprises: —a silicon carrier substrate, —an electrically insulating layer arranged on the carrier substrate, —a single-crystal layer arranged on the electrically insulating layer, the substrate being characterized in that it further comprises a layer of silicon carbide SiC arranged between the carrier substrate and the electrically insulating layer, which has a thickness between 1 nm and 5 nm, the surface of the layer of silicon carbide SiC that is on the side of the electrically insulating layer being rough. | 2022-03-10 |
| 20220076992 | SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS - A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region. | 2022-03-10 |
| 20220076993 | SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS, AND METHOD FOR MANUFACTURING SUCH A STRUCTURE - The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer. | 2022-03-10 |
