| 10th week of 2012 patent applcation highlights part 51 |
| Patent application number | Title | Published |
|---|
| 20120059945 | Data-Transfer Method and Terminal - A first terminal connectable to a wireless LAN pre-stores utilization information required in order for a terminal to utilize the wireless LAN. At least one of either the first terminal, or a second terminal connectable to the wireless LAN, determines whether a predetermined operation requesting data transfer is present in the one terminal, and on the basis of the predetermined operation the first terminal transfers its stored utilization information via wireless means to the second terminal. The second terminal stores the utilization information transferred from the first terminal. | 2012-03-08 |
| 20120059946 | BANDWIDTH ALLOCATION WITH MODIFIED SEEK FUNCTION - A computer-implemented method, apparatus, system, article of manufacture, and computer readable storage medium provide the ability to stream media content to multiple users. A first stream of/for the media content is streamed from a first location in the media content to a first user. A request is received from the first user to seek to a seek location (e.g., forward or backward) in the media content. A second location in the media content compatible with the seek location is determined. The second location is based on a second stream being streamed to one or more second users. The second stream is then streamed to the first user and the second user. | 2012-03-08 |
| 20120059947 | APPARATUS, SYSTEMS AND METHODS FOR STORING MUSIC PROGRAM CONTENT EVENTS RECEIVED IN A CONTENT STREAM - Systems and methods are operable to store music program content events received in a content stream. An exemplary system and method stores the content stream that includes at least an initial portion of a music program content event, receives a request to store the music program content event, accesses the stored content stream, identifies a start of the music program content event in the accessed content stream, and re-stores the initial portion of the music program content event based upon the start of the music program content event. Then, the exemplary system and method receives a continuing portion of the music program content event in the content stream, and stores the continuing portion of the music program content event with the initial portion of the music program content event. Accordingly, an entirety of the music program content event is stored. | 2012-03-08 |
| 20120059948 | Methods for Transmitting and Receiving Data Contents, Corresponding Source and Destination Nodes and Storage Means - A method is proposed for transmitting at least two data contents by means of a source node to a destination node via at least two transmission paths. The method for transmitting includes steps of: sub-dividing each content into a succession of elementary data groups according to a predetermined pattern of repetition comprising at least two types of different elementary groups; transmitting elementary groups on at least one of the paths, according to a predefined alternation of elementary groups resulting from the sub-division of at least two different contents. | 2012-03-08 |
| 20120059949 | Internet Multimedia Advertisement Insertion Architecture - An architecture for inserting listener targeted advertisements into Internet retransmission of terrestrial radio broadcasts is provided. An Internet server provides aggregation of a plurality of radio broadcast programming for dissemination over the Internet to a plurality of listeners/users. Each Internet provided radio broadcast includes advertisements targeted for each individual listener/user based on a demographics profile. The demographics profile for each listener/user provides a basis for the targeted advertisements. A readily scaleable architecture is capable of supporting rapid growth in listeners/users. Scheduling data is used to predict and prestage advertising content. Timestamping of the radio broadcast aids in calculating where in the broadcast data sequence to pick up after an advertisement. Scalability is preferably achieved by a multiplexer in order to support large numbers of listener connections for streaming audio. | 2012-03-08 |
| 20120059950 | Method and Apparatus for Carrying Transport Stream - The present invention discloses a method and an apparatus for bearing a Transport Stream (TS). The method includes: extracting TS packets continuously from the TS to constitute one or more sampling units, and obtaining index information of the sampling units; writing the sampling units into a data portion of a streaming media file, and generating an index portion of the streaming media file according to the index information. The present invention can encapsulate the TS into the streaming media files, so that the TS can be read by a standard streaming media file analyzing program, which facilitates multi-party interaction of the TS data in the streaming media field, and improves the practicability of the TS in the streaming media field. | 2012-03-08 |
| 20120059951 | METHOD AND APPARATUS FOR ADAPTIVE BIT RATE SWITCHING - A method and apparatus for adaptively receiving media streams of different bit rates is disclosed. Data describing the variability of the bit rate of different versions of a media program is transmitted to the media player, and used by the media player to select the appropriate version for reception over the communication channel. | 2012-03-08 |
| 20120059952 | METHOD AND APPARATUS FOR GENERATING CONTROL PACKET - Methods and apparatuses directed to generating a control packet, which may involve generating data rate information indicating whether a device supports a data rate modifying function regarding uncompressed data; and generating a control packet including the data rate information. Data rate information indicates whether a device supports a data rate modifying function regarding compressed data. Control packets may be exchanged between devices to determine a modified data rate and a type of data packet to be sent. | 2012-03-08 |
| 20120059953 | SYSTEMS AND METHODS FOR DISPLAYING PERSONALIZED MEDIA CONTENT - Systems and methods for generating and/or displaying personalized video content are provided. In some embodiments, a video asset made up of a set of frames, including a preliminary frame with an object region, is received at user equipment. A media element is identified and transmitted to a remote server, where it is processed to produce a modified version of the media element and then transmitted back to the user equipment. The video asset is displayed at the user equipment, except that a modified frame incorporating the modified version of the media element is displayed in place of the preliminary frame. The modified version of the media element is incorporated in an area of the modified frame corresponding to the object region of the preliminary frame. | 2012-03-08 |
| 20120059954 | PROVIDING ENHANCED CONTENT - Methods, systems, computer readable media, and apparatuses for providing enhanced content are presented. Data including a first program, a first caption stream associated with the first program, and a second caption stream associated with the first program may be received. The second caption stream may be extracted from the data, and a second program may be encoded with the second caption stream. The first program may be transmitted with the first caption stream including first captions and may include first content configured to be played back at a first speed. In response to receiving an instruction to change play back speed, the second program may be transmitted with the second caption stream. The second program may include the first content configured to be played back at a second speed different from the first speed, and the second caption stream may include second captions different from the first captions. | 2012-03-08 |
| 20120059955 | TRANSITION AN INPUT/OUTPUT DEVICE - Managing an input/output device including receiving a request to remotely connect a computing machine with a device, detecting an signal to power down the input/output device of the computing machine in response to establishing a remote connection with the device, and transitioning the input/output device from a first power state to second power state in response to detecting the signal. | 2012-03-08 |
| 20120059956 | DIRECT MEMORY ACCESS (DMA) TRANSFER OF NETWORK INTERFACE STATISTICS - In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor. | 2012-03-08 |
| 20120059957 | AUTOMATIC PORT ACCUMULATION - In a first embodiment of the present invention, a method for configuring a plurality of input/output (I/O) interconnect switch ports is provided, the method comprising: starting a link training and status state machine (LTSSM) for each of the plurality of ports; placing each of the LTSSMs in a receiver detect state; changing all of the LTSSMs to a polling state only once receivers are detected or timeouts occur in the receiver detect states in each of the LTSSMs; changing all of the LTSSMs to a configuration state only once polling is successful or timeouts occur in the polling states in each of the LTSSMs; and completing the configuration state of each of the LTSSMs. | 2012-03-08 |
| 20120059958 | SYSTEM AND METHOD FOR A HIERARCHICAL BUFFER SYSTEM FOR A SHARED DATA BUS - The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing. | 2012-03-08 |
| 20120059959 | Method for Assigning Addresses to Nodes of a Bus System, and Installation - A method for assigning addresses to nodes of a bus system, and installation, | 2012-03-08 |
| 20120059960 | METHOD FOR CONTROLLING A DATA TRANSFER ON A SERIAL TRANSMISSION DATA TRANSFER BUS - Method for controlling a data transfer on a serial transmission data transfer bus by means of a central processing unit and associated system. The method includes various steps, including determining an available bandwidth for a data bus, determining an available computing capacity percentage of the central processing unit, and determining a maximum data rate that a data transfer can be performed on the data bus based on the available bandwidth and the available computing capacity percentage. Furthermore, the method provides that the data transfer rate is controlled to not exceed the maximum data rate. | 2012-03-08 |
| 20120059961 | SYSTEM AND METHOD FOR SHARING MEMORY - A system and method for interfacing multiple SoCs (System on a Chip) to a single, shared memory device are provided. The system and method of the present disclosure provides for controlling the downloading of operating code to two or more SoC controller circuits sharing a memory containing the operating code and a common communications bus, where each controller is a master controller of the communications bus in normal operation. The system and method involves sequentially controlling access of each of the controller circuits to the communications bus to allow each device to separately download the common operating code. The system and method utilize a separate initializing circuit or device along with chaining the controllers together in a series such that each controller be held in a reset state to prevent communications bus access until the previous controller in the chain has completed its code download. | 2012-03-08 |
| 20120059962 | PROVIDING A FINE-GRAINED ARBITRATION SYSTEM - In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed. | 2012-03-08 |
| 20120059963 | Adaptive Locking of Retained Resources in a Distributed Database Processing Environment - System, method, computer program product embodiments and combinations and sub-combinations thereof for adaptive locking of retained resources in a distributed database processing environment are provided. An embodiment includes identifying a locking priority for at least a portion of a buffer pool, determining lock requests based upon the identified locking priority, and granting locks for the lock requests. | 2012-03-08 |
| 20120059964 | HIGH DENSITY, LOW JITTER, SYNCHRONOUS USB EXPANSION - A method of providing high density expansion of a USB network, the method comprising: attaching a plurality of USB hubs to adjacent slots in a PXI instrumentation chassis; configuring one of the USB hubs as a primary USB Hub; connecting an upstream port of the primary USB Hub to a USB network; configuring a first downstream port of the primary USB Hub to communicate across a first PXI Local Bus to a first adjacent USB Hub of the USB Hubs other than the primary USB Hub, the first adjacent USB Hub being adjacent to the primary USB Hub; configuring a plurality of other downstream ports of the primary USB Hub to provide expansion of the primary USB Hub; connecting an upstream port of the first adjacent USB Hub to the first PXI Local Bus, wherein the first PXI Local Bus is in the direction of the primary USB Hub; configuring a first downstream port of the first adjacent USB Hub to communicate across a second PXI Local Bus to a second adjacent USB Hub of the USB Hubs other than the primary USB Hub, the second adjacent USB Hub being adjacent to the first adjacent USB Hub; configuring a plurality of other downstream ports of the first adjacent USB Hub to provide expansion of the first adjacent USB Hub; and configuring any other of the USB hubs and the first adjacent USB Hub in like manner. | 2012-03-08 |
| 20120059965 | PRECISION SYNCHRONISATION ARCHITECTURE FOR SUPERSPEED UNIVERSAL SERIAL BUS DEVICES - A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines. | 2012-03-08 |
| 20120059966 | STORAGE DEVICE AND METHOD FOR MANAGING SIZE OF STORAGE DEVICE - The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. | 2012-03-08 |
| 20120059967 | MEMORY BUS ARCHITECTURE FOR CONCURRENTLY SUPPORTING VOLATILE AND NON-VOLATILE MEMORY MODULES - A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus. | 2012-03-08 |
| 20120059968 | PROCESSING SYSTEM WITH RF DATA BUS FOR INTRA-DEVICE COMMUNICATION - A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via intra-device RF communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via intra-device RF communications to at least one of the plurality of second circuit modules. | 2012-03-08 |
| 20120059969 | NON-INVASIVE DIRECT-MAPPING USB SWITCHING DEVICE - A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function. | 2012-03-08 |
| 20120059970 | MEMORY CONTROLLER SUPPORTING CONCURRENT VOLATILE AND NONVOLATILE MEMORY MODULES IN A MEMORY BUS ARCHITECTURE - A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus. | 2012-03-08 |
| 20120059971 | METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING - The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load. | 2012-03-08 |
| 20120059972 | HYBRID STORAGE APPARATUS AND HYBRID STORAGE MEDIUM CONTROLLLER AND ADDRESSING METHOD THEREOF - A hybrid storage apparatus including a non-volatile memory module, a hard disk module, and a hybrid storage medium controller is provided. The hybrid storage medium controller groups physical bocks of the non-volatile memory module into at least a storage area and a replacement area, and the hybrid storage medium controller configures a plurality of logical blocks for mapping to the physical blocks in the storage area and configures a plurality of logical disk addresses for mapping to physical disk addresses of the hard disk module. The hybrid storage medium controller further configures a plurality of logical access addresses to be accessed by a host system and initially maps a portion of the logical access addresses to the logical blocks and the other logical access addresses to a portion of the logical disk addresses. Accordingly, the hybrid storage apparatus can have improved data access performance and prolonged lifespan. | 2012-03-08 |
| 20120059973 | HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE WITH GUEST PAGE MAPPINGS - Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a shadow page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the shadow page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the shadow page mapping. The MMU is further configured to perform the write access. | 2012-03-08 |
| 20120059974 | METHOD AND APPARATUS FOR IMPROVING COMPUTER SYSTEM PERFORMANCE BY ISOLATING SYSTEM AND USER DATA - An apparatus comprising a logic unit to separate system data and user data from host data to be processed by a processor; a first memory to store the system data separated by the logic unit; and a second memory to store the user data separated by the logic unit, wherein the first memory is a non-volatile memory which is physically located closer to the processor than the second memory. | 2012-03-08 |
| 20120059975 | PROCESSOR INDEPENDENT LOOP ENTRY CACHE - A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump. | 2012-03-08 |
| 20120059976 | STORAGE ARRAY CONTROLLER FOR SOLID-STATE STORAGE DEVICES - A storage array controller provides a method and system for autonomously issuing trim commands to one or more solid-state storage devices in a storage array. The storage array controller is separate from any operating system running on a host system and separate from any controller in the solid-state storage device(s). The trim commands allow the solid-state storage device to operate more efficiently. | 2012-03-08 |
| 20120059977 | ELECTRONIC DEVICE, CONTROLLER FOR ACCESSING A PLURALITY OF CHIPS VIA AT LEAST ONE BUS, AND METHOD FOR ACCESSING A PLURALITY OF CHIPS VIA AT LEAST ONE BUS - An electronic device includes a plurality of chips, at least a bus and a controller, where the plurality of chips include a first chip and a second chip, the bus includes a plurality of data lines, the controller couples to the plurality of chips via the bus, and the controller is utilized for accessing the plurality of chips. The controller determines an allocation for data transmission of external data according to information about which chip the external data will be written to, where the allocation for data transmission is an arrangement of a plurality of bits of the external data transmitted on the plurality of data lines, and a first allocation for data transmission corresponding to the first chip is different from a second allocation for data transmission corresponding to the second chip. | 2012-03-08 |
| 20120059978 | Storage array controller for flash-based storage devices - The invention is an improved storage array controller that adds a level of indirection between host system and storage array. The storage array controller controls a storage array comprising at least one solid-state storage device. The storage array controller improvements include: garbage collection, sequentialization of writes, combining of writes, aggregation of writes, increased reliability, improved performance, and addition of resources and functions to a computer system with a storage subsystem. | 2012-03-08 |
| 20120059979 | MEMORY MANAGEMENT APPARATUS AND MEMORY MANAGEMENT METHOD - A terminal apparatus including a non-volatile memory for which writing is performed in units of blocks; and a control unit configured to perform a first method of managing bad blocks in the non-volatile memory with respect to blocks corresponding to an information management table in a file system of the non-volatile memory, and to perform a second method of managing bad blocks in the non-volatile memory with respect to blocks corresponding to user data in the file system. | 2012-03-08 |
| 20120059980 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 2012-03-08 |
| 20120059981 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY - An apparatus, system, and method are disclosed for storage space recovery. A storage division selection module selects a first storage division for recovery. The first storage division comprises a portion of solid-state storage in a solid-state storage device. A data recovery module reads valid data from the first storage division in response to selecting the first storage division for recovery. The data recovery module stores the valid data in a second storage division of the solid-state storage device. The data recovery module passes the valid data through at least a portion of a write data pipeline for the solid-state storage device without passing the valid data to a host device and/or without routing the valid data outside of a solid-state storage controller for the solid-state storage device. | 2012-03-08 |
| 20120059982 | INTEGRATED CIRCUIT FOR EXECUTING EXTERNAL PROGRAM CODES AND METHOD THEREOF - An integrated circuit for executing external program codes comprises a processor, a read only memory for storing program codes of a first routine and a second routine, and a random access memory comprising a first memory block and a second memory block. The processor executes the first routine and uses a plurality of first memory units in the first memory block for accessing data. The processor executes the second routine and uses a plurality of second memory units in the first memory block for accessing data. The first and second memory units comprise one or more common memory units. The processor executes a third routine stored in an external read only memory and accesses the data of the third routine in the second memory block. | 2012-03-08 |
| 20120059983 | PREDICTOR-BASED MANAGEMENT OF DRAM ROW-BUFFERS - A method for managing memory includes storing a history of accesses to a memory page, and determining whether to keep the memory page open or to close the memory page based on the stored history. A memory system includes a plurality of memory cells arranged in rows and columns, a row buffer, and a memory controller configured to manage the row buffer at a per-page level using a history-based predictor. A non-transitory computer readable medium is also provided containing instructions therein, wherein the instructions include storing an access history of a memory page in a lookup table, and determining an optimal closing policy for the memory page based on the stored histories. The histories can include access numbers or access durations. | 2012-03-08 |
| 20120059984 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias. | 2012-03-08 |
| 20120059985 | SYSTEMS AND METHODS FOR ALLOCATING CONTROL OF STORAGE MEDIA IN A NETWORK ENVIRONMENT - A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device. | 2012-03-08 |
| 20120059986 | DISK APPARATUS, DATA REPLICATING METHOD ONTO DISK APPARATUS AND PROGRAM RECORDING MEDIUM - A disk apparatus includes a second volume to which data of a first volume is copied, a third volume which stores a snapshot of the first volume, and an I/O processing unit which reads out data from the third volume when data of an area in which difference data exists in the third volume is read out, when data of an address in which the difference data does not exist in the third volume is read out, reads out data from the first volume if data copying from the first volume to the second volume has not been completed, and reads out data from the second volume if the data copying has been completed. | 2012-03-08 |
| 20120059987 | STORAGE SYSTEM, COPY METHOD, AND PRIMARY STORAGE APPARATUS - A storage system having a primary storage apparatus for storing data from a host computer in a primary logical volume, and a secondary storage apparatus connected to the primary storage apparatus, for providing a secondary logical volume for storing a copy of the data, the storage system comprising: a search unit for checking whether or not data exists in each primary slot area formed by partitioning a storage area in the primary logical volume into predetermined storage areas; a transmission unit for sending, if no data is held in the primary slot area, a notice indicating no data stored to the secondary storage apparatus; and a data write unit for writing, when the notice is received from the primary storage apparatus, zero data in the secondary slot area. | 2012-03-08 |
| 20120059988 | STORAGE APPARATUS AND DATA ACCESS METHOD - Improving response time performance by executing exclusive extent processing of a plurality of I/O requests is proposed. A storage apparatus, which includes a plurality of microprocessors, a first memory which stores counter values indicating the order of the I/Os to and from the storage areas, and a second memory which stores control information of the I/O requests for each of the I/O requests, is configured such that the microprocessors store, if there is one I/O request from the host apparatus, an I/O request range of the one I/O request in an area for storing control information of the one I/O request of the second memory, the microprocessors acquire the counter value from the first memory and store the counter value in the area for storing control information of the one I/O request of the second memory, and the microprocessors compare, if the counter value of the one I/O request is greater than the counter value of another I/O request, the I/O request range of the one I/O request stored in the second memory with the I/O request range of the other I/O request. | 2012-03-08 |
| 20120059989 | CLUSTER TYPE STORAGE SYSTEM AND METHOD OF CONTROLLING THE SAME - The present invention can adjust the ratio between a global namespace storage area and a local namespace storage area. Each of the nodes adjusts the ratio between GNS storage areas and LNS storage areas of logical volumes according to the operating condition. When received a LNS-based access request as an access request for storing business affair data from each client, each of the nodes store the business affair data in their own LNS storage areas. When received a GNS-based access request, the node checks the unused capacity of the GNS storage areas of each of the nodes, and transfers the business affair data via a network switch to the node which comprises a logical volume with the largest unused capacity. | 2012-03-08 |
| 20120059990 | STORAGE APPARATUS AND CONTROL METHOD OF STORAGE APPARATUS - A start time of recovery processing performed during a fall-back operation of the RAID can be flexibly controlled. A storage apparatus including an I/O processing unit that receives a data input/output request sent from an information processing device communicatively coupled to the I/O processing unit, and performs reading and writing of data from and to storage drives, includes: a priority storage unit that stores a priority set to each RAID group; a failure information storage unit that acquires and stores information on a failure occurred in the storage drives; a blockage processing unit that determines whether or not to block each of the storage drive based on the information on the failure, and blocks the storage drive that is determined to be blocked; a start time calculation unit that calculates a start time for starting recovery processing to delete a fall-back state of the RAID group to which the blocked storage drive belongs according to the priority set to the RAID group; and a recovery processing execution unit that starts the recovery processing at the start time. | 2012-03-08 |
| 20120059991 | SYSTEM AND METHOD FOR REPRESENTATION OF TARGET DEVICES IN A STORAGE ROUTER - The present invention provides an improved device, system and method for representation of target devices in a storage router. In one aspect, a device, system and method are provided for predictive representation of SAS/SATA-based target devices in a storage router corresponding to the physical layout of the target devices. In another aspect, a storage router is communicatively connectable to a plurality of target storage devices. In one embodiment, a router discovery manager or module is configured to discover the physical layout of the target storage devices; a host system interface receives and responds to data storage commands; a computer bus interface connects/communicates with SAS and SATA storage; and a plurality of host system interface to target storage device maps correspond to the physical layout of the target storage devices. | 2012-03-08 |
| 20120059992 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 2012-03-08 |
| 20120059993 | SECURE EXECUTION OF NATIVE CODE - A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed. | 2012-03-08 |
| 20120059994 | USING A MIGRATION CACHE TO CACHE TRACKS DURING MIGRATION - Provided are a method, system, and computer program product for using a migration cache to cache tracks during migration. Indication is made in an extent list of tracks in an extent in a source storage subject to Input/Output (I/O) requests. A migration operation is initiated to migrate the extent from the source storage to a destination storage. In response to initiating the migration operation, a determination is made of a first set of tracks in the extent in the source storage indicated in the extent list. A determination is also made of a second set of tracks in the extent. The tracks in the source storage in the first set are copied to a migration cache, wherein updates to the tracks in the migration cache during the migration operation are applied to the migration cache. The tracks in the second set are copied directly from the source storage to the destination storage without buffering in the migration cache. The tracks in the first set are copied from the migration cache to the destination storage. The migration operation is completed in response to copying the first set of tracks from the migration cache to the destination storage and copying the second set of tracks from the source storage to the destination storage, wherein after the migration the tracks in the extent are located in the destination storage. | 2012-03-08 |
| 20120059995 | Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy - Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation. | 2012-03-08 |
| 20120059996 | Avoiding Cross-Interrogates in a Streaming Data Optimized L1 Cache - A mechanism is provided for avoiding cross-interrogates for a streaming data optimized level one cache. The mechanism adds a set of dedicated registers, referred to as “copex registers,” to track ownership of the cache lines that the co-processor's L1 cache holds exclusive. The mechanism extends the cache directory of the L2 cache by a bit that identifies exclusive ownership of a cache line in the co-processor cache. The co-processor continuously provides an indication of which copex registers are valid. On any action that requires a directory lookup in the L2 cache, the mechanism compares the valid copex registers against the lookup address in parallel to the directory lookup. The mechanism considers the “exclusive ownership in co-processor” bit in the directory valid only if the cache line is also currently in a valid copex register. | 2012-03-08 |
| 20120059997 | APPARATUS AND METHOD FOR DETECTING DATA RACE - An apparatus and method for detecting a data race of a multithread system is provided. A thread may be divided into an open sub region or a closed sub region according to a vector clock and an execution state. In order to detect a data race before the execution is terminated, when an open sub region is converted to a closed sub region, a memory access event corresponding to the closed sub region is investigated and a memory access event having no parallel relation with an open sub region is deleted among memory access events having been subject to the investigation. | 2012-03-08 |
| 20120059998 | BIT MASK EXTRACT AND PACK FOR BOUNDARY CROSSING DATA - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full. | 2012-03-08 |
| 20120059999 | METHODS AND SYSTEMS FOR STORING VARIABLE WIDTH STACK ELEMENTS IN A SINGLE MEMORY STACK - A system and method for storing variable width stack elements in a single memory stack is disclosed. In one example embodiment a first variable width stack element is split into one or more sub-elements. The width of the sub-elements may be less than or equal to a width of the single memory stack. A first memory pointer is created for providing an address of a first read pointer in the single memory stack. The first read pointer may provide an address corresponding to a first sub-element of the first variable width stack element. The first sub-element is written in a first available location in the single memory stack. A write pointer of the single memory stack is incremented when the first sub-element is written to the first available location on the single memory stack. The steps of writing and incrementing are repeated for a next sub-element until all of the sub-elements are stored in the single memory stack. | 2012-03-08 |
| 20120060000 | SYSTEM AND METHOD FOR FLEXIBLY STORING, DISTRIBUTING, READING, AND SHARING ELECTRONIC BOOKS - An electronic book card includes a communication interface that can communicate with a host reading device having a display device configured to display images in a display configuration. The communication interface can receive the display configuration from the host reading device. A non-volatile memory can store content of an electronic book. A data processing unit can generate page images in accordance with the display configuration of the display device. The page images incorporate the content of the electronic book. | 2012-03-08 |
| 20120060001 | MEMORY LIFETIME GAUGING SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT - Techniques are taught for reducing writes, and estimating and displaying estimated remaining lifetime of non-volatile memories. The write reducing is optionally via determining a difference between write operation results and data stored in the non-volatile memories. The estimated remaining lifetime is optionally based at least in part on a previous lifetime. The displaying is optionally via a gauge. | 2012-03-08 |
| 20120060002 | SYSTEM AND METHOD FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES - A storage subsystem receives writes from a computer via a standard storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two. | 2012-03-08 |
| 20120060003 | MEMORY CONTROL CIRCUIT, MEMORY CONTROL METHOD, AND INTEGRATED CIRCUIT - Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed. | 2012-03-08 |
| 20120060004 | SYSTEM FOR VIRTUAL DISKS VERSION CONTROL | 2012-03-08 |
| 20120060005 | TECHNIQUES FOR COPYING ON WRITE - Techniques for copying on write are provided. Snapshots are managed and maintained for a source volume via sparse files. Metadata defines the sparse files and operations of a file system are used to create, define, and manipulate the metadata. | 2012-03-08 |
| 20120060006 | MANAGING ACCESS OF MULTIPLE EXECUTING PROGRAMS TO NON-LOCAL BLOCK DATA STORAGE - Techniques are described for managing access of executing programs to non-local block data storage. In some situations, a block data storage service uses multiple server storage systems to reliably store network-accessible block data storage volumes that may be used by programs executing on other physical computing systems. A group of multiple server block data storage systems that store block data volumes may in some situations be co-located at a data center, and programs that use volumes stored there may execute on other physical computing systems at that data center. If a program using a volume becomes unavailable, another program (e.g., another copy of the same program) may in some situations obtain access to and continue to use the same volume, such as in an automatic manner in some such situations. | 2012-03-08 |
| 20120060007 | TRAFFIC CONTROL METHOD AND APPARATUS OF MULTIPROCESSOR SYSTEM - A method and apparatus for controlling traffic of multiprocessor system or multi-core system is provided. The traffic control apparatus of a multiprocessor system according to the present invention includes a request handler for processing a traffic request of a first processor, and a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler. The request handler adjusts the traffic of the first processor according to the received traffic adjustment signal. The traffic control method and apparatus of the present invention is capable of adjusting the required bandwidths of individual technologies and guaranteeing the real-timeness in the multiprocessor system or multi-core system. | 2012-03-08 |
| 20120060008 | INFORMATION PROCESSING TRMINAL, METHOD, PROGRAM, AND INTEGRATED CIRCUIT FOR CONTROLLING ACCESS TO CONFIDENTIAL INFORMATION, AND RECORDING MEDIUM HAVING THE PROGRAM RECORDED THEREON - An information processing terminal ( | 2012-03-08 |
| 20120060009 | DYNAMIC BACK-UP STORAGE SYSTEM WITH RAPID RESTORE AND METHOD OF OPERATION THEREOF - A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device. | 2012-03-08 |
| 20120060010 | STORAGE SYSTEM COMPRISING FUNCTION FOR MIGRATING VIRTUAL COMMUNICATION PORT ADDED TO PHYSICAL COMMUNICATION PORT - A switch unit, which is connected to one or more computers and one or more storage systems, comprises an update function for updating transfer management information (a routing table, for example). The storage system has a function for adding a virtual port to a physical port. The storage system migrates the virtual port addition destination from a first physical port to a second physical port and transmits a request of a predetermined type which includes identification information on the virtual port of the migration target to the switch unit. The transfer management information is updated by the update function of the switch unit so that the transfer destination which corresponds with the migration target virtual port is the switch port connected to the second physical port. | 2012-03-08 |
| 20120060011 | ALLOCATING REGISTER HALVES INDEPENDENTLY - Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers. | 2012-03-08 |
| 20120060012 | MANAGEMENT OF LOW-PAGING SPACE CONDITIONS IN AN OPERATING SYSTEM - A virtual memory management unit can implement various techniques for managing paging space. The virtual memory management unit can monitor a number of unallocated large sized pages and can determine when the number of unallocated large sized pages drops below a page threshold. Unallocated contiguous smaller-sized pages can be aggregated to obtain unallocated larger-sized pages, which can then be allocated to processes as required to improve efficiency of disk I/O operations. Allocated smaller-sized pages can also be reorganized to obtain the unallocated contiguous smaller-sized pages that can then be aggregated to yield the larger-sized pages. Furthermore, content can also be compressed before being written to the paging space to reduce the number of pages that are to be allocated to processes. This can enable efficient management of the paging space without terminating processes. | 2012-03-08 |
| 20120060013 | Effective Memory Clustering to Minimize Page Fault and Optimize Memory Utilization - An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More specifically, data access requests to the cloud computing environment are monitored to identifying data addresses having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein the creating of the memory page includes creating a cross-sectional partition from the multi-dimensional cluster. The multi-dimensional clusters and the memory page are stored in the cloud computing environment. A request for a data object in the cloud computing environment is received from a user interface. The data address corresponding to the data object is identified and mapped to the multi-dimensional cluster and/or the memory page. The memory page is transferred to the user interface. | 2012-03-08 |
| 20120060014 | ELECTRONIC DEVICE AND METHOD FOR PROTECTING ELECTRONIC KEYS USING THE SAME - A method for protecting electronic keys sets a plurality of hash functions, divides an electronic key into a plurality of key segments, creates a data storage structure for each of the key segments, and calculates a hash address for each of the key segments of the electronic key using each of the hash functions. The method further obtains a plurality of hash addresses of the plurality of key segments corresponding to the plurality of hash functions, stores information of the data storage structure of each key segment in a hash table according to the hash address of the key segment corresponding to one of the hash functions. | 2012-03-08 |
| 20120060015 | Vector Loads with Multiple Vector Elements from a Same Cache Line in a Scattered Load Operation - Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor. | 2012-03-08 |
| 20120060016 | Vector Loads from Scattered Memory Locations - Mechanisms for performing a scattered load operation are provided. With these mechanisms, a gather instruction is receive in a logic unit of a processor, the gather instruction specifying a plurality of addresses in a memory from which data is to be loaded into a target vector register of the processor. A plurality of separate load instructions for loading the data from the plurality of addresses in the memory are automatically generated within the logic unit. The plurality of separate load instructions are sent, from the logic unit, to one or more load/store units of the processor. The data corresponding to the plurality of addresses is gathered in a buffer of the processor. The logic unit then writes data stored in the buffer to the target vector register. | 2012-03-08 |
| 20120060017 | PROCESSOR - A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units. | 2012-03-08 |
| 20120060018 | Collective Operations in a File System Based Execution Model - A mechanism is provided for group communications using a MULTI-PIPE synthetic file system. A master application creates a multi-pipe synthetic file in the MULTI-PIPE synthetic file system, the master application indicating a multi-pipe operation to be performed. The master application then writes a header-control block of the multi-pipe synthetic file specifying at least one of a multi-pipe synthetic file system name, a message type, a message size, a specific destination, or a specification of the multi-pipe operation. Any other application participating in the group communications then opens the same multi-pipe synthetic file. A MULTI-PIPE file system module then implements the multi-pipe operation as identified by the master application. The master application and the other applications then either read or write operation messages to the multi-pipe synthetic file and the MULTI-PIPE synthetic file system module performs appropriate actions. | 2012-03-08 |
| 20120060019 | REDUCTION OPERATION DEVICE, A PROCESSOR, AND A COMPUTER SYSTEM - A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit. | 2012-03-08 |
| 20120060020 | VECTOR INDEX INSTRUCTION FOR PROCESSING VECTORS - The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a start value and an increment value, and optionally receiving a predicate vector with N elements as inputs. The processor then executes the vector instruction. Executing the vector instruction causes the processor to generate a result vector. When generating the result vector, if the predicate vector is received, for each element in the result vector for which a corresponding element of the predicate vector is active, otherwise, for each element in the result vector, the processor sets the element in the result vector equal to the start value plus a product of the increment value multiplied by a specified number of elements to the left of the element in the result vector. | 2012-03-08 |
| 20120060021 | Method and Device For Modular Configuration Deployment At Run Time - A device includes a data interface and a memory. The memory includes a first memory area and a second memory area. The first memory area stores a base module including an operating system and boot logic operative to load a further module. The second memory area stores a module comprising a software application. The first memory area and the second memory area do not reside within a file system. | 2012-03-08 |
| 20120060022 | METHOD AND SYSTEM FOR ADJUSTING CPU FREQUENCY - A method for adjusting central processing unit (CPU) frequency according to the CPU utilization rate in a computer, the method includes the following steps. A Basic Input Output System (BIOS) is booted by turning on the computer. A performance monitor in the CPU is started by the BIOS. A timer is turned on by the BIOS. The system management interrupt program is read by the timer during a time period. A number of clock signals and time values is recorded by the performance monitor in two adjacent time periods. The CPU utilization rate is determined by the performance monitor according to number of clock signals, the time values, and a CPU clock speed. A CPU frequency is adjusted by the BIOS according to the CPU utilization rate. The computer's operation system (OS) is booted by the BIOS. | 2012-03-08 |
| 20120060023 | METHODS FOR BOOTING AN OPERATING SYSTEM USING NON-VOLATILE MEMORY - A method of booting an operating system can be provided by determining file information that is associated with files accessed during booting of an operating system by a processor. Files associated with the file information can be written into a non-volatile memory. The files can be transferred from the non-volatile memory to a volatile memory during a power on self-test of the processor. | 2012-03-08 |
| 20120060024 | MECHANISM FOR ADJUSTING SYSTEM SETTINGS BASED ON DYNAMIC DISCOVERY OF POWER USAGE - A measurement circuit measures a first power consumption value corresponding to a first configuration of a component of a computing device and a second power consumption value corresponding to a second configuration of the component. A user interface module provides a the first power consumption value for the first configuration and the second power consumption value for the second configuration. A user selection indicating one of the first configuration and the second configuration is received and a configuration module implements the configuration indicated by the user selection in the component. | 2012-03-08 |
| 20120060025 | SERVICE PROVIDER INVOCATION - A service provider may provide one or more services to and/or for a client. Providing a service may involve receiving a service request including a security token at the service provider and determining whether the security token is valid. Providing the service may also involve determining a session security token if the security token is valid and generating a service response including the session security token. Providing the service may further involve receiving a service request including the session security token, determining whether the session security token is valid, and, if the session security token is valid, generating a second service response. | 2012-03-08 |
| 20120060026 | CERTIFICATE MANAGEMENT AND TRANSFER SYSTEM AND METHOD - A method and system for Certificate management and transfer between messaging clients are disclosed. When communications are established between a first messaging client and a second messaging client, one or more Certificates stored on the first messaging client may be selected and transferred to the second messaging client. Messaging clients may thereby share Certificates. Certificate management functions such as Certificate deletions, Certificate updates and Certificate status checks may also be provided. | 2012-03-08 |
| 20120060027 | CERTIFYING THE IDENTITY OF A NETWORK DEVICE - According to one aspect, a method for certifying the identity of a network device. The method includes an initial step of coupling the network device to a provisioning device via a physically secure communications link. The provisioning device then certifies the identity of the network device including generating a cryptographic private key for the network device and sending the generated private key to the network device over the physically secure communications link. | 2012-03-08 |
| 20120060028 | SIGNATURE DEVICE, SIGNATURE VERIFICATION DEVICE, ANONYMOUS AUTHETICATION SYSTEM, SIGNING METHOD, SIGNATURE AUTHENTICATION METHOD, AND PROGRAMS THEREFOR | 2012-03-08 |
| 20120060029 | METHOD AND SYSTEM FOR DYNAMIC SECURED GROUP COMMUNICATION - A system and method directed to carrying out dynamic secured group communication is provided. The method includes: obtaining a first packet that includes a first header; forming a frame that includes the first header in encrypted form; combining the first header and the frame to form a second packet and forming a second header; encapsulating the second packet with the second header to form a third packet, and communicating the third packet into the second network from the second source node for termination to the second-destination node. The first header includes a first source address of a first source node of a first network, and a first destination address of a first destination node of the first network. The second header includes a second source address of a second source node of a second network, and a second destination address of a second destination node of the second network. | 2012-03-08 |
| 20120060030 | SYSTEM AND METHOD OF PROVIDING TRUSTED, SECURE, AND VERIFIABLE OPERATING ENVIRONMENT - A method and system of synergizing hardware, firmware, software, and useful feature(s) into a trusted, secure, and verifiable operating environment (TSVOE) that is critical for businesses and consumers that rely on information technology products and/or services. Such products provide various capabilities such as protecting the corporate infrastructure from attack, protecting the client from attack, designing a customizable operating schema, advanced validation of client authentication, establishing a clean environment within a dirty environment, etcetera. Moreover, by ensuring that operating environment security is achieved, a product can provide guarantees that modern state-of-the-art systems cannot. Finally, diversification of hardware, software, firmware, and features creates robust products. | 2012-03-08 |
| 20120060031 | SECURE VIDEO CONTENT PROVISIONING USING DIGITAL RIGHTS MANAGEMENT - A method that includes receiving a first request for video content from a user of a user device; retrieving an identifier for the user device using an application programming interface; sending a second request to receive the video content that includes the identifier; receiving an instruction to provide payment to rent or purchase the video content; sending the payment in response to the instruction; receiving the video content and a token, where the video content is encrypted based on a key and where the token indicates that the payment was processed; sending a third request to obtain a license associated with the video content that includes the token and the identifier; receiving the license, which includes the key and terms under which the video content is to be processed; decrypting the video content, using the key, when the decrypting is performed in a manner permitted by the terms; and playing the decrypted video content. | 2012-03-08 |
| 20120060032 | SYSTEM, METHOD AND COMPUTER PRODUCT FOR SENDING ENCRYPTED MESSAGES TO RECIPIENTS WHERE THE SENDER DOES NOT POSSESS THE CREDENTIALS OF THE RECIPIENT - A system for encrypting and decrypting messages using a browser in either a web or wireless device or secure message client software for transmission to or from a web server on the Internet connected to an email server or message server for the situation where the sender does not possess the credentials and public key of the recipients. The encryption and decryption is conducted using a standard web browser on a personal computer or a mini browser on a wireless device, or message client software on either a personal computer or wireless devices such that messages transmitted to the web or wireless browser or message client software can be completed and encrypted and signed by the user such that encrypted and signed data does not require credentials and public key of the recipients. A method for delivering and using private keys to ensure that such keys are destroyed after use is also provided. A method of transmitting encrypted messages to a web or wireless browser or message client and decrypting and verifying such messages by recipients who do not possess or who are not enrolled in a PKI and do not have private keys. A method for authenticating the sender/user of the browser, and a method for accessing or generating public and private keys for encrypting and decrypting messages for recipients who are not enrolled in a public key infrastructure. | 2012-03-08 |
| 20120060033 | SPLIT KEY SECURE ACCESS SYSTEM - The present invention is a secure access system whereby the key that facilitates entrance to electronic data is split into at least two segments. Electronic data may be accessed by the application of the key segments in combination. A server may be used to derive key segments by way of algorithms, in a manner that improves the bit security of the key. Bit strings generated by the present invention may be concatenated to form data blocks whereby plaintext may be encrypted or ciphertext decrypted. The concatenation of the unique bit string variables and the generation of bit strings of specific sizes, as may occur through padding of blocks, work to provide a secure means of encrypting a key. A different bit string may be generated for each encryption/decryption transmission which limits the opportunity for an adversary to decrypt the plaintext. | 2012-03-08 |
| 20120060034 | DIGITAL INFORMATION STREAM COMMUNICATION SYSTEM AND METHOD - A digital information stream communication (DISC) system within a first conditional access system (CAS) is disclosed. The DISC system communicates information from a digital information stream (DIS) having DIS attributes for accessibility using the first CAS or associated with a digital media (DM) content in the DIS. The DISC system includes a monitoring module configured to receive the DIS and identify one or more of the DIS attributes for accessibility using the first CAS. The DISC system also includes a processing module configured to identify one or more of the DIS attributes associated with the DM content and analyze the DIS attributes. It does this to determine whether to send DIS data from the DIS to a second CAS based upon the DIS data being included in the DIS attributes. The DISC system also includes a processor configured to operate the monitoring module and the processing module. | 2012-03-08 |
| 20120060035 | Secure and Verifiable Data Handling - The described implementations relate to secure and verifiable data handling. One implementation can receive a request to add information from a drop-off site to a user account. The request can include a location element and a security element. This implementation can also obtain encrypted units of the referenced data from the drop-off site based upon the location element. This implementation can associate the information with the user account and store the security element. | 2012-03-08 |
| 20120060036 | Method of Providing Transactions Employing Advertising Based Verification - A method of improving electronic security establishes a secure trusted path between a user and an institution seeking an electronic signature to verify a transaction before any request for signature and completing electronic transaction activities occurs. The secure trusted path providing the user with a first predetermined portion of a branded watermark, for instance an advertisement, provided from the institution in conjunction with the request, and a second predetermined portion of the branded watermark being provided upon a personalized device that cannot be intercepted or manipulated by malware, allowing the user to verify that the request as displayed upon the user's primary computing device is valid. | 2012-03-08 |
| 20120060037 | PROTECTING AGAINST DIFFERENTIAL POWER ANALYSIS ATTACKS ON DECRYPTION KEYS - An embodiment of a method is disclosed for protecting a key from discovery during decryption of a data stream. This embodiment of the method includes decrypting the data stream with the key. Before completing decryption of the data stream, the method checks consistency between a decrypted portion of the data stream and expected data using a circuit arrangement. In response to an inconsistency between the decrypted portion and the expected data, a tampering signal is generated to indicate tampering is suspected. | 2012-03-08 |
| 20120060038 | PROTECTING AGAINST DIFFERENTIAL POWER ANALYSIS ATTACKS ON SENSITIVE DATA - An embodiment of a method is disclosed for protecting sensitive data from discovery during an operation performed on input data with the sensitive data. This embodiment of the method includes performing the operation on a first quantity of random data with the sensitive data using a circuit arrangement before performing the operation with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the first quantity of the random data, the operation is performed with the sensitive data on the input data using the circuit arrangement. After performing the operation with the sensitive data on the input data, the operation is performed with the sensitive data on a second quantity of random data using the circuit arrangement. | 2012-03-08 |
| 20120060039 | Code Download and Firewall for Embedded Secure Application - A device includes a demodulator for receiving an encrypted content, an interface unit communicatively coupled to an external memory, and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received content. The hardware unit includes a processing unit, a ROM having a boot code causing the device to fetch data from the external memory, a RAM for storing the fetched data, multiple non-volatile memory registers or fuse banks, and a mechanism configured to write the stored data to an external storage device in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage device. The interface unit may include a wired or wireless communication link. The boot code includes executable instructions performing a series of validations. The device disables the executable instructions in the event of a validation failure. | 2012-03-08 |
| 20120060040 | FLASH MEMORY DISTRIBUTION OF DIGITAL CONTENT - Methods, apparatuses, and computer-readable media for distributing digital content. One embodiment comprises an apparatus comprising: a device ( | 2012-03-08 |
| 20120060041 | SYSTEM FOR CONTROLLING TOTAL POWER CONSUMPTION OF PLURAL APPARATUSES AND CONTROL METHOD THEREOF - A system according to the present invention includes a server and a plurality of apparatuses each incorporating a device. The apparatuses control power supply ON and OFF states of the devices in accordance with an instruction from the server. The server collects pieces of operation state information indicating operation states of the apparatuses from the apparatuses, and groups, based on the collected information, the apparatuses into groups which respectively correspond to different operation states and respectively have different priorities. The server further sends an allowance notification indicating a device power supply allowance to apparatuses which belong to respective groups in descending order of priority taking into consideration a parameter associated with power consumption values of apparatuses to which the device power supply allowance is given. Each apparatus sets the device in a power supply ON state when the allowance notification is received from the server. | 2012-03-08 |
| 20120060042 | Maintaining power through a data transmission cable - A powered device receives electrical power through a data transmission cable from a power supplying device that monitors a load on the data transmission cable and turns off the power to the load if the load is outside of a range. The powered device draws a first current at least part of a time during which the powered device is in a low power mode. The powered device is operable during the low power mode to draw a second current. And the powered device increases and decreases the second current to maintain a sum of the first current and the second current, or a level of a current into the powered device, at least at a minimum level for at least a portion of a cycle time. | 2012-03-08 |
| 20120060043 | APPARATUS AND METHOD FOR CONTROLLING POWER IN A WIRELESS COMMUNICATION SYSTEM - An apparatus and method for controlling power in a wireless communication system are provided. The method includes determining one or more available communication modes based on at least one of suppliable power information and data bit rate information, setting one of the one or more determined available communication modes as a communication mode during negotiation of a communication mode with a base station, and transmitting and receiving data by applying the set communication mode. | 2012-03-08 |
| 20120060044 | POWER NODE WITH NETWORK SWITCH - A power node provides energy management and network expansion features in a networked data communications and control environment that may be utilized in an energy management system implementing a method of managing energy. Network expansion may be provided by integrating a networking bridge from a power line network to one or more wired network ports or a wireless network. The power outlet on the power node providing power to a device may be identified and associated with information about the device. | 2012-03-08 |
