| 10th week of 2012 patent applcation highlights part 37 |
| Patent application number | Title | Published |
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| 20120058540 | Probiotic Enriched and Low Organic Acid Food Products - This invention relates to a fruit-based food product such as beverages or fruit purees, comprising a concentration of live and stable probiotics, which is preferably greater than 10 | 2012-03-08 |
| 20120058541 | ENGINEERING RESISTANCE TO ALIPHATIC ALCOHOLS - The present disclosure provides improved systems for the biological production of certain aliphatic alcohol compounds. In particular, the present disclosure provides biological systems that show improved resistance to aliphatic alcohol toxicity; in sonic embodiments, such improved resistance allows for increased levels of aliphatic alcohol production. Accordingly, the present disclosure provides, inter alia, engineered microorganisms that both produce an aliphatic alcohol compound and show resistance to that compound as measured by an ability to grow to predetermined levels in the presence of a given concentration of the compound. | 2012-03-08 |
| 20120058542 | SYSTEMS AND METHODS FOR REGULATING ALGAL BIOMASS - The invention relates to systems and methods for regulating algal biomass in offshore waters near an oil and gas production platform. The systems of the invention encompasses a plurality of modules for managing nutrients, algae, and aquaculture, including enclosures for containing aquatic organisms, and various operating subsystems that are operably associated with surface and underwater structures of the platform. In one embodiment of the invention, aquatic organisms are cultured in eutrophic water to feed on algae, thereby reducing the algal biomass. In other embodiments, the diversity of algae in an algal bloom is modified and the productivity of oligotrophic water is increased. | 2012-03-08 |
| 20120058543 | Purified Plasmodium and Vaccine Compositions - Disclosed are substantially purified | 2012-03-08 |
| 20120058544 | BIOMASS DECOMPOSITION APPARATUS AND METHOD THEREOF, AND SUGAR-SOLUTION PRODUCTION SYSTEM USING BIOMASS MATERIAL - To include a hydrothermal decomposition unit | 2012-03-08 |
| 20120058545 | METHOD OF TREATING AN OFF-GAS STREAM AND AN APPARATUS THEREFOR - The present invention provides a method of treating an off-gas stream ( | 2012-03-08 |
| 20120058546 | MULTIPLE SURFACE ACOUSTIC WAVE SENSOR SYSTEM - Provided is a multiple SAW sensor system capable of sensing a plurality of target materials in the SAW sensor with a single detector by using a multiplexer. According to the multiple SAW sensor system, the target materials in SAW sensors may be sensed with a single detector, thereby avoiding unnecessary power loss. Also, a plurality of target materials in a sample may be sensed, thereby reducing a waste of the sample. | 2012-03-08 |
| 20120058547 | METHOD AND SYSTEM FOR NUCLEIC ACID DETECTION USING ELECTROCONDUCTIVE OR ELECTROCHEMICALLY ACTIVE LABELS - A method for electrochemically or electrically detecting nucleic acids, utilizes electrochemically active or electrically conductive reporter materials. An electric voltage is applied and electric signals are measured to the electrodes that are suitable for detecting or quantifying the nucleic acid(s) in a sample. This technique is suitable for point-of-use applications, e.g. detecting bioanalytes in remote locations. A microchip, device, kit used adapted to be used for this method is also disclosed. | 2012-03-08 |
| 20120058548 | DETECTION OF BIOTARGETS USING BIORECEPTOR FUNCTIONALIZED NANOPARTICLES - A system for determining a presence of biomolecule targets includes a vessel holding a sample solution suspected of containing the biomolecule targets and a plurality of probes including bioreceptor functionalized metal nanoparticles including a plurality of metal atoms. The biomolecule targets when present in the sample solution bind to the plurality of probes. A separation device is for separating the plurality of probes into a first group of probes having the biomolecule targets bound thereto and a second group of probes not having the biomolecule targets bound thereto. A reagent is introduced via a port for breaking down the metal nanoparticles in the first group or second group of probes, wherein at least one signal moiety solution is formed. A device measures a parameter of the signal moiety solution. | 2012-03-08 |
| 20120058549 | METHOD AND APPARATUS FOR ANALYZING VITAMIN E IN LIPOPROTEINS - A method of analyzing vitamin E components in a lipoproteinby subjecting a lipoprotein-containing sample to ion exchange chromatography to separate the lipoprotein, reacting the separated lipoprotein to a pretreating solution containing an organic solvent and a surfactant to liberate vitamin E components, and then subjecting the liberated vitamin E components to reverse phase chromatography. Also described is a method of judging various pathological conditions such as the pathological conditions of diabetes, the risks of coronary artery diseases, and the pathological conditions of myocardial infarction using levels of vitamin E components in the lipoprotein as an index. | 2012-03-08 |
| 20120058550 | BIOREACTORS COMPRISING FUNGAL STRAINS - Disclosed herein are compositions comprising an isolated cellulose degrading fungus. Also disclosed are culture compositions and bioreactor compositions comprising the cellulose degrading fungus. Further described herein are filtration and extraction devices comprising the cellulose degrading fungus. Still further disclosed are bioprocessing facilities for and methods for producing co-products resulting from one or more bioprocesses of the cellulose degrading fungus. | 2012-03-08 |
| 20120058551 | TECHNOLOGY AND METHOD TO STUDY MICROBIAL GROWTH AND ADHESION TO HOST-RELATED SURFACES AND THE HOST-MICROBIOTA INTERACTIONS - The present invention relates to in vitro adhesion modules that allow growth, stabilization and study of microbial communities that adhere to and colonize host-related surfaces, that mimic transport of chemical compounds across epithelial surfaces and simulate host-microorganism interactions and adaptation. It includes the provision of micromolar amounts of oxygen via the basal side of a mucus layer towards the adhered microorganisms thus establishing the microaerophilic conditions prevailing at the base of a biofilm. It can also include cells, simulating the host, in a chamber on the basal side of a functional layer comprising said mucus layer. The adhesion module of the present invention can be placed between the different compartments of the SHIME—the Simulator of the Human Intestinal Microbial Ecosystem. An extension of the SHIME is made where the duodenum, jejunum and ileum are separately mimicked. | 2012-03-08 |
| 20120058552 | SAMPLE PROCESSING UNITS, SYSTEMS, AND RELATED METHODS - Sample processing units useful for mixing and purifying materials, such as fluidic materials are provided. A sample processing unit typically includes a container configured to contain a sample comprising magnetically responsive particles, and one or more magnets that are in substantially fixed positions relative to the container. A sample processing unit also generally includes a conveyance mechanism configured to convey the container to and from a position that is within magnetic communication with the magnet, e.g., such that magnetically responsive particles with captured analytes can be retained within the container when other materials are added to and/or removed from the container. Further, a sample processing unit also typically includes a rotational mechanism that is configured to rotate the container, e.g., to effect mixing of sample materials disposed within the container. Related carrier mechanisms, sample processing stations, systems, and methods are also provided. | 2012-03-08 |
| 20120058553 | Apparatus for Transporting Biological Samples - A container assembly for storing, treating, transporting and stabilizing a biological sample includes a container, a cap and a sample holder removably received in the container. The sample holder can be a platform-like device dimensioned to be supported on a ledge formed in the side wall of the container. The sample holder includes a central cavity for receiving the sample and immersing the sample in the stabilizing agent in the container. In another embodiment, the sample holder has a closure member for closing the open top end of the cavity. The container includes a liquid reagent in an amount sufficient to treat the biological sample. The biological sample is retained in a predetermined containment area of the container to maintain the biological sample immersed in the reagent without regard to the orientation of the container. | 2012-03-08 |
| 20120058554 | Synthetic Polysaccharide Microcarriers for Culturing Cells - A cell culture polysaccharide microcarrier includes (1) a cross-linked polysaccharide microcarrier base having a neutral or negative charge at pH 7, and (ii) a polypeptide conjugated to the base. The polypeptide may contain a cell adhesive sequence, such as RGD. Cells cultured with such microcarriers exhibit peptide-specific binding to the microcarriers. | 2012-03-08 |
| 20120058555 | RNAi EXPRESSION CONSTRUCTS - The present invention provides compositions and methods suitable for expressing 1-x RNAi agents against a gene or genes in cells, tissues or organs of interest in vitro and in vivo so as to treat diseases or disorders. | 2012-03-08 |
| 20120058556 | High Surface Area Substrate for Cell Culture - A cell culture microcarrier includes (1) a polystyrene microcarrier base having a remnant of a carboxylic acid group, and (ii) a polypeptide conjugated to the base via the remnant of the carboxylic acid group. The polypeptide may contain a cell adhesive sequence, such as RGD. Cells cultured with such microcarriers exhibit peptide-specific binding to the microcarriers. | 2012-03-08 |
| 20120058557 | Mineralized Three-Dimensional Bone Constructs - The present disclosure provides ex-vivo derived mineralized three-dimensional bone constructs. The bone constructs are obtained by culturing osteoblasts and osteclast precursors under randomized gravity vector conditions. Preferably, the randomized gravity vector conditions are obtained using a low shear stress rotating bioreactor, such as a High Aspect Ratio Vessel (HARV) culture system. The bone constructs of the disclosure have utility in physiological studies of bone formation and bone function, in drug discovery, and in orthopedics. | 2012-03-08 |
| 20120058558 | COMPOSITION FOR PRESERVING PLATELETS AND METHOD OF USING THE SAME - The present invention relates to compositions and methods for storing platelets to preserve the function and freshness of the platelets. More particularly, the present invention relates to the use of a preservative composition having an antiplatelet agent, an anticoagulant, and an oxygen carrier, for maintaining the freshness of platelets. Additionally, the composition may also contain an ultra-short acting broad spectrum anti-microbial agents. The preservative composition may be used to store platelets in a liquid state, a frozen state, or a freeze-dried state. | 2012-03-08 |
| 20120058559 | Monocyte Activation Test Better Able to Detect Non-Endotoxin Pyrogenic Contaminants in Medical Products - An improved monocyte activation test is described that is better able to detect non-endotoxin pyrogens in medical products, in which a sample is incubated with a monocyte-containing reagent in an assay system comprising at least one surface comprising polypropylene. The invention also concerns assay systems for use in these tests that include at least one microtiter well having at least one interior surface comprising polypropylene and having a shape such that monocyte-containing reagent is concentrated in the well to provide greater cell to cell contact. The invention also relates to a diagnostic kit that can be used to test for the presence of non-endotoxin pyrogens in a sample. | 2012-03-08 |
| 20120058560 | Bioreactor System - Bioreactors may be used for the cultivation of cells, in particular of adherent cells, and, in particular for the cultivation and propagation of cell cultures, and utilized in methods for the cultivation of cells. A particular area of application is the use of the bioreactors in the GMP-compliant, fully automatic cultivation and propagation of cells. | 2012-03-08 |
| 20120058561 | METHODS AND COMPOSITIONS FOR STEM CELL CULTURES - The disclosure provides methods and compositions useful for culturing stem cell including embryonic stem cells, adult stem cells, and embryonic germ cells. | 2012-03-08 |
| 20120058562 | REPROGRAMMING IMMORTALIZED B CELLS - Methods and composition for providing induced pluripotent stem (iPS) cells are provided. For example, in certain aspects methods including reprogramming B lymphocytes transformed by episomal vectors such as Epstein-Barr virus-based vectors are described. Furthermore, the invention provides induced pluripotent stem cells essentially free of exogenous elements and having B cell immunoglobin variable region rearrangement. | 2012-03-08 |
| 20120058563 | PRODUCTION OF 2-KETO-L-GULONIC ACID - The present invention relates to the production of recombinant microorganisms, in particular of the genus | 2012-03-08 |
| 20120058564 | TEST KIT AND METHOD FOR MEASUREMENT OF METALS IN BIOLOGICAL FLUIDS - A test kit and a biomedical process is provided to estimate metals particularly non-transferrin bound iron levels (NTBI) in circulating body fluids particularly, serum. NTBI appears in serum when there is excess iron in the body. The method comprises of employing a signal generating moiety capable of complexing with iron that is a peptide like molecule having an iron binding site and also an optical signal generating functional group. The molecule is of microbial origin. The measurement is based on the alteration of optical characteristics of the probe molecule upon attachment of iron to its binding site on the molecule. Hence it generates a signal proportionate to the amount of iron available for binding and provides a direct estimate of free or unbound iron in the sample. According to this instant invention a rapid estimation method of NTBI in body fluids can be undertaken in an inexpensive way without the need of specialized expertise. | 2012-03-08 |
| 20120058565 | CONJUGATES OF 1,4,7-TRIAZACYCLONONANES, DINUCLEAR METAL COMPLEXES OF SUCH CONJUGATES, AND METHODS OF USE FOR BOTH 1,4,7-TRIAZACYCLONONANES AND CONJUGATES - Conjugates of 1,3-bis(1,4,7-triazacyclonon-1-yl)-2-hydroxypropanes with a variety of conjugating members are used in the formation of dinuclear metal complexes which bind to phosphate esters. By virtue of their conjugated forms, the complexes are incorporated into chromatographic media, affinity binding reagents, and dyes, which make the complexes useful in a wide range of assays, separations, and purifications. In addition, dinuclear metal complexes of 1,3-bis(1,4,7-triazacyclonon-1-yl)-2-hydroxypropanes that are not so conjugated are used in the detection of phosphate esters of biological species by either MALDI-TOF mass spectrometry or by dye displacement. | 2012-03-08 |
| 20120058566 | DETECTION OF IMMOBILIZED NUCLEIC ACID - The present invention provides methods for determining the presence of immobilized nucleic acid employing unsymmetrical cyanine dyes that are derivatives of thiazole orange, a staining solution and select fluorogenic compounds that are characterized as being essentially non-genotoxic. The methods comprise immobilizing nucleic acid, single or double stranded DNA, RNA or a combination thereof, on a solid or semi solid support, contacting the immobilized nucleic acid with an unsymmetrical cyanine dye compound and then illuminating the immobilized nucleic acid with an appropriate wavelength whereby the presence of the nucleic acid is determined. The cyanine dye compounds are typically present in an aqueous staining solution comprising the dye compound and a tris acetate or tris borate buffer wherein the solution facilitates the contact of the dye compound and the immobilized nucleic acid. Typically the solid or semi-solid support is selected from the group consisting of a polymeric gel, a membrane, an array, a glass bead, a glass slide, and a polymeric microparticle. Preferably, the polymeric gel is agarose or polyacrylamide. The methods employing the non-genotoxic compounds represent an improvement over commonly used methods employing ethidium bromide wherein the present methods retain the advantages of ethidium bromide, ease of use and low cost, but without the disadvantageous, known mutagen requiring special handling and waste procedures. | 2012-03-08 |
| 20120058567 | POROUS OPTICAL SENSOR WITH FIDUCIAL MARKER AND METHOD FOR DETECTION OF ANALYTES - The invention provides a porous sensor and sensing methods that use a porous sensor with a porous nanostructure having an optical response and having a portion of the porous nanostructure filled with a fiducial marker that is non-reactive to an analyte of interest. In a preferred sensing method, reflectance spectra from both the fiducial marker and reactive portions of the porous structure are acquired simultaneously. The fiducial marker provides an internal reference that permits compensation for humidity, as well as off angle measurements. In addition, simple visual observations can reveal the presence of an analyte, including human observations. | 2012-03-08 |
| 20120058568 | LIQUID CHROMATOGRAPH AND ANALYSIS METHOD - It is an object of the present invention to provide a liquid chromatograph which, in a high performance liquid chromatograph analysis using a post-column method, can maintain mixing precision of a sample eluted from a column and a reaction reagent without a special mixing and reacting portion, prevent diffusion of a target component, and perform measurement with high sensitivity. | 2012-03-08 |
| 20120058569 | METHOD AND DEVICE FOR DETERMINING REFLECTION COEFFICIENTS ON FILTER ARRANGEMENTS HAVING THIN LAYERS - The invention relates to a method for determining optical properties by measuring intensities on a thin layer, wherein light is irradiated onto a carrier ( | 2012-03-08 |
| 20120058570 | IN SITU HEAT INDUCED ANTIGEN RECOVERY AND STAINING METHOD - An automated in situ heat induced antigen recovery and staining method and apparatus for treating a plurality of microscope slides. The process of heat induced antigen recovery and the process of staining the biological sample on the microscope slide are conducted in the same apparatus, wherein the microscope slides do not need to be physically removed from one apparatus to another. The reaction conditions for treating a slide can preferably be controlled independently, including the individualized application of reagents to each slide and the individualized treatment of each slide. | 2012-03-08 |
| 20120058571 | METHODS, DEVICES, AND SYSTEMS FOR FLUID MIXING AND CHIP INTERFACE - In one aspect, the present invention provides methods, devices, and systems for ensuring that multiple components of a mixture are fully mixed in a continuous flow microfluidic system while ensuring that mixing between segments flowing through the chip is minimized. In some embodiments, the present invention includes mixing fluids in a droplet maintained at the tip of a pipette before the mixture is introduced to the microfluidic device. In another aspect, the present invention provides a pipette tip having a ratio of an outside diameter to an inside diameter that provides sufficient surface area for a droplet comprising up to the entire volume of the liquid to suspend from the pipette tip intact. In yet another aspect, the present invention provides methods, devices, and systems for delivering a reaction mixture to a microfluidic chip comprising a docking receptacle, an access tube and a reservoir. | 2012-03-08 |
| 20120058572 | ANTIBODY AGAINST PERIOSTIN, AND A PHARMACEUTICAL COMPOSITION COMPRISING IT FOR PREVENTING OR TREATING A DISEASE IN WHICH PERIOSTIN IS INVOLVED - The present invention provides an antibody against a periostin isoform having anti-cell adhesive activity, especially an anti-periostin antibody having the ability to neutralize anti-cell adhesive properties, as well as a prophylactic or therapeutic agent for periostin-related diseases comprising the antibody. The present invention also provides methods for detecting and quantifying the periostin isoform in a sample by using the antibody, as well as a method for diagnosing periostin-related diseases comprising measuring the amount of the periostin isoform by the detection or quantification method. | 2012-03-08 |
| 20120058573 | INNOVATIVE BLOOD PLATELETS BIOMARKER FOR EARLY DIAGNOSIS OF ALZHEIMER'S DISEASE - The present invention is directed to a method for early, non-invasive, rapid, efficient, reliable and accurate diagnose of Alzheimer's disease. The present invention particularly addresses obtaining blood samples, and stabilizing platelets from healthy persons and patients with probable cognitive impairment and/or Alzheimer's disease; extracting proteins from the platelets; identifying both monomeric and oligomeric tau proteins in the platelets with at least two monoclonal antibodies against the tau proteins, quantifying the amounts of the identified tau proteins, and comparing the amounts and protein profiles of the tau molecular species in the platelets of the healthy person and the patient. | 2012-03-08 |
| 20120058574 | MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure. | 2012-03-08 |
| 20120058575 | Low switching current dual spin filter (DSF) element for STT-RAM and a method for making the same - A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc | 2012-03-08 |
| 20120058576 | Deposition System - A pumping and valve control device can be used in an atomic layer deposition system. | 2012-03-08 |
| 20120058577 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT | 2012-03-08 |
| 20120058578 | METHOD OF MANUFACTURING A SUBSTRATE FOR LIQUID EJECTION HEAD - Provided is a method of manufacturing a substrate for liquid ejection head, including: forming a groove portion by etching on one surface side of a silicon substrate, the groove portion being formed so as to surround a portion at which a liquid supply port is to be formed on an inner side of the groove portion; forming a protective layer on the one surface side of the silicon substrate, the protective layer being formed inside the groove portion and on an outer side of the groove portion; and forming the liquid supply port by subjecting the silicon substrate to crystal anisotropic etching treatment with use of the protective layer as a mask. | 2012-03-08 |
| 20120058579 | METHOD FOR PACKAGING LED CHIP MODULES AND MOVING FIXTURE THEREOF - A method for packaging LED chip modules is provided. First, a first sacrificial layer is disposed on a substrate. Afterwards, LED chips are synchronously disposed on the first sacrificial layer before the first sacrificial layer cures. Next, a first material, a second sacrificial layer, and a second material are used to form a support layer on the first sacrificial layer. The first sacrificial layer and the second sacrificial layer are then removed, so that LED chip modules are obtained, wherein each LED chip module has a corresponding support layer. Furthermore, a moving fixture is provided to synchronously remove chips from a wafer and dispose them on the sacrificial layer. | 2012-03-08 |
| 20120058580 | Surface-Textured Encapsulations for Use With Light Emitting Diodes - Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a light emitting diode with an encapsulation having a surface texture configured to extract light. In an aspect, a light emitting diode lamp is provided that includes a package, at least one light emitting diode disposed within the package, and an encapsulation formed upon the at least one light emitting diode having a surface texture configured to extract light. In another aspect, a method includes determining one or more regions of an encapsulation, the encapsulation configured to cover a light emitting diode, and surface-texturing each region of the encapsulation with one or more geometric features that are configured to extract light. | 2012-03-08 |
| 20120058581 | METHOD OF MANUFACTURING LASER DIODE - Manufacturing a laser diode includes growing an active layer, a first InP layer, and a diffraction grating layer; forming an alignment mark having a recess by etching the diffraction grating layer and the first InP layer; forming a first etching mask; forming a diffraction grating in the diffraction grating layer using the first etching mask; forming a modified layer containing InAsP on a surface of the alignment mark recess by supplying a first source gas containing As and a second source gas containing P; growing a second InP layer on the diffraction grating layer and on the alignment mark; forming a second etching mask on the second InP layer; selectively etching the second InP layer embedded in the recess of the alignment mark through the second etching mask by using the modified layer serving as an etching stopper; and forming a waveguide structure using the alignment mark. | 2012-03-08 |
| 20120058582 | METHOD FOR ETCHING INSULATING FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A method for etching an insulating film includes the steps of forming an insulating film; forming a first resin layer composed of a non-silicon-containing resin on the insulating film; forming a pattern including projections and recesses in the first resin layer; forming a second resin layer composed of a silicon-containing resin to cover the projections and the recesses of the pattern in the first resin layer; etching the second resin layer by reactive ion etching with etching gas containing CF | 2012-03-08 |
| 20120058583 | GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD FOR FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - Provided is a group-III nitride semiconductor laser device with a laser cavity allowing for a low threshold current, on a semipolar surface of a support base in which the c-axis of a hexagonal group-III nitride is tilted toward the m-axis. First and second fractured faces | 2012-03-08 |
| 20120058584 | Multi-Junction LED - A light source and method for making the same are disclosed. The light source includes a substrate and a light emitting structure that is deposited on the substrate. A barrier divides the light emitting structure into first and second segments that are electrically isolated from one another. A serial connection electrode connects the first segment in series with the second segment. A first blocking diode between the light emitting structure and the substrate prevents current from flowing between the light emitting structure and the substrate when the light emitting structure is emitting light. The barrier extends through the light emitting structure into the first blocking diode. | 2012-03-08 |
| 20120058585 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LASER ELEMENT - A method for manufacturing a nitride semiconductor laser element has: (a) forming a nitride semiconductor layer on a substrate; (b) forming a ridge on a surface of the nitride semiconductor; (c) forming a first protective film on the nitride semiconductor layer including the ridge; (d) removing the first protective film from at least a top face of the ridge; (e) forming a conductive layer composed of a two or more of multilayer film with different compositions on the first protective film and the nitride semiconductor layer including the ridge, and introducing a gap at locations of at least at the uppermost conductive layer corresponding to the base portion from the ridge shoulders; and (f) removing part of the conductive layer through a gap to form a void defined the first protective film and the conductive layer at least on the ridge base portions. | 2012-03-08 |
| 20120058586 | OPTICAL DEVICES FEATURING TEXTURED SEMICONDUCTOR LAYERS - A semiconductor sensor, solar cell or emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate. The textured layers enhance light extraction or absorption. Texturing in the region of multiple quantum wells greatly enhances internal quantum efficiency if the semiconductor is polar and the quantum wells are grown along the polar direction. Electroluminescence of LEDs of the invention is dichromatic, and results in variable color LEDs, including white LEDs, without the use of phosphor. | 2012-03-08 |
| 20120058587 | METHOD FOR MANUFACTURING CAPACITIVE ELECTROMECHANICAL TRANSDUCER - A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm. | 2012-03-08 |
| 20120058588 | DEVICE AND METHOD FOR SIMULTANEOUSLY MICROSTRUCTURING AND DOPING SEMICONDUCTOR SUBSTRATES - The invention relates to a device and a method for simultaneous microstructuring and doping of semiconductor substrates with boron, in which the semiconductor substrate is treated with a laser beam coupled into a liquid jet, the liquid jet comprising at least one boron compound. The method according to the invention is used in the field of solar cell technology and also in other fields of semiconductor technology in which a locally delimited boron doping is important. | 2012-03-08 |
| 20120058589 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device which can form a high-performance photodiode in which variation in output characteristics and performance deterioration are suppressed. A prescribed gate metal is used to form a shield section | 2012-03-08 |
| 20120058590 | METHOD FOR MANUFACTURING SOLAR CELL MODULE - In manufacturing of a solar cell module in which a solar cell having a surface electrode to which a tab lead is connected is sealed with a resin, the step of connecting the tab lead and the step of sealing the solar cell with the resin are performed simultaneously at a relatively low temperature that is used for the resin sealing step. To perform these steps simultaneously, the solar cell having the surface electrode to which the tab lead is connected with an adhesive is resin-sealed using a vacuum laminator to manufacture the solar cell module. The vacuum laminator used includes a first chamber and a second chamber partitioned by a flexible sheet. The internal pressures of these chambers can be controlled independently, and a heating stage for heating is provided in the second chamber. | 2012-03-08 |
| 20120058591 | Method of fabricating epitaxial structures - A method of fabricating epitaxial structures including applying an etch stop to one side of a substrate and then growing at least one epitaxial layer on a first side of said substrate, flipping the substrate, growing a second etch stop and at least one epitaxial layer on a second side of the substrate, applying a carrier medium to the ultimate epitaxial layer on each side, dividing the substrate into two parts generally along an epitaxial plane to create separate epitaxial structures, removing any residual substrate and removing the etch stop. | 2012-03-08 |
| 20120058592 | LASER FIRING APPARATUS FOR HIGH EFFICIENCY SOLAR CELL AND FABRICATION METHOD THEREOF - Disclosed are a laser firing apparatus for a high efficiency solar cell including laser generating unit and a fabrication method thereof. The laser firing apparatus for a high efficiency solar cell includes at least one laser generating unit that irradiates a laser irradiation on to an electrode region formed on a semiconductor substrate for the solar cell and heat-treats the electrode region. In addition, the fabrication method of a solar cell includes forming an electrode material on a semiconductor substrate for the solar cell; and forming an electrode by heat treating the electrode material by laser irradiation. | 2012-03-08 |
| 20120058593 | MICRO/NANOSTRUCTURE PN JUNCTION DIODE ARRAY THIN-FILM SOLAR CELL AND METHOD FOR FABRICATING THE SAME - The present invention discloses a micro/nanostructure PN junction diode array thin-film solar cell and a method for fabricating the same, wherein a microstructure or sub-microstructure PN junction diode array, such as a nanowire array or a nanocolumns array, is transferred from a source-material wafer to two pieces of transparent substrates, which are respectively corresponding to two electric conduction types, to fabricate a thin-film solar cell. In the present invention, the micro/nanostructure PN junction diode array has advantages of a fine-quality crystalline semiconductor, and the semiconductor substrate can be reused to save a lot of semiconductor material. Besides, the present invention can make the best of sunlight energy via stacking up the solar cells made of different types of semiconductor materials to absorb different wavebands of the sunlight spectrum. | 2012-03-08 |
| 20120058594 | METHOD FOR MANUFACTURING AN ARRAY-TYPE NANOTUBE LAYER OF A THIN-FILM SOLAR CELL - A method for manufacturing an array-type nanotube layer for a thin-film solar cell comprises the steps of: preparing an isotropic Si-substrate; sputtering a metal Ti layer onto the isotropic Si-substrate; heat-treating the Ti-coated Si-substrate in a vacuum heat-treatment environment; annealing the Ti-coated Si-substrate in an annealing heat-treatment environment to produce an intermediate-phase metal Ti layer ; anodizing the intermediate-phase metal Ti layer so as to transform the intermediate-phase metal Ti layer into an array-type nanotube layer for the solar cell; and finally applying a reverse voltage to separate the array-type nanotube layer from the isotropic Si-substrate. | 2012-03-08 |
| 20120058595 | DEVELOPMENT OF AN ELECTRONIC DEVICE QUALITY ALUMINUM ANTIMONIDE (AlSb) SEMICONDUCTOR FOR SOLAR CELL APPLICATIONS - Electronic device quality Aluminum Antimonide (AlSb)-based single crystals produced by controlled atmospheric annealing are utilized in various configurations for solar cell applications. Like that of a GaAs-based solar cell devices, the AlSb-based solar cell devices as disclosed herein provides direct conversion of solar energy to electrical power. | 2012-03-08 |
| 20120058596 | METHODS AND APPARATUS FOR REAL-TIME MONITORING OF CADMIUM ION DURING SOLUTION GROWTH OF CADMIUM SULFIDE THIN FILMS - The present invention provides a reaction chamber to monitor a metal ion in solution during the formation of a metal-sulfide layer on a substrate. The reaction chamber houses a solution of an ammonium ion, a metal ion and a buffer. The reaction chamber includes an anion-selective electrode in the solution to monitor the metal ion that measures the metal ion during metal-ammonium complex formation, metal-thiourea complex formation, metal sulfide composition formation, metal sulfide layer formation or a combination thereof. | 2012-03-08 |
| 20120058597 | FABRICATION METHOD FOR THIN-FILM FIELD-EFFECT TRANSISTORS - A thin-film field-effect transistor is formed by forming a dielectric layer adjacent a gate, forming a source region and a drain region, and forming a semiconductor layer on the dielectric layer. The semiconductor layer is deposited by spray pyrolysis and comprises a material selected from a group comprising: oxides; oxide-based materials; mixed oxides; metallic type oxides; group I-IV, II-VI, III-VI, IV-VI, V-VI and VIII-VI binary chalcogenides; and group I-II-VI, II-II-VI, II-III-VI, II-VI-VI and V-II-VI ternary chalcogenides. | 2012-03-08 |
| 20120058598 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment. | 2012-03-08 |
| 20120058599 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity. The semiconductor layer and the source and drain electrode layers are electrically connected to each other through the buffer layer. | 2012-03-08 |
| 20120058600 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to increase field effect mobility of a thin film transistor including an oxide semiconductor. Another object is to stabilize electrical characteristics of the thin film transistor. In a thin film transistor including an oxide semiconductor layer, a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor is formed over the oxide semiconductor layer, whereby field effect mobility of the thin film transistor can be increased. Further, by forming a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor between the oxide semiconductor layer and a protective insulating layer of the thin film transistor, change in composition or deterioration in film quality of the oxide semiconductor layer is prevented, so that electrical characteristics of the thin film transistor can be stabilized. | 2012-03-08 |
| 20120058601 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SAME, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode. | 2012-03-08 |
| 20120058602 | METHOD OF FORMING A WAVEGUIDE IN DIAMOND - N-V centers in diamond are created in a controlled manner. In one embodiment, a single crystal diamond is formed using a CVD process, and then annealed to remove N-V centers. A thin layer of single crystal diamond is then formed with a controlled number of N-V centers. The N-V centers form Qubits for use in electronic circuits. Masked and controlled ion implants, coupled with annealing are used in CVD formed diamond to create structures for both optical applications and nanoelectromechanical device formation. Waveguides may be formed optically coupled to the N-V centers and further coupled to sources and detectors of light to interact with the N-V centers. | 2012-03-08 |
| 20120058603 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage. | 2012-03-08 |
| 20120058604 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE CARRIER AND MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE USING THE SAME - A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed. | 2012-03-08 |
| 20120058605 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When forming a conductive film by a method comprising sputtering after grinding the back surface of a semiconductor substrate, in order to avoid discharge from a part of an adhesive flown out at the outer periphery of the substrate, wherein the adhesive is used to fix the substrate to a support during grinding, at least the substrate end or the adhesive is removed after grinding the semiconductor substrate and before forming the conductive film, so that a gap between the substrate end and the adhesive may have a predetermined size. | 2012-03-08 |
| 20120058606 | Method of Fabricating A Semiconductor Device Having A Resin With Warpage Compensated Structures - A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion. | 2012-03-08 |
| 20120058607 | Method of fabricating a deep trench Insulated Gate Bipolar Transistor - In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region. | 2012-03-08 |
| 20120058608 | METHOD OF FABRICATING SOI SUPER-JUNCTION LDMOS STRUCTURE CAPABLE OF COMPLETELY ELIMINATING SUBSTRATE-ASSISTED DEPLETION EFFECTS - The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar, and therefore completely eliminating the substrate-assisted depletion effects and elevating the breakdown voltage of the device. | 2012-03-08 |
| 20120058609 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench. | 2012-03-08 |
| 20120058610 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess. | 2012-03-08 |
| 20120058611 | METHODS OF FORMING AND PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE RESISTOR - Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region. | 2012-03-08 |
| 20120058612 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed. | 2012-03-08 |
| 20120058613 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate. | 2012-03-08 |
| 20120058614 | PRE-METAL DEPOSITION CLEAN PROCESS - A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC | 2012-03-08 |
| 20120058615 | Method of Forming Shielded Gate Power Transistor Utilizing Chemical Mechanical Planarization - A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches. | 2012-03-08 |
| 20120058616 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING PRELIMINARY TRENCHES WITH EPITAXIAL GROWTH - A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate. | 2012-03-08 |
| 20120058617 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - The present invention includes steps below: (a) forming, on a drift layer, a first ion implantation mask and a second ion implantation mask individually by photolithography to form a third ion implantation mask, the first ion implantation mask having a mask region corresponding to a channel region and having a first opening corresponding to a source region, the second ion implantation mask being positioned in contact with an outer edge of the first ion implantation mask and configured to form a base region; (b) implanting impurities of a first conductivity type from the first opening with an ion beam using the third ion implantation mask to form a source region in an upper layer part of the silicon carbide drift layer; (c) removing the first ion implantation mask after the formation of the source region; and (d) implanting impurities of a second conductivity type with an ion beam from a second opening formed in the second ion implantation mask after the removal of the first ion implantation mask to form a base region deeper than the source region in the upper layer part of the drift layer. | 2012-03-08 |
| 20120058618 | Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method - A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer. | 2012-03-08 |
| 20120058619 | NAND FLASH MEMORY ARRAY HAVING PILLAR STRUCTURE AND FABRICATING METHOD OF THE SAME - A method is provided for fabricating a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. The NAND flash memory array has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. The NAND flash memory array allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. The method for fabricating the NAND flash memory array having a pillar structure uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs. | 2012-03-08 |
| 20120058620 | EXPOSURE MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device. | 2012-03-08 |
| 20120058621 | FABRICATION OF SUBSTRATES WITH A USEFUL LAYER OF MONOCRYSTALLINE SEMICONDUCTOR MATERIAL - The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate. | 2012-03-08 |
| 20120058622 | METHOD FOR PRODUCING BONDED WAFER - When a thermal expansion coefficient of a handle substrate is higher than that of a donor substrate, delamination is provided without causing a crack in the substrates. A method for producing a bonded wafer, with at least the steps of: implanting ions into a donor substrate ( | 2012-03-08 |
| 20120058623 | Method for Thinning Wafer - The present invention provides a method of thinning a wafer. First, a wafer is provided. The wafer includes an active surface, a back surface and a side surface. The active surface is disposed opposite to the back surface. The side surface is disposed between the active surface and the back surface and encompasses the peripheral of the wafer. Next, a protective structure is formed on the wafer to at least completely cover the side surface. Last, a thinning process is performed upon the wafer from the back surface. | 2012-03-08 |
| 20120058624 | METHOD AND STRUCTURE FOR FABRICATING SOLAR CELLS USING A THICK LAYER TRANSFER PROCESS - A method includes providing a donor substrate comprising single crystal silicon and having a surface region, a cleave region, and a thickness of material to be removed between the surface region and the cleave region. The method also includes introducing through the surface region a plurality of hydrogen particles within a vicinity of the cleave region using a high energy implantation process. The method further includes applying compressional energy to cleave the semiconductor substrate and remove the thickness of material from the donor substrate. | 2012-03-08 |
| 20120058625 | FILM FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The present invention provides a film for a semiconductor device that is capable of suppressing the generation of a transfer mark on an adhesive film when a film for a semiconductor device, in which an adhesive film with a dicing sheet obtained by laminating an adhesive film onto a dicing film is laminated onto a cover film leaving a prescribed spacing, is wound up into a roll. It is a film for a semiconductor device in which an adhesive film with a dicing sheet obtained by laminating an adhesive film onto a dicing film is laminated onto a cover film leaving a prescribed spacing, wherein a ratio Ea/Eb of the tensile storage modulus Ea of the adhesive film at 23° C. to the tensile storage modulus Eb of the cover film at 23° C. is in a range of 0.001 to 50. | 2012-03-08 |
| 20120058626 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL LAYER - According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness. | 2012-03-08 |
| 20120058627 | COMPOUND SEMICONDUCTOR DEPOSITION METHOD AND APPARATUS - Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate. In the compound semiconductor deposition method of depositing a compound semiconductor of a ternary or higher system on a substrate, propagation light of a smaller energy than a desired ideal excitation energy for the compound semiconductor is irradiated onto the substrate | 2012-03-08 |
| 20120058628 | Multiple-Gate Transistors with Reverse T-Shaped Fins - A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric. | 2012-03-08 |
| 20120058629 | METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES - Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves. | 2012-03-08 |
| 20120058630 | Linear Cluster Deposition System - A linear cluster deposition system includes a plurality of reaction chambers positioned in a linear horizontal arrangement. First and second reactant gas manifolds are coupled to respective process gas input port of each of the reaction chambers. An exhaust gas manifold having a plurality of exhaust gas inputs is coupled to the exhaust gas output port of each of the plurality of reaction chambers. A substrate transport vehicle transports at least one of a substrate and a substrate carrier that supports at least one substrate into and out of substrate transfer ports of each of the reaction chambers. At least one of a flow rate of process gas into the process gas input port of each of the reaction chambers and a pressure in each of the reaction chambers being chosen so that process conditions are substantially the same in at least two of the reaction chambers. | 2012-03-08 |
| 20120058631 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer. | 2012-03-08 |
| 20120058632 | METHODS OF FORMING A METAL CONTACT ON A SILICON SUBSTRATE - A method of forming a metal contact on a silicon substrate is disclosed. The method includes depositing a nanoparticle ink on a substrate surface in a pattern, the nanoparticle ink comprising set of nanoparticles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified nanoparticle layer with a nanoparticle layer thickness of greater than about 50 nm. The method further includes depositing an SiN | 2012-03-08 |
| 20120058633 | Methods Of Forming Features Of Integrated Circuitry - Methods of forming features such as word lines of memory circuitry are disclosed. One such method includes forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area. Thereafter, a subsequent feature pattern is formed which extends from the target array area into the other of the first or second periphery area. The initial and subsequent feature patterns may be used in forming features in an underlying material which extend from the target area to the first and second periphery areas. Other embodiments are disclosed. | 2012-03-08 |
| 20120058634 | METHOD OF FABRICATING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE - A method of fabricating a CMOS device having high-k dielectric layer and metal gate electrode is provided. First, an isolation structure is formed in a substrate to define a first-type and a second-type MOS regions; an interfacial layer and a high-k dielectric layer are sequentially formed over the substrate; a first and a second cover layers are respectively formed over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; afterwards, an in-situ etching step is performed to sequentially etch the first and second cover layers using a first etching solution and to etch both the high-k dielectric layer and the interfacial layer using a second etching solution until the substrate is exposed. Wherein, the second etching solution is a mixed etching solution containing the first etching solution. | 2012-03-08 |
| 20120058635 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A method for manufacturing includes the steps of forming a BCB resin region on a semiconductor optical device; processing a surface of the BCB resin region with inductively coupled plasma produced with a high-frequency power supply for supplying ICP power and a high-frequency power supply for supplying bias power, thus forming a silicon oxide film on the surface of the BCB resin region and roughening the surface of the BCB resin region with projections and recesses; and forming an electrode pad on the surface of the BCB resin region in direct contact with the silicon oxide film. The surface roughness of the BCB resin region and the thickness of the silicon oxide film on the surface of the BCB resin region are controlled by adjusting the bias power and the ICP power. | 2012-03-08 |
| 20120058636 | COMPOSITION FOR REMOVING A PHOTORESIST AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE COMPOSITION - Provided are a composition for removing a photoresist and a method of manufacturing a semiconductor device using the composition. The composition includes about 60-90 wt % of dimethyl sulfoxide, about 10-30 wt % of a polar organic solvent, about 0.5-1.5 wt % of hydroxy alkyl ammonium and about 1-10 wt % of an amine containing no hydroxyl group. | 2012-03-08 |
| 20120058637 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device, includes: forming a first and second interconnect trenches adjacent to each other in an interlayer insulating film; providing a first interconnect and a space thereon within the first interconnect trench, and a second interconnect and a space thereon within the second interconnect trench; forming a first trench larger in width from the first interconnect trench and a second trench larger in width from the second interconnect trench, by conducting isotropic-etching; and forming a first insulating film within the first trench and a second insulating film within the second trench by filling an insulating material in the first trench and the second trench. | 2012-03-08 |
| 20120058638 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method comprises defining a region in which absorptance of light illuminated for annealing to a substrate on which a pattern of a semiconductor integrated circuit is formed is not larger than a preset value as a coarse pattern region, locally forming a thin film that enhances light absorptance on the coarse pattern region, and annealing the substrate by illuminating light onto the substrate on which the pattern of the integrated circuit and thin film are formed. | 2012-03-08 |
| 20120058639 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of forming a nonvolatile memory device includes providing conductive pillars disposed in a first insulating layer and disposed on a semiconductor substrate, providing an etch stop layer on the first insulating layer, disposing a mold layer on the etch stop layer, and forming grooves in the mold layer. The grooves respectively extend over the conductive pillars in a first direction. The method further includes patterning the etch stop layer using the grooves to form holes respectively corresponding to the conductive pillars, and filling a metal into the grooves and the holes. The metal in the holes contacts the conductive pillars. | 2012-03-08 |
