| 10th week of 2012 patent applcation highlights part 25 |
| Patent application number | Title | Published |
|---|
| 20120057338 | LIGHT EMITTING DEVICE - A light emitting device according to one embodiment includes a board; plural first light emitting elements mounted on the board to emit light having a wavelength of 250 nm to 500 nm; plural second light emitting elements mounted on the board to emit light having a wavelength of 250 nm to 500 nm; a first fluorescent layer formed on each of the first light emitting elements, the first fluorescent layer including a first phosphor; and a second fluorescent layer formed on each of the second light emitting elements, the second fluorescent layer including a second phosphor. The second phosphor is higher than the first phosphor in luminous efficiency at 50° C., and is lower than the first phosphor in the luminous efficiency at 150° C. | 2012-03-08 |
| 20120057339 | LIGHT EMITTING DEVICE - A light emitting device according to one embodiment includes: a board; plural first light emitting units each including a first light emitting element and a first fluorescent layer formed on the first light emitting element having a green phosphor; plural second light emitting units each including a second light emitting element and a second fluorescent layer formed on the second light emitting element having a red phosphor; the second fluorescent layers and the first fluorescent layers being separated in a non-contact manner with gas interposed there between; and plural third light emitting units each including a third light emitting element and a resin layer formed on the third light emitting element having neither a green phosphor nor the red phosphor, the third light emitting units being disposed between the first light emitting units and the second light emitting units. | 2012-03-08 |
| 20120057340 | Lighting Unit and Luminaire for Road and/or Street Lighting - A lighting unit for use in a luminaire, in particular a luminaire for road and/or street lighting, has an adaptable light distribution wherein he lighting unit comprises at least two light sources or groups of light sources, each of the light sources or groups of light sources having an individual light distribution characteristic, wherein the overall light distribution of the lighting unit is adapted by modifying the ratio of the light outputs of the at least two light sources or groups of light sources | 2012-03-08 |
| 20120057341 | Lantern, and Method for Retrofitting a Lantern - A lantern is disclosed that includes a lamp post ( | 2012-03-08 |
| 20120057342 | Article having back light - An article includes a light guide member having an inclined surface and one or more cavities formed in the rear portion, a circuit board is disposed in front of the light guide member and having one or more light sources directed toward the cavities of the light guide member, and a cover member is disposed in front of the circuit board and the light guide member, and the cavities of the light guide member refract the light generated by the light sources toward the inclined surface of the light guide member for generating a back light on the outer peripheral portion of the light guide member and the cover member and for allowing the article to be clearly seen in the dark area or in the dark environment. | 2012-03-08 |
| 20120057343 | ILLUMINATING APPARATUS HAVING HEAT DISSIPATION BASE AND MULTILAYER ARRAY-TYPE LED MODULE - An illuminating apparatus having a heat dissipation base and a multilayer array-type LED module is provided. The multilayer array-type LED module serves as a light source, and a heat dissipation element is provided. The multilayer array-type LED module is featured with a high luminescent efficiency and consumes less power, and the heat dissipation element is adapted for dissipating the heat generated by the multilayer array-type LED module by natural air convection. The combination of the multilayer array-type LED module and the heat dissipation element achieves a better performance of the illuminating apparatus, and can be conveniently further combined with other lamps, or even customized for satisfying different requirements and demands. | 2012-03-08 |
| 20120057344 | LED DISC LAMP - A light emitting diode (LED) disc lamp includes a lamp base, a plurality of LED modules on the lamp base and a lampshade to cover the lamp base. The lamp base is made of aluminum. The lamp base includes a bottom plate which is integrally formed with a circular trough by stamping. The circular trough has a circumferential wall and a bottom which are formed with a plurality of apertures. Each of the plurality of LED modules includes a heat sink fin which is disposed in the circular trough of the lamp base. The LED modules can be replaced with ease. The heat generated from the LED modules can be radiated effectively. The height of the disc lamp can be reduced to beautify the disc lamp. | 2012-03-08 |
| 20120057345 | LINE-PROJECTION APPARATUS FOR ARRAYS OF DIODE-LASER BAR STACKS - In optical apparatus for illuminating a mask-plane with a line of light, a light source includes four fast-axis stacks of laser diode bars. One optical arrangement collects light beams from all of the diode-laser bar stacks, homogenizes and expands the beams in the fast-axis direction of the diode-laser bar stacks and partially overlaps the homogenized and expanded beams in the fast-axis direction. Another optical arrangement homogenizes the sum of the partially overlapped beams and images the sum of the beams as a line of light having a length in the fast-axis-direction and a width in the slow-axis direction. | 2012-03-08 |
| 20120057346 | Vertical & Horizontal Blinds with Lighting - The invention is based on a certain number of hollow translucent vertical blinds ( | 2012-03-08 |
| 20120057347 | LIGHTING UNIT - The invention provides a lighting unit comprising a substantially continuous, pliable surface ( | 2012-03-08 |
| 20120057348 | LED LIGHTING FIXTURE - An LED lighting fixture including a housing and an LED assembly secured with respect to the housing to permit air/water-flow over the LED assembly. The LED assembly includes (a) an LED heat sink having an LED-engaging surface and a heat-transfer surface and (b) an LED-array at the heat-transfer surface. The housing and the heat sink define an air gap permitting air/water-flow to and from the heat sink | 2012-03-08 |
| 20120057349 | LIGHTING UNIT - The invention describes a lighting unit ( | 2012-03-08 |
| 20120057350 | SWITCHABLE LIGHT-DUCT EXTRACTION - The disclosure generally relates to switchable light extractors and in particular to switchable light extractors useful for extracting light from light ducts used for interior lighting of a building. The disclosure also relates to lighting systems that include the light extractors, and methods of extracting light from a lighting system. The switchable light extractors generally include a first and a second reflective film, each having a plurality of voids that can aligned to extract light from a light duct. | 2012-03-08 |
| 20120057351 | LED Lighting Fixture - An LED lighting fixture including a housing having a hollow interior cavity defined by a backwall and a surrounding wall extending therefrom to a forward edge. An LED illuminator is mounted in the housing. An LED-support structure extends in the interior cavity from the housing to an LED-supporting surface positioning the LED illuminator in a desired orientation and spaced from the backwall. The LED-support structure is a heat sink transferring heat from the LED illuminator to the housing. | 2012-03-08 |
| 20120057352 | LED Lighting Fixture - An LED lighting fixture comprising (a) a front-housing portion having a surrounding lateral wall defining a front cavity and extending to a front-housing forward edge at an open front-end, (b) a rear-housing portion having a backwall and a surrounding wall which define a rear cavity, the surrounding wall extending to a rear-housing forward edge, the rear-housing portion joined to the front-housing portion with the rear-housing surrounding wall substantially in alignment with the front-housing surrounding wall, (c) a cross-member secured with respect to the housing portions in a position at the juncture thereof and spanning the interior of the joined housing portions, the cross-member having a front surface facing the front cavity, and (d) an LED illuminator secured to the front surface of the cross-member. | 2012-03-08 |
| 20120057353 | ILLUMINATION BEAM SHAPING SYSTEM - The present invention provides an illumination beam shaping system, which enables the emergent surface of a lighting system of light excitation chips to emit a light beam of uniform illumination brightness. The present invention uses a dividing device, structured from curved lenses arranged in an array, to effect a pre-dividing operation on the total quantity of light from a light excitation chip, after which post-diffusion is carried out to form a light beam with uniform illumination brightness. A plurality of conical light beams in an array are shaped and emerge from an output side, and the bottom portion of each of the conical light beams form an actual optical surface, which act on an optical diffusing component for refraction and diffusion processing, thereby enabling the emergent face of the system to obtain uniform illumination brightness. | 2012-03-08 |
| 20120057354 | OPTICAL LENS AND LIGHT SOURCE MODULE, AND STREET LAMP HAVING THE SAME - There are provided an optical lens and a light source module, and a street lamp having the same. The optical lens includes a concave dome shaped inner surface formed to have a similarly-oval shaped lower surface, and formed to include a plurality of light incident surfaces formed to be stepped along the inner surface thereof and stepped surfaces connecting the plurality of light incident surfaces to one another; and an outer surface formed to surround the inner surface. | 2012-03-08 |
| 20120057355 | Lamp Assembly - A lamp assembly includes a connecting member interconnecting a support member and a lampshade member. The lampshade member includes a shade body, and a housing body adapted for mounting of and connecting electrically with a light source. The housing body has a shade-engaging end connected removably to the shade body, and further has opposite lateral parts, each formed with a slit that has an opening formed in the shade-engaging end. The connecting member has a support-coupling portion connected to the support member, and a fork portion with a pair of branches. The housing body is disposed between the branches, and the branches engage removably and respectively the slits in the housing body. | 2012-03-08 |
| 20120057356 | ELECTRICAL ISOLATION OF AN ION WIND FAN IN ENCLOSURE - Ion wind fans can charge up or spark to the walls of an enclosure. In one embodiment, a heat source can be thermally managed using an ion wind fan by coupling the heat source to a heat spreader that also functions as a wall of an enclosure that contains the ion wind fan. A portion of the heat spreader is then electrically isolated from the ion wind fan, the portion being less than a minimum predetermined distance from the one or more emitter electrodes of the ion wind fan, to avid sparking between the emitters and the enclosure. | 2012-03-08 |
| 20120057357 | LIGHTING MODULE AND LIGHTING APPARATUS COMPRISING THE SAME - A lighting module may be provided that includes a light emitting device module including at least one light emitting diode; and a heat sink radiating heat generated from the light emitting device module and including at least one partition wall formed on a base. | 2012-03-08 |
| 20120057358 | LIGHT EMITTING DIODE MODULE - A light emitting diode (LED) module including a circuit board and at least one LED package is provided. The circuit board has a plurality of driving signal wirings and at least one ground wiring. The LED package is disposed on the circuit board and is electrically connected to the driving signal wirings. The LED package includes at least one LED chip, a plurality of signal leads, and at least one ground lead. The signal leads are electrically connected to the LED chip. The ground lead is electrically insulated from the signal lead and is electrically connected to the ground wiring. The ground lead is electrically insulated from the LED chip and has favorable electrostatic discharge (ESD) protection performance. | 2012-03-08 |
| 20120057359 | LIGHT EMITTING APPARATUS AND LIGHT UNIT - A light emitting device according to an embodiment includes: a body including a cavity formed with a stepped section; an electrode of which one end is disposed on the stepped section and the other end is disposed outside of the body; a heat sink including a main frame and a sub frame, wherein the sub frame includes a slope and a portion of the heat sink is disposed outside of the body; and a light emitting diode disposed on the heat sink. | 2012-03-08 |
| 20120057360 | Integrated Illumination Device Mount - Embodiments include a method and apparatus for an integrated illumination device mount and for mounting the integrated illumination device and mount to a firearm or helmet. In some embodiments, the integrated illumination device mount is a low profile mount. In some embodiments, the integrated illumination device mount allows rigid mounting of an illumination device to a rail of a firearm. In other embodiments, the integrated illumination device allows pivotal mounting of the illumination device to a rail of a firearm. In yet other embodiments, the integrated illumination device mount allows pivotal mounting of the illumination device to a rail of a helmet. | 2012-03-08 |
| 20120057361 | Novelty Trailer Hitch Lighted Figure - A novelty trailer hitch attachment for vehicle personalization and decorative purposes, comprising an illuminated character attached to a trailer hitch receiver tube and mateably inserted into a trailer hitch socket. The illuminated character may include a human skull likeness, adorned with a sports helmet for a particular sports team or organization. Likewise, the character may include a team or school mascot likeness with similar illumination means. The character receives electrical power via a trailer brake light connector, which provides light via embedded Light Emitting Diodes (LEDs) within the character's structure, projected through the eyes of the character when the vehicle brake pedal is depressed. The present invention provides a novelty trailer hitch item for displaying affiliation or support for a particular sports team or for further accessorizing a vehicle exterior. | 2012-03-08 |
| 20120057362 | OPTIMAL LIGHT COUPLING FOR REAR VIEW DEVICES - The invention relates to a device for optimal coupling of light into a light conductor in an illuminating element in a vehicle rear view device, which comprises a light conductor with a coupling surface. The light conductor is placed at a distance from a TIR lens and a light source of at least one LED. The LED protrudes into a recess of the TIR lens, which includes the LED. | 2012-03-08 |
| 20120057363 | VEHICLE LAMP - A vehicle lamp includes a semiconductor light emitting device arranged to face toward a front of the vehicle lamp, a first optical member disposed in front of the semiconductor light emitting device, and a second optical member disposed in front of the first optical member. The first optical member comprises a front surface and a back surface. The front surface is configured to internally reflect light from the semiconductor light emitting device toward the back surface. The back surface is configured to internally reflect the light reflected by the front surface back toward the front surface such that the light exits the first optical member from the front surface. The second optical member is disposed directly in front of the front surface of the first optical member and diffuses the light from the first optical member to form a light distribution pattern. | 2012-03-08 |
| 20120057364 | LIGHT-EMITTING DEVICE, ILLUMINATING DEVICE, VEHICLE HEADLAMP, AND METHOD FOR PRODUCING LIGHT-EMITTING DEVICE - A headlamp disclosed includes: a laser diode for emitting a laser beam; a light emitting section including a fluorescent material which emits light in response to excitation light emitted from the laser diode; a light-transmitting heat conducting member which is provided so as to face a laser beam irradiation surface of the light emitting section and receive heat of the light emitting section; and an adhesive layer filling a gap between the heat conducting member and the laser beam irradiation surface. This arrangement improves efficiency of the heat conducting member in absorbing the heat of the light emitting section, and consequently cools the light emitting section efficiently. | 2012-03-08 |
| 20120057365 | Vehicle headlight - The vehicle head light is provided with a heat radiating member including a pillar member provided to extend from a bottom wall of a housing, on which a light source is mounted, a heat radiating fins fixed radially to the outer periphery of the pillar member, and a guide wall provided surrounding sides of the heat radiating fins. The guide wall is sloped with respect to bottom wall of the housing so that spaces each formed by adjacent two of the heat radiating fins and the guide wall become narrower with increasing distance from the lower end of the guide wall. The guide wall is formed with slits to make air communication between the light chamber and each of the spaces, the slits being shaped to be narrower with increasing distance from the lower end of the guide wall. | 2012-03-08 |
| 20120057366 | OPTICAL SWITCH - An optical fiber switch ( | 2012-03-08 |
| 20120057367 | BACKLIGHT UNIT - Disclosed herein is a backlight unit including a light guide plate including a light emitting portion to emit light, side surfaces defining corners, and a first light incidence portion and a second light incidence portion to receive light, at least two light emitting modules respectively disposed to face the first light incidence portion and the second light incidence portion, and an optical sheet disposed on the light guide plate, wherein the first light incidence portion is disposed one corner region of the light guide plate, and the second light incidence portion is disposed another corner region of the light guide plate, wherein the first light incidence portion is facing the second light incidence portion or disposed to both sides of one side surface of the light guide plate. | 2012-03-08 |
| 20120057368 | BACKLIGHT MODULE AND DISPLAY DEVICE USING THE SAME - A backlight module including a first casing, a light guiding member, a light source and a limiting structure is provided. The first casing has a top portion and a first side portion connected to the top portion. The light guiding member is located at an inner side of the first side portion and has a light incident surface and a top surface. The light source is located at the inner side of the first side portion and is disposed adjacent to the light guiding member. The light source has a light emitting surface facing the light incident surface. The limiting structure is protruded from a wall below the top portion and located above at least part of the light source and at least part of the top surface of the light guiding member. | 2012-03-08 |
| 20120057369 | LIGHT EMITTING STRUCTURE FOR BACKLIGHTED SIGN - There is provided a light emitting assembly for a backlighted sign. The assembly may include first and second light emitting units configured to emit light in corresponding first and second directions into edges of first and second adjacent light guide plates. The assembly may also include a third light emitting unit configured to emit light in a direction substantially transverse to the first and second directions into a backlightable sign panel. Light emitting units are slidably insertable and slidably removable. | 2012-03-08 |
| 20120057370 | Interchange Universal Kits for LED LIght Device - An interchangeable power source light device has an AC power sealed-unit that fits into a uniform compartment of the light device housing. The AC power sealed-unit can be replaced by a DC power battery-pack, which also fits into the uniform compartment-means of the light device housing. The light device may have a built-in light source within the housing for connection with the sealed-unit or battery unit by to deliver electric signals from the sealed-unit or battery pack to the light source. Each sealed-unit and battery pack not only has its own power source, but also circuitry and a trigger, and optionally other light source(s) having low power consumption such as an LED(s), electro-luminescent (EL) element, organic LED, or organic EL element. | 2012-03-08 |
| 20120057371 | LAMP AND LIGHTING APPARATUS - A lamp capable of suppressing an increase in a temperature of semiconductor light-emitting devices such as LED is provided. The lamp includes an LED module ( | 2012-03-08 |
| 20120057372 | CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER - A resonant mode power converter is controlled with a control unit including a current limiting circuit coupled to receive a first current representative of a power converter output and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. An oscillator is coupled to receive the first current to generate a control signal having a control frequency in response to the first current. The power converter output is controlled in response to the control frequency of the control signal. | 2012-03-08 |
| 20120057373 | Boost-Forward-Flyback High Gain Converter - A boost-forward-flyback convertor has a boost converting circuit, a forward converting circuit, a flyback converting circuit and a transformer. The boost converting circuit, the forward converting circuit and the flyback converting circuit are coupled by using elements of the boost and forward converting circuits to form the transformer. The boost-forward-flyback convertor combines benefits of conventional boost, forward and flyback convertors, specifically combines active clamping and lower power pressure to the element from the boost convertor, increases gain ratio by using the forward convertor and provides output to the load during a switch OFF-state from the combination of the flyback and boost converting circuit. The boost-forward-flyback convertor combines benefits of conventional boost, forward and flyback convertors and not only has very high gain, high converting efficiency and lower power loading for devices, but also is simple, cost less, easy to use and has a small volume. | 2012-03-08 |
| 20120057374 | DUTY ADJUSTER CIRCUIT AND CONVERTER INCLUDING THE SAME - The present invention relates to a duty adjuster circuit and a converter. | 2012-03-08 |
| 20120057375 | METHOD AND APPARATUS FOR A FLYBACK POWER CONVERTER PROVIDING OUTPUT VOLTAGE AND CURRENT REGULATION WITHOUT INPUT CAPACITOR - A control circuit of a power converter according to the present invention comprises an output circuit, at least one input circuit and an input-voltage detection circuit. The output circuit generates a switching signal for regulating an output of the power converter in response to at least one feedback signal. The switching signal is coupled to switch a transformer of the power converter. The input circuit samples at least one input signal for generating the feedback signal. The input signal is correlated to the output of the power converter. The input-voltage detection circuit generates an input-voltage signal in response to the level of the an input voltage of the power converter. The input circuit will not sample the input signal when the input-voltage signal is lower than a threshold. The control circuit can eliminate the need of the input capacitor for improving the reliability of the power converter. | 2012-03-08 |
| 20120057376 | POWER SUPPLY CIRCUIT - It is an object to obtain a detection circuit for detecting feedback voltage without variation in output voltage/current or in output voltage by the operation temperature, and a power supply circuit including thereof. A power supply circuit includes a detection circuit, an amplifier circuit outputting an output voltage, a control circuit, and a divider circuit. The detection circuit includes first and second reference voltage generation circuits and an input signal adjustment circuit. The control circuit is electrically connected to the amplifier circuit and includes the detection circuit, an error amplifier circuit, a pulse width modulation driver, a triangle-wave generation circuit, and a capacitor. The divider circuit is electrically connected to the amplifier circuit and the control circuit and inputs a voltage obtained by dividing the output voltage to the second reference voltage generation circuit. Note that the first and second reference voltage generation circuits are each a reference voltage circuit. | 2012-03-08 |
| 20120057377 | UNINTERRUPTIBLE POWER SUPPLY WITH A DUAL GAIN VOLTAGE REGULATOR CONTROLLING AN INVERTER OUTPUT VOLTAGE BASED ON ACTIVE AND REACTIVE COMPONENTS OF CURRENT - An uninterruptible power supply (UPS) system has an inverter having an output coupled to a primary side of an output transformer. The UPS system has a controller having a dual gain voltage regulator for controlling the output voltage of the inverter of a UPS system that uses active and reactive current components of a load current flowing out an output of the UPS system. | 2012-03-08 |
| 20120057378 | STATIC CONVERSION METHOD AND SYSTEM FOR THE REGULATION OF POWER IN AN ALTERNATING CURRENT ELECTRICAL NETWORK - The method can be used for the regulation of power in an alternating current electrical network (ACNW; ACNW | 2012-03-08 |
| 20120057379 | POWER SUPPLY CIRCUIT FOR REMOTELY TURNING-ON ELECTRICAL APPLIANCES - A power supply circuit for an electrical appliance, including a turning-on stage configured for determining a transition from a turned-off state, in which the power supply circuit is off and does not supply electric power, to a turned-on state of the power supply circuit. The turning-on stage includes a transducer of the remote-control type configured for triggering the transition in response to the reception of a wireless signal. | 2012-03-08 |
| 20120057380 | MULTILEVEL INVERTER - A multilevel inverter includes an inverter arm. The inverter arm is provided between a highest electric potential point and a lowest electric potential point, and includes (i) a second switching element group to which switching elements that are connected in series belong, the switching elements being connected to respective diodes which are connected in an opposite polarity and in parallel and (ii) a diode for each power supply connection point. One of connection points at which the switching elements belonging to the second switching element group are connected to each other and a U phase output terminal are connected, the one connection point being located such that at least one of the switching elements provided between the one connection point and the highest electric potential point is equal in number to the other switching elements which belong to the second switching element group and are provided between the one connection point and the lowest electric potential point. | 2012-03-08 |
| 20120057381 | ELECTRIC-POWER CONVERSION APPARATUS - There is provided an electric-power conversion apparatus including a chopper circuit; a current sense resistor that detects the output current of the chopper circuit; a differential detection circuit that outputs, as a differential detection signal (vo), the electric potential difference across the current sense resistor; and a calculation means that corrects the differential detection signal (vo) from the differential detection circuit by use of a control signal (D | 2012-03-08 |
| 20120057382 | POWER FACTOR CORRECTION CONVERTER - A switching control circuit includes an A/D converter that converts detection signals of an input voltage detection circuit, a current detection resistor, and an output voltage detection circuit into a digital signal, a D/A converter that provides a reference voltage to an analog comparator, a PWM circuit that outputs a control voltage to a switching element, and a CPU that provides a specified value to the D/A converter as a reference value, reads the values converted by the A/D converter, and obtains the average value of the inductor current. The CPU reads an inductor current Ib when the output of the PWM circuit is set at a high level, and obtains the average value of an inductor current peak value Ip determined by the specified value and the inductor current value Ib at turn-on as an average inductor current value ILav. | 2012-03-08 |
| 20120057383 | Standalone and Grid-Tie Power inverter - A standalone and grid-tie power inverter includes a DC-to-AC converter, an output circuit electrically connected to the DC-to-AC converter, and a control unit electrically connected to the DC-to-AC converter and the output circuit. The DC-to-AC converter converts a DC power source into an AC power output. The output circuit includes a grid-tie switch for connecting the AC power output to a grid or isolating the AC power output from the grid. The control unit instructs the DC-to-AC converter to provide the AC power output based on a command signal and a feedback signal from the DC-to-AC converter. The control unit controls the grid-tie switch to switch the standalone and grid-tie power inverter between a standalone mode and a grid-tie mode. | 2012-03-08 |
| 20120057384 | METHOD OF ADAPTING A CONFIGURATION OF A VOLTAGE CONVERTING DEVICE AND VOLTAGE CONVERTING UNIT FOR A VOLTAGE CONVERTING DEVICE - A method of adapting a configuration of a voltage converting device is provided. The voltage converting device includes a plurality of voltage converting units in parallel electrical connection to one another, and a plurality of inter-bridge transforming units. Each of the inter-bridge transforming units has a primary coil and a secondary coil. Each of the voltage converting units is electrically connected to a primary coil of a different one of the inter-bridge transforming units. The method includes detecting a status of at least one element of the group consisting of the voltage converting units and the inter-bridge transforming units. The method further includes adapting an activity state of the element based on the detected status of the element by moving the element from a first position to a second position. | 2012-03-08 |
| 20120057385 | POWER CONTROL CIRCUIT - This invention relates to a power control circuit, and, an inventive PWM controller, switching circuit, high voltage discharge circuit and magnetic amplifier are also introduced and used to construct the power control circuit. The power control circuit has featured power saving and wide frequency band. | 2012-03-08 |
| 20120057386 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND POWER CONVERTER - A semiconductor element | 2012-03-08 |
| 20120057387 | HYBRID SWITCH FOR RESONANT POWER CONVERTERS - A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters. | 2012-03-08 |
| 20120057388 | Solar Photovoltaic Inverters - The invention relates to improved techniques for manufacturing power conditioning units (inverters) for use with photovoltaic (PV) modules, and to inverters manufactured by these techniques. We describe a solar photovoltaic inverter, comprising: a power conditioning circuit mounted on a circuit board, the power conditioning circuit having a dc power input to receive dc power from one or more photovoltaic panels and an ac power output to deliver ac power to an ac mains power supply; an electrically conductive shield enclosing said circuit board; and a plastic overmould over said conductive shield and said circuit board; wherein said electrically conductive shield has one or more holes to allow said plastic overmould to extend through said shield to cover said circuit board. | 2012-03-08 |
| 20120057389 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a memory device configured to read control data for operating conditions from a content addressed memory (CAM) block by performing a CAM read operation and to perform a data input/output operation based on the control data and a memory controller configured to store the control data of the memory device and to determine whether the memory device is to perform the CAM read operation by comparing the stored control data with the control data of the memory device when an operating mode of the memory device or the memory controller changes. | 2012-03-08 |
| 20120057390 | MEMORY ARRAY WITH WRITE FEEDBACK - A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance. | 2012-03-08 |
| 20120057391 | Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices - Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. | 2012-03-08 |
| 20120057392 | High Density Non-Volatile Information StorageHigh Density Non-Volatile information Storage - The present invention provides for a composition comprising a nanostructure comprising a semiconductor component and a metallic component, with the proviso that when the semiconductor component is Ge the metallic component is not Te. The nanostructure can be in one of two types of structures: (1) a segregated structure, and (2) a mixed structure. In the segregated structure, the semiconductor component and the metallic component are spatially separate, such as in a lobe-lobe structure, poly-lobe structure, or a core-shell structure. In some embodiments, the lobe-lobe structure comprises a metallic component lobe and a semiconductor component lobe. The composition can be used in a memory device. | 2012-03-08 |
| 20120057393 | Reading A Phase Change Memory - A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals. | 2012-03-08 |
| 20120057394 | Securing Non Volatile Data In An Embedded Memory Device - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 2012-03-08 |
| 20120057395 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a cell block including a plurality of cell mats having a plurality of word lines and a plurality of bit lines perpendicular to the plurality of word lines, a cell plate electrode formed over a whole area of the cell block, and a plate power mesh line including a first plate power mesh line electrically connected to the cell plate electrode while extending in a direction parallel to the word lines, and a second plate power mesh line extending in a direction parallel to the bit lines. The first plate power mesh line includes at least one cutting part. | 2012-03-08 |
| 20120057396 | SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is provided with both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small) and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed). The peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion; thus, the area and size of the semiconductor device can be decreased. | 2012-03-08 |
| 20120057397 | METHOD FOR DRIVING SEMICONDUCTOR DEVICE - In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation. | 2012-03-08 |
| 20120057398 | SRAM DEVICE - An SRAM device uses a four-terminal double gate field effect transistor as a selection transistor, wherein the four-terminal double gate field effect transistor comprises a gate which drives the transistor and a gate which controls a threshold voltage, which are electrically separated from each other, on both surfaces of a standing semiconductor thin plate, and wherein a voltage used to reduce a threshold voltage is input to the gate which controls the threshold voltage of the selection transistor during a writing operation than during a reading operation. The SRAM device which can increase both the read and write margins is provided. | 2012-03-08 |
| 20120057399 | ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF - The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system. | 2012-03-08 |
| 20120057400 | System and Method for Shared Sensing MRAM - Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array. | 2012-03-08 |
| 20120057401 | PHASE CHANGE MEMORY CYCLE TIMER AND METHOD - A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE. | 2012-03-08 |
| 20120057402 | WRITE DRIVER, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND PROGRAMMING METHOD - A write driver, a semiconductor memory apparatus using the same, and a programming method. The write driver includes a reset control unit configured to output a first current pulse for a first period of time and subsequently output a second current pulse having a higher current level than the first current pulse for a second period of time to a memory cell array in response to a reset program command. | 2012-03-08 |
| 20120057403 | MEMORY ELEMENT AND MEMORY DEVICE - There is disclosed a memory element including a memory layer that maintains information through the magnetization state of a magnetic material, a magnetization-fixed layer with a magnetization that is a reference of information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The storing of the information is performed by inverting the magnetization of the memory layer by using a spin torque magnetization inversion occurring according to a current flowing in the lamination direction of a layered structure having the memory layer, the intermediate layer, and the magnetization-fixed layer, the memory layer includes an alloy region containing at least one of Fe and Co, and a magnitude of an effective diamagnetic field which the memory layer receives during magnetization inversion thereof is smaller than the saturated magnetization amount of the memory layer. | 2012-03-08 |
| 20120057404 | MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 2012-03-08 |
| 20120057405 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a cell array, voltage generation circuits, and a control circuit. The cell array comprises memory cell strings. The voltage generation circuits are arranged below the cell array. Each of the memory cell strings comprises a semiconductor layer, control gates, and memory cell transistors. The semiconductor layer comprises a pair of pillar portions, and a connecting portion. The control gates intersect the pillar portion. The memory cell transistors are formed at intersections of the pillar portion and the control gates. In a write operation and a read operation, the control circuit does not drive voltage generation circuits which give noise to memory cell strings as a write target and a read target, and drives voltage generation circuits which do not give noise to the memory cell strings as the write target and the read target. | 2012-03-08 |
| 20120057406 | FLASH MEMORY APPARATUS - A flash memory apparatus includes a plurality of memory sectors and a plurality of path transistors, and each memory sector has a local low voltage line, and each path transistor corresponds to one of the memory sectors, and the path transistors are installed in an alignment direction of the memory sectors. One of the path transistors is installed between two adjacent memory sectors, whose gate is connected to a sector select signal line, and whose drain is connected to the local low voltage line of the corresponding memory sector, and whose source is connected to a global low voltage line, and the global low voltage line is installed at an angle substantially equal to 90 degrees across the gate, so as to save the area occupied by peripheral circuits in the path transistors, and lower the manufacturing cost of the flash memory apparatus. | 2012-03-08 |
| 20120057407 | CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM AND METHODS THEREOF - A storage system according to one embodiment includes logic adapted for determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a set of tracks of the extent is presently being accessed; logic adapted for determining whether any track from the set of tracks is presently being written to; logic adapted for designating to a write-stack associated with the source-tier each track that is presently being written to and designating to a read-stack associated with the source-tier remaining tracks from the set of tracks; logic adapted for removing oldest tracks from the read-stack and the write-stack until the read-stack and the write-stack have been depleted of tracks; logic adapted for populating a destination-tier cache with the tracks as they are removed from the read-stack and the write-stack using a predetermined read-to-write ratio when a parameter of the extent exceeds a migration threshold; logic adapted for removing any tracks from a source-tier cache that were removed from the read-stack and the write-stack; and logic adapted for migrating the extent from the source-tier to the destination-tier. | 2012-03-08 |
| 20120057408 | ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE - A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage. | 2012-03-08 |
| 20120057409 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME - A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells. | 2012-03-08 |
| 20120057410 | Method and Apparatus for the Erase Suspend Operation - Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector. | 2012-03-08 |
| 20120057411 | Latch Based Memory Device - A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach. | 2012-03-08 |
| 20120057412 | MEMORY MACRO CONFIGURATION AND METHOD - A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments. | 2012-03-08 |
| 20120057413 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal. | 2012-03-08 |
| 20120057414 | DATA INPUT CIRCUIT OF NONVOLATILE MEMORY DEVICE - The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals. | 2012-03-08 |
| 20120057415 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a number of page buffer groups each comprising a number of normal page buffers, I/O lines corresponding to the respective normal page buffers, and a column decoder generating a column address decoding signal for coupling the normal page buffers of one of the page buffer groups and the respective I/O lines in response to a normal control clock signal. | 2012-03-08 |
| 20120057416 | SRAM LEAKAGE REDUCTION CIRCUIT - A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of V | 2012-03-08 |
| 20120057417 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CONTROLLING PROGRAMMING CURRENT PULSE - A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code. | 2012-03-08 |
| 20120057418 | MEMORIES AND METHODS FOR SHARING A SIGNAL NODE FOR THE RECEIPT AND PROVISION OF NON-DATA SIGNALS - Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals. | 2012-03-08 |
| 20120057419 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes an address controller for storing fail column addresses and sequentially outputting the fail column addresses while a first control signal is activated and a control logic for performing control so that data indicating a program pass is inputted to each of main page buffers associated with the respective fail column addresses outputted from the address controller while the first control signal is activated. | 2012-03-08 |
| 20120057420 | SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME - A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads. | 2012-03-08 |
| 20120057421 | DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS - Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. | 2012-03-08 |
| 20120057422 | LOW POWER SENSE AMPLIFIER FOR READING MEMORY - A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current. | 2012-03-08 |
| 20120057423 | ELECTRICAL FUSE MEMORY ARRAYS - Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column. | 2012-03-08 |
| 20120057424 | Memory Device Having Multiple Power Modes - A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command. | 2012-03-08 |
| 20120057425 | CARTRIDGE FROM WHICH BONE CEMENT IS DISCHARGED, THE CARTRIDGE HAVING A REMOVABLE COUPLE NOZZLE - A cartridge in which bone cement is mixed and from which the cement is discharged. A blade with plural vanes is disposed in the cartridge for mixing the cement. A piston located in one end of the cartridge is actuated to push the mixed cement out of the cartridge. The blade has plural vanes, one for scraping cement off the side of the cartridge, one for scraping cement off the piston and one for scraping cement off the end of the cartridge opposite the end in which the piston is normally located. The blade is collapsible so that when the piston is actuated the blade compresses to allow the cement in the cartridge to be pushed out. | 2012-03-08 |
| 20120057426 | Cylindrical tank for the thermal treatment of a food mixture in general and machine for the production of food mixtures equipped with this cylindrical tank - The invention relates to a cylindrical tank for the thermal treatment of a food product which includes heating and/or cooling means for the food product, in addition to a mixer housed so as to be revolving in its interior. The tank has a cylindrical mantle, closed by a rear bottom and by a front flange, there also being means for feeding the mentioned product inside the tank. At least one temperature sensor of the food product is also positioned in correspondence with an area situated in the front portion of the mantle, corresponding to the discharge area of the same food product from the tank. The invention also relates to machines which use the above-mentioned tank. | 2012-03-08 |
| 20120057427 | FLOW CONDITIONING APPARATUS - Apparatus for homogenization of multi-phase fluid; the fluid including at least a first phase and a second phase a gaseous phase and a liquid phase; the apparatus including an inner reservoir fluidly communicative with an outer receptacle; the inner reservoir including an inlet for multiphase fluid, an outlet having a smaller cross sectional area than the body for outflow of the first phase and at least one opening into the outer receptacle for outflow of the second phase, the opening being spaced from the first phase outlet; wherein the outer receptacle has an inlet conduit having a neck which at least partially surrounds the inner reservoir outlet. | 2012-03-08 |
| 20120057428 | CALIBRATION OF ULTRASOUND PROBES - A method of calibrating an ultrasound probe includes mounting an ultrasound probe onto a calibration system, transmitting an ultrasound test signal from an element of the probe through a test medium of the calibration system, and receiving the test signal on a matrix of hydrophones such that an element's position relative to other elements and other arrays within the same probe can be computed. Further, the system described herein is configured to detect the acoustic performance of elements of a probe and report the results to an end user or service provider. | 2012-03-08 |
| 20120057429 | TUNING UNIQUE COMPOSITE RELATIVELY ADJUSTED PULSE - The invention relates to acquiring seismic data in either land or marine environments, but typically marine environments where a pulse-type source is fired in a distinctive composite pulse like a distinctive rumble. In a preferred embodiment, a number of pulse-type seismic sources, sometimes called an array, are fired in a distinctive composite pulse to be able to identify within the returning wavefield the energy resulting from the composite pulse. Firing the pulse-type sources creates an identifiable signature so that two or more marine seismic acquisition systems with source arrays can be acquiring seismic data concurrently and the peak energy delivered into the water will be less, which will reduce the irritation of seismic data acquisition to marine life. In addition, the composite pulse may be formulated by timing the firing of several of the sources with respect to energy emitted by “ringing” bubbles that attenuate within 100 to 300 ms to provide either or both of low frequency pulses and high frequency pulses to provide data for various processing and analysis of the data returned from the subsurface. On land, the complicating factor to be addressed is reverberation rather than bubbles. | 2012-03-08 |
| 20120057430 | MULTI-COMPONENT, ACOUSTIC-WAVE SENSOR AND METHODS - A multi-component sensor of a fluid-borne acoustic wave that senses pressure and up to three orthogonal particle motion components. The sensor is unresponsive to motion of the sensor mount. Furthermore, the sensor is substantially unresponsive to the turbulent flow of the acoustic medium past the sensor. | 2012-03-08 |
| 20120057431 | GENERATING INVERSION READY SEISMIC DATA - A technique includes receiving first seismic data acquired by one or more receivers in response to energy produced by one or more seismic sources interacting with a subsurface feature. The first seismic data is indicative of measured reflection coefficients for image points for the subsurface feature, the measured reflection coefficients are associated with incidence angles, and a range of the incidence angles varies with respect to an image point position. The technique includes processing the first seismic data in a machine to generate second data indicative of a normal incidence reflection coefficient for at least one of the image points not associated with a normal angle of incidence. | 2012-03-08 |
| 20120057432 | Well Monitoring by Means of Distributed Sensing Means - This application describes methods and apparatus for downhole monitoring in real-time. The method involves interrogating an unmodified optic fibre ( | 2012-03-08 |
| 20120057433 | Display for Use in Managing Movement of a Patient in a Bed - A system is provided for communicating to health care workers the turning, positioning and schedule requirements of dependent patients with pressure ulcers, or at risk for the development of pressure ulcers. The system includes a display indicating a next required position of the patient and a display indicating a time for next movement of the patient to the next position. The time of next movement is calculated by entering an indication of a maximum allowable time for the patient to remain in each position and adding this to the current time. | 2012-03-08 |
| 20120057434 | TIMEPIECE FURNISHED WITH A DEVICE FOR DISPLAYING DETERMINED TIME PERIODS - This device for displaying time periods comprises a display element (A), an indicator component ( | 2012-03-08 |
| 20120057435 | Drive control apparatus, timepiece apparatus, and electronic apparatus - The invention is intended to allow a motor to be driven normally even when an output voltage of a primary power source unit varies. A motor drive control unit configured to attenuate a charge of a secondary cell by an electromotive force of a solar cell to a level lower than the charge at that moment before driving the motor, and then intensify the charge of a level higher than the charge at that moment after having driven the motor is provided. | 2012-03-08 |
| 20120057436 | Electronic device, electronic device control method, and electronic device control program - An electronic device includes a primary power supply portion generating power by converting a first energy into electric energy as a second energy; a secondary power supply portion storing the electric energy obtained by the power generation; a charge detection portion detecting a state where the secondary power supply portion is not charged with the electric energy; a clocking portion clocking time and stopping display of clocked time when an operation input is detected; and a low power consumption state control portion which measures a time of a state where the operation input is detected and the charging is not performed, and stops the operation of the clocking portion when the measured time exceeds a preset time. | 2012-03-08 |
| 20120057437 | Power supply unit and electronic timepiece - A power supply unit includes: a first power supply circuit that supplies a voltage to a load driving unit that drives a load unit; a second power supply circuit that supplies a voltage to circuits other than the load driving unit; and a control unit that switches the voltage supplied to the first power supply circuit and the voltage supplied to the second power supply circuit in accordance with properties of the load driving unit. | 2012-03-08 |
