| 10th week of 2013 patent applcation highlights part 56 |
| Patent application number | Title | Published |
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| 20130060988 | METHOD FOR SYMMETRIC LIVE MIGRATION OF VIRTUAL MACHINES - A method is provided for symmetric live migration of virtual machines. According to the method, a first least recently used map is generated for a set of memory pages of a first virtual machine. The first least recently used map includes metadata including memory page physical address location information. A first memory page of the first virtual machine and the metadata for the first memory page is sent from the first virtual machine to a second virtual machine while the first virtual machine is executing. A first memory page and meta data associated therewith of the second virtual machine is received from the second virtual machine. The memory pages of the first virtual machine are ordered from a first location of the first least recently used map to a last location of the first least recently used map based on how recently each of the memory pages of the first virtual machine has been used. | 2013-03-07 |
| 20130060989 | APPARATUS, SYSTEM, AND METHOD FOR REFERENCING DATA BLOCK USAGE INFORMATION BY WAY OF AN INTERFACE - An apparatus, system, and method are disclosed for data management. The method includes referencing data block usage information provided by way of an interface operable to communicate with a storage controller managing non-volatile storage media. The method also includes identifying to the storage controller one or more blocks for deallocation by the data block usage information. | 2013-03-07 |
| 20130060990 | DATA MOVING METHOD FOR FLASH MEMORY MODULE, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of moving a first portion of data and a second portion of data, which belong to one page data and respectively stored in a second physical page and a third physical page, into a first physical page in a flash memory module is provided. The method includes transmitting a read command for reading page data stored in the second physical page; reading the first portion of data from a buffer area of the rewritable non-volatile memory module into a buffer memory; transmitting a read command for reading page data stored in the third physical page; transmitting the first portion of data from the buffer memory to the buffer area; and transmitting a write command for writing data stored in the buffer area into the first physical page. Accordingly, the method can effectively move one page data dispersedly stored in different physical pages into one physical page. | 2013-03-07 |
| 20130060991 | SOLID STATE DRIVE AND GARBAGE COLLECTION CONTROL METHOD THEREOF - A garbage collection control method for a solid state drive is provided. The garbage collection control method includes the following steps. Firstly, a total number of releasable spaces in a plurality of data-containing blocks of a flash memory is calculated and defined as A. A total number of spaces in a plurality of blank blocks of the flash memory is calculated and defined as B. If the ratio B/A is smaller than a first threshold value, a garbage collection is performed. During the garbage collection is performed, if the ratio B/A is larger than a second threshold value, the garbage collection is ended. The first threshold value is smaller than the second threshold value. | 2013-03-07 |
| 20130060992 | DATA COMPRESSION METHOD - A data compression method includes; generating compressed data from raw data having a normal size, defining a super page for a memory having a super size greater than the normal size, selecting a compressed data set from among the compressed data having a compression ratio less than a reference compression ratio ranging between 0.5 and 1.0, and storing the compressed data set in the memory using the super page. | 2013-03-07 |
| 20130060993 | STORAGE DEVICE AND STREAM FILTERING METHOD THEREOF - A storage device may include a main storage part including one or more memories; and a controller configured to control an overall operation of the main storage part. The controller includes a filter manager configured to store data format information and a filtering condition provided from a host; one or more stream filters configured to search and project data stored in the one or more memories in parallel in response to a control of the filter manager to produce searched and projected data; and a merge filter configured to merge the searched and projected data of the one or more stream filters in response to the control of the filter manager. | 2013-03-07 |
| 20130060994 | NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH TIME MEASURE MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory management system includes: selecting a specific time period by a unit controller; establishing a first time pool having super blocks written during the specific time period; and promoting to a second time pool, the super blocks from the first time pool, at the lapse of the specific time period. | 2013-03-07 |
| 20130060995 | MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card | 2013-03-07 |
| 20130060996 | System and Method for Controller Independent Faulty Memory Replacement - In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component. | 2013-03-07 |
| 20130060997 | MITIGATING BUSY TIME IN A HIGH PERFORMANCE CACHE - Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory. | 2013-03-07 |
| 20130060998 | CONTROL SYSTEM AND METHOD OF DISK ARRAY - A control system of a disk array including multiple data storage disks is provided. The control system includes a front-end circuit, a central processing unit and a back-end circuit. The front-end circuit is for receiving multiple packets corresponding to a first protocol from a network. The central processing unit has multiple cores. One of the cores is configured as a first dedicated core to interpret the packets corresponding to the first protocol into multiple first commands. The other non-dedicated cores are for processing the first commands and outputting multiple first access instructions. The back-end circuit is for translating the first access instructions to access the data storage disks. | 2013-03-07 |
| 20130060999 | SYSTEM AND METHOD FOR INCREASING READ AND WRITE SPEEDS OF HYBRID STORAGE UNIT - The present invention is to provide a system for increasing read and write speeds of a hybrid storage unit, which includes a cache controller connected to the hybrid storage unit and a computer respectively, and stores forward and backward mapping tables each including a plurality of fields. The hybrid storage unit is composed of at least one regular storage unit (e.g., an HDD) having a plurality of regular sections corresponding to forward fields respectively, and at least one high-speed storage unit (e.g., an SSD) having a plurality of high-speed storage sections corresponding to backward fields respectively with higher read and write speeds than the regular storage unit. The cache controller can make the high-speed storage section corresponding to each backward field correspond to the regular section corresponding to the forward field, thus allowing the computer to rapidly read and write data from and into the hybrid storage unit. | 2013-03-07 |
| 20130061000 | SOFTWARE COMPILER GENERATED THREADED ENVIRONMENT - A computer-implemented method for creating a threaded package of computer executable instructions from software compiler generated code includes allocating, through a computer processor, the computer executable instructions into a plurality of stacks, differentiating between different types of computer executable instructions for each computer executable instruction allocated to each stack of the plurality of stacks, creating switch points for each stack of the plurality of stacks based upon the differentiating, and inserting the switch points within each stack of the plurality of stacks. | 2013-03-07 |
| 20130061001 | SYSTEM REFRESH IN CACHE MEMORY - System refresh in a cache memory that includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory and activating a refresh request at the centralized refresh controller based on generating the RTIM pulse. The refresh request is associated with a single cache memory bank of the cache memory. A refresh grant is received and transmitted to a bank controller. The bank controller is associated with and localized at the single cache memory bank of the cache memory. | 2013-03-07 |
| 20130061002 | PERFORMANCE OPTIMIZATION AND DYNAMIC RESOURCE RESERVATION FOR GUARANTEED COHERENCY UPDATES IN A MULTI-LEVEL CACHE HIERARCHY - A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit. | 2013-03-07 |
| 20130061003 | COHERENCE SWITCH FOR I/O TRAFFIC - A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing. | 2013-03-07 |
| 20130061004 | MEMORY/LOGIC CONJUGATE SYSTEM - In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories ( | 2013-03-07 |
| 20130061005 | METHOD FOR POWER OPTIMIZED MULTI-PROCESSOR SYNCHRONIZATION - One embodiment of the present invention sets forth a technique for synchronization between two or more processors. The technique implements a spinlock acquire function and a spinlock release function. A processor executing the spinlock acquire function advantageously operates in a low power state while waiting for an opportunity to acquire spinlock. The spinlock acquire function configures a memory monitor to wake up the processor when spinlock is released by a different processor. The spinlock release function releases spinlock by clearing a lock variable and may clear a wait variable. | 2013-03-07 |
| 20130061006 | DATA MASK ENCODING IN DATA BIT INVERSION SCHEME - Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte. | 2013-03-07 |
| 20130061007 | GENERATING CODE THAT CALLS FUNCTIONS BASED ON TYPES OF MEMORY - In an embodiment, in response to reading a declaration of a function that specifies a name of the function and a type of memory on which the function operates, the name of the function, a pointer to the function, and the type are saved to a template. In response to reading a call statement that specifies the name of the function and an identifier of an object, first code is generated. The first code, when executed, reads the pointer to the function from a virtual function table pointed to by the object, finds an entry in the virtual function table that represents the function, and reads the pointer from the entry in the virtual function table. The call statement, when executed, requests a call of the function. Second code is generated that, when executed, calls the function using the pointer read from the virtual function table. | 2013-03-07 |
| 20130061008 | CONCURRENT CODING OF DATA STREAMS - A method begins by a dispersed storage (DS) processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the DS processing module segmenting each of the first and second data streams to produce a first plurality of data segments and a second plurality of data segments, dividing one of the first plurality of data segments into a first plurality of data blocks, and dividing one of the second plurality of data segments into a second plurality of data blocks. The method continues with the DS processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the DS processing module outputting one or more pairs of coded values of the coded matrix to the receiving entity. | 2013-03-07 |
| 20130061009 | High Performance Free Buffer Allocation and Deallocation - The disclosure includes an apparatus comprising a memory configured to store a free list comprising a plurality of nodes, wherein at least one of the plurality of nodes is configured to store a plurality of node addresses, and wherein each of the plurality of node addresses corresponds to one node in the plurality of nodes. The disclosure further includes a method of memory management comprising using a free list comprising a plurality of nodes and storing a plurality of node addresses in at least one of the plurality of nodes, and wherein each of the plurality of node addresses corresponds to one node in the plurality of nodes. | 2013-03-07 |
| 20130061010 | ORDERING WRITE BURSTS TO MEMORY - A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on the determined number of the requests intended for each of the banks, and send one of the requests to the memory based on the determined order. | 2013-03-07 |
| 20130061011 | METHOD OF MANAGING MEMORY AND IMAGE FORMING APPARATUS TO PERFORM THE SAME - A method of managing memory, the method including extracting location information of erasure data in which file allocation information has been deleted, and performing an overwrite job on the erasure data in a memory, based on the extracted location information. | 2013-03-07 |
| 20130061012 | VIRTUAL MACHINE CODE INJECTION - A memory has a page to store code executable by a processor. A management component is to inject the code into a virtual machine. The management component is to indicate within a memory table for the virtual machine that the page of the memory has an injected code type. | 2013-03-07 |
| 20130061013 | STORAGE SYSTEM, AND APPARATUS AND METHOD FOR CONTROLLING STORAGE - A write control unit executes, for example, asynchronously a process of writing data to a first volume and a process of generating a code corresponding to the written data with respect to each partial area in the first volume and registering the generated codes in a code storing unit. The replication control unit replicates data of a replication target area in the first volume to a second volume, and determines partial areas of the replication target area, in which partial areas identical data is stored, based on the codes registered in the code storing unit and allocates the same physical storage area to partial areas of the second volume, which partial areas correspond to the determined partial areas. | 2013-03-07 |
| 20130061014 | SYSTEMS AND METHODS FOR MANAGEMENT OF VIRTUALIZATION DATA - Described in detail herein is a method of copying data of one or more virtual machines being hosted by one or more non-virtual machines. The method includes receiving an indication that specifies how to perform a copy of data of one or more virtual machines hosted by one or more virtual machine hosts. The method may include determining whether the one or more virtual machines are managed by a virtual machine manager that manages or facilitates management of the virtual machines. If so, the virtual machine manager is dynamically queried to automatically determine the virtual machines that it manages or that it facilitates management of. If not, a virtual machine host is dynamically queried to automatically determine the virtual machines that it hosts. The data of each virtual machine is then copied according to the specifications of the received indication. | 2013-03-07 |
| 20130061015 | ACCESS CONTROL APPARATUS AND ACCESS CONTROL SYSTEM - According to one embodiment, an access control apparatus includes a medium communication module configured to perform communication with a removable medium, a access module configured to perform access to the removable medium using the communication module, a wireless communication module configured to perform wireless communication with a external device, and to receive access request to the removable medium, and a controller configured to assign an access right to access the removable medium to one of the access module and the external device, the control module assigning the access right in response to a request of assignment of the access right, the request being transmitted from the external device or the access module. | 2013-03-07 |
| 20130061016 | VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER - A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed. | 2013-03-07 |
| 20130061017 | Method and Apparatus for Managing Video Memory in Embedded Device - A method for managing an image memory in an embedded device is provided. A node is obtained from a linked list of the image memory. It is judged whether valid data is present in a memory block corresponding to the node. When no valid data is present, it is judged whether valid data is present in a memory block corresponding to a previous node of the node. When valid data is present in the previous node, it is further judged whether the valid data is movable. When the valid data is movable, memory block information described in the two nodes is exchanged, and the valid data previously stored in the memory block corresponding to the previous node is moved to the memory block corresponding to the node. | 2013-03-07 |
| 20130061018 | MEMORY ACCESS METHOD FOR PARALLEL COMPUTING - A memory access method for parallel computing, which is applied in the case that n (n≧2) parallel threads invoke the same original execution module, comprises the following steps: S | 2013-03-07 |
| 20130061019 | STORAGE CONTROL SYSTEM WITH WRITE AMPLIFICATION CONTROL MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: partitioning logical addresses into a number of subdrives, the logical addresses associated with a memory device; and monitoring a data write measure of one of the subdrives. | 2013-03-07 |
| 20130061020 | Computer System with Processor Local Coherency for Virtualized Input/Output - A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output. | 2013-03-07 |
| 20130061021 | SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR CONTROLLING SAME - Disclosed are a semiconductor memory system and a method for controlling same. The semiconductor memory system according to one embodiment of the present invention includes: a first memory for storing normal data and master metadata, the master metadata representing a relationship between a local address and a physical address for accessing the normal data; and a control logic generating compression metadata compressed in accordance with update metadata and storing the generated metadata in the first memory in response to a first control signal. | 2013-03-07 |
| 20130061022 | COMPILER FOR PROVIDING INTRINSIC SUPPORTS FOR VLIW PAC PROCESSORS WITH DISTRIBUTED REGISTER FILES AND METHOD THEREOF - A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations. | 2013-03-07 |
| 20130061023 | COMBINING DATA VALUES THROUGH ASSOCIATIVE OPERATIONS - A method for combining data values through associative operations. The method includes, with a processor, arranging any number of data values into a plurality of columns according to natural parallelism of the associative operations and reading each column to a register of an individual processor. The processors are directed to combine the data values in the columns in parallel using a first associative operation. The results of the first associative operation for each column are stored in a register of each processor. | 2013-03-07 |
| 20130061024 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2013-03-07 |
| 20130061025 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2013-03-07 |
| 20130061026 | CONFIGURABLE MASS DATA PORTIONING FOR PARALLEL PROCESSING - A configurable mass data portioning for parallel processing is described herein. One or more operation attributes are selected to participate in parallelization criteria. The values of the selected operation attributes for a number of operations are submitted to a specified algorithm using to provide parallelization values corresponding to the operations. The parallelization values are applied to group the operations in comparable portions for parallel execution without conflicts. | 2013-03-07 |
| 20130061027 | TECHNIQUES FOR HANDLING DIVERGENT THREADS IN A MULTI-THREADED PROCESSING SYSTEM - This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction identified by a program counter value stored in a program counter register. The control flow instruction may include a target value indicative of a target program counter value for the control flow instruction. The control flow unit may select one of the target program counter value and a minimum resume counter value as a value to load into the program counter register. The minimum resume counter value may be indicative of a smallest resume counter value from a set of one or more resume counter values associated with one or more inactive threads. Each of the one or more resume counter values may be indicative of a program counter value at which a respective inactive thread should be activated. | 2013-03-07 |
| 20130061028 | Method and system for multi-mode instruction-level streaming - The present invention relates to systems, apparatuses and methods for parallel computing of an application, by streaming instructions between cores, where the cores can execute more than one instruction during the course of the application. | 2013-03-07 |
| 20130061029 | METHOD AND APPARATUS FOR CONSOLIDATING BOOT DRIVES AND IMPROVING RELIABILITY/AVAILABILITY/SERVICEABILITY IN HIGH DENSITY SERVER ENVIRONMENTS - The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and Ethernet connection which may be used for providing alerts regarding the health of the components of the boot appliance and/or data storage system to a monitoring system, such as a network management system. The boot appliance may provide a boot drive and operating system image to multiple servers at the same time. | 2013-03-07 |
| 20130061030 | SYSTEM CAPABLE OF BOOTING THROUGH A UNIVERSAL SERIAL BUS DEVICE AND METHOD THEREOF - A system capable of booting through a Universal Serial Bus device includes a Universal Serial Bus port, an embedded controller, a platform control hub, and a basic input/output system. The embedded controller is used for generating a boot signal when the system is powered off and at least one Universal Serial Bus device is plugged into the Universal Serial Bus port. The platform control hub is restored according to the boot signal. The basic input/output system has boot sequence setting values. The basic input/output system first starts to boot the at least one Universal Serial Bus device through the platform control hub according to the boot sequence setting values when the basic input/output system is restored according to the boot signal. | 2013-03-07 |
| 20130061031 | SYSTEM AND METHOD FOR BIOS AND CONTROLLER COMMUNICATION - A system and method for BIOS and controller communication is provided herein. The system may include an information handling system that includes a central processing unit coupled to a memory. The memory may contain a basic input/output system (BIOS). The information handling systems may also include a controller coupled to a nonvolatile memory and a register coupled to the central processing unit and the controller. The controller may be operable to store a key in the nonvolatile memory; write the key to the register in response to a signal from the BIOS; receive a command from the BIOS; verify the command is from the BIOS using the key; and execute the command if the command is from the BIOS. | 2013-03-07 |
| 20130061032 | EXTERNAL BOOT DEVICE, EXTERNAL BOOT METHOD, INFORMATION PROCESSING APPARATUS, AND NETWORK COMMUNICATION SYSTEM - An external boot device includes a storage unit ( | 2013-03-07 |
| 20130061033 | DATA PROCESSING SYSTEM AND METHOD FOR SWITCHING BETWEEN HETEROGENEOUS ACCELERATORS - A method for operating a system on chip includes receiving an acceleration request signal generated upon execution of an application program, in response to receipt of the acceleration request signal, comparing a current usage of a central processing unit (CPU) with a threshold value to generate a comparison signal, and performing switching between heterogeneous accelerators to accelerate a function executed by the application program in response to the comparison signal. | 2013-03-07 |
| 20130061034 | Transparent Mode Encapsulation - A method for providing transparent Ethernet frame adjacency may include removing a MAC addresses from a received Ethernet frame to generate a partial Ethernet frame. The partial Ethernet frame may then be encrypted. The encrypted Ethernet frame may be encapsulated in an Internet Protocol (IP) packet. The IP packet may include an indication of a Security Association (SA). The packet may be sent over a non-secure network. A device may de-encapsulate the payload of a received IP packet to generate the encrypted partial Ethernet frame. The device may decrypt the encrypted partial Ethernet frame to generate a partial Ethernet frame. The decryption device may new MAC addresses based on the SA indicated in the received IP packet. The device may append the new MAC addresses to the partial Ethernet frame such the transmitted Ethernet frame is identical to the Ethernet Frame originated at the source network device. | 2013-03-07 |
| 20130061035 | METHOD AND SYSTEM FOR SHARING ENCRYPTED CONTENT - The present invention relates to the field of sharing encrypted content. In one form, the invention relates to multiple user access and management of encrypted content. In one particular aspect, the present invention is suitable for use in community controlled encryption of shared content using indirect keys. | 2013-03-07 |
| 20130061036 | METHOD AND APPARATUS FOR PROVIDING A STRUCTURED AND PARTIALLY REGENERABLE IDENTIFIER - An approach is provided for generating a structured and partially regenerable identifier. An identification generation platform receives a request to generate at least one regenerable that includes, at least in part, a plurality of fields. The identification generation platform determines to separately hash and/or encrypt the respective ones of the plurality of fields. A generation of the at least one identifier is caused, based at least in part, on the hashed and/or encrypted respective ones of the plurality of fields. | 2013-03-07 |
| 20130061037 | ENCRYPTION COMMUNICATION METHOD, APPARATUS AND SYSTEM - An encrypted communication method relating to communication technologies includes allocating a same encryption key for a first application and a terminal that is only bound to the first application. The method also includes transparently transmitting information communicated between the terminal and the first application when determining that the terminal communicates with the first application by using the same encryption key. | 2013-03-07 |
| 20130061038 | Proxy Apparatus for Certificate Authority Reputation Enforcement in the Middle - Network security administrators are enabled with their customizable certificate authority reputation policy store which is informed by an independent certificate authority reputation server. The custom policy store overrides trusted root certificate stores accessible to an operating system web networking layer or to a third party browser. Importing revocation lists or updating browsers or operating system is made redundant. The apparatus redirects or rewrites traffic to protect a plurality of endpoints from a man-in-the-middle attack when a certificate authority has lost control over certificates used in TLS. | 2013-03-07 |
| 20130061039 | METHOD AND SYSTEM FOR SECURING DATA UTILIZING RECONFIGURABLE LOGIC - A method, an article of manufacture, and a process are provided for securing data sets by dynamically hopping amongst a variety of data encryption and/or manipulation protocols. Such dynamic protocol hopping can be implemented in reconfigurable logic. The encryption protocol applied to the data set is selected from among a plurality of encryption protocols. Preferably, the selection can be driven by a random number generator. | 2013-03-07 |
| 20130061040 | SYSTEMS AND METHODS FOR PROTECTING ALTERNATIVE STREAMS IN ADAPTIVE BITRATE STREAMING SYSTEMS - Systems and methods for performing adaptive bitrate streaming using alternative streams of protected content in accordance with embodiments of the invention are described. One embodiment includes a processor, and non-volatile storage containing an encoding application. In addition, the encoding application configures the processor to: receive source content; obtain common cryptographic information; encode the source content as a plurality of streams including a plurality of alternative streams of content; and protect the plurality of alternative streams of content using the common cryptographic information. | 2013-03-07 |
| 20130061041 | IMAGE FORMING APPARATUS, PRINTING METHOD, AND STORAGE MEDIUM - An image forming apparatus, for use in a printing system including a print client, a printer server, and an authentication server, enables a secure print setting according to received policy information specifying that printing is to be performed using a secure print protocol employing a certificate. | 2013-03-07 |
| 20130061042 | Apparatus and Method for Monitoring Certificate Acquisition - A system that incorporates teachings of the present disclosure may include, for example, a set-top-box having a controller to transmit a request to a remote management server for status information associated with a x.509 certificate intended for the STB, and receive the status information associated with the x.509 certificate from the remote management server, where events associated with the status information are received by the remote management server from at least one of the STB, a certificates proxy, an external certificate web service, and a certificate authority, and where the status information comprises at least a portion of the received events. Other embodiments are disclosed. | 2013-03-07 |
| 20130061043 | METHOD OF VALIDATION PUBLIC KEY CERTIFICATE AND VALIDATION SERVER - In response to a validation request that includes second information identifying the certificate authority, key information of the certificate authority at issuance of the public key certificate, and information identifying the public key certificate, if the second information identifying the certificate authority included in the validation request corresponds to the first information identifying the certificate authority included in the authority certificate, and the information identifying the public key certificate included in the validation request does not exist in the revocation information, the validation server creates a validation result indicating that the public key certificate corresponding to the information identifying the public key certificate included in the validation request is valid. | 2013-03-07 |
| 20130061044 | SYSTEM AND METHOD FOR INDEPENDENT CONTROL OF FOR-HIRE VEHICLES - A computer system storing parameters pertaining to the regulatory restrictions placed on a for-hire vehicle compares the parameters to a current operating environment of the for-hire vehicle. In some embodiments, the computer system acts as the meter (such as a taximeter) of the for-hire vehicle. The operating parameters may include expiration or exclusion parameters that define the scope of operation of the for-hire vehicle stemming from the for-hire vehicle's medallion or certificate of public convenience and necessity. The expiration or exclusion parameters may also correspond to a driver's permit or any general regulation enacted by the regulatory agency. If the current operating environment does not comply with the expiration or exclusion parameters, the computer system shuts down, or enters a standby mode, and may not accept additional passenger fares until the current operating environment complies with the expiration and exclusion parameters. | 2013-03-07 |
| 20130061045 | Systems and Methods for Playing Back Alternative Streams of Protected Content Protected Using Common Cryptographic Information - Systems and methods for performing adaptive bitrate streaming using alternative streams of protected content in accordance with embodiments of the invention are described. One embodiment of the invention includes a processor, and memory containing a client application. In addition, the client application configures the processor to: request a top level index file identifying a plurality of alternative streams of protected content, where each of the alternative streams of protected content are encrypted using common cryptographic information; obtain the common cryptographic information; request portions of content from at least the plurality of alternative streams of protected content; access the protected content using the common cryptographic information; and playback the content. | 2013-03-07 |
| 20130061046 | Stateless Application Notifications - Stateless application notifications are described that enable third parties to provide messages to client applications. A communication channel can be established between a notification service and an application. Upon request, the notification service can generate obfuscated routing data for the channel, which can be in the form of a channel handle or token. The routing data can be encrypted and digitally signed to obscure the content and format of the routing data from third parties. An application service possessing the obfuscated routing data can package a notification with the data and send the package to the notification service for delivery. The application service does so without knowing the channel particulars encoded by the obfuscated routing data. The notification service that produces the obfuscated routing data can decrypt and interpret the data, and deliver the notification on the channel to an appropriate endpoint application on behalf of the application service. | 2013-03-07 |
| 20130061047 | SECURE AND EFFICIENT OFFLOADING OF NETWORK POLICIES TO NETWORK INTERFACE CARDS - Techniques for efficient and secure implementation of network policies in a network interface controller (NIC) in a host computing device operating a virtualized computing environment. In some embodiments, the NIC may process and forward packets directly to their destinations, bypassing a parent partition of the host computing device. In particular, in some embodiments, the NIC may store network policy information to process and forward packets directly to a virtual machine (VM). If the NIC is unable to process a packet, then the NIC may forward the packet to the parent partition. In some embodiments, the NIC may use an encapsulation protocol to transmit address information in packet headers. In some embodiments, this address information may be communicated by the MC to the parent partition via a secure channel. The NIC may also obtain, and decrypt, encrypted addresses from the VMs for routing packets, bypassing the parent partition. | 2013-03-07 |
| 20130061048 | CONTENT DELIVERY SYSTEM, DELIVERY SERVER, AND USER TERMINAL - Provided are a content delivery system, a delivery server and a user terminal whereby the load of a party who transmits content data cau be reduced. A delivery server ( | 2013-03-07 |
| 20130061049 | DISTRIBUTED NETWORK SYSTEM - A method of storing data from a first node on a peer-to-peer network. The method includes creating a public and private key pair from a data item. The method also includes determining a hash value for the public key and assigning the hash value as a user identifier for the user of the node. The method also includes storing the public key within a distributed hash table of the peer-to-peer network. The user identifier corresponds to the key for the public key within the distributed hash table. | 2013-03-07 |
| 20130061050 | Computational systems and methods for linking users of devices - Methods, apparatuses, computer program products, devices and systems are described that carry out accepting device-identifier data corresponding to at least one communication device; accepting network-participation identifier data associated with a verified real-world user associated with the at least one communication device; and assigning a unique identifier at least partly based on the device-identifier data and the network-participation identifier data. | 2013-03-07 |
| 20130061051 | METHOD FOR AUTHENTICATING ELECTRONIC TRANSACTION, SERVER, AND TERMINAL - A method for authenticating an electronic transaction includes: transmitting first authentication data to a first terminal and transmitting second authentication data to a second terminal; receiving first encryption data from the first terminal and receiving second encryption data from the second terminal, the first encryption data corresponding to the first authentication data and the second encryption data corresponding to the second authentication data; storing the first encryption data and the second encryption data; and authenticating the first terminal and the second terminal according to the first authentication data and the second authentication data. The first encryption data is encrypted by a first internal key of the first terminal, and the second encryption data is encrypted by a second internal key of the second terminal. | 2013-03-07 |
| 20130061052 | SYSTEM AND METHOD FOR AUTHENTICATION IN WIRELESS NETWORKS BY MEANS OF ONE-TIME PASSWORDS - The present invention is directed to perform high-reliable authentication using a one-way function that a communication is a communication which was performed with the same apparatus to be authenticated by storing a password only in an apparatus to be authenticated (it is unnecessary to store a password in both of an authentication apparatus and an apparatus to be authenticated) without transmitting a challenge code. When a setting is updated in a setting management server, authentication is performed by using a one-time password obtained last time. A sound communication terminal performs a process using a hash function once on a one-time password transmitted this time, and performs authentication by determining whether the processed one-time password matches a one-time password obtained last time or not. Whether the information at the time of the change in the setting is proper or not is determined by a sound terminal. | 2013-03-07 |
| 20130061053 | RECORDING MEDIUM DEVICE, TERMINAL DEVICE, DISTRIBUTION DEVICE, CONTROL METHOD, AND PROGRAM RECORDING MEDIUM - When the terminal device | 2013-03-07 |
| 20130061054 | METHOD TO CONTROL AND LIMIT READABILITY OF ELECTRONIC DOCUMENTS - A series of data treatment processes, software applications and hardware devices jointly used to achieve the ability to make an electronic document available to the public or to a limited audience to either cease being readable, or start being readable, at a given moment in time or after a given event has occurred. A typical usage scenario consists in “automatic destruction” of documents used internally by an organization and that must be made unreadable after a certain project is complete. Conversely, public offers for auctions may be posted to all the participants and the issuer in an unreadable form, and made then readable after the deadline of the auction is expired. Again, documents may be made unreadable after a certain number of reads, or forwarded to a specific address under some conditions, or accessed only through well-known unmodified clients. | 2013-03-07 |
| 20130061055 | Apparatus and Methods for Providing Scalable, Dynamic, Individualized Credential Services Using Mobile Telephones - A virtual smartcard and methods for creating the same are provided. A virtual smartcard is a set of computer-implemented processes, associated with an individual, which simulate the behavior of a physical smartcard or other authentication token containing a hardware security module. In one embodiment, a computer receives credential data derived from the physical credential and authentication data pertinent to the individual such as a biometric imprint, and creates a virtual smartcard by storing the credential data in association with the authentication data in a network storage. The credential data may later be used for identification and encryption purposes upon the individual providing the authentication data to the network storage, even if the physical credential itself has been lost. Thus, the virtual smartcard provides a network-based method for backing up a passport, driver's license, credit card, public transportation card, or other such identification card or device. | 2013-03-07 |
| 20130061056 | EXTENDING AN INTEGRITY MEASUREMENT - A method of extending an integrity measurement in a trusted device operating in an embedded trusted platform by using a set of policy commands to extend a list of Platform Configuration Registers (PCRs) for the device and the current values of the listed PCRs and an integrity value identifying the integrity measurement into a policy register, verify a signature over the integrity value extended into the policy register, and, if verification succeeds, extend a verification key of the trusted platform, plus an indication that it is a verification key, into the policy register, compare the integrity value extended into the policy register with a value stored in the trusted platform, and, if they are the same: extend the stored value, plus an indication that it is a stored value, into the policy register, and extend the integrity measurement in the trusted device if the value in the policy register matches a value stored with the integrity measurement. | 2013-03-07 |
| 20130061057 | AUTHENTICATION METHOD AND DEVICE - The present invention describes a method for authenticating a user of a mobile device by a verification authority, by making use of at least a personal identification number (PIN) and at least one cryptographic key, such that the PIN and the cryptographic key is known only to the user and the verification authority. The cryptographic key has at least one session key. Firstly, the user encodes the PIN by using at least one session key and then transfers the encoded PIN to a predefined address of the verification authority via the mobile device. Next, the verification authority decodes the PIN by using the cryptographic key authenticates the user if the decoded PIN matches a PIN stored corresponding to the user. | 2013-03-07 |
| 20130061058 | PROTECTING APPLICATION PROGRAMS FROM MALICIOUS SOFTWARE OR MALWARE - An apparatus includes a memory to store a secure object comprising at least one of code and data that is encrypted when stored in the memory and a central processing unit (CPU) that is capable of executing an EnterSecureMode (esm) instruction that enables the decryption of the secure object's information when the secure object information is retrieved from the memory into the CPU. The CPU further comprises a feature to protect the secure object from code received from other software. | 2013-03-07 |
| 20130061059 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - An information processing apparatus including a virtual computer includes a key pair generating unit that generates a key pair of a virtual computer secret key and a virtual computer public key, a public key output unit that outputs the virtual-computer public key, a process target data retrieving unit that retrieves process target data encrypted with the virtual computer public key, a decryption unit that decrypts the retrieved process target data, a process program retrieving unit that retrieves a process program, an executing unit that executes the retrieved process program on the decrypted process target data, a public key retrieving unit that retrieves a process requester public key, an encryption unit that encrypts, with the retrieved process requester public key, process result data as a process result of the process program, and a process result data output unit that outputs the encrypted process result data. | 2013-03-07 |
| 20130061060 | Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof - Embodiments provide systems and methods for controlling the use of processing algorithms, and applications thereof. In an embodiment, authorization to use an algorithm is validated in a system having a processor capable of executing user defined instructions, by executing a user defined instruction that writes a first value to a first storage of a user defined instruction block, uses the first value to transform a second value located in a second storage of the user defined instruction block, and compares the transformed second value to a third value located in a third storage. Use of the algorithm is permitted only if the comparison of the transformed second value to the third value indicates that use of the algorithm is authorized. In another embodiment, authorization to use an at least partially decrypted algorithm is validated via a key for enablement. | 2013-03-07 |
| 20130061061 | PROTECTING LOOK UP TABLES BY MIXING CODE AND OPERATIONS - In the field of computer enabled cryptography, such as a cipher using lookup tables, the cipher is hardened against an attack by a protection process which obscures the lookup tables using the properties of bijective functions and applying masks to the tables' input and output values, for encryption or decryption. This is especially advantageous in a “White Box” environment where an attacker has full access to the cipher algorithm, including the algorithm's internal state during its execution. This method and the associated computing apparatus are useful for protection against known attacks on “White Box” ciphers, by obfuscating lookup table data, thereby increasing the cipher's complexity against reverse engineering and other attacks. | 2013-03-07 |
| 20130061062 | DATA COPYRIGHT MANAGEMENT - A data copyright management apparatus for handling data copyrights, and data of digital cash and video conference system is provided. The data copyright management apparatus comprises a CPU, ROM, EEPROM, and RAM. The ROM, EEPROM, and RAM are connected to the CPU bus, and a system bus of a device which utilizes the data can be connected to the CPU bus. A data copyright management system program, cryptographic algorithm, and user information are stored in the ROM, and a first public-key, a first private-key, a second public-key, a second private-key, a first secret-key, a second secret-key, and copyright information are stored in the EEPROM. The data copyright management apparatus may be configured in the form of a monolithic or hybrid IC, a thin IC card, PC card, insertion board, and further, may be incorporated in a computer, television set, set-top box, digital video tape recorder, digital video disk recorder, digital audio tape apparatus, or personal digital assistants, and the like. | 2013-03-07 |
| 20130061063 | Physical Digital Media Delivery - The inventions relate to the delivery, transfer of cement, and return of uniquely customized physical digital media. Digital content is specifically encrypted for use on a target player associated with a specific customer account. After use, the media is returned to a receiving location where use information is read from the media. Attention is given to cost of delivery, security of content, user experience in selecting, choosing, paying for, viewing or utilizing the content, and usage information created as a result of the content being utilized, rented, purchased, loaded or deleted. | 2013-03-07 |
| 20130061064 | Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor - In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed. | 2013-03-07 |
| 20130061065 | SYSTEM AND METHOD FOR AN INTERLEAVED MULTI-STAGE PHASE ARRAY VOLTAGE REGULATOR - In accordance with the present disclosure, a system and method for an interleaved, multi-stage phase array voltage regulator is described. The interleaved, multi-stage phase array voltage regulator includes a first phase array with a plurality of first power stages and a second phase array with a plurality of second power stages. The interleaved, multi-stage phase array voltage regulator may also include a voltage control loop that at least partially controls a duty cycle of the first phase array and the second phase array. Also, the interleaved, multi-stage phase array voltage regulator may include a current control loop that at least partially controls which of the plurality of first power stages and second power stages are active. | 2013-03-07 |
| 20130061066 | COMMUNICATION SYSTEM FOR USE IN HAZARDOUS ENVIRONMENTS - A communication system includes a host device and a peripheral device. The host device includes a data terminal and a power terminal. A data conductor extends between the host device and the peripheral device. The data conductor is configured to channel data between the data terminal and the peripheral device. A power conductor extends between the host device and the peripheral device. The power conductor is configured to channel power between the power terminal and the peripheral device. A zener diode couples the data conductor to the power conductor. The zener diode is configured to control a voltage channeled between the host device and the peripheral device while data is channeled through the data conductor at a desired speed that is greater than a predetermined threshold. | 2013-03-07 |
| 20130061067 | ELECTRONIC SYSTEMS AND POWER MANAGEMENT METHODS THEREOF - An electronic device is provided, including an input output expander, at least one electronic device and a control module. The input output expander outputs a power source to a peripheral device by at least one output terminal The electronic device is coupled to the input output expander in a daisy chain configuration. The control module adjusts current powers of the electronic device and the peripheral device according to real time powers of the electronic device and the peripheral device, a maximum output power and parameters, thereby preventing power outputted by the input output expander from being larger than the maximum output power. | 2013-03-07 |
| 20130061068 | METHOD AND APPARATUS FOR DYNAMIC POWER MANAGEMENT CONTROL USING SERIAL BUS MANAGEMENT PROTOCOLS - An apparatus for on-demand power management including an I/O serial communication master device, peripheral devices that communicate with the master device along the serial communications bus, and a power manager that buffers the peripheral devices from the serial communication master. The power manager also manages voltage regulation and clock sources to the peripheral devices, with the ability of placing the peripheral devices in an inactive state, or in any number of active states as a means to conserve energy. In some embodiments, the I/O serial communications master acts as if the peripheral devices are always in the highest activity state, and the power manager manages the communications to and from the peripheral devices and the power management of the peripheral devices to reduce energy consumption and system latency. | 2013-03-07 |
| 20130061069 | SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME - Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit. | 2013-03-07 |
| 20130061070 | MASSIVELY MULTICORE PROCESSOR AND OPERATING SYSTEM TO MANAGE STRANDS IN HARDWARE - A computing apparatus and corresponding method for operating are disclosed. The computing apparatus may comprise a set of interconnected central processing units (CPUs). Each CPU may embed an operating system including a kernel comprising a protocol stack. At least one of the CPUs may further embed executable instructions for allocating multiple strands among the rest of the CPUs. The protocol stack may comprise a Transmission Control Protocol/Internet Protocol (TCP/IP), a User Datagram Protocol/Internet Protocol (UDP/IP) stack, an Internet Control Message Protocol (ICMP) stack or any other suitable Internet protocol. The method for operating the computing apparatus may comprise receiving input/output (I/O) requests, generating multiple strands according to the I/O requests, and allocating the multiple strands to one or more CPUs. | 2013-03-07 |
| 20130061071 | Energy Efficient Implementation Of Read-Copy Update For Light Workloads Running On Systems With Many Processors - A technique for determining if a processor in a multiprocessor system implementing a read-copy update (RCU) subsystem may be placed in low power state. The technique may include determining whether the processor has any RCU callbacks that are ready for invocation or the RCU subsystem requires grace period advancement processing from the processor. The processor may be placed in a low power state if either (1) a first condition holds wherein the processor has one or more pending RCU callbacks, but does not have any RCU callbacks that are ready for invocation and the RCU subsystem does not require grace period advancement processing from the processor, (2) a second condition holds wherein the processor does not have any pending RCU callbacks. | 2013-03-07 |
| 20130061072 | POWER SAVING NODE CONTROLLER - A method and apparatus are provided which allow telecommunication equipment to adjust its power consumption. A controller within a telecommunication node uses data to determine whether to reduce the power consumption of components within the node. The data can be real-time data fed to the node or controller, or data read from storage, or both, depending on the particular implementation. Various examples of data and decision-making are given. | 2013-03-07 |
| 20130061073 | COMPUTER SYSTEM AND COMPUTER - Disclosed herein is a computer system including multiple worker nodes, each being equipped with an electric power generation unit and an electric power storage unit storing electric power generated by the electric power generation unit, and a master node responsible for management of tasks that are assigned to the worker nodes. Each worker node determines an operating cycle time of the worker node to execute a task assigned by the master node or communicate with any other worker node, based on information indicating a change in electric power stored in the electric power storage unit of the worker node. | 2013-03-07 |
| 20130061074 | ELECTRONIC DEVICE AND COMPUTER PROGRAM PRODUCT - An electronic device has, as operation modes, a first mode and a second mode reduced in power consumption from the first mode. The electronic device includes a main unit an operation of which is suppressed in the second mode; and a sub-unit. The sub-unit includes a communicating unit that performs communication via a communication line; and an operation mode controller that changes the operation modes from the second mode to the first mode when the communication with a predefined prescribed device is requested during the second mode and changes the operation modes from the first mode to the second mode at a timing corresponding to termination of the communication. | 2013-03-07 |
| 20130061075 | IMAGE FORMING APPARATUS AND CONTROL METHOD OF IMAGE FORMING APPARATUS - An image forming apparatus includes a reading unit, a first control unit, a second control unit, and a power supply control unit. The reading unit reads authentication information including a card type and a user code. The first control unit determines, in a state where power is not being supplied to the second control unit, whether a card type included in the authentication information read by the reading unit corresponds to a predetermined card type. The second control unit requests an authentication apparatus to perform user authentication based on the authentication information read by the reading unit. The power supply control unit controls power supply to the second control unit. In response to the first control unit determining that the card type included in the authentication information read by the reading unit corresponds to the predetermined card type, the power supply control unit supplies power to the second control unit. | 2013-03-07 |
| 20130061076 | POWER CONSERVATION IN A DISTRIBUTED DIGITAL VIDEO RECORDER/CONTENT DELIVERY NETWORK SYSTEM - A method is provided in one example embodiment and includes determining that a network storage module has resources for buffering data currently being sent to a local storage module; determining if the local storage module should enter into a power saving mode; and buffering the configurable amount of data at the network storage module while the local storage module is in the power saving mode. In more particular embodiments, the method includes communicating the configurable amount of data to the local storage module after it resumes a normal operating mode. In addition, the method may include communicating at least a portion of the configurable amount of data to the local storage module using a unicast protocol or a multicast protocol. | 2013-03-07 |
| 20130061077 | Power Management For A System On A Chip (SoC) - In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed. | 2013-03-07 |
| 20130061078 | Massively Multicore Processor and Operating System to Manage Strands in Hardware - A computing apparatus and corresponding method for operating are disclosed. The computing apparatus may comprise a set of interconnected central processing units (CPUs). Each CPU may embed an operating system including a kernel comprising a protocol stack. At least one of the CPUs may further embed executable instructions for allocating multiple strands among the rest of the CPUs. The protocol stack may comprise a Transmission Control Protocol/Internet Protocol (TCP/IP), a User Datagram Protocol/Internet Protocol (UDP/IP) stack, an Internet Control Message Protocol (ICMP) stack or any other suitable Internet protocol. The method for operating the computing apparatus may comprise receiving input/output (I/O) requests, generating multiple strands according to the I/O requests, and allocating the multiple strands to one or more CPUs. | 2013-03-07 |
| 20130061079 | IMAGE PROCESSING APPARATUS, METHOD FOR CONTROLLING THE SAME AND STORAGE MEDIUM - An image processing apparatus according to the present invention, when shifting from a normal operation state to a power saving state, obtains property information indicating a power supply capability from an external apparatus connected thereto via a DC power source line. Based on the obtained property information, the image processing apparatus controls supply of power from a power source unit to devices included in the image processing apparatus in a power saving state. Specifically, in the power saving state, the image processing apparatus supplies, to a portion of the devices, power supplied from the external apparatus via the DC power source line when the power supply capability of the external apparatus is higher than that of the image processing apparatus, and power supplied from a rechargeable battery when otherwise. | 2013-03-07 |
| 20130061080 | INFORMATION PROCESSING APPARATUS HAVING A PLURALITY OF POWER MODES, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An information processing apparatus capable of reducing time taken to return to a standby state after turn-off of a power switch in a power saving state. A power supply supplies power to a CPU and a RAM in a standby state, supplies power to the RAM without supplying power to the CPU in a second waiting state caused by turning off the power switch, and supplies power to the RAM without supplying power to the CPU in the power saving state caused without having the power switch turned off when a shift-to-power saving state requirement defined in advance is satisfied. A power supply controller causes the apparatus to shift from the second waiting state to the standby state using a standby memory image. The CPU writes the standby memory image in the RAM for storage in the power saving state. | 2013-03-07 |
| 20130061081 | THERMAL PROTECTION METHOD AND RELATED SYSTEM FOR A COMPUTER SYSTEM - A thermal protection method for a computer system comprising a thermal detector, a controller, and an input/output system, the thermal protection method including the thermal detector measuring the temperature of the computer system and generating a temperature value, the controller comparing the temperature value and a threshold value, the controller periodically transmitting an over-temperature indication signal to the input/output system when the temperature value is not lower than the threshold value, the input/output system executing a temperature-lowering process when receiving the over-temperature indication signal, and the controller executing a compulsory thermal protection process when determining that the temperature-lowering process is unsuccessfully executed. | 2013-03-07 |
| 20130061082 | BALANCING POWER CONSUMPTION AND HIGH AVAILABILITY IN AN INFORMATION TECHNOLOGY SYSTEM - A method is disclosed for balancing the requirements of high availability achieved by redundant active components and power saving achieved by less active components. The requirement for high availability can be expressed by the recovery time objective (RTO) which specifies the amount of time it takes to recover from a failure in the system. Based on the configured RTO, the system configures the most appropriate power mode. | 2013-03-07 |
| 20130061083 | Quad-Data Rate Controller and Realization Method Thereof - A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, used to arbitrates commands and data according to the state of the control state machine; a read data sampling clock generating module, used to generate read data sampling clocks with the same source and same frequency and different phases; a read data path calibrating module, used to determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; a read data path module, used to synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. | 2013-03-07 |
| 20130061084 | Massively Scalable Object Storage - Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system. | 2013-03-07 |
| 20130061085 | SYSTEM AND METHOD FOR MANAGING A NETWORK INFRASTRUCTURE USING A MOBILE DEVICE - A system and method for managing an IT infrastructure using a mobile device, the method comprises identifying, using one or more processors of a network management system, an issue in one or more components in the infrastructure; retrieving a message instruction for the identified issue from an action database, wherein the message instruction includes information identifying a support personnel and a mobile device of the support personnel to contact regarding the identified issue; sending an alert message to the mobile device of the identified support personnel, wherein the alert message contains information of the identified issue; receiving, at the network management system, a reply message from the mobile device, wherein the reply message contains an instruction to resolve the identified issue; generating an executable command corresponding to the instruction in the reply message; and executing the executable command on the affected components in the infrastructure to resolve the identified issue. | 2013-03-07 |
| 20130061086 | FAULT-TOLERANT SYSTEM, SERVER, AND FAULT-TOLERATING METHOD - To provide a fault-tolerant system requiring only one new server when the number of jobs to he processed concurrently exceeds the number of jobs processable by the current servers and requiring no standby servers. Servers | 2013-03-07 |
| 20130061087 | SYSTEM AND METHOD FOR UNCOVERING DATA ERRORS - According to the presently disclosed subject matter there is provided inter alia, a method and system which enable to uncover errors which are correctable by a data integrity mechanism in a computer system. The same data is read with the help of two different types of read commands. The first command is a read command which does not implement an inherent ECC and therefore does not correct corrupted data. The second command is a read command which includes an ECC and is adapted to correct errors which are detected in the data which is being read. The data obtained by each of the two read commands is compared, and in cases where a difference is identified between the two data, it is determined that an error has been detected and corrected by the ECC. | 2013-03-07 |
