| 10th week of 2013 patent applcation highlights part 40 |
| Patent application number | Title | Published |
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| 20130059383 | CELL-CULTURE-BAG - The present invention is directed to a method to expand adherent cells comprising addition of adherent cells to an expansion container comprising microcarriers and culture medium; removing medium from the expansion container through a 8-20 mm filter; allowing cells to attach to microcarriers and keeping the expansion container in motion with an angle of between 30 to 90° and −30 to −90°. The present invention is also directed to a device suitable in the method. The advantage of the present invention is that fewer steps are needed to expand adherent cells, including stem cells like MSC opening the way for the use of autologeous and allogenous stem cell therapy. In addition, contamination risk is limited since the present invention may be carried out in a closed, disposable system. | 2013-03-07 |
| 20130059384 | COMPOSITIONS AND METHODS FOR ENHANCING BIOENERGETIC STATUS IN FEMALE GERM CELLS - Compositions and methods comprising bioenergetic agents for restoring the quality of aged oocytes, enhancing oogonial stem cells or improving derivatives thereof (e.g., cytoplasm or isolated mitochondria) for use in fertility-enhancing procedures, are described. | 2013-03-07 |
| 20130059385 | METHODS OF GENERATING PLURIPOTENT STEM CELLS - Disclosed are methods, compositions, and kits of producing an induced pluripotent stem cell from a mammalian non-pluripotent cell that does not endogenously or heterologously express Sox2 and is not in contact with a Sox2 polypeptide. | 2013-03-07 |
| 20130059386 | INDUCED PLURIPOTENT STEM CELLS PRODUCED WITH OCT3/4, KLF AND SOX - The present invention relates to a nuclear reprogramming factor having an action of reprogramming a differentiated somatic cell to derive an induced pluripotent stem (iPS) cell. The present invention also relates to the aforementioned iPS cells, methods of generating and maintaining iPS cells, and methods of using iPS cells, including screening and testing methods as well as methods of stem cell therapy. The present invention also relates to somatic cells derived by inducing differentiation of the aforementioned iPS cells. | 2013-03-07 |
| 20130059387 | MEGANUCLEASE VARIANTS CLEAVING A DNA TARGET SEQUENCE FROM THE HPRT GENE AND USES THEREOF - A method for inducing a site-specific modification in the HPRT gene, for a non-therapeutic purpose, by contacting a DNA target sequence selected from the group consisting of the sequences SEQ ID NO: 1 to 14 thereby cleaving the DNA target with an I-CreI variant or single-chain derivative having at least one substitution in one of the two functional subdomains of the LAGLIDADG (SEQ ID NO: 153) core domain situated from positions 26 to 40 and 44 to 77 of I-CreI. | 2013-03-07 |
| 20130059388 | METHODS FOR GENERATING ENDOGENOUSLY TAGGED PROTEINS - The present disclosure provides a method for endogenously tagging an endogenous protein in a cell, and a cell comprising an endogenously tagged protein. Also described are cells produced using such a method and a kit comprising a cell having tagged endogenous protein. | 2013-03-07 |
| 20130059389 | Method for Producing Kluyveromyces Marxianus Transformant - An object to be solved by the present invention is to provide, for example, a method for producing a | 2013-03-07 |
| 20130059390 | SYSTEM AND METHOD FOR MONITORING THE ATMOSPHERE OF AN ANAEROBIC WORKSTATION - Aspects of the invention relates to a system and method for determining the efficacy of the catalyst comprising means to detect any temperature change in the catalyst when oxygen is present in the anaerobic workstation and determine the efficacy of the catalyst in accordance with the temperature change. A detectable rise in the temperature of the catalyst is indicative of a catalytic reaction to remove oxygen from the anaerobic work station. Thus, the system determines the catalyst is an active catalyst if the temperature of the catalyst rises when oxygen is present in the anaerobic workstation. The system determines the catalyst is an inactive catalyst if the temperature of the catalyst does not rise when oxygen is present in the anaerobic workstation. Further aspect of the invention relate to a system and method for determining the atmosphere of an anaerobic workstation in accordance with the efficacy of the catalyst of the anaerobic workstation. | 2013-03-07 |
| 20130059391 | TEST PIECE FOR HEAVY METAL ION, PROCESS FOR DETECTING HEAVY METAL ION, KIT AND SENSOR - The invention provides a test piece for detecting heavy metal ions in an aqueous system to be detected, comprising a substrate, a polymer coating layer and a layer of heavy metal ion-detecting agent, wherein the polymer coating layer is provided such that the surface of the test piece is hydrophobic. The invention further provides a process for detecting heavy metal ions in an aqueous system, a kit comprising the heavy metal ion test piece and a sensor. A portable test piece and/or a device can be provided by the test piece according to the invention, so as to detect the heavy metal ions in a convenient, efficient and rapid manner. | 2013-03-07 |
| 20130059392 | AGGREGATION-INDUCED EMISSION LUMINOGENS FOR METAL ION DETECTION - Pyridine-containing polyenes and their applications as metal ion sensors. These polyenes are practically nonluminescent in the solution state but become highly emissive as nanoparticle suspensions in aqueous solutions or thin films in the solid state, due to aggregation-induced emission (AIE). The nanoaggregates of these compounds can work as “turn-off” fluorescent chemosensors for metal ions and display different fluorescence responses to various metal ions. For example, a characteristic red shift in the emission spectra is observed with a terpyridine-containing luminogen in the presence of Zn | 2013-03-07 |
| 20130059393 | AFFINITY/LECTIN CHROMATOGRAPHY METHODS - Methods for making designed carbohydrate affinity columns and lectin columns are provided. Reducing sugar of choice is dissolved in pH 6.0 acetate buffer and injected onto a primary amino group functionality column. The column is washed with pH 6.0 acetate buffer and the column effluent monitored with a variable wavelength UV detector. Lectin columns are made by injecting appropriate lectin to the designed carbohydrate and the lectin binds to this scaffold. The lectin column is formed. | 2013-03-07 |
| 20130059394 | INDICATOR SYSTEM FOR FIBRE OPTIC SENSOR - The invention provides an optical sensor, e.g a fibre optic sensor, for determining the presence or amount of an analyte in a medium, the sensor having an indicator provided in the form of a fluid. In one aspect, the sensor contains either a solution of the indicator itself, or a solution of a support material which is bonded to the indicator. Dendrimers are examples of suitable support materials. | 2013-03-07 |
| 20130059395 | HUMIDITY AND TEMPERATURE CORRECTIONS TO IMPROVE ACCURACY OF HF AMBIENT AIR MONITORS BASED ON TUNABLE DIODE LASER IR ABSORPTION MEASUREMENTS - Method of determining a total HF concentration metric in an environment including measuring an uncorrected HF concentration metric in the environment based on a first infrared absorption measurement at a wavelength corresponding to a vibrational frequency of a non-hydrogen bonded gas phase HF molecule; determining an ambient H | 2013-03-07 |
| 20130059396 | PHOTOELECTROCATALYTIC FLUID ANALYTE SENSORS INCLUDING REFERENCE ELECTRODES, AND METHODS OF FABRICATING AND USING SAME - Fluid analyte sensors include a photoelectrocatalytic element that is configured to be exposed to the fluid, if present, and to respond to photoelectrocatalysis of at least one analyte in the fluid that occurs in response to impingement of optical radiation upon the photoelectrocatalytic element. A semiconductor light emitting source is also provided that is configured to impinge the optical radiation upon the photoelectrocatalytic element. Related solid state devices and sensing methods are also described. | 2013-03-07 |
| 20130059397 | AUTOMOTIVE FOGGING ANALYSES BY XENON UV EXPOSURE - Processes and apparatuses are provided for the liberation of one or more volatile organic compounds from a test sample. The processes include exposing a sample to light of a wavelength less than 400 nm, subjecting the sample to heat, and collecting one or more volatile organic compounds produced from the sample. The volatile organic compounds are detected by any of various methods, and are optionally identified by methods such as FTIR. The processes and apparatus provide for improved detection of relevant volatile organic compounds that are otherwise undetectable by traditional processes. | 2013-03-07 |
| 20130059398 | USE OF NOVEL MATERIALS IN MARKER SYSTEMS - The present invention relates to the use of marker systems for the security and tracing of items, articles, goods, vehicles or persons. The present invention provides a marker for applying to the surfaces of items, the marker comprising at least one fluorescent material capable of fluorescing at a specific wavelength when subjected to stimulus. The marker can also include at least one material which is phosphorescent and emitting at a specific wavelength. In use, the measured fluorescence and phosphorescent response obtained from the marker are visually compared to examples of the desired colour output for the case in hand to verify the authenticity of the item. | 2013-03-07 |
| 20130059399 | Lateral Flow Test Kit and Method for Detecting an Analyte - A method and device for detecting analytes in a test sample. Embodiments include methods for quantitatively detecting analytes within a range of concentrations. In an embodiment the method includes a lateral flow test strip with multiple test areas for capturing a labeled receptor to provide a detectable signal. | 2013-03-07 |
| 20130059400 | Scanning Analyzer for Single Molecule Detection and Methods of Use - The invention encompasses analyzers and analyzer systems that include a single molecule analyzer, methods of using the analyzer and analyzer systems to analyze samples, either for single molecules or for molecular complexes. The single molecule uses electromagnetic radiation that is translated through the sample to detect the presence or absence of a single molecule. The single molecule analyzer provided herein is useful for diagnostics because the analyzer detects single molecules with zero carryover between samples. | 2013-03-07 |
| 20130059401 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a depression in an upper portion of a semiconductor substrate, placing a sacrificial material in the depression, forming a plurality of fins extending in one direction and arranged periodically by selectively removing the semiconductor substrate and the sacrificial material, forming a device isolation insulating film in a lower portion of space between the fins, removing the sacrificial material, forming a gate insulating film on an exposed surface of the fin, and forming a gate electrode. The gate electrode extends in a direction crossing the one direction so as to straddle the fin on the device isolation insulating film. | 2013-03-07 |
| 20130059402 | Method and A System for Producing a Semi-Conductor Module - In a method for producing a semi-conductor module ( | 2013-03-07 |
| 20130059403 | METHOD AND APPARATUS FOR WAFER TEMPERATURE MEASUREMENT USING AN INDEPENDENT LIGHT SOURCE - An apparatus is provided for measuring a substrate temperature during an etching process, comprising: one or more windows formed in a substrate supporting surface; a first signal generator configured to pulse a first signal; and a first sensor positioned to receive energy transmitted from the first signal generator through the one or more windows. A method is provided for measuring a substrate temperature during an etching process comprising: heating a substrate using radiant energy; pulsing a first light; determining a metric indicative of total transmittance through the substrate when the first light is pulsed on; determining a metric indicative of background transmittance through the substrate when the first light is pulsed off; and determining a process temperature. | 2013-03-07 |
| 20130059404 | Method of Manufacturing A Semiconductor Device - At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber. | 2013-03-07 |
| 20130059405 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - Provided is a method for manufacturing a light-emitting device in which an organic electroluminescent (EL) layer having an intended shape is formed. The method is, for manufacturing a light-emitting device ( | 2013-03-07 |
| 20130059406 | ORGANIC OPTOELECTRONIC DEVICE ELECTRODES WITH NANOTUBES - An electrode for use in an organic optoelectronic device is provided. The electrode includes a thin film of single-wall carbon nanotubes. The film may be deposited on a substrate of the device by using an elastomeric stamp. The film may be enhanced by spin-coating a smoothing layer on the film and/or doping the film to enhance conductivity. Electrodes according to the present invention may have conductivities, transparencies, and other features comparable to other materials typically used as electrodes in optoelectronic devices. | 2013-03-07 |
| 20130059407 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - On a light-emitting layer, a p cladding layer of AlGaInN doped with Mg is formed at a temperature of 800° C. to 950° C. Subsequently, on the p cladding layer, a capping layer of undoped GaN having a thickness of 5 Å to 100 Å is formed at the same temperature as employed for a p cladding layer. Next, the temperature is increased to the growth temperature contact layer in the subsequent process. Since the capping layer is formed, and the surface of the p cladding layer is not exposed during heating, excessive doping of Mg or mixture of impurities into the p cladding layer is suppressed. The deterioration of characteristics of the p cladding layer is prevented. Then, on the capping layer, a p contact layer is formed at a temperature of 950° C. to 1100° C. | 2013-03-07 |
| 20130059408 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Certain embodiments provide a method for manufacturing a semiconductor light emitting device, including: providing a first stack film on a first substrate, the first stack film being formed by stacking a p-type nitride semiconductor layer, an active layer having a multiquantum well structure of a nitride semiconductor, and an n-type nitride semiconductor layer in this order; forming an n-electrode on an upper face of the n-type nitride semiconductor layer; and forming a concave-convex region on the upper face of the n-type nitride semiconductor layer by performing wet etching on the upper face of the n-type nitride semiconductor layer with the use of an alkaline solution, except for a region in which the n-electrode is formed. | 2013-03-07 |
| 20130059409 | MINIATURE MEMS CONDENSER MICROPHONE PACKAGES AND FABRICATION METHOD THEREOF - MEMS microphone packages and fabrication methods thereof are disclosed. One method for fabricating a MEMS microphone package, includes providing a substrate, forming a cavity enclosed by a top cover part, wherein a housing wall part surrounds and supports the top cover part, and the substrate supports the housing wall part and the cover part, forming a MEMS sensing element and an IC chip inside the cavity, forming an opening comprising an acoustic passage connecting the cavity to an ambient space, and forming a conductive casing enclosing the top cover part and the housing wall, wherein the conductive casing is soldered to a PCB board and is electrically connected to a common analog ground lead on the PCB board. | 2013-03-07 |
| 20130059410 | Solution-Based Fabrication of Photovoltaic Cell - An ink for forming CIGS photovoltaic cell active layers is disclosed along with methods for making the ink, methods for making the active layers and a solar cell made with the active layer. The ink contains a mixture of nanoparticles of elements of groups IB, IIIA and (optionally) VIA. The particles are in a desired particle size range of between about 1 nm and about 500 nm in diameter, where a majority of the mass of the particles comprises particles ranging in size from no more than about 40% above or below an average particle size or, if the average particle size is less than about 5 nanometers, from no more than about 2 nanometers above or below the average particle size. The use of such ink avoids the need to expose the material to an H | 2013-03-07 |
| 20130059411 | UV CURABLE ENCAPSULANT - The present invention relates to UV curable encapsulant compositions based on acrylic and/or methacrylic block copolymers, to structures containing these compositions especially photovoltaic cells and to the use of these compositions in photovoltaic cells. The liquid encapsulant composition according to the invention comprises:
| 2013-03-07 |
| 20130059412 | IN-SITU POLYMERIZATION IN BULK HETEROJUNCTION ORGANIC DEVICES - Fabrication of bulk heterojunction organic devices are disclosed that utilize in-situ polymerization of an active component of the device or an in-situ polymerization of an additive that controls the device morphology. According to an aspect, a method for the synthesis of a BHJ photovoltaic film may comprise preparing a homogeneous solution comprising 2,5-dibromothiophene and/or 2,5-diiodothiophene, P3HT and PCBM. The method may also comprise preparing a thin film of the homogeneous solution on the solid surface of a material or an assembly capable of acting as an anode. Oxygen may be excluded from the environment where the thin film will be exposed to photopolymerization by placing the thin film and anode assembly in an inert-gas environment. The method also comprises exposing the liquid film to UV light for a sufficient duration of time and at a sufficient temperature to cause photopolymerization to occur. | 2013-03-07 |
| 20130059413 | PIXEL OF IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure. | 2013-03-07 |
| 20130059414 | COMPOSITIONS USED IN FORMATION OF OXIDE MATERIAL LAYERS, METHODS OF FORMING AN OXIDE MATERIAL LAYER USING THE SAME, AND METHODS OF FABRICATING A THIN FILM TRANSISTOR USING SAME - Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution. | 2013-03-07 |
| 20130059415 | FILM DEPOSITION APPARATUS, FILM DEPOSITION METHOD AND STORAGE MEDIUM - A film deposition apparatus includes a turntable having a substrate mounting area, a first plasma gas supplying part, a second plasma supplying part, a first plasma gas generating part to convert the first plasma generating gas to first plasma, and a second plasma generating part provided away from the first plasma generating part in a circumferential direction and to convert the second plasma generating gas to second plasma. The first plasma generating part includes an antenna facing the turntable so as to convert the first plasma generating gas to the first plasma, and a grounded Faraday shield between the antenna and an area where a plasma process is performed, and to include plural slits respectively extending in directions perpendicular to the antenna and arranged along an antenna extending direction to prevent an electric field from passing toward the substrate and to pass a magnetic field toward the substrate. | 2013-03-07 |
| 20130059416 | FLIP-CHIP BGA ASSEMBLY PROCESS - A method for assembling a flip chip ball grid array package includes mounting solder spheres to a ball grid array substrate, applying flux to a plurality of flip chip solder bumps provided on a diced wafer, aligning the ball grid array substrate over a chip on the diced wafer, picking and separating the chip from the diced wafer by urging the chip upwards towards the ball grid array substrate until the flip chip solder bumps on the chip come in contact with the ball grid array substrate, whereby the chip attaches to the ball grid array substrate in an upside-down orientation, and subjecting the chip and the ball grid array substrate to a thermal process whereby the solder spheres reflow and form solder balls and the flip chip solder bumps reflow and form solder joints between the chip and the ball grid array. | 2013-03-07 |
| 20130059417 | METHOD FOR MANUFACTURING A PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR DEVICE - Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step. | 2013-03-07 |
| 20130059418 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE DEVICE, AND FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer. | 2013-03-07 |
| 20130059419 | METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES INCLUDING A SEMICONDUCTOR DEVICE AND A REDISTRIBUTION ELEMENT, METHODS OF FORMING REDISTRIBUTION ELEMENTS AND METHODS FOR PACKAGING SEMICONDUCTOR DEVICES - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. | 2013-03-07 |
| 20130059420 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained. | 2013-03-07 |
| 20130059421 | METHOD FOR RADIATION HARDENING AN INTEGRATED CIRCUIT - Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity. | 2013-03-07 |
| 20130059422 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer. | 2013-03-07 |
| 20130059423 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device, including: forming an active region surrounded by an element isolation region in a substrate; forming a pair of gate trenches in the active region; forming a pair of gate electrodes by embedding a conductor in the gate trenches; forming an implanted layer by implanting ions into a substrate surface between the gate electrodes; and thermally diffusing impurities of the implanted layer at least to a depth of bottom portions of the gate trenches by a transient enhanced diffusion method to form a diffusion layer region between the gate electrodes at least to a depth of bottom portions of the gate electrodes. | 2013-03-07 |
| 20130059424 | Buried Gate Transistor - An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess. | 2013-03-07 |
| 20130059425 | Imprinted Memory - The rising mask cost would make mask-ROM economically un-viable below 90 nm. The present invention discloses an imprinted memory, more particularly a three-dimensional imprinted memory (3D-iP). It uses imprint-lithography (also referred to as nano-imprint lithography, or NIL) to record data. The data-template used by imprint-lithography is much less expensive than the data-mask used by photo-lithography. | 2013-03-07 |
| 20130059426 | METHOD FOR MANUFACTURING MOLECULAR MEMORY DEVICE - According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members. | 2013-03-07 |
| 20130059427 | Nonvolatile Memory Elements - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. | 2013-03-07 |
| 20130059428 | WAFER DIVIDING METHOD - A wafer is divided by setting the focal point of a laser beam inside the wafer at positions corresponding to division lines, thereby forming modified layers inside the wafer along the division lines. Each modified layer has a thickness ranging from the vicinity of the front side of the wafer to the vicinity of the back side of the wafer. An etching gas or an etching liquid is supplied to the wafer to erode the modified layers, thereby dividing the wafer into individual devices. The modified layers are not crushed, so fine particles are not generated in dividing the wafer. Accordingly, fine particles do not stick to the surface of each device and cause a reduction in quality. Further, since the modified layers are removed by etching, it is possible to prevent a reduction in die strength of each device due to the remainder of the modified layers. | 2013-03-07 |
| 20130059429 | METHOD OF PRODUCTION OF SIC SEMICONDUCTOR DEVICE - A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate. | 2013-03-07 |
| 20130059430 | High Throughput Multi-Wafer Epitaxial Reactor - An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart to minimize the process volume. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. Purge gases flow outside the wafer sleeve within a reactor chamber to minimize wall deposition. In addition, sequencing of the illumination of the individual lamps in the lamp module may further improve the linearity of variation in deposition rates within the wafer sleeve. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration. Combining lamp sequencing with cross-flow processing in a multiple reactor system enables high throughput deposition with good film uniformities and efficient use of process gases. | 2013-03-07 |
| 20130059431 | DEVICE AND METHOD FOR SUBSTRATE PROCESSING - The present invention relates to a device for processing substrates in a processing system with at least one process tool disposed in at least one process area, which tool has two substrate levels disposed opposite each other in the process area, which are aligned at least approximately vertical, wherein the device is adapted to process at least two substrates at the same time in the process area by means of the process tool, wherein the substrates can be disposed in the substrate levels such that coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates. It further relates to a method for processing coated substrates in a processing system, wherein the substrates have coatings and the substrates are each disposed opposite each other such that the coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates. | 2013-03-07 |
| 20130059432 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern. | 2013-03-07 |
| 20130059433 | METHODS AND COMPOSITIONS FOR DOPING SILICON SUBSTRATES WITH MOLECULAR MONOLAYERS - Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred. | 2013-03-07 |
| 20130059434 | METHOD FOR MANUFACTURING ELECTRODES AND WIRES IN GATE LAST PROCESS - The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process. Such a design has the advantages of simplifying complexity of process integration on one hand and greatly strengthening control of defects by CMP process on the other hand, thereby avoiding the defects like erosion and dishing that may be produced between different metal materials. | 2013-03-07 |
| 20130059435 | Method of Manufacturing Dummy Gates in Gate Last Process - The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved. | 2013-03-07 |
| 20130059436 | DEVICE FABRICATION - Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes. | 2013-03-07 |
| 20130059437 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a film containing boron on a semiconductor substrate, forming a film containing silicon oxide on the film containing boron, patterning the film containing silicon oxide and etching the film containing boron with a gas containing chlorine by using the patterned film containing silicon oxide as a mask. | 2013-03-07 |
| 20130059438 | METHOD FOR FORMING PATTERN AND MASK PATTERN, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps. | 2013-03-07 |
| 20130059439 | CMP POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND ELECTRONIC COMPONENT - The CMP polishing liquid of the invention is used by mixing a first solution and a second solution, the first solution comprises cerium-based abrasive grains, a dispersant and water, the second solution comprises a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, the pH of the second solution is 6.5 or higher, and the first solution and second solution are mixed so that the phosphoric acid compound content is within a prescribed range. The CMP polishing liquid of the invention comprises cerium-based abrasive grains, a dispersant, a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, with the phosphoric acid compound content being within a prescribed range. | 2013-03-07 |
| 20130059440 | SELECTIVE SUPPRESSION OF DRY-ETCH RATE OF MATERIALS CONTAINING BOTH SILICON AND NITROGEN - A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H | 2013-03-07 |
| 20130059441 | METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value. | 2013-03-07 |
| 20130059442 | METHOD FOR ADJUSTING TRENCH DEPTH OF SUBSTRATE - A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer. | 2013-03-07 |
| 20130059443 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface. | 2013-03-07 |
| 20130059444 | GAS CLUSTER ION BEAM ETCHING PROCESS FOR METAL-CONTAINING MATERIALS - A method and system for performing gas cluster ion beam (GCIB) etch processing of metal-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element. | 2013-03-07 |
| 20130059445 | GAS CLUSTER ION BEAM ETCHING PROCESS FOR Si-CONTAINING and Ge-CONTAINING MATERIALS - A method and system for performing gas cluster ion beam (GCIB) etch processing of Si-containing material and/or Ge-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element. | 2013-03-07 |
| 20130059446 | GAS CLUSTER ION BEAM ETCHING PROCESS FOR ACHIEVING TARGET ETCH PROCESS METRICS FOR MULTIPLE MATERIALS - A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics. | 2013-03-07 |
| 20130059447 | METHOD AND APPARATUS FOR REDUCTION OF VOLTAGE POTENTIAL SPIKE DURING DECHUCKING - Provided is a substrate dechucking system of a plasma processing chamber adapted to remove a substrate from an ESC with reduction in voltage potential spike during dechucking of the substrate. | 2013-03-07 |
| 20130059448 | Pulsed Plasma Chamber in Dual Chamber Configuration - Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to set parameters to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF period, and to assist in the re-striking of the bottom plasma during the ON period. | 2013-03-07 |
| 20130059449 | GAS CLUSTER ION BEAM ETCH PROFILE CONTROL USING BEAM DIVERGENCE - A method of etching a substrate is described. In one embodiment, the method includes preparing a mask layer having a pattern formed therein on or above at least a portion of a substrate, etching a feature pattern into the substrate from the pattern in the mask layer using a gas cluster ion beam (GCIB), and controlling a sidewall profile of the feature pattern etched into the substrate by adjusting a beam divergence of the GCIB. | 2013-03-07 |
| 20130059450 | ETCH PROCESS FOR 3D FLASH STRUCTURES - A method for etching features in a plurality of silicon based bilayers forming a stack on a wafer in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a plasma, while providing a first pressure. A wafer temperature of less than 20° C. is maintained. The pressure is ramped to a second pressure less than the first pressure as the plasma etches through a plurality of the plurality of silicon based bilayers. The flow of the main etch gas is stopped after a first plurality of the plurality of bilayers is etched. | 2013-03-07 |
| 20130059451 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATAUS - A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate an atomic oxygen, and oxidizing the element-containing layer by the atomic oxygen. | 2013-03-07 |
| 20130059452 | CARD DEVICE AND SOCKET - The present application discloses a card device configured to be inserted into and ejected from a host device in a first direction. The card device includes a first housing including a leading edge which is inserted into the host device on ahead, and a trailing edge opposite to the leading edge; a first electrode array including first electrodes aligned in a second direction along the leading edge; and a second electrode array including second electrodes aligned in the second direction between the first electrode array and the trailing edge. The second electrodes include an electrode shifted from the first electrodes in the second direction. | 2013-03-07 |
| 20130059453 | INTEGRATED CIRCUITS - An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for coupling to a first pair of differential pins of the USB receptacle, a second group for coupling to a second pair of differential pins of the USB receptacle, a third group for coupling to a third pair of differential pins to the USB receptacle, a ground pin, a first and second power pins. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the USB 2.0 or USB 3.0 signals. | 2013-03-07 |
| 20130059454 | COVER STRUCTURE - A cover structure, adapted for mounting on a housing that is formed with an opening and a connection base having a plugging end exposing by the opening, comprising: a frame, formed with a first end and a second end that are arranged opposite to each other with respect to the radial of a coupling position where the frame is coupled to the housing through a pivot axis of two pivot blocks in a direction parallel to a first axis direction and enabling the first end to expose by the opening; and an elastic element, disposed inside the housing for providing an elastic force to the frame, for enabling the first end and the second end to move relative to each other centering the coupling position; wherein an accommodation space is formed between the frame and the connection base so as to be used for receiving a plug of a connector. | 2013-03-07 |
| 20130059455 | CARD EDGE CONNECTOR - A card edge connector | 2013-03-07 |
| 20130059456 | FAST COUPLING APPARTUS FOR CONNECTING MEDIA-CARRYING LINES - A fast coupling apparatus on a media-carrying line is provided. The fast coupling apparatus includes a plug piece arranged on a first line end and a receiver piece arranged on a second line end coupled together with the plug piece, where an electrically-conductive contact sleeve is arranged on an inner periphery of the receiver piece, the electrically-conductive contact sleeve is electrically-conductively connected with the receiver piece and has a contact lip that protrudes from a surface of the contact sleeve and touches the plug piece in a connected position. | 2013-03-07 |
| 20130059457 | CONNECTOR WITH LEVER - A connector is provided with a rotatable toggle lever which is movable between a first position where the connector is fitted to a counterpart connector and a second position in which the connector is secured to the counterpart connector. The connector includes a housing and a lock member for locking the lever at the second position. The lock member has a body portion extending approximately parallel with one wall surface of the housing. The lock member has a locking engaging projection portion for engagement with the lever and, at one end of the body, has a releasing operation portion for releasing the engagement of the projection. A first connection portion connects the other end of the body portion to the one wall surface while second connection portions are arranged on both sides of the releasing operation portion to connect the one end of the body portion to the one wall surface. The lock member further includes cable protective projections projecting from the surfaces of the second connection portions in a direction away from the one wall surface. The lever includes a cross frame portion having a concave portion formed in a position located adjacent the releasing operation portion when the lever is in the second position. | 2013-03-07 |
| 20130059458 | CARD EDGE CONNECTOR - A card edge connector for receiving an electronic card to be inserted therein includes an insulating body, with a slot formed therein for receiving the electronic card therein; multiple conductive terminals, accommodated in the insulating body, in which each of the conductive terminals at least partially enters the slot and contacts the electronic card therein; and at least one latch. The latch includes a connecting arm with one end disposed in the insulating body and located at a side of the slot; a bent section, extending backward from the other end of the connecting arm and bent toward a side away from the electronic card; and a guide chamfer, disposed at a side of the bent section close to the electronic card and inclined downward. | 2013-03-07 |
| 20130059459 | ELECTRICAL PLUG FASTENER - A plug fastener is provided to avoid a plug with a power line disengaging from a power strip. The plug fastener includes two fixing members, two connecting clips, and a fixing clip. The fixing members are detachably engaged with each other for sandwiching the power line therebetween. The fixing clip is placed around the power strip. A first end of each of the connecting clips is rotatably connected to the fixing clip, and a second end of each of the connecting clips opposite to the first end is rotatably connected to a respective one of the fixing members. | 2013-03-07 |
| 20130059460 | Miniature Receptacle Electrical Connector - A receptacle connector includes a housing and first and second sets of conductive terminals attached to a respective first and second main surfaces of the housing. Each conductive terminal has a first end, a second end and a contact portion therebetween. The first end is offset from the contact portion along a direction perpendicular to the contact portion. The contact portion is attached to one of the first and second main surfaces by insert-molding. The first end extends through an end surface of the housing. The first ends are aligned in one row parallel to the first and second main surfaces such that the molding process is simplified. In a one type of example receptacle connector, the conductive terminals are strongly and precisely attached to the housing, hence the physical dimension can be ensured, and the mateability with counterpart plug connector as well as manufacturability can be improved. | 2013-03-07 |
| 20130059461 | ELECTRICAL CONNECTOR WITH SEPARATING EXTENSIONS ON TERMNALS - An anti-electromagnetic interference electrical connector having a terminal assembly is provided. The anti-EMI electrical connector includes an electrical insulation case, plural first terminals, and plural second terminals. The electrical insulation case includes a slot. Each first terminal is disposed in the electrical insulation case and includes a contact end located in the slot. Each second terminal is disposed in the electrical insulation case and in a staggered manner with the first terminals. Each second terminal includes a body and a first extended portion. The body is located in the electrical insulation case and includes a connection end located in the slot. The first extended portion extends from the body and an included angle is defined between the first extended portion and the body. The first extended portion isolates the first terminals adjacent to each of the second terminals by increasing a lateral projected area of the second terminal. | 2013-03-07 |
| 20130059462 | DEVICE FOR CONNECTING A CABLE TO AN ELECTRIC COMPONENT ARRANGED IN A HOUSING - A device for connecting a cable ( | 2013-03-07 |
| 20130059463 | CRYOGENIC CABLE TERMINATION CONNECTOR - A cryogenic cable termination connector having a small heat inflow from the outside and stable electrical insulation properties. The cryogenic cable termination connector includes a lead-out conductor led out from a site at a very low temperature to a site at room temperature via a liquid refrigerant layer, a refrigerant gas layer, and an oil layer. The lead-out conductor includes a capacitor-cone insulator in which plural metal foils for dividing an electric field from a high voltage level down to the ground voltage level are stacked through an insulator. Among electric field tilting portions in which voltage changes gradually from the high voltage level to the ground voltage level, an electric field tilting portion positioned at a lower part is located in the liquid refrigerant layer and an electric field tilting portion positioned at an upper part is located in the oil layer. | 2013-03-07 |
| 20130059464 | AUDIO TEST CABLE - An audio test cable includes three types of audio input and output (I/O) ports. The input port and the output port in each type of audio I/O ports form a short circuit for carrying a loopback test for a motherboard. The audio test cable also includes a test audio jack which connects to the output port of all types of audio I/O ports for carrying out an audio-quality test for the motherboard. | 2013-03-07 |
| 20130059465 | SWIMMING POOL DECKPLATE FOR HORIZONTAL SURFACES WITH INTEGRATED SLOPES AROUND ELECTRICAL CONTACTS - A horizontally mounted connector deckplate for swimming pools to connect swim timing devices and other devices with electrical contacts with potential difference mounted on slopes integrated into the body of the deckplate. These integrated slopes cause corrosive pool water that is splashed on the deckplate, which creates water bridges between electrical contacts, to flow off through gravity, overcoming the water surface tension. Therefore electrolytic currents through the water bridges are greatly reduced, reducing corrosion of the electrical contacts of the deckplate. In addition corrosion resistant materials such as titanium are used for the electrical contacts. | 2013-03-07 |
| 20130059466 | DEVICE CONNECTOR AND DEVICE CONNECTOR SYSTEM - A male connector ( | 2013-03-07 |
| 20130059467 | MODULAR LIMB SEGMENT CONNECTOR - A joint assembly for releasably securing a first and a second segment of an associated modular limb is provided. The joint assembly includes a male connector including a base and a load bearing blade secured to the base of the male connector protruding therefrom. The male connector is adapted to be secured to one of the first and second segments of the associated modular limb. A female connector is provided and includes a base and a load bearing socket secured to the base of the female connector. The socket is configured to selectively receive the blade of the male connector. The female connector is adapted to be secured to the other of the first and second segments of the associated modular limb. A locking member selectively retains the blade of the male connector in the socket of the female connector. The male connector, the female connector, and the locking member cooperate to form a resilient and selectively releasable modular limb joint. | 2013-03-07 |
| 20130059468 | Coaxial Connectors Having Rearwardly-Seating Compression Elements and Related Jumper Cables and Methods of Using Such Connectors - Coaxial connectors include have a rear cable-receiving end and a front connection end that is opposite the cable-receiving end. These connectors include a connector body having a front end that extends toward the front connection end of the coaxial connector and a rear end opposite the front end and a compression element that is configured to move between an unseated position and a seated position, the compression element configured to impart a compressive force to secure one or more elements of a cable within the connector body when the compression element is in the seated position. The compression element is designed to be closer to the front connection end of the coaxial connector when in the unseated position than it is when in the seated position. | 2013-03-07 |
| 20130059469 | CONNECTOR-CONNECTING TERMINAL TREATMENT STRUCTURE FOR SHIELDED WIRES AND METHOD OF PRODUCING CONNECTOR-CONNECTING TERMINAL TREATMENT STRUCTURE FOR SHIELDED WIRES - A connector-connecting terminal treatment structure for shielded wires includes the plurality of shielded wires, a first water stopper, and a second water stopper. The plurality of shielded wires are arranged in parallel to one another, and each of the shielded wires has an exposed strand portion and a covered portion. The first water stopper is configured with a paste waterproof agent integrally covering a boundary portion between the exposed strand portions and the covered portions in the plurality of shielded wires. The sheet-like water stopper through which the paste waterproof agent does not penetrate is provided so as to cover the outer periphery of the first water stopper as well as to tightly attach to the outer periphery of the exposed strand portions and the covered portions at both the lateral sides of the first water stopper in the extending direction of the shielded wires. | 2013-03-07 |
| 20130059470 | ELECTRICAL CONNECTOR FOR TRANSMITTING ELECTRICAL POWER - An electrical connector includes an insulative housing, a first terminal and a second terminal both disposed in the insulative housing. The insulative housing defines a receiving passageway for fixing the terminals and an inserted channel through with the receiving passageway. Each of the first terminal or the second terminal has a base portion located in the receiving passageway, a contacting portion extending into the inserted channel and a tail extending out of the insulative housing. The first terminal further has a encircling portion at an end of the tail of the first terminal. At least, a portion of the tail of the second terminal located in the encircling portion so as that the tail of the second terminal may be held by the tail of the first terminal. Therefore the tails of the two terminals are immovable respectively. | 2013-03-07 |
| 20130059471 | CENTER CONDUCTOR WITH SURROUNDING SHIELD AND EDGE CARD CONNECTOR WITH SAME - An edge card connector includes a connector housing; a plurality of center conductors disposed in the connector housing, spaced apart from one another, and arranged to make contact with a surface of an edge card when the edge card is inserted into the edge card connector; and a plurality of shields disposed in the connector housing, surrounding three sides of a corresponding one of the plurality of center conductors, and arranged to make contact with the surface of the edge card when the edge card is inserted into the edge card connector. | 2013-03-07 |
| 20130059472 | SHIELDED CONNECTOR - There is provided a shielded connector that can prevent collapse of a cantilever wall in a housing while pursing a lower profile. A shielded connector has a tubular inner shell that covers terminals for connection with another connector; an outer shell that covers the inner shell; and a housing for retaining the inner shell in the outer shell. The outer housing has receiving grooves formed in an indented manner in free-end side walls of a cantilever wall that extends along an interior wall of the outer shell in a direction of insertion of the connector and that has a lock receiving portion to engage with a lock portion of another connector. The outer shell has, in upper portions of respective leading-side side walls, supporting projections to engage with the receiving grooves of the cantilever wall. | 2013-03-07 |
| 20130059473 | Production of an Electrical Cable and Method for Producing a Connection - Connection of an electrical cable consisting of a plurality of wires or strands to a terminal, in particular for the electrical system of a motor vehicle, having a support sleeve which encloses an end area of the cable and serves to accommodate an end face of the cable, so that the wires or strands are held in the support sleeve, wherein the face side of the cable consisting of the individual wires or strands is welded to the terminal by means of an at least face side weld seam. A particularly simple connection is then possible if the terminal is hollow on the side opposite the weld seam. | 2013-03-07 |
| 20130059474 | Conical Inductive Coupler - In one aspect of the present invention, an inductive coupling comprises a pin section and a box section. The pin section comprises an inner electrical conductor supported in an exterior tapered surface of the pin section. The box section comprises an outer electrical conductor supported in an interior tapered surface of the box section. The exterior and interior tapered surfaces are configured to align each other such that the interior and exterior tapered surfaces are coaxial with each other when fully engaged. | 2013-03-07 |
| 20130059475 | USB Connector - The present invention discloses a USB connector, comprising: a USB shell, an insulation spacer, metal sheets with metal weld legs respectively. The metal sheets are installed on the insulation spacer, the metal sheets are configured to be connected to a USB interface of a personal computer, the metal weld legs are connected to a printed circuit board within an external product, and the insulation spacer is fixed in the USB shell; the metal sheets comprise one ground pin, two signal pins and one power supply pin, wherein the ground pin is configured with an extending resilient metal sheet contacted with the USB shell. Widths of the metal sheets and the metal weld legs are widen and thicknesses of the metal sheets and the insulation spacer are thicken, so that the USB connector and the USB interface of the computer are contacted sufficiently, enhancing the ground effect of the USB connector. | 2013-03-07 |
| 20130059476 | ELECTRICAL CONNECTOR - A simple structure capable of preventing a cam part of an actuator from coming out of position when the actuator is in an open position. The cam part | 2013-03-07 |
| 20130059477 | BATTERY COUPLING ARRANGEMENT - A battery has on opposite sides male and female terminal blocks. The female block includes positive and negative power terminals, a communications line and a link detect line. The female terminals include annular female connectors for receiving a male electrical terminal. The male terminal block has a recess for accommodating the female terminal dock. Within the recess there extend a plurality of male terminal pins, which include a positive voltage terminal, a communications line terminal, a battery status terminal and a negative or nominal ground terminal. The pins are positioned and sized so as to fit into respective female terminals. As each battery is provided with both female and male terminal blocks, any number of batteries can be stacked together. The male block includes a protective cover and latch for protecting the pins and locking the battery to a device or other battery. | 2013-03-07 |
| 20130059478 | DUAL-CARD CONNECTOR - A dual-card connector for receiving dual SIM (Subscriber Identification Module) cards therein includes an insulating housing, a plurality of conductive terminals, an upper cover and a lower cover. The insulating housing has a base body. A top and a bottom of the base body define two sets of longitudinal terminal grooves. Each set of the terminal grooves is divided into a front row and a rear row penetrating a front end and a rear end of the base body, respectively. The conductive terminals are received in the corresponding terminal grooves of the insulating housing for electrically connecting with the respective SIM cards. The upper cover is covered to the insulating housing to form a first insertion space therebetween for receiving a first SIM card. The lower cover is covered to the insulating housing to form a second insertion space therebetween for receiving a second SIM card. | 2013-03-07 |
| 20130059479 | COMBO CONNECTOR - A receptacle connector includes an insulative housing, at least three terminal groups and a metal shell. The insulative housing has a base and at least three tongue pieces which integrally extend from the base and are transversally spaced apart to each other and in which a tongue piece of the tongue pieces at a left side thereof belongs to a left tongue piece, a tongue piece of the tongue pieces at a right side thereof belongs to a right tongue piece, and the other of the tongue pieces between the left tongue piece and the right tongue piece belongs to a middle tongue piece. The metal shell surrounds the tongue pieces and defines a common mating space as well as a first and second mating space. | 2013-03-07 |
| 20130059480 | CARD CONNECTOR ASSEMBLY - A connector assembly for a small modular device that connects to a larger host device, including a receptacle forming part of a host electronic device, the receptacle including N conducting pins, where N is at least 20, the receptacle being a portion of a host device, and a connector plug forming part of a modular electronic device, including a first connector including N conducting pins, for engagement with said receptacle when the modular electronic device is connected with the host device, and a second connector comprising at most 5 conducting pins, for engagement with a cable when the modular electronic device is not connected with the host device, wherein the second connector is completely covered when the modular electronic device is connected with the host device. | 2013-03-07 |
| 20130059481 | PLUG-IN CONNECTOR AND A PLUG-IN MODULE SYSTEM - The invention relates to a plug-in connector ( | 2013-03-07 |
| 20130059482 | MALE CONNECTOR, FEMALE CONNECTOR AND CONNECTOR ARRANGEMENT - The male connector ( | 2013-03-07 |
