| 10th week of 2013 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20130056783 | THERMAL MANAGEMENT IN LARGE AREA FLEXIBLE OLED ASSEMBLY - A large area, flexible, OLED assembly has improved thermal management by providing a metal cathode of increased thickness of at least 500 nm. A thermal heat sink trace may be used as alternative or in conjunction with the increased thickness cathode where the trace leads from a central region of the OLED toward a perimeter region, or by other backsheet thermal management designs. External heat sinking, for example to a plate, fixture, etc. may be additionally used or in conjunction with the increased thickness cathode and/or backsheet design to provide further thermal management. | 2013-03-07 |
| 20130056784 | Organic Light-Emitting Display Device and Method of Fabricating the Same - An organic electro-luminescence device capable of reducing a resistance of a cathode electrode to enhance brightness uniformity at each location within the device is described. The organic electro-luminescence device includes a bank layer formed over a substrate, the bank layer including a first, second, and third portion. A first electrode is formed between the first and second portions of the bank layer. An auxiliary electrode is formed where at least a part of the auxiliary electrode is formed between the second and third portions of the bank layer. A pattern is formed on the auxiliary electrode. An organic material layer formed between the first and second portions of the bank layer. A second electrode formed on the organic material layer, where at least a portion of the second electrode is electrically coupled to the auxiliary electrode. | 2013-03-07 |
| 20130056785 | LIGHT EMITTING DEVICE - A light emitting device includes a first section and a second section. The first section includes a first semiconductor layer doped with a first dopant, a second semiconductor layer doped with a second dopant, and a first active layer between the first and second semiconductor layers, and the second section includes a third semiconductor layer disposed on the first section, and the third semiconductor layer having an exposed region, a fourth semiconductor layer disposed on the third semiconductor layer except for the exposed region, and a second active layer between the third and fourth semiconductor layers, a first electrode disposed on the first semiconductor layer, a second electrode disposed on the fourth semiconductor layer and a third electrode inserted into a hole in the exposed region and disposed on the exposed region and the second semiconductor layer, the third electrode electrically connected to the second and third semiconductor layers. | 2013-03-07 |
| 20130056786 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device in which an optical semiconductor element connected to a silver-plated copper lead frame is sealed with an addition curing silicone resin composition, the addition curing silicone resin composition having (A) organopolysiloxane that contains an aryl group and an alkenyl group and does not contain an epoxy group; (B) organohydrogenpolysiloxane that has at least two hydrosilyl groups per molecule and an aryl group, the organohydrogenpolysiloxane that contains 30 mol % or more of an HR | 2013-03-07 |
| 20130056787 | LIGHT EMITTING DEVICE - A light emitting device includes a package equipped on a front face with a window for installing a light emitting element, and outer lead electrodes that protrude from a bottom face of the package. The package has, on the bottom face, two side face convex components provided on the side face sides and a center convex component provided at a center. The outer lead electrodes are housed in a concave components defined by the side face convex components and the center convex component. The side face convex component has groove provided on the side face. | 2013-03-07 |
| 20130056788 | PACKAGE FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE - An object of the present invention is to provide a package from which a metal wiring and the like are difficult to be detached even when heat is generated from a semiconductor light-emitting element. This object is achieved with a package for a semiconductor light-emitting device comprising at least a molded resin containing (A) a SiH-containing polyorganosiloxane and (B) a filler, wherein an amount of SiH existing in the molded resin, after a heat treatment thereof at 200° C. for 10 minutes, is 20 to 65 μmol/g. | 2013-03-07 |
| 20130056789 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a conductive support member; a light emitting structure under the conductive support member; an insulating layer including a protrusion disposed along an outer circumference of the light emitting structure; an electrode layer having an outer portion on the insulating layer and an inner portion on an inner portion of a top surface of the light emitting structure; and an electrode under the light emitting structure, wherein the inner portion of the electrode layer is protruded to the light emitting structure relative to the outer portion of the electrode layer, and wherein a portion of the insulating layer surrounds a portion of the light emitting structure. | 2013-03-07 |
| 20130056790 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes: a drain layer; a drift layer formed on the drain layer, an effective impurity concentration of the drift layer being lower than an effective impurity concentration of the drain layer; a base layer formed on the drift layer; a source layer selectively formed on the base layer; a gate insulating film formed on inner surfaces of trenches, the trenches piercing the base layer from an upper surface of the source layer; a gate electrode filled into an interior of the trench; an inter-layer insulating film formed on the trench to cover an upper surface of the gate electrode, at least an upper surface of the inter-layer insulating film being positioned higher than the upper surface of the source layer; and a contact mask. The contact mask is formed on the inter-layer insulating film, and is conductive or insulative. | 2013-03-07 |
| 20130056791 | SEMICONDUCTOR DEVICE - A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns. | 2013-03-07 |
| 20130056792 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR - An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit. The first and second switching devices are arranged so as to provide, when in use, a bidirectional snapback characteristic and a snapback voltage associated therewith. | 2013-03-07 |
| 20130056793 | PROVIDING GROUP V AND GROUP VI OVER PRESSURE FOR THERMAL TREATMENT OF COMPOUND SEMICONDUCTOR THIN FILMS - Embodiments of the invention provide methods for forming high quality, low resistivity Group III-V or Group II-VI compounds. In one embodiment, the method includes growing a compound semiconductor layer having a n-type or p-type dopant over a substrate, the compound semiconductor layer comprising at least a first component and a second component, and the second component has a vapor pressure relatively higher than the first component, forming a supplemental layer consisted essentially of the second component at or near an upper surface of the compound semiconductor layer, and anneal the substrate. A capping layer may be formed on the supplemental layer to help prevent loss of crystallinity of the second component at elevated temperatures. An overpressure of the second component gas may be provided onto an exposed surface of the substrate during annealing to enhance the surface morphology of the compound semiconductor layer. | 2013-03-07 |
| 20130056794 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, AND METHOD OF PRODUCING ELECTRONIC DEVICE - A semiconductor wafer includes a base wafer, a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type, a separation layer that is formed over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion, and a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type. | 2013-03-07 |
| 20130056795 | FinFET Design Controlling Channel Thickness - System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate. | 2013-03-07 |
| 20130056796 | Novel Method to Increase Breakdown Voltage of Semiconductor Devices - Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN. | 2013-03-07 |
| 20130056797 | SEMICONDUCTOR DEVICE HAVING SCHOTTKY DIODE STRUCTURE - A semiconductor device including a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) generated within the semiconductor layer; a plurality of first ohmic electrodes which are disposed on the central region of the semiconductor layer and have island-shaped cross sections; a second ohmic electrode which is disposed on edge regions of the semiconductor layer; and a Schottky electrode part has first bonding portions bonded to the first ohmic electrodes, and a second bonding portion bonded to the semiconductor layer. A depletion region is provided to be spaced apart from the 2DEG when the semiconductor device is driven at an on-voltage and is provided to be expanded to the 2DEG when the semiconductor device is driven at an off-voltage, the depletion region being generated within the semiconductor layer by bonding the semiconductor layer and the second bonding portion. | 2013-03-07 |
| 20130056798 | Three-Dimensional Printed Memory - As technology scales, the mask cost rises sharply. It was generally believed that three-dimensional mask-programmed read-only memory (3D-MPROM) would become economically un-viable. The present invention discloses a three-dimensional printed memory (3D-P). It is a type of 3D-MPROM and uses shared data-masks to print data. By forming the mask-patterns for a plurality of distinct mass-contents on a same data-mask, the share of the data-mask cost on each mass-content is significantly reduced. For mass publication, the minimum feature size of the 3D-P is preferably less than 45 nm. | 2013-03-07 |
| 20130056799 | CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in the active region, where a region not overlapping with the gate electrode in the adjacent active region is formed of a material such as SiGe, includes a step of calculating an electrical characteristic (e.g., flowing current, threshold voltage, etc.) of the transistor based on a distance between an edge closer to the transistor, of both edges of the adjacent active region disposed near the transistor, and the gate electrode formed in the adjacent active region. Thus, circuit simulation can be performed with high accuracy with respect to an electrical characteristic of the transistor. | 2013-03-07 |
| 20130056800 | Image Sensor With Reduced Noise By Blocking Nitridation Using Photoresist - An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers. | 2013-03-07 |
| 20130056801 | JUNCTION FIELD EFFECT TRANSISTOR AND ANALOG CIRCUIT - A junction field effect transistor comprising: a semiconductor substrate having a first conductivity type; a channel region having a second conductivity type different from the first conductivity type, and being formed in a surface of the semiconductor substrate; a first buried region having the second conductivity type, being formed within the channel region, and having an impurity concentration higher than the channel region; a first gate region having the first conductivity type, and being formed in a surface of the channel region; and first drain/source region and a second drain/source region both having the second conductivity type, which are formed each on an opposite side of the first gate region in the surface of the channel region, in which the first buried region is not formed below the second drain/source region, but is formed below the first drain/source region. | 2013-03-07 |
| 20130056802 | IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES - A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of | 2013-03-07 |
| 20130056803 | SEMICONDUCTOR DEVICE - Power supply plugs, which couple a power supply active region to a power supply metal interconnect, include a plurality of first plugs, which are arranged at first pitches of a predetermined length, and a second plug, which is spaced apart from the closest one of the first plugs by a center-to-center distance different from an integral multiple of the predetermined length. Among the power supply plugs, the second plug is closest to a third plug, which is an interconnect plug closest to the power supply active region and the power supply metal interconnect. | 2013-03-07 |
| 20130056804 | SEMICONDUCTOR DEVICE - A semiconductor device includes a MIS transistor. The MIS transistor includes an active region surrounded by an isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the isolation region, and having a high dielectric constant film, and a gate electrode formed on the gate insulating film. A nitrided region is formed in at least part of a portion of the gate insulating film that is located on the isolation region. A concentration of nitrogen contained in the nitrided region is nx, and a concentration of nitrogen contained in a portion of the gate insulating film that is located on the active region is n, wherein a relationship of nx>n is satisfied. | 2013-03-07 |
| 20130056805 | TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS - A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack. | 2013-03-07 |
| 20130056806 | UNIT PIXEL OF COLOR IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film having one surface thereof being in contact with the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel formed between the source and the drain and configured to form flow of an electric current between the source and drain. | 2013-03-07 |
| 20130056807 | PHOTOELECTRIC CONVERTING APPARATUS - A photoelectric converting apparatus has first and third semiconductor layers of a first conductivity type which respectively output signals obtained by photoelectric conversion, and second and fourth semiconductor layers of a second conductivity type supplied with potentials from a potential supplying unit. In the photoelectric converting apparatus, the first, second, third and fourth semiconductor layers are arranged in sequence, the second and fourth semiconductor layers are electrically separated from each other, and the potential to be supplied to the second semiconductor layer and the potential to be supplied to the fourth semiconductor layer are controlled independently from each other. | 2013-03-07 |
| 20130056808 | Isolation Area Between Semiconductor Devices Having Additional Active Area - An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel. | 2013-03-07 |
| 20130056809 | Image Sensor with Reduced Noiseby Blocking Nitridation Over Selected Areas - An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, an imaging pixel of an image sensor includes a photodiode region to accumulate an image charge in response to incident light, a first transistor having a gate oxide layer, the gate oxide layer having a first level of nitridation, and a second transistor having a gate oxide layer, the gate oxide layer having a second level of nitridation that is higher than the first level of nitridation. | 2013-03-07 |
| 20130056810 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes, a semiconductor substrate including a plurality of fins formed in an upper surface of the semiconductor substrate in a first region to extend in a first direction, a first gate electrode extending in a second direction intersecting the first direction to straddle the fins, a first gate insulating film provided between the first gate electrode and the fins, a second gate electrode provided on the semiconductor substrate in the second region; and a second gate insulating film provided between the semiconductor substrate and the second gate electrode. A layer structure of the first gate electrode is different from a layer structure of the second gate electrode. | 2013-03-07 |
| 20130056811 | Hydrogen-Blocking Film for Ferroelectric Capacitors - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH | 2013-03-07 |
| 20130056812 | SEMICONDUCTOR MEMORY DEVICES INCLUDING VERTICAL TRANSISTOR STRUCTURES - A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line. | 2013-03-07 |
| 20130056813 | CAPACITOR STRUCTURE APPLIED TO INTEGRATED CIRCUIT - A capacitor structure applied to an integrated circuit (IC) is provided. The capacitor structure includes a metal-oxide semiconductor (MOS) capacitor and two metal structures with different structures. The MOS capacitor has a first terminal and a second terminal. The two metal capacitors are formed above the MOS capacitor and respectively coupled between the first terminal and the second terminal. Subject to the confined chip area, the capacitance of the above-mentioned capacitor structure can still reach the design value, and the above-mentioned capacitor structure is further characterized by a large amount of current flow. | 2013-03-07 |
| 20130056814 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a first stacked body, a second stacked body, a memory film, a gate insulating film, and a channel body. The first stacked body has a plurality of electrode layers and a plurality of first insulating layers. The second stacked body has a selector gate and a second insulating layer. The memory film is provided on a sidewall of a first hole. The gate insulating film is provided on a sidewall of a second hole. The channel body is provided on an inner side of the memory film and on an inner side of the gate insulating film. A step part is provided between a side face of the selector gate and the second insulating layer. A region positioned near a top end of the selector gate of the channel body is silicided. | 2013-03-07 |
| 20130056815 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating flm provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating flm in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer. | 2013-03-07 |
| 20130056816 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film. | 2013-03-07 |
| 20130056817 | SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION STRUCTURES AND METHOD OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced. | 2013-03-07 |
| 20130056818 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a structural body; semiconductor layers; a memory film; a connecting member; and a conductive member. The structural body is provided above a memory region of a substrate including the memory region and a non-memory region, and includes electrode films stacked along a first axis perpendicular to a major surface of the substrate. The semiconductor layers penetrate through the structural body along the first axis. The memory film is provided between the electrode films and the semiconductor layer. The connecting member is provided between the substrate and the structural body and connected to respective end portions of two adjacent ones of the semiconductor layers. The conductive member is provided between the substrate and the connecting member, extends from the memory region to the non-memory region, includes a recess provided above the non-memory region, and includes a first silicide portion provided in the recess. | 2013-03-07 |
| 20130056819 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The second insulating layer comprises a stacked structure provided in order of a first lanthanum aluminate layer, a lanthanum aluminum silicate layer and a second lanthanum aluminate layer from the charge storage layer side to the control gate electrode side. | 2013-03-07 |
| 20130056820 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer. | 2013-03-07 |
| 20130056821 | TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region. | 2013-03-07 |
| 20130056822 | SEMICONDUCTOR DEVICE - A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate. | 2013-03-07 |
| 20130056823 | SEMICONDUCTOR DEVICES - A device isolation layer is formed in a substrate to define spaced-apart linear active regions in the substrate. Buried gate patterns are formed in the substrate and extending along a first direction to cross the active regions. An etch stop layer and a first insulating layer are formed on the substrate. Bit line structures are formed on the first insulating layer and extending along a second direction transverse to the first direction to cross the active regions. A second insulating layer is formed on the bit line structures. Contact plugs are formed penetrating the second insulating layer, the first insulating layer, and the etch stop layer to contact one of the active regions between adjacent ones of the bit line structures. | 2013-03-07 |
| 20130056824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion. | 2013-03-07 |
| 20130056825 | MOS DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 2013-03-07 |
| 20130056826 | Multi-Fin Device and Method of Making Same - A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned. | 2013-03-07 |
| 20130056827 | NON-PLANAR SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure. | 2013-03-07 |
| 20130056828 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon. | 2013-03-07 |
| 20130056829 | Semiconductor Structure and Method for Manufacturing the Same - The present invention relates to a semiconductor structure and a method for manufacturing the same. A semiconductor structure comprises: a semiconductor substrate; a first insulating material layer, a first conductive material layer, a second insulating material layer, a second conductive material layer and an insulating buried layer formed in sequence on the semiconductor substrate; a semiconductor layer bonded on the insulating buried layer; transistors formed on the semiconductor layer, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer. | 2013-03-07 |
| 20130056830 | Semiconductor Structure and Method - An embodiment is a semiconductor structure. The semiconductor structure comprises at least two gate structures on a substrate. The gate structures define a recess between the gate structures, and the recess is defined by a depth in a vertical direction. The depth is from a top surface of at least one of the gate structures to below a top surface of the substrate, and the depth extends in an isolation region in the substrate. The semiconductor structure further comprises a filler material in the recess. The filler material has a first thickness in the vertical direction. The semiconductor structure also comprises an inter-layer dielectric layer in the recess and over the filler material. The inter-layer dielectric layer has a second thickness in the vertical direction below the top surface of the at least one of the gate structures. The first thickness is greater than the second thickness. | 2013-03-07 |
| 20130056831 | SEMICONDUCTOR DEVICE - A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor. | 2013-03-07 |
| 20130056832 | SEMICONDUCTOR DEVICE - A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region. | 2013-03-07 |
| 20130056833 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first field-effect transistor of a first conductivity type formed on a first active region of a semiconductor substrate. The first field-effect transistor includes a first gate insulating film formed on the first active region, and a first gate electrode formed on the first gate insulating film. The first gate electrode includes a first metal electrode formed on the first gate insulating film, a first interface layer formed on the first metal electrode, and a first silicon electrode formed on the first interface layer. | 2013-03-07 |
| 20130056834 | MICROELECTRONIC DEVICE WITH DISCONNECTED SEMICONDUCTOR PORTIONS AND METHODS OF MAKING SUCH A DEVICE - A microelectronic device includes a plurality of disconnected similar semiconducting portions, electrically isolated from each other and forming a semiconductor layer, at a spacing by a constant distance and with a shape parallel to the other portions. The microelectronic device also includes two electrodes arranged in contact with the semiconductor layer such that a maximum distance separating the two electrodes is less than the largest dimension of one of the semiconductor portions. The shape and dimensions of the semiconductor portions, the spacing between the semiconductor portions, the shape and dimensions of the electrodes and the layout of the electrodes relative to the semiconductor portions are such that at least one of the semiconductor portions electrically connects the two electrodes to each other. The largest dimensions of the semiconductor portions are perpendicular to the largest dimension of the electrodes, the electrodes being similar. | 2013-03-07 |
| 20130056835 | TRANSISTOR STRUCTURES AND METHODS OF FABRICATION THEREOF - An electronic device is presented, such as a thin film transistor. The device comprises a patterned electrically-conductive layer associated with an active element of the electronic device. The electrically-conductive layer has a pattern defining an array of spaced-apart electrically conductive regions. This technique allows for increasing an electric current through the device. | 2013-03-07 |
| 20130056836 | Techniques Providing Metal Gate Devices with Multiple Barrier Layers - A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers. | 2013-03-07 |
| 20130056837 | SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure. | 2013-03-07 |
| 20130056838 | SENSOR CHIP AND METHOD FOR MANUFACTURING A SENSOR CHIP - The present sensor chip comprises a substrate. A plurality of electrode elements is arranged at a first level on the substrate with at least one gap between neighbouring electrode elements. A metal structure is arranged at a second level on the substrate, wherein the second level is different from the first level. The metal structure at least extends over an area of the second level that is defined by a projection of the at least one gap towards the second level. | 2013-03-07 |
| 20130056839 | ULTRASENSITIVE BIOSENSORS - The present invention is a biosensor apparatus that includes a substrate, a source on one side of the substrate, a drain spaced from the source, a conducting channel between the source and the drain, an insulator region, and receptors on a gate region for receiving target material. The receptors are contacted for changing current flow between the source and the drain. The source and the drain are relatively wide compared to length between the source and the drain through the conducting channel. | 2013-03-07 |
| 20130056840 | ACOUSTIC TRANSDUCERS WITH PERFORATED MEMBRANES - A MEMS device, such as a microphone, uses a fixed perforated plate. The fixed plate comprises an array of holes across the plate area. At least a set of the holes adjacent the outer periphery comprises a plurality of rows of elongate holes, the rows at different distances from the periphery. This design improves the mechanical robustness of the membrane and can additionally allow tuning of the mechanical behaviour of the plate. | 2013-03-07 |
| 20130056841 | MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICE AND METHOD FOR FABRICATING THE SAME - A MEMS device includes a substrate. The substrate has a plurality of through holes in the substrate within a diaphragm region and optionally an indent space from the second surface at the diaphragm region. A first dielectric structural layer is then disposed over the substrate from the first surface, wherein the first dielectric structural layer has a plurality of openings corresponding to the through holes, wherein each of the through holes remains exposed by the first dielectric structural layer. A second dielectric structural layer with a chamber is disposed over the first dielectric structural layer, wherein the chamber exposes the openings of the first dielectric structural layer and the through holes of the substrate to connect to the indent space. A MEMS diaphragm is embedded in the second dielectric structural layer above the chamber, wherein an air gap is formed between the substrate and the MEMS diaphragm. | 2013-03-07 |
| 20130056842 | HIGH VOLTAGE PHOTO-SWITCH PACKAGE MODULE HAVING ENCAPSULATION WITH PROFILED METALLIZED CONCAVITIES - A photo-conductive switch package module having a photo-conductive substrate or wafer with opposing electrode-interface surfaces metalized with first metallic layers formed thereon, and encapsulated with a dielectric encapsulation material such as for example epoxy. The first metallic layers are exposed through the encapsulation via encapsulation concavities which have a known contour profile, such as a Rogowski edge profile. Second metallic layers are then formed to line the concavities and come in contact with the first metal layer, to form profiled and metalized encapsulation concavities which mitigate enhancement points at the edges of electrodes matingly seated in the concavities. One or more optical waveguides may also be bonded to the substrate for coupling light into the photo-conductive wafer, with the encapsulation also encapsulating the waveguides. | 2013-03-07 |
| 20130056843 | PHOTOMULTIPLIER AND MANUFACTURING METHOD THEREOF - Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region. | 2013-03-07 |
| 20130056844 | Stepped Package For Image Sensor And Method Of Making Same - An image sensor package includes a crystalline handler having opposing first and second surfaces, and a cavity formed into the first surface. At least one step extends from a sidewall of the cavity, wherein the cavity terminates in an aperture at the second surface. A cover is mounted to the second surface and extends over and covers the aperture. The cover is optically transparent to at least one range of light wavelengths. A sensor chip is disposed in the cavity and mounted to the at least one step. The sensor chip includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors. | 2013-03-07 |
| 20130056845 | METHOD FOR FORMING AN ISOLATION TRENCH - A method forms at least one isolation trench in a substrate having an upper surface. The method includes at least: forming, across the substrate thickness, at least one first cavity opened towards the upper surface; totally filling this first cavity with a dielectric material of a first type; forming a second cavity in an upper portion of the first cavity thus filled, said second cavity being opened towards the upper surface and having a substantially concave profile; totally filling this second cavity with a dielectric material of a second type; and leveling the free surface of the trench substantially down to the upper surface level. | 2013-03-07 |
| 20130056846 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening. | 2013-03-07 |
| 20130056847 | SMALL SIZE AND FULLY INTEGRATED POWER CONVERTER WITH MAGNETICS ON CHIP - An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary. | 2013-03-07 |
| 20130056848 | INDUCTIVE LOOP FORMED BY THROUGH SILICON VIA INTERCONNECTION - The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. | 2013-03-07 |
| 20130056849 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor and a second spiral inductor formed in the multilayer interconnect, and an interconnect substrate formed over the semiconductor chip and having a third spiral inductor and a fourth spiral inductor. The third spiral inductor overlaps the first spiral inductor in a plan view. The fourth spiral inductor overlaps the second spiral inductor in the plan view. The third spiral inductor and the fourth spiral inductor collectively include a line, the line being spirally wound in a same direction in the third spiral inductor and the fourth spiral inductor. | 2013-03-07 |
| 20130056850 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region. | 2013-03-07 |
| 20130056851 | Molybdenum Oxide Top Electrode for DRAM Capacitors - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO | 2013-03-07 |
| 20130056852 | Methods For Depositing High-K Dielectrics - Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide. | 2013-03-07 |
| 20130056853 | HORIZONTAL INTERDIGITATED CAPACITOR STRUCTURE WITH VIAS - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis. | 2013-03-07 |
| 20130056854 | COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS - Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices. | 2013-03-07 |
| 20130056855 | METHOD OF MANUFACTURING IC COMPRISING A BIPOLAR TRANSISTOR AND IC - Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. | 2013-03-07 |
| 20130056856 | SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PLASMA INDUCED DAMAGE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device having reduced plasma-induced damage includes providing a p-type semiconductor substrate. The p-type semiconductor substrate has a front surface including the semiconductor device and a back surface. The method further includes doping the back surface with an n-type dopant to form an n-type semiconductor region before forming metal interconnections on the front surface. The n-type semiconductor region and the p-type semiconductor substrate form a pn junction. The method also includes forming an insulation layer on an exposed surface of the n-type semiconductor region. | 2013-03-07 |
| 20130056857 | DEVICE CHIP AND MANUFACTURING METHOD THEREFOR - A manufacturing method for a device chip having a substrate, a device formed on the front side of the substrate, and chip identification information marked inside the substrate includes preparing a device wafer having a base wafer and a plurality of devices formed on the front side of the base wafer so as to be partitioned by division lines, next applying a laser beam having a transmission wavelength to the device wafer from the back side thereof in the condition where the focal point of the laser beam is set inside the base wafer at the positions respectively corresponding to the devices, thereby forming a plurality of modified layer marks as the chip identification information inside the base wafer at the positions respectively corresponding to the devices, and finally dividing the device wafer along the division lines to obtain a plurality of device chips. | 2013-03-07 |
| 20130056858 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity. An integrated circuit is also provided. | 2013-03-07 |
| 20130056859 | SEMICONDUCTOR DEVICE HAVING GROOVES ON A SIDE SURFACE AND METHOD OF MANUFACTURING THE SAME - In one embodiment of a method of manufacturing a semiconductor device, a plurality of substantially columnar trenches are formed along a region for forming a dicing line in a semiconductor substrate having first surface and second surfaces opposed to each other, from the first surface. The substrate is subjected to a heat treatment. At least one hollow portion is formed in the substrate by migration of a material which composes the substrate. Semiconductor devices are formed in semiconductor regions of the substrate which are surrounded by the region for forming the dicing line. The semiconductor regions are provided on a side of the first surface. A portion of the substrate is removed from a side of the second surface until the thickness is reduced to a predetermined value. The substrate is divided into chips along a dicing line from at least the one hollow portion as a starting point. | 2013-03-07 |
| 20130056860 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE - According to one embodiment, a resin-encapsulated semiconductor includes a base a semiconductor chip provided on the base, stress relief members provided on the base and out side semiconductor chip, and each of the stress relief members relieving stress applied to the semiconductor chip. | 2013-03-07 |
| 20130056861 | SEMICONDUCTOR DEVICES AND METHODS OF ASSEMBLING SAME - A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element. | 2013-03-07 |
| 20130056862 | Semiconductor Device and Method of Forming a Low Profile Dual-Purpose Shield and Heat-Dissipation Structure - A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader. | 2013-03-07 |
| 20130056863 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a stiffener, having a stiffener opening completely through the stiffener, on the substrate; molding an encapsulation on the substrate and directly on an outer upper periphery surface of the stiffener and exposing an inner upper periphery surface of the stiffener, the encapsulation exposing a portion of the substrate; mounting an integrated circuit over the substrate and within the perimeter of the stiffener; and attaching a lid plate on the inner upper periphery surface of the stiffener and over the integrated circuit, the lid plate extending above an encapsulation top side. | 2013-03-07 |
| 20130056864 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED THERMAL HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a bottom integrated circuit on a bottom substrate having a peripheral thermal via connected to a peripheral thermal interconnect; mounting an inner heat shield, having a top planar portion, over the bottom integrated circuit with the inner heat shield connected to the peripheral thermal via; mounting a top integrated circuit over the inner heat shield; and forming a package encapsulation over the bottom integrated circuit, the inner heat shield, and the top integrated circuit with the top planar portion exposed only at each corners of a package topside of the package encapsulation. | 2013-03-07 |
| 20130056865 | Method of Three Dimensional Integrated Circuit Assembly - A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages. | 2013-03-07 |
| 20130056866 | STACKED WAFER-LEVEL PACKAGE DEVICE - Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When the semiconductor package device is positioned over the semiconductor device, each micro-solder bump is connected to a respective electrical interconnection that is formed in the semiconductor device. | 2013-03-07 |
| 20130056867 | Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheralregion of semiconductor die - A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements. | 2013-03-07 |
| 20130056868 | ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER - The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM. | 2013-03-07 |
| 20130056869 | PILLAR STRUCTURE HAVING A NON-PLANAR SURFACE FOR SEMICONDUCTOR DEVICES - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 2013-03-07 |
| 20130056870 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having oppositely-facing first and second surfaces and a first aperture extending between the first and second surfaces, a first microelectronic element having a surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, signal leads connected to contacts of the second microelectronic element and extending through the first aperture to at least some of a plurality of electrically conductive elements on the substrate, and at least one power regulation component having active circuit elements therein disposed between the first surface of the substrate and the front surface of the second microelectronic element. The first microelectronic element can have another surface remote from the surface of the first microelectronic element, and an edge extending between the surfaces thereof. The contacts of the second microelectronic element can project beyond the edge of the first microelectronic element. | 2013-03-07 |
| 20130056871 | Thermally Enhanced Structure for Multi-Chip Device - A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. | 2013-03-07 |
| 20130056872 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 2013-03-07 |
| 20130056873 | SEMICONDUCTOR DEVICE - According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively. | 2013-03-07 |
| 20130056874 | Protection of intermetal dielectric layers in multilevel wiring structures - A semiconductor device is accepted at a stage of its fabrication, at which stage the device includes a diffusion-barrier cap-material (DBCM) layer and an intermetal dielectric layer covering the DBCM layer. The DBCM layer is exposed and it is suitable for removal by an etching procedure in a portion of a pattern contained in the intermetal dielectric layer. A silylation treatment is performed on the semiconductor device prior to the etching procedure for removing the DBCM layer. The intermetal dielectric layer of the completed device has surfaces in contact with metal interconnects and metal vias, and it may have an excess of carbon content near at least a portion of the these surfaces. | 2013-03-07 |
| 20130056875 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin. | 2013-03-07 |
| 20130056876 | COMPOSITE ELECTRODE AND METHOD OF MANUFACTURE THEREOF - The present invention provides a composite electrode and method of manufacturing such a composite electrode, the method comprising the steps of: providing a first substrate layer with an electrically conducting surface; providing a non-conducting curable material; providing a second substrate layer which has a surface relief pattern defining at least one retaining feature corresponding to a desired metal track pattern; forming a line of contact between the conducting carrier layer and at least a part of the surface relief pattern; depositing curable material onto at least part of the surface relief pattern or the electrically conducting surface along the line of contact; advancing the line of contact and curing the curable material through the second substrate layer; releasing the cured material from the surface relief pattern feature so as to leave behind a surface relief pattern on the conducting carrier layer; depositing a first metal layer onto the exposed regions of the electrically conducting surface of the conducting carrier layer and optionally deposition further metal layers on the first metal layer. | 2013-03-07 |
| 20130056877 | CHIP-HOUSING MODULE AND A METHOD FOR FORMING A CHIP-HOUSING MODULE - A chip-housing module including a carrier configured to carry one or more chips; the carrier including: a first plurality of openings, wherein each opening of the first plurality of openings is separated by a first pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a first range of voltage values to a chip; a second plurality of openings, wherein each opening of the second plurality of openings is separated by a second pre-determined distance, and configured to receive a chip connection for providing a voltage lying within a second range of voltage values to a chip; and wherein a pair of openings consisting of one opening of the first plurality of openings and one opening of the second plurality of openings is separated by a distance different from at least one of the first pre-determined distance and the second pre-determined distance, is provided. | 2013-03-07 |
| 20130056878 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region. | 2013-03-07 |
| 20130056879 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 2013-03-07 |
| 20130056880 | SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME - An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die. | 2013-03-07 |
| 20130056881 | Discrete Three-Dimensional Memory - The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%. | 2013-03-07 |
| 20130056882 | SEMICONDUCTOR PACKAGE HAVING SUPPORT MEMBER - Semiconductor packages including a substrate, a plurality of first semiconductor chips stacked on the substrate, a second semiconductor chip interposed between the substrate and a lowermost semiconductor chip among the first semiconductor chips, and a supporting member disposed between the substrate and the lowermost semiconductor chip among the first semiconductor chips to support the first semiconductor chips, may be provided. The supporting member may include a passive element such as a capacitor, a resistor, or an inductor. By including the supporting member, the semiconductor packages may achieve a smaller planar size and have an improved tolerance for subsequent interconnections. | 2013-03-07 |
