| 10th week of 2014 patent applcation highlights part 61 |
| Patent application number | Title | Published |
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| 20140065734 | METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES - The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished. | 2014-03-06 |
| 20140065735 | IMPRINT APPARATUS, IMPRINT METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position. | 2014-03-06 |
| 20140065736 | DEVICE CORRELATED METROLOGY (DCM) FOR OVL WITH EMBEDDED SEM STRUCTURE OVERLAY TARGETS - Aspects of the present disclosure describe a target for use in measuring a relative position between two substantially coplanar layers of a device. The target includes periodic structures in first and second layers. Differences in relative position of the first and the second layers between the first and second periodic structures and the respective device-like structure can be measured to correct the relative position of the first and the second layers between the first and second periodic structures. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-03-06 |
| 20140065737 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - Provided is an ion implantation method of transporting ions generated by an ion source to a wafer and implanting the ions into the wafer by irradiating an ion beam on the wafer, including, during the ion implantation into the wafer, using a plurality of detection units which can detect an event having a possibility of discharge and determining a state of the ion beam based on existence of detected event having a possibility of discharge and a degree of influence of the event on the ion beam. | 2014-03-06 |
| 20140065738 | LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS - A method of testing a semiconductor substrate having through substrate vias for current leakage which includes: forming a current leakage measurement structure that includes substrate contacts, sensing circuits to sense current leakage from the through substrate vias, the sensing circuits connected to the through substrate vias and to the substrate contacts so that there is a one-to-one correspondence of a substrate contact and sensing circuit to each through substrate via, and a built-in self test (BIST) engine to sense one of the through substrate vias for current leakage. A reference current is applied to the sensing circuits to set a current leakage threshold for the through substrate vias. A through substrate via is selected for sensing for current leakage. The sensing circuit senses the selected through substrate via to determine whether there is current leakage from the selected through substrate via. | 2014-03-06 |
| 20140065739 | METHOD FOR HYBRID ENCAPSULATION OF AN ORGANIC LIGHT EMITTING DIODE - Methods and apparatus for encapsulating organic light emitting diode (OLED) structures disposed on a substrate using a hybrid layer of material are provided. The encapsulation methods may be performed as single or multiple chamber processes. The processing parameters used during deposition of the hybrid layer of material allow control of the characteristics of the deposited hybrid layer. The hybrid layer may be deposited such that the layer has characteristics of an inorganic material in some sublayers of the hybrid layer and characteristics of an organic material in other sublayers of the hybrid layer. Use of the hybrid material allows OLED encapsulation using a single hard mask for the complete encapsulating process with low cost and without alignment issues present in conventional processes. | 2014-03-06 |
| 20140065740 | Single Phosphor Layer Photonic Device for Generating White Light or Color Lights - A photonic device generates light from a full spectrum of lights including white light. The device includes two or more LEDs grown on a substrate, each generating light of a different wavelength and separately controlled. A light-emitting structure is formed on the substrate and apportioned into the two or more LEDs by etching to separate the light-emitting structure into different portions. At least one of the LEDs is coated with a phosphor material so that different wavelengths of light are generated by the LEDs while the same wavelength of light is emitted from the light-emitting structure. | 2014-03-06 |
| 20140065741 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 2014-03-06 |
| 20140065742 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method for making a light emitting diode includes the following steps. A first epitaxial substrate having a first epitaxial growth surface is provided. A carbon nanotube layer is placed on the first epitaxial growth surface. An intrinsic semiconductor layer is grown on the first epitaxial growth surface epitaxially. A second epitaxial substrate is formed by removing the carbon nanotube layer, wherein the second epitaxial substrate has a second epitaxial growth surface. A first semiconductor layer, an active layer and a second semiconductor layer are grown on the second epitaxial growth surface in that order. A part of the first semiconductor layer is exposed by etching a part of the active layer and the second semiconductor layer. A first electrode is applied on the first semiconductor layer and a second electrode is applied on the second semiconductor layer. | 2014-03-06 |
| 20140065743 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE DIE - An exemplary method of manufacturing a light emitting diode (LED) die includes steps: providing a preformed LED structure, the LED structure including a first substrate, and a nucleation layer, a buffer layer, an N-type layer, a muti-quantum well layer and an P-type layer formed successively on the first substrate; forming at least one insulation block on the P-type layer; forming a mirror layer on the on the P-type layer and covering the insulation block; forming a conductive second substrate on the mirror layer; removing the first substrate, the nucleation layer and the buffer layer and exposing a bottom surface of the N-type layer; and disposing one N-electrode on the exposed surface of the N-type layer. The N-electrode is located corresponding to the insulation block. | 2014-03-06 |
| 20140065744 | METHOD FOR MANUFACTURING IMAGE DISPLAY DEVICE - A liquid photocurable resin composition not containing a thermal polymerization initiator is applied to a surface of a light-transmitting cover member having a light-shielding layer or a surface of an image display member, irradiated with ultraviolet rays under an atmosphere where the oxygen concentration is significantly decreased and cured, to form a light-transmitting cured resin layer. Subsequently, the image display member and the light-transmitting cover member are stacked through the light-transmitting cured resin layer to manufacture an image display device of the present invention. | 2014-03-06 |
| 20140065745 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE - A manufacturing method for an LED (light emitting diode) includes following steps: providing a substrate; disposing a transitional layer on the substrate, the transitional layer comprising a planar area with a flat top surface and a patterned area with a rugged top surface; coating an aluminum layer on the transitional layer; using a nitriding process on the aluminum layer to form an AlN material on the transitional layer; disposing an epitaxial layer on the transitional layer and covering the AlN material, the epitaxial layer contacting the planar area and the patterned area of the transitional layer, a plurality of gaps being defined between the epitaxial layer and the slugs of the second part of the AlN material in the patterned area of the transitional layer. | 2014-03-06 |
| 20140065746 | SUPPORTING SUBSTRATE FOR PREPARING SEMICONDUCTOR LIGHT-EMITTING DEVICE AND SEMICONDUCTOR LIGHT-EMITTING DEVICE USING SUPPORTING SUBSTRATES - A method may be provided for preparing a semiconductor light-emitting device. The method may include: preparing a first wafer in which a semiconductor multi-layered light-emitting structure is disposed on an upper part of an initial substrate; preparing a second wafer which is a supporting substrate; bonding the second wafer on an upper part of the first wafer; separating the initial substrate of the first wafer from a result of the bonding; and fabricating a single-chip by severing a result of the passivation. Other embodiments may be provided. | 2014-03-06 |
| 20140065747 | METHOD AND DEVICE FOR PRODUCING SOLAR CELL STRINGS - A method and an apparatus for producing solar cell strings by connecting at least two solar cells by a least one conductor ribbon of a first length, wherein the solar cells are respectively spaced from one another at a string cell spacing(s), until a desired number of solar cells for producing a first solar cell string is connected together, connecting a further solar cell with a last solar cell of the first solar string by at least another conductor ribbon which is longer than the at least one conductor ribbon, wherein the second solar cell is spaced from the last solar cell at a greater spacing than the string cell spacing(s) and wherein the second solar cell forms the first solar cell for a second solar string, and separating the at least another conductor ribbon for decoupling the first solar cell string. | 2014-03-06 |
| 20140065748 | METHOD FOR MANUFACTURING DISTRIBUTED FEEDBACK LASER ARRAY - A method for manufacturing a distributed feedback laser array includes: forming a bottom separate confinement layer on a substrate; forming a quantum-well layer on the bottom separate confinement layer; forming a selective-area epitaxial dielectric mask pattern on the quantum-well layer; forming a top separate confinement layer on the quantum-well layer through selective-area epitaxial growth using the selective-area epitaxial dielectric mask pattern, the top separate confinement layer having different thicknesses for different laser units; removing the selective-area epitaxial dielectric mask pattern; forming an optical grating on the top separate confinement layer; and growing a contact layer on the optical grating. The present disclosure achieves different emission wavelengths for different laser units without significantly affect emission performance of the quantum-well material. | 2014-03-06 |
| 20140065749 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes: a substrate including a display area and a drive region in which a driving chip for transmitting a driving signal to the pixels is located; a gate line in the display area; a storage electrode line; a gate driving pad coupled to the driving chip; a gate insulating layer; a first semiconductor layer on the gate insulating layer and overlapped with a gate electrode protruding from the gate line; a second semiconductor layer formed on the gate insulating layer and overlapped with a sustain electrode protruding from the storage electrode line; a data line crossing the gate line in an insulated manner and a drain electrode separated from the data line; and a pixel electrode coupled to the drain electrode, and the drain electrode comprises a drain bar facing the source electrode, and a drain extender overlapped with the second semiconductor layer. | 2014-03-06 |
| 20140065750 | PATTERNING METHOD FOR OLEDS - Methods of fabricating a device having laterally patterned first and second sub-devices, such as subpixels of an OLED, are provided. Exemplary methods may include depositing via organic vapor jet printing (OVJP) a first organic layer of the first sub-device and a first organic layer of the second sub-device. The first organic layer of the first sub-device and the first organic layer of the second sub-device are both the same type of layer, but have different thicknesses. The type of layer is selected from an ETL, an HTL, an HIL, a spacer and a capping layer. | 2014-03-06 |
| 20140065751 | Method For Manufacturing Three-Dimensionally Shaped Comb-Tooth Electret Electrode - A method for manufacturing a three-dimensionally shaped comb-tooth electret electrode, provided with positive ions, includes: forming a three-dimensional movable comb-tooth electrode and a three-dimensional fixed comb-tooth electrode from an Si substrate; contacting a vapor including ions thereto, and forming an oxide layer including ions upon surfaces of the comb-tooth electrodes with heat applied thereto; and applying a voltage between the movable electrode and the fixed electrode with heat applied thereto, and thereby causing the ions included in the oxide layer to shift to a surface of the oxide layer; wherein, the voltage between the movable electrode and the fixed electrode is changed, so that the operation of each of the comb-teeth of the movable electrode being alternatingly pulled in against two opposed comb-teeth of the fixed electrode is repeated, and the pulling in voltage and the pulled-in state release voltage are gradually increased. | 2014-03-06 |
| 20140065752 | UNIFORMLY DISTRIBUTED SELF-ASSEMBLED SOLDER DOT FORMATION FOR HIGH EFFICIENCY SOLAR CELLS - A method for fabricating a photovoltaic device includes performing a gettering process in a processing chamber which restricts formation of a layer of gettering materials on a substrate and forming a solder layer on the substrate. The solder layer is annealed to form uniformly distributed solder dots which grow on the substrate. The substrate is etched using the solder dots to protect portions of the substrate and form cones in the substrate such that the cones provide a three-dimensional radiation absorbing structure for the photovoltaic device. | 2014-03-06 |
| 20140065753 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor having a pixel region and a peripheral circuit region, includes forming an oxide film on a semiconductor substrate, forming an insulating film on the oxide film, forming a first opening in the insulating film and the oxide film in the peripheral circuit region, forming a trench in the semiconductor substrate in the peripheral circuit region by etching the semiconductor substrate through the first opening using the insulating film as a mask, forming a second opening in the insulating film to penetrate through the insulating film in the pixel region and to reach a predetermined depth of the oxide film, and forming insulators in the trench and the second opening. | 2014-03-06 |
| 20140065754 | METHOD FOR FABRICATING POWER-GENERATING MODULE WITH SOLAR CELL - The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit. | 2014-03-06 |
| 20140065755 | Method Of Making A Low Stress Cavity Package For Back Side Illuminated Image Sensor - An image sensor package includes an image sensor chip and crystalline handler. The image sensor chip includes a substrate, and a plurality of photo detectors and contact pads at the front surface of the substrate. The crystalline handler includes opposing first and second surfaces, and a cavity formed into the first surface. A compliant dielectric material is disposed in the cavity. The image sensor front surface is attached to the crystalline substrate handler second surface. A plurality of electrical interconnects each include a hole aligned with one of the contact pads, with a first portion extending from the second surface to the cavity and a second portion extending through the compliant dielectric material, a layer of insulation material formed along a sidewall of the first portion of the hole, and conductive material extending through the first and second portions of the hole and electrically coupled to the one contact pad. | 2014-03-06 |
| 20140065756 | Sidewall for Backside Illuminated Image Sensor Metal Grid and Method of Manufacturing Same - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 2014-03-06 |
| 20140065757 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell includes performing a dry etching process to form a textured surface including a plurality of minute protrusions on a first surface of a semiconductor substrate, performing a first cleansing process for removing damaged portions of surfaces of the minute protrusions using a basic chemical and removing impurities adsorbed on the surfaces of the minute protrusions, performing a second cleansing process for removing impurities remaining or again adsorbed on the surfaces of the minute protrusions using an acid chemical after performing the first cleansing process, and forming an emitter region at the first surface of the semiconductor substrate. | 2014-03-06 |
| 20140065758 | COVER FOR PROTECTING SOLAR CELLS DURING FABRICATION - A removable cover system for protecting solar cells from exposure to moisture during fabrication processes. The cover system includes a cover having a configuration that complements the configuration of a solar cell substrate to be processed in an apparatus where moisture is present. A resiliently deformable seal member attached to the cover is positionable with the cover to engage and seal the top surface of the substrate. In one embodiment, the cover is dimensioned and arranged so that the seal member engages the peripheral angled edges and corners of the substrate for preventing the ingress of moisture beneath the cover. An apparatus for fabricating a solar cell using the cover and associated method are also disclosed. | 2014-03-06 |
| 20140065759 | METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE - A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure. | 2014-03-06 |
| 20140065760 | METHOD OF FORMING ZINC OXIDE PROMINENCE AND DEPRESSION STRUCTURE AND METHOD OF MANUFACTURING SOLAR CELL USING THEREOF - A method of forming a nanometer-scale prominence and depression structure on a zinc oxide thin film in a wet-etching method, and the method includes the steps of: preparing a substrate; forming a nano structure having a height and a width of a nanometer range; forming the zinc oxide thin film on the substrate on which the nano structure is formed; and wet-etching the zinc oxide thin film, in which in the wet-etching step, zinc oxide having relatively low physical compactness is preferentially etched since the zinc oxide is positioned on the nano structure, and thus the prominence and depression structure is formed around the nano structure by the etching. | 2014-03-06 |
| 20140065761 | COMPOSITION FOR FORMING P-TYPE DIFFUSION LAYER, METHOD OF FORMING P-TYPE DIFFUSION LAYER, AND METHOD OF PRODUCING PHOTOVOLTAIC CELL - The composition for forming a composition for forming a p-type diffusion layer, the composition containing a glass powder and a dispersion medium, in which the glass powder includes an acceptor element and a total amount of a life time killer element in the glass powder is 1000 ppm or less. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment. | 2014-03-06 |
| 20140065762 | METHOD OF CONTROLLING THE AMOUNT OF Cu DOPING WHEN FORMING A BACK CONTACT OF A PHOTOVOLTAIC CELL - Methods for preparing an exposed surface of a p-type absorber layer of a p-n junction for coupling to a back contact in the manufacture of a thin film photovoltaic device are provided. The method can include: applying a treatment solution onto the exposed surface defined by the p-type absorber layer of cadmium telluride; and annealing the device with the p-type absorber layer in contact with the treatment solution to form a tellurium-enriched region in the p-type absorber layer at the exposed surface. The treatment solution comprises a chlorinated compound component that is substantially free from copper, a copper-containing metal salt, and a solvent. | 2014-03-06 |
| 20140065763 | METHODS OF TREATING A SEMICONDUCTOR LAYER - Methods for treating a semiconductor layer including a semiconductor material are presented. A method includes contacting at least a portion of the semiconductor material with a passivating agent. The method further includes forming a first region in the semiconductor layer by introducing a dopant into the semiconductor material; and forming a chalcogen-rich region. The method further includes forming a second region in the semiconductor layer, the second region including a dopant, wherein an average atomic concentration of the dopant in the second region is greater than an average atomic concentration of the dopant in the first region. Photovoltaic devices are also presented. | 2014-03-06 |
| 20140065764 | METHOD FOR MANUFACTURING A PHOTOVOLTAIC CELL WITH A LOCALLY DIFFUSED REAR SIDE - A method for manufacturing a photovoltaic cell with a locally diffused rear side, comprising steps of: (a) providing a doped silicon substrate, the substrate comprising a front, sunward facing, surface and a rear surface; (b) forming a silicon dioxide layer on the front surface and the rear surface; (c) depositing a boron-containing doping paste on the rear surface in a pattern, the boron-containing paste comprising a boron compound and a solvent; (d) depositing a phosphorus-containing doping paste on the rear surface in a pattern, the phosphorus-containing doping paste comprising a phosphorus compound and a solvent; (e) heating the silicon substrate in an ambient to a first temperature and for a first time period in order to locally diffuse boron and phosphorus into the rear surface of the silicon substrate. | 2014-03-06 |
| 20140065765 | MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF FUNCTIONAL ELEMENT - According to one embodiment, the manufacturing method of a functional element includes filling a solvent comprising hydrogen gas and having organic molecules dispersed therein into a gap between the first electrode and the second electrode formed facing the first electrode, and forming an organic layer containing the organic molecules mentioned above between the first electrode and the second electrode. | 2014-03-06 |
| 20140065766 | METHOD FOR FABRICATING WELL-ALIGNED ZINC OXIDE MICRORODS AND NANORODS AND APPLICATION THEREOF - The present invention relates to a method for fabricating well-aligned zinc oxide microrods and nanorods and application thereof and particularly relates to a method for fabricating well-aligned zinc oxide microrods and nanorods on a general substrate by hydrothermal method and application thereof. | 2014-03-06 |
| 20140065767 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip. | 2014-03-06 |
| 20140065768 | METHOD FOR PROCESSING A WAFER AND METHOD FOR DICING A WAFER - In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die. | 2014-03-06 |
| 20140065769 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof. | 2014-03-06 |
| 20140065770 | PACKAGE INTERFACE PLATE FOR PACKAGE ISOLATION STRUCTURES - A package assembly comprises a package base, a sensor die, an isolation plate, and a package interface plate. The isolation plate is bonded to the sensor die and has a plurality of flexible beams. Each flexible beam is configured to deflect under stress such that effects on the sensor die of a thermal mismatch between the package base and the sensor die are reduced. The package interface plate is bonded to the isolation plate and the package base. The package interface plate is configured to limit the maximum distance each flexible beam is able to deflect. | 2014-03-06 |
| 20140065771 | DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING - Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly. | 2014-03-06 |
| 20140065772 | METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING - A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 2014-03-06 |
| 20140065773 | ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE - A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs. | 2014-03-06 |
| 20140065774 | EMBEDDED PLANAR SOURCE/DRAIN STRESSORS FOR A FINFET INCLUDING A PLURALITY OF FINS - Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins. | 2014-03-06 |
| 20140065775 | FABRICATION METHOD FOR SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer. | 2014-03-06 |
| 20140065776 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed. | 2014-03-06 |
| 20140065777 | DRAM WITH DUAL LEVEL WORD LINES - A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels. | 2014-03-06 |
| 20140065778 | LOW LOSS SIC MOSFET - A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses. | 2014-03-06 |
| 20140065779 | METHOD FOR MANUFACTURING FINFET - Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies. | 2014-03-06 |
| 20140065780 | Split-Channel Transistor and Methods for Forming the Same - A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel. | 2014-03-06 |
| 20140065781 | Ultra-High Voltage N-Type-Metal-Oxide-Semiconductor (UHV NMOS) Device and Methods of Manufacturing the same - An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer. | 2014-03-06 |
| 20140065782 | METHOD OF MAKING A FINFET DEVICE - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure. | 2014-03-06 |
| 20140065783 | OXYGEN SCAVENGING SPACER FOR A GATE ELECTRODE - At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer. | 2014-03-06 |
| 20140065784 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE WITH CAPACITORS USING MOLD STRUCTURE AND PROTECTION LAYER - A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes. | 2014-03-06 |
| 20140065785 | SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE - Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes. | 2014-03-06 |
| 20140065786 | Large Dimension Device and Method of Manufacturing Same in Gate Last Process - An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode. | 2014-03-06 |
| 20140065787 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode. | 2014-03-06 |
| 20140065788 | Combinatorial Approach for Screening of ALD Film Stacks - In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner. | 2014-03-06 |
| 20140065789 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode. | 2014-03-06 |
| 20140065790 | Work Function Tailoring for Nonvolatile Memory Applications - Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another. | 2014-03-06 |
| 20140065791 | ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS - An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology. | 2014-03-06 |
| 20140065792 | HIGH BREAKDOWN VOLTAGE EMBEDDED MIM CAPACITOR STRUCTURE - Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material. | 2014-03-06 |
| 20140065793 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening. | 2014-03-06 |
| 20140065794 | Method for Forming a Buried Dielectric Layer Underneath a Semiconductor Fin - Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin. | 2014-03-06 |
| 20140065795 | METHOD FOR FORMING TRENCH ISOLATION - A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench. | 2014-03-06 |
| 20140065796 | GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD - The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers. | 2014-03-06 |
| 20140065797 | IN-SITU DEPOSITED MASK LAYER FOR DEVICE SINGULATION BY LASER SCRIBING AND PLASMA ETCH - Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off. | 2014-03-06 |
| 20140065798 | METHOD AND APPARATUS FOR FORMING GATE STACK ON Si, SiGe or Ge CHANNELS - Provided are methods and apparatus for functionalizing a substrate surface used as the channel in a gate stack. Silicon, germanium and silicon germanium substrates surfaces are functionalized with one or more of sulfur and selenium by plasma processing. | 2014-03-06 |
| 20140065799 | Methods and Systems for Low Resistance Contact Formation - Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include exposing the substrate to an activated hydrogen species to remove contaminant layers such as native oxide layers followed by exposing the substrate to plasma activated dopant species to passivate the surface. The methods can further include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate. The cleaning, passivation, and deposition steps are performed in-situ without breaking vacuum. | 2014-03-06 |
| 20140065800 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Gas containing Si, gas containing C and gas containing Cl are introduced into a reacting furnace. SiC epitaxial film is grown on the surface of a 4H—SiC substrate by CVD in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas. The amount of the gas containing Cl relative to the gas containing Si in the gas atmosphere is reduced gradually. At the start of growth, the number of Cl atoms in the gas containing Cl is three times as large as the number of Si atoms in the gas containing Si. The number of Cl atoms in the gas containing Cl relative to the number of Si atoms in the gas containing Si in the gas atmosphere is reduced at a rate of 0.5%/min to 1.0%/min. The method grows silicon carbide semiconductor film at a high rate. | 2014-03-06 |
| 20140065801 | Group III-V Substrate Material With Particular Crystallographic Features And Methods Of Making - A method of forming a semiconductor substrate including providing a base substrate including a semiconductor material, and forming a first semiconductor layer overlying the base substrate having a Group 13-15 material via hydride vapor phase epitaxy (HVPE), the first semiconductor layer having an upper surface having a N-face orientation. | 2014-03-06 |
| 20140065802 | TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES - Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided. | 2014-03-06 |
| 20140065803 | PATTERNED THIN FILM DIELECTRIC STACK FORMATION - A method of producing an inorganic multi-layered thin film structure includes providing a substrate. A patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. A second inorganic thin film material layer is selectively deposited on the region of the substrate where the thin film deposition inhibiting material layer is not present using an atomic layer deposition process. | 2014-03-06 |
| 20140065804 | LOW TEMPERATURE POLYSILICON THIN FILM AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S | 2014-03-06 |
| 20140065805 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - According to one embodiment, a manufacturing method of a semiconductor device includes forming a crystal film on a semiconductor substrate by irradiating the semiconductor substrate with a first microwave, obtained by providing frequency modulation or phase modulation of a first carrier wave which is a sine wave with a first frequency, using a first signal wave which is a sine wave or a pulse wave with a third frequency lower than a first frequency, and irradiating the semiconductor substrate with a second microwave, obtained by providing frequency modulation or phase modulation of a second carrier wave, which is a sine wave with a second frequency higher than the first frequency, using a second signal wave which is a sine wave or a pulse wave with a fourth frequency lower than the second frequency. | 2014-03-06 |
| 20140065806 | ELECTRONIC DEVICES INCLUDING BARIUM STRONTIUM TITANIUM OXIDE FILMS - Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition. | 2014-03-06 |
| 20140065807 | PARTIALLY-BLOCKED WELL IMPLANT TO IMPROVE DIODE IDEALITY WITH SiGe ANODE - A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction. | 2014-03-06 |
| 20140065808 | METHOD OF FORMING A MATERIAL LAYER IN A SEMICONDUCTOR STRUCTURE - A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer. | 2014-03-06 |
| 20140065809 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern. | 2014-03-06 |
| 20140065810 | METHOD OF FORMING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded. | 2014-03-06 |
| 20140065811 | REPLACEMENT METAL GATE SEMICONDUCTOR DEVICE FORMATION USING LOW RESISTIVITY METALS - Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof. | 2014-03-06 |
| 20140065812 | MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array. A second mandrel is formed on the hard-mask material in a region of a selection gate transistor. First sidewall-masks are formed on side-surfaces of the first mandrels. A second sidewall-mask is formed on a side-surface of the second mandrel. An upper side-surface of the second sidewall-mask is exposed. A sacrificial film is embedded between the first sidewall-masks. A sacrificial spacer is formed on the upper side-surface of the second sidewall-mask. A resist film covers the second mandrel. An outer edge of the resist film is located between the first mandrel closest to the second mandrel and the sacrificial spacer. The first mandrels are removed using the resist film as a mask. And, the sacrificial film and spacer are removed. | 2014-03-06 |
| 20140065813 | SIZE-FILTERED MULTIMETAL STRUCTURES - A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width. | 2014-03-06 |
| 20140065814 | MANUFACTURING METHOD FOR MICRO BUMP STRUCTURE - A manufacturing method for a micro bump structure includes the following steps as follows. A substrate is provided and a under bump metallurgy (UBM) is formed on the substrate for accommodating a solder ball. A buffer layer is disposed on the substrate and then the solder ball is disposed on the UBM. Finally, the solder ball is grinded in order get the height reduced to a predetermined height. | 2014-03-06 |
| 20140065815 | BEOL INTEGRATION SCHEME FOR COPPER CMP TO PREVENT DENDRITE FORMATION - Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired. | 2014-03-06 |
| 20140065816 | DIELECTRIC FORMATION - Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated. | 2014-03-06 |
| 20140065817 | HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface. | 2014-03-06 |
| 20140065818 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature. | 2014-03-06 |
| 20140065819 | Methods and Systems for Low Resistance Contact Formation - Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate. | 2014-03-06 |
| 20140065820 | PATTERN STRUCTURES IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING PATTERN STRUCTURES IN SEMICONDUCTOR DEVICES - A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line. The pad includes a protruding portion extending from a lateral portion of the pad. The pattern structure may be formed by simplified processes and may be employed in various semiconductor devices requiring minute patterns and pads. | 2014-03-06 |
| 20140065821 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 2014-03-06 |
| 20140065822 | METHOD FOR FORMING PATTERN - A method for forming a pattern according to an embodiment, includes forming a first film pattern having a wide width dimension above a processed film; forming a second film pattern covering a portion of the first film pattern and a third film pattern connected to the second film pattern together above the processed film, the third film pattern having a width dimension narrower than the first film pattern, and to be a line pattern of a line and space pattern; forming a fourth film pattern on a side face of the first film pattern and a plurality of film patterns by the fourth film to be a line pattern of a line and space pattern on both side faces of the third film pattern; and removing the second film pattern and the third film pattern. | 2014-03-06 |
| 20140065823 | METHODS OF FORMING PATTERNS, AND METHODS OF FORMING INTEGRATED CIRCUITRY - Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern. | 2014-03-06 |
| 20140065824 | MAINTAINING MASK INTEGRITY TO FORM OPENINGS IN WAFERS - One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas. | 2014-03-06 |
| 20140065825 | POLISHING SLURRY FOR CMP AND POLISHING METHOD - A method including preparing a polishing slurry for CMP for polishing at least a conductor layer and a conductive substance layer in contact with the conductor layer, wherein the absolute value of the potential difference between the conductive substance and the conductor at 50±5° C. is 0.25 V or less in the polishing slurry when a positive electrode and a negative electrode of a potentiometer are connected to the conductive substance and the conductor, respectively. The polishing slurry for CMP preferably comprises at least one compound selected from heterocyclic compounds containing any one of hydroxyl group, carbonyl group, carboxyl group, amino group, amide group and sulfinyl group, and containing at least one of nitrogen and sulfur atoms. | 2014-03-06 |
| 20140065826 | POLISHING SLURRY FOR METAL FILMS AND POLISHING METHOD - Provided are a polishing slurry for metal films and a polishing method which restrain the generation of erosion and seams, and makes the flatness of a surface polished therewith or thereby high. The slurry and the method are a polishing slurry, for metal films, comprising abrasive grains, a methacrylic acid based polymer and water, and a polishing method using the slurry, respectively. | 2014-03-06 |
| 20140065827 | GAS DISTRIBUTION SHOWERHEAD FOR INDUCTIVELY COUPLED PLASMA ETCH REACTOR - A two piece ceramic showerhead includes upper and lower plates which deliver process gas to an inductively coupled plasma processing chamber. The upper plate overlies the lower plate and includes radially extending gas passages which extend inwardly from an outer periphery of the upper plate, axially extending gas passages in fluid communication with the radially extending gas passages and an annular recess forming a plenum between the upper and lower plates. The lower plate includes axially extending gas holes in fluid communication with the plenum. The two piece ceramic showerhead forms a dielectric window of the chamber through which radiofrequency energy generated by an antenna is coupled into the chamber. The gas delivery system is operable to supply an etching gas and a deposition gas into the processing chamber such that the etching gas in the plenum can be replaced with the deposition gas. | 2014-03-06 |
| 20140065828 | SELECTIVE FIN CUT PROCESS - A process is provided for selective removal of one or more unwanted fins during FINFET device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s). In enhanced aspects, the removing includes removing a hard mask from the at least one unwanted fin structure(s) exposed through the opening(s), and selectively removing semiconductor material of at least one unwanted fin structure(s). The conformal protective layer protects one or more remaining fin structures during the selective removal of the semiconductor material of the unwanted fin structure(s). | 2014-03-06 |
| 20140065829 | TRENCH FORMATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a trench formation method uses a plasma source to make a trench in a silicon substrate by alternately repeating a depositing step and an etching step. The method includes implementing the depositing step and the etching step to satisfy the formulas recited below, where a distance between the silicon substrate and a region where plasma is to be confined is x (mm), an RF power to induce the plasma is w (kW), a pressure of the depositing step is y (Pa), and a tolerable limit of fluctuation in a plane of the silicon substrate of a width of the trench to be made is z | 2014-03-06 |
| 20140065830 | PATTERNED THIN FILM DIELECTRIC STACK FORMATION - A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process. The first and second inorganic thin film dielectric material layers form a patterned inorganic thin film dielectric stack. | 2014-03-06 |
| 20140065831 | PATTERNED THIN FILM DIELECTRIC LAYER FORMATION - A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process. | 2014-03-06 |
| 20140065832 | ENHANCED FINFET PROCESS OVERLAY MARK - An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin. | 2014-03-06 |
| 20140065833 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns. | 2014-03-06 |
