| 10th week of 2015 patent applcation highlights part 84 |
| Patent application number | Title | Published |
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| 20150067357 | PREDICTION FOR POWER GATING - The present application describes embodiments of methods for tournament prediction of power gating in processing devices. Some embodiments of the method include selecting one of a plurality of predictions of a duration of a time to a power state transition of a component in a processing device. The plurality of predictions are generated using a corresponding plurality of prediction algorithms. Some embodiments of the method also include deciding whether to transition the component from a first power state to a second power state based on the selected prediction. | 2015-03-05 |
| 20150067358 | INJECTION LOCKED PHASING FOR A PEAK-VALLEY MULTIPHASE REGULATOR - A system and method capable of injection locking the phases of a peak-valley multiphase regulator includes comparing an output voltage error signal with a ramp control signal and providing a corresponding slope reset signal, using transitions of the slope reset signal to develop a equally spaced high side ramp signals and equally spaced low side ramp signals, and injecting a corresponding one of the high side signals and a corresponding one of the low side ramp signals into each of the phases which correspondingly develop equally spaced pulse control signals for multiphase operation. Such injection locking allows the additional phases to operate out of phase with the first phase and allows operation at high duty cycles. | 2015-03-05 |
| 20150067359 | INFORMATION PROCESSING APPARATUS AND POWER CONTROL METHOD - An information processing apparatus includes a power circuit, a system control circuit, an information processing unit, a device connection port, a first switch, a second switch, and a power control circuit to supply the electric power to the device connection port from the power circuit with the system control circuit booting up the information processing unit when accepting the instruction of the power supply by the first switch, and to supply the electric power to the device connection port from the power circuit with the system control circuit restraining the information processing unit from being booted up when accepting the instruction of the power supply by the second switch in a state of the first switch not accepting the instruction of the power supply. | 2015-03-05 |
| 20150067360 | PROVIDING POWER MANAGEMENT SERVICES IN A SOFTWARE PROVISIONING ENVIRONMENT - A software provisioning server can communicate with a power management system of the target machines to alter the power state of the target machines during actions requiring a change in the power state, such as power cycling the target machines during a software installation. The software provisioning server can communicate with the power management system of the target machines and instruct the power management systems to alter the power state of the target machines during the actions. | 2015-03-05 |
| 20150067361 | Adaptively Controlling Low Power Mode Operation For A Cache Memory - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions distributed across a die of the processor, a plurality of sleep circuits each coupled to one of the portions of the cache memory, and at least one sleep control logic coupled to the cache memory portions to dynamically determine a sleep setting independently for each of the sleep circuits and to enable the corresponding sleep circuit to maintain the corresponding cache memory portion at a retention voltage. Other embodiments are described and claimed. | 2015-03-05 |
| 20150067362 | Adaptive Integral Battery Pack and Voltage Regulator - An information handling system includes battery packs, loads, and a power management module operable to set an output voltage of a battery pack and direct power from the battery pack to one or more loads. The power management module can direct power from multiple batteries to a load simultaneously. A battery pack includes a converter circuit to convert the voltage provided by battery cells within the battery pack to a voltage set by a power management module. | 2015-03-05 |
| 20150067363 | CLOCK GENERATOR CIRCUIT WITH AUTOMATIC SLEEP MODE - A clock generator circuit for an integrated circuit (IC) component (e.g., a microcontroller unit) is disclosed that provides an automatic sleep mode for modules of the IC component. In some implementations, the clock generator circuit provides a simplified user interface and low power consumption by implementing one sleep mode level and allowing modules in the IC to start and stop internal clocks dynamically on demand. In active mode, the power consumption can be reduced to a minimum by turning off clocks for unused modules. | 2015-03-05 |
| 20150067364 | INFORMATION PROCESSING APPARATUS AND POWER SUPPLY MONITORING CIRCUIT - A CPU and a miscellaneous system are operated by electrical power supplied from an AC adapter or a battery. An AC adapter identifying circuit includes a voltage determining comparator that determines whether a voltage from the AC adapter is equal to or greater than a voltage threshold; a current determining comparator that determines whether a current supplied from the AC adapter is equal to or greater than a current threshold; and an electrical power saving control circuit that drops, when the supplied voltage is lower than the voltage threshold and the supplied current is equal to or greater than the current threshold, electrical power consumed by the CPU and the miscellaneous system. | 2015-03-05 |
| 20150067365 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND POWER CONTROL METHOD - There is provided an information processing apparatus including a mode control unit configured to perform control at least so as to switch a first mode that causes the information processing apparatus to be operated at a first voltage level and a second mode that causes the information processing apparatus to be operated at a second voltage level higher than the first voltage level, and an operation control unit configured to disable certain input operation performed by a user if a state satisfies a certain condition after the mode control unit switches a mode to the second mode. | 2015-03-05 |
| 20150067366 | Electronic Apparatus And Information Processing Method - An electronic apparatus includes a first processing unit for executing an operation of a first type; a second processing unit for executing an operation of a second type, with the average power consumption of the second processing unit being less than average power consumption of the first processing unit; a sharing unit connected to the first processing unit and the second processing unit and for operating cooperatively with either or both of the first processing unit and the second processing unit selectively according to predetermined condition; and a fixing unit for fixing relative position relation of the electronic apparatus with the user. | 2015-03-05 |
| 20150067367 | METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS - An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency. | 2015-03-05 |
| 20150067368 | CORE SYNCHRONIZATION MECHANISM IN A MULTI-DIE MULTI-CORE MICROPROCESSOR - A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores. | 2015-03-05 |
| 20150067369 | MULTI-CORE SYNCHRONIZATION MECHANISM - A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred. | 2015-03-05 |
| 20150067370 | POWER SAVING METHOD AND CONTROL CIRCUITRY AND POWER SUPPLY - The present disclosure provides a control circuitry used in a computing system, for enabling or disabling a standby module of a power supply. The control circuitry is electrically coupled to two nodes of the standby module, and comprises a determination circuit, a transistor, and an optical coupler. The present disclosure further provides a power saving method used in a computing system is illustrated. Whether the computing system is turned off is determined. If the computing system is turned off, a setting that whether the turned off computing system requires the standby voltage is judged. If the turned off computing system does not require the standby voltage, a standby module of a power supply is disabled. | 2015-03-05 |
| 20150067371 | COMMUNICATION DEVICE, METHOD FOR CUSTOMIZING THE SAME, AND COMPUTER-READABLE STORAGE MEDIUM FOR COMPUTER PROGRAM - A communication device is provided which includes a first controller functioning as a main controller and a second controller which responds to received data based on a proxy program independently of the first controller. The communication device includes a storage portion configured to store, every time data is received, a combination of attributes of the data and details of a response to the data made by the first controller; a generating portion configured to determine at least one pattern with which a response independently of the first controller is possible based on a plurality of the combinations stored in the storage portion to generate the proxy program based on the pattern determined; and an applying portion configured to apply the proxy program generated by the generating portion to the second controller. | 2015-03-05 |
| 20150067372 | CONTROL DEVICE FOR A VEHICLE NETWORK AND METHOD FOR OPERATING A VEHICLE NETWORK - A control device for a vehicle network, having a microprocessor and a transceiver. The control device can be switched off or switched to a sleep mode during a previously defined state or event during the operation of the motor vehicle and/or the control device can be awakened from the sleep mode during a previously defined state or event during the operation. The disclosed embodiments also relate to a method for operating a vehicle network. | 2015-03-05 |
| 20150067373 | BIOS CONTROLLED PERIPHERAL DEVICE PORT POWER - A BIOS controlled peripheral device port power device is described. The device includes a processor and at least one peripheral device port. The processor powers up a host controller in preparation for the processor to enter a sleep state. The processor also places the processor in the sleep state after the host controller is powered up. The processor also selectively powers the at least one peripheral device port by the host controller when the processor is in the sleep state according to at least one setting stored in the processor. | 2015-03-05 |
| 20150067374 | ELECTRONIC DEVICE, CONTROL METHOD OF ELECTRONIC DEVICE, AND IMAGE FORMING APPARATUS - An electronic device, a control method of the electronic device, and an image forming apparatus to cut off unnecessary power after recognizing connection/disconnection statuses of Universal Serial Bus (USB) hosts/devices connected to a USB hub are provided. The electronic device includes a USB hub connected to a USB host/device, a first switch configured to switch power supply to the USB hub for reducing power consumption, a controller configured to turn the first switch off to cut off power supply to the USB hub when no USB host/device is connected to the USB hub or only a USB host/device not requiring constant power supply is connected to the USB hub. | 2015-03-05 |
| 20150067375 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING METHOD - An information processing system includes a receiving unit that receives user operation; a setting unit that holds association information in which pieces of necessity information each indicating necessity of a shutdown process indicating a process required for stopping power supply to a corresponding device are associated with a plurality of devices, respectively; a first instruction unit that instructs a target device for which the power supply is to be stopped to perform the shutdown process when the receiving unit receives operation to stop the power supply and the target device requires the shutdown process based on the association information; and a second instruction unit that instructs a power supply control device that controls execution or stop of the power supply to the target device to stop the power supply to the target device when the shutdown process of the target device is completed. | 2015-03-05 |
| 20150067376 | POWER MANAGEMENT IN A CIRCUIT - The present disclosure is generally related to power management in a circuit on a circuit board of a processor. The circuit includes a first power connector coupled to a first power input rail. The circuit includes a second power connector and a second power input rail. The circuit includes a control module. The control module is configured to determine a power specification of the circuit board. The control module is configured to detect a power cable connected to the first control connector. The control module is configured to sense a voltage at the second power connector. The control module is configured to couple the second power input rail with the first power connector or the second power connector in response to the determined power specification of the circuit board and the sensed voltage at the second power connector. | 2015-03-05 |
| 20150067377 | Method, Devices and Systems for Dynamic Multimedia Data Flow Control for Thermal Power Budgeting - Methods and devices for managing data flows for concurrent multimedia applications executing on a device including a SoC, in response to determining that a temperature or power consumption exceeds a threshold are disclosed. A lowest priority data flow may be identified. A data flow path associated with the identified lowest priority data flow may be traced. A multimedia parameter of any hardware module along the data flow path may be reduced. When the temperature or power consumption no longer exceeds the threshold, a highest priority data flow among the multimedia applications that has had the multimedia parameter reduced may be identified. A data flow path for a data flow associated with the identified highest priority data flow may be traced. The multimedia parameter may be restored to an original value along the traced data flow path for the data flow associated with the identified highest priority data flow. | 2015-03-05 |
| 20150067378 | MEASURING APPARATUS, MEASURING METHOD, AND MEASURING SYSTEM - A measuring apparatus, includes: a switch configured to short-circuit, among a plurality of power supply lines on a print board, second power supply lines other than a first power supply line to be measured and short-circuit with a ground; and an ohmmeter configured to measure a first resistance value between the first power supply line and the ground. | 2015-03-05 |
| 20150067379 | BATTERY CONTROL DEVICE AND BATTERY CHARGE CAPACITY DIAGNOSIS METHOD - A battery control device includes: a battery; a storage circuitry configured to store a disconnection time which indicates a time at which a power supply is disconnected; and a diagnosis circuitry configured to, when the power supply is reactivated, diagnose a charge capacity of the battery at the time of reactivation based on a disconnection period obtained from the disconnection time and a time at when the power supply is reactivated, a temperature of the battery in a state during the power supply is disconnected and a deterioration degree of the battery | 2015-03-05 |
| 20150067380 | POWER CONTROL METHOD AND APPARATUS - The application provides a power control method and apparatus. The power control method includes: obtaining, by a transmit end of a link, bit error rate information of a receive end of the link; and if the bit error rate information does not meet a predetermined condition, adjusting a transmit power class value of the transmit end. According to the power control method and apparatus of the application, the transmit power class value of the transmit end of the link can be dynamically adjusted according to a change of a system or an external environment, thereby improving interference immunity of the link and ensuring stability and reliability of data transmission. | 2015-03-05 |
| 20150067381 | DISCRETE TIME COMPENSATION MECHANISMS - Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels. | 2015-03-05 |
| 20150067382 | SYNCHRONIZING DATA FROM DIFFERENT CLOCK DOMAINS - An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry. | 2015-03-05 |
| 20150067383 | Distributed Delay Locked Loop - In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal. | 2015-03-05 |
| 20150067384 | Crossing Pipelined Data between Circuitry in Different Clock Domains - An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading. | 2015-03-05 |
| 20150067385 | INFORMATION PROCESSING SYSTEM AND METHOD FOR PROCESSING FAILURE - An information processing system includes a plurality of nodes and a shared memory connected to the plurality of nodes. Each of the nodes includes a plurality of functional circuits, a control device, and a register configured to store a plurality of interrupt factors that occur in the plurality of functional circuits. And The control device in one node among the plurality of nodes receives the interrupt factor in each register of a plurality of other nodes in response to an occurrence of the interrupt factor, extracts an interrupt factor to be detected as a failure among the received interrupt factors, specifies a fail node according to an extraction result, and, after suppressing access to the shared memory by the fail node, controls to separate the fail node from the information processing system on basis of log information received from the plurality of other nodes. | 2015-03-05 |
| 20150067386 | INTEGRATION NETWORK DEVICE AND SERVICE INTEGRATION METHOD THEREOF - An integration network device and a service integration method thereof are provided. The integration network device receives a connecting request from the VDI user device. The integration network device establishes a connection between the VDI user device and the first management network device according to the connecting request. The integration network device determines that the first management network device fails the connection according to a first management information of the first management network device. The integration network device routes the VDI user device to the second management network device according to a second management information of the second management network device. | 2015-03-05 |
| 20150067387 | METHOD AND APPARATUS FOR DATA STORAGE - In response to detecting a failure on a secondary storage device, a transmission of a data write request to the primary storage device is suspended. Identifying an outstanding data write request, wherein the outstanding data write request has been performed by the primary storage device, but has not been performed by a disaster recovery (DR) storage device. Instructing the DR storage device to update data on the DR storage device according to the identified outstanding data write request. Setting the primary storage device to enable the primary storage device to forward a subsequently received data write request to the DR storage device. And restoring the transmission of the data write requests to the primary storage device. | 2015-03-05 |
| 20150067388 | SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE DEVICE - A serial advanced technology attachment dual in-line memory module (SATA DIMM) device includes a circuit board. A storage chip is arranged on the circuit board and stores a first firmware. A memory is arranged on the circuit board and stores a second firmware. A control chip is arranged on the circuit board and connected to the memory, to read the second firmware from the memory and load the second firmware in the storage chip when the first firmware stored in the storage chip is damaged. The control chip is also connected to the storage chip, to control the storage chip to read or to write data. | 2015-03-05 |
| 20150067389 | Programmable Substitutions for Microcode - The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered. | 2015-03-05 |
| 20150067390 | LIVE SNAPSHOT OF A VIRTUAL MACHINE - The subject matter of this specification can be implemented in, among other things, a method including receiving a request to create a live snapshot of a state of a virtual machine at a reference point-in-time. The virtual machine can have a memory and an original disk file. The method further includes creating, at the reference point-in-time, an overlay disk file to copy data from the original disk file. Data modifications after the reference point-in-time are performed in the original disk file but not in the overlay disk file. The method also includes creating a memory snapshot at the reference point-in-time. The method includes providing the live snapshot corresponding to the reference point-in-time. The live snapshot includes the overlay disk file and the memory snapshot. | 2015-03-05 |
| 20150067391 | CORRECTING OPERATIONAL STATE AND INCORPORATING ADDITIONAL DEBUGGING SUPPORT INTO AN ONLINE SYSTEM WITHOUT DISRUPTION - Techniques are provided for correcting the operational state of a multi-process system without disrupting any running processes. A library providing error correction and logging functionality is statically linked to modules in the system. A script in the library loads a package file having a patch for returning an error state to a normal state. The script issues commands to invoke functions in the patch. Once the error state has returned to a normal state, the script issues commands to remove the package file from the system. | 2015-03-05 |
| 20150067392 | CLOCK DATA RECOVERY DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - A clock data recovery device includes a clock recovery device for separating a recovery clock signal and a data signal from an input signal and generating a clock fail signal in response to noise of the input signal; a clock generator for receiving a control voltage to generate one or more delay clock signals, delaying the recovery clock signal to generate the delay clock signals in a first mode, delaying the generated delay clock signal to generate the delay clock signal in a second mode, and switching the first mode to the second mode in response to the clock fail signal; and a phase frequency detector for comparing at least one of the delay clock signals with the recovery clock signal to generate a voltage adjusting signal; and a control voltage generator for receiving the voltage adjusting signal to generate the control voltage. | 2015-03-05 |
| 20150067393 | METHOD AND APPARATUS TO REMOTELY TAKE A SNAPSHOT OF A COMPLETE VIRTUAL MACHINE FROM A SOFTWARE DEFINED CLOUD WITH BACKUP AND RESTORE CAPACITY - Method and Apparatus for rapid scalable unified infrastructure system management platform are disclosed by discovery of compute nodes, network components across data centers, both public and private for a user; assessment of type, capability, VLAN, security, virtualization configuration of the discovered unified infrastructure nodes and components; configuration of nodes and components covering add, delete, modify, scale; and rapid roll out of nodes and components across data centers both public and private. | 2015-03-05 |
| 20150067394 | METHOD AND APPARATUS FOR PROCESSING VIRTUAL MACHINE INSTANCES IN REAL TIME EVENT STREAM FOR ROOT CAUSE ANALYSIS AND DYNAMICALLY SUGGESTING INSTANCE REMEDY - Method and Apparatus for rapid scalable unified infrastructure system management platform are disclosed by discovery of compute nodes, network components across data centers, both public and private for a user; assessment of type, capability, VLAN, security, virtualization configuration of the discovered unified infrastructure nodes and components; configuration of nodes and components covering add, delete, modify, scale; and rapid roll out of nodes and components across data centers both public and private. | 2015-03-05 |
| 20150067395 | METHODS AND STRUCTURE FOR HARDWARE SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA) ERROR RECOVERY IN A SERIAL ATTACHED SCSI (SAS) EXPANDER - Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from an initiator device to a target device and to process errors in control circuits of the expander without intervention from the general purpose programmable processor of the expander. A PHY of an expander is associated with control circuits that comprise buffering of commands to be forwarded to an end device directly coupled to the PHY. The control circuits locally process errors detected from the end device. The control circuits comprise a SATA host circuit adapted to communicate with a SATA end device to detect and clear error conditions and a SATA target circuit to communicate with one or more STP initiator devices to report and clear error conditions reported by the end device. The structures and methods may also service SAS connections (in addition to STP connections). | 2015-03-05 |
| 20150067396 | COMMUNICATION DEVICE AND COMMUNICATION METHOD - A communication device includes: a first communication section, a second communication section, a storage section, a determination section, and a control section. The first communication section communicates with a storage device based on predefined interface communication standards to perform data transfer. The second communication section communicates with an external device in a method other than the interface communication standards to perform data transmission. The storage section stores the selected error code that is previously defined to cause a bit error by noise. The determination section determines whether or not an error code indicated by the error information agrees with the selected error code. The control section, upon determination by the determination section that the error codes agrees with each other, gives the first communication section and the second communication section instructions for cancelling the data transfer and performing data re-transfer. | 2015-03-05 |
| 20150067397 | METHOD AND APPARATUS FOR RESTORING FAILED USER WORKFLOW INSTANCES FROM DATA STORE - Method and Apparatus for rapid scalable unified infrastructure system management platform are disclosed by discovery of compute nodes, network components across data centers, both public and private for a user; assessment of type, capability, VLAN, security, virtualization configuration of the discovered unified infrastructure nodes and components; configuration of nodes and components covering add, delete, modify, scale; and rapid roll out of nodes and components across data centers both public and private. | 2015-03-05 |
| 20150067398 | METHOD, APPARATUS, AND RECORDING MEDIUM FOR INTERWORKING WITH EXTERNAL TERMINAL - A method for interworking with an external terminal is provided. The method includes, at a mobile terminal, displaying a screen for selecting whether or not to reset the mobile terminal, if a connection request is received from a second terminal while the mobile terminal interworks with a first terminal, at the mobile terminal, generating first backup data including information about one or more execution files corresponding to one or more functions linked to the first terminal, if resetting of the mobile terminal has been selected on the screen, and at the mobile terminal, transmitting the first backup data to the first terminal, and performing resetting. | 2015-03-05 |
| 20150067399 | ANALYSIS, RECOVERY AND REPAIR OF DEVICES ATTACHED TO REMOTE COMPUTING SYSTEMS - A method and system to perform analysis, recovery or repair of devices attached to a remote computing system from a local computing system is presented. The remote computing system is initialized with an independent operating system that executes computer code, and interfaced, over a digital network, with a local computing system. This converts the remote computing system into an analysis, recovery and repair tool for the remote delivery of advanced technical services such as: network analysis, data recovery, digital forensics, software installation and operating system repair, data cloning, and malware remediation. | 2015-03-05 |
| 20150067400 | GENERATING A FAULT TREE - A method, computer program product, and system that discards unneeded elements when generating a fault tree of an object to be analyzed. Configuration information identifies a plurality of functional blocks comprised by the object and a plurality of signal lines that connect the functional blocks in logical relationships. Exclusion target information identifies a signal line that may be excluded from the plurality of signal lines without loss of information or a functional block that may be excluded from the plurality of functional blocks without loss of information. Exclusion of a block or signal line may be determined by detecting a redundant functional block or by detecting a circular signal path traversed by two or more signal lines. The generated fault tree omits the excluded block or signal line and identifies the existence of a redundant block or of a circular signal path. | 2015-03-05 |
| 20150067401 | COMPUTER RECOVERY METHOD, COMPUTER SYSTEM, AND STORAGE MEDIUM - A computer recovery method for a computer system, the computer system having: a management computer having a processor and a memory; and a computer having a processor, a memory, and a monitoring part for notifying, when an abnormality occurs, the management computer of the abnormality, the management computer being configured to instruct recovery from the abnormality, the computer recovery method having: a first step of obtaining, by the management computer, hardware components and software components of the computer as configuration information; a second step of receiving, by the management computer, notification of an abnormality from the monitoring part of the computer; and a third step of generating, by the management computer, after the notification is received, component string information for identifying a component where the abnormality has occurred from the configuration information. | 2015-03-05 |
| 20150067402 | PROVIDING A REMOTE DIAGNOSIS FOR AN INFORMATION APPLIANCE VIA A SECURE CONNECTION - A processor-implemented method provides a remote diagnosis for an information appliance via a secure connection. A command is received from a console, and an examination is performed to determine whether or not the command is permitted to be issued. In response to a remote diagnostic module being initiated, a determination is made as to whether a secure connection to a remote information appliance has been created. In response to determining that the secure connection to the remote information appliance has been created, the command is transmitted to the remote information appliance via the secure connection. | 2015-03-05 |
| 20150067403 | METHOD AND APPARATUS FOR A HIGHLY AVAILABLE, SCALABLE, AND ROBUST ORCHESTRATION ENGINE TO MANAGE USER PROCESSES - Method and Apparatus for rapid scalable unified infrastructure system management platform are disclosed by discovery of compute nodes, network components across data centers, both public and private for a user; assessment of type, capability, VLAN, security, virtualization configuration of the discovered unified infrastructure nodes and components; configuration of nodes and components covering add, delete, modify, scale; and rapid roll out of nodes and components across data centers both public and private. | 2015-03-05 |
| 20150067404 | FLEXIBLE AND MODULAR LOAD TESTING AND MONITORING OF WORKLOADS - Various embodiments monitor a distributed software system. In one embodiment, at least one monitoring policy associated with a distributed software system is selected. A policy type associated with the monitoring policy is identified. An installer is selected based on the policy type associated with the monitoring policy. Monitoring software is installed in a computing environment utilizing the installer. The monitoring software is configured to monitor the distributed software system based on the monitoring policy. | 2015-03-05 |
| 20150067405 | SYSTEM STABILITY PREDICTION USING PROLONGED BURST DETECTION OF TIME SERIES DATA - Embodiments of the invention relate to a system comprising a processor, a burst detection module executing on the processor, and a resource monitor. The burst detection module is configured to receive a set of resource usages samples measuring an availability of a resource, calculate an absolute moving average (AMA) of the set of resource usage samples, calculate a mean dispersion of the set of resource usage samples, and determine that the set of resource usage samples comprises an aberrant sample by comparing the AMA to the mean dispersion. The resource monitor is configured to execute a recovery procedure in response to the determination that the set of resource usage samples comprise the aberrant sample. | 2015-03-05 |
| 20150067406 | TESTING SYSTEM AND METHOD FOR FAN MODULE - Testing system includes a testing device and a testing circuit board connected to the testing device. The testing device includes a storing module, a transmit-receive module, and an analyzing module. A number of specification parameters of a fan module is stored in the storing module. The transmit-receive module sends a testing code to the testing circuit board. The testing circuit board responds to the testing code to detect a number of running information of the fan module, and sends the running information to the transmit-receive module. The analyzing module receives the number of running information from the transmit-receive module and compares the number of running information with the number of specification parameters for determining whether the fan is qualified. The disclosure further provides a testing method. | 2015-03-05 |
| 20150067407 | ELECTRONIC DEVICE AND METHOD FOR TESTING STORAGE SYSTEM - In a method for testing a storage system, each disk of a storage system is numbered, and a disk of a number is selected as a root node of a binary tree. A probability that the nodes of each level of the binary tree is completely added into the binary tree is computed according to a predefined algorithm, and the nodes of each level of the binary tree are added into the binary tree according to the computed probability. And each disk is tested when the disk is added into the binary tree as the node of the binary tree. | 2015-03-05 |
| 20150067408 | EVENT COMMUNICATION APPARATUS FOR PROTECTION RELAY - Disclosed is an event communication apparatus for a protection relay, which effectively simplifies an event determination operation by a main processing module and a communication module, thereby enhancing updating. The event communication apparatus for the protection relay includes a shared memory configured to store and provide data needed to share, a main processing module configured to, whenever an event occurs, update previous event data to a status information of the event and a status occurrence time information as new event data, and write the updated event data into the shared memory, and a communication module configured to periodically read status information from the shared memory, compare the read status information with pre-stored previous status information to determine whether there is a status change, determine occurrence of a new event when there is the status change, and transmit corresponding event data to an supervisory monitor immediately when the new event occurs. | 2015-03-05 |
| 20150067409 | DETECTION OF CODE INJECTION ATTACKS - A method for detecting foreign code injected into a computer system including a processor and memory, the processor being configured to execute instructions stored in the memory, includes: detecting, on the computer system, an illegal instruction error; recording the illegal instruction error; determining whether a threshold condition is met; and generating an alert if the threshold condition is met. | 2015-03-05 |
| 20150067410 | HARDWARE FAILURE PREDICTION SYSTEM - The present subject matter discloses a method for predicting failure of hardware components. The method comprises obtaining a syslog file stored in a Hadoop Distributed File System (HDFS), where the syslog file includes at least one or more syslog messages. Further, the method comprises categorizing each of the one or more syslog messages into one or more groups based on a hardware component generating the syslog message. Further, a current dataset comprising one or more records based on the categorization is generated, where each of the one or more records include a syslog message from amongst the one or more syslog messages. The method further comprises analysing the current dataset for identifying at least one error pattern of syslog messages, based on a plurality of error patterns of reference syslog messages, for predicting failure of the hardware components. | 2015-03-05 |
| 20150067411 | PROACTIVE FAILURE HANDLING IN NETWORK NODES - Embodiments are directed to predicting the health of a computer node using health report data and to proactively handling failures in computer network nodes. In an embodiment, a computer system monitors various health indicators for multiple nodes in a computer network. The computer system accesses stored health indicators that provide a health history for the computer network nodes. The computer system then generates a health status based on the monitored health factors and the health history. The generated health status indicates the likelihood that the node will be healthy within a specified future time period. The computer system then leverages the generated health status to handle current or predicted failures. The computer system also presents the generated health status to a user or other entity. | 2015-03-05 |
| 20150067412 | Providing Error Handling Support To Legacy Devices - In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed. | 2015-03-05 |
| 20150067413 | METHODS FOR TRANSITIONING CONTROL BETWEEN TWO CONTROLLERS OF A STORAGE SYSTEM - Described herein are methods for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system. | 2015-03-05 |
| 20150067414 | METHODS FOR TRANSITIONING CONTROL BETWEEN TWO CONTROLLERS OF A STORAGE SYSTEM - Described herein are techniques for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system. | 2015-03-05 |
| 20150067415 | MEMORY SYSTEM AND CONSTRUCTING METHOD OF LOGICAL BLOCK - According to one embodiment, a memory system includes a bit-error-rate manager configured to manage information associated with a bit error rate for each physical block, a logical-block constructing unit configured to construct a logical block based on the information associated with the bit error rate, and a block manager configured to manage the correspondence between the logical block constructed by the logical-block constructing unit and the physical blocks. The logical block is a collection of a plurality of physical blocks. | 2015-03-05 |
| 20150067416 | NRZ SIGNAL AMPLIFYING DEVICE AND METHOD, AND ERROR RATE MEASUREMENT DEVICE AND METHOD - To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying device | 2015-03-05 |
| 20150067417 | METHOD FOR TESTING DATA PACKET SIGNAL TRANSCEIVERS WITH MULTIPLE RADIO ACCESS TECHNOLOGIES USING INTERLEAVED DEVICE SETUP AND TESTING - A method of using tester data packet signals and control instructions for testing a radio frequency (RF) data packet signal transceiver device under test (DUT) capable of communicating using multiple radio access technologies (RATs) having one or more mutually distinct signal characteristics. During mutually alternating time intervals, selected ones of which are substantially contemporaneous, tester data packet signals and control instructions are used for concurrent testing and configuration for testing, respectively, of multiple RATs of the DUT. | 2015-03-05 |
| 20150067418 | STORAGE TESTER CAPABLE OF INDIVIDUAL CONTROL FOR A PLURALITY OF STORAGE - Disclosed is a storage tester capable of individual control for a plurality of storages, which comprises a host terminal for receiving user's control signal for storage test; a communication interface unit transmitting data among the host terminal, an embedded processor and a data engine unit; a data engine unit for generating pattern data and command data and reading the data from the storage; a sequence control module for controlling respectively a plurality of SATA/SAS/PCIe interface units; and SATA/SAS/PCIe interface unit for connecting to the storage through one among SATA, SAS, PCIe interface according to the signal for interface selection generated from the embedded processor and controlling a plurality of storages according to control of the sequence control module by the embedded processor in order to test respectively connected storage. | 2015-03-05 |
| 20150067419 | Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors. | 2015-03-05 |
| 20150067420 | MEMORY MODULE ERRORS - Techniques for handling errors on memory modules are provided. An uncorrected error from a pair of memory modules may be received. Memory modules other than the pair of memory modules producing the error may be de-configured. Diagnostic tests may be run on the faded pair of memory modules. The memory module of the pair of memory modules that caused the uncorrected error may be determined. | 2015-03-05 |
| 20150067421 | DISPERSED STORAGE WITH VARIABLE SLICE LENGTH AND METHODS FOR USE THEREWITH - A dispersed storage processing unit selects a slice length for a data segment to be stored in a dispersed storage network (DSN). The data segment is encoded using a dispersed storage error coding function to produce a set of data slices in accordance with the slice length. A storage file is selected based on the slice length. A storage file identifier (ID) is generated that indicates the storage file. A set of DSN addresses are generated corresponding to the set of data slices, wherein the set of DSN addresses each include the storage file ID and a corresponding one of a plurality of offset identifiers (IDs). The set of data slices are written in accordance with the set of DSN addresses. A directory is updated to associate the set of DSN addresses with an identifier of the data segment. | 2015-03-05 |
| 20150067422 | FUSION OF MULTIPLE MODALITIES FOR DETERMINING A UNIQUE MICROELECTRONIC DEVICE SIGNATURE - An example of the invention includes a process and apparatus combining test modalities that collates data, processes it into a standard format, evaluates trends and interrogates via an expert system can increase efficiency and yield greater confidence in testing of parts in a variety of supply chain segments. An exemplary process and test system can collect a variety of test data as pre-processed raw data from a plurality of modalities as an evaluation database. The evaluation database post-processes said raw data via data analysis output to an expert system and decision engine as exemplary rule sets. The decision engine generating a probability that a microelectronic device is unauthorized, does not meet specification(s), is defective or counterfeit. | 2015-03-05 |
| 20150067423 | A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS) TESTING AND AN ALGORITHM TO IDENTIFY BEST Q-GATING CANDIDATES - A method for creating an architecture to support Q-gating for launch-off-shift (LOS) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops. The method may further include applying a global scan enable signal directly to each of a plurality of Q-gates corresponding to each of the plurality of flip-flops, wherein the global scan enable signal traverses a signal path that bypasses combinational logic located between any two flip-flops of the plurality of flip-flops. | 2015-03-05 |
| 20150067424 | PROCESSOR TAP SUPPORT FOR REMOTE SERVICES - An apparatus can include a circuit board; a processor chip mounted to the circuit board that includes a Test Access Port (TAP); a controller mounted to the circuit board that includes a port operatively coupled to the Test Access Port (TAP) of the processor chip; and a network interface operatively coupled to the controller. Various other apparatuses, systems, methods, etc., are also disclosed. | 2015-03-05 |
| 20150067425 | INTEGRATED CIRCUIT (IC) FOR RECONSTRUCTING VALUES OF FLIP-FLOPS CONNECTED IN A SCAN-CHAIN BY USING A JOINT TEST ACTION GROUP (JTAG) INTERFACE, A METHOD OF OPERATING THE IC, AND DEVICES HAVING THE IC - An integrated circuit (IC) includes an on-chip logic that includes an input terminal, an output terminal, and a plurality of synchronizing circuits connected in a scan-chain; a test data in (TDI) line; a test data out (TDO) line connected to the output terminal; and a test access port (TAP) controller that transmits, to the input terminal, data output from one of a plurality of data sources, the data sources including the TDI line and the output terminal, in response to one or more selection signals. | 2015-03-05 |
| 20150067426 | PACKET BASED INTEGRATED CIRCUIT TESTING - Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system. | 2015-03-05 |
| 20150067427 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 2015-03-05 |
| 20150067428 | SYSTEM-ON-CHIP, METHOD OF MANUFACTURE THEREOF AND METHOD OF COMMUNICATING DIAGNOSTIC DATA - A system-on-chip comprises an internal module having diagnostic functionality, and a physical communications port coupled to a first data path and arranged to support, when in use, a datagram-based communications interface for communicating with an external data communications unit. Debug logic circuitry is operably coupled to a debug interface and the internal module, the debug interface being arranged to support communication of debug data relating to the internal module. The system-on-chip also comprises configurable hardware logic circuitry configured as datagram processing logic and is arranged to support use of a datagram to communicate with the debug logic. The datagram processing logic is operably coupled to the first data path and a second data path, the second data path being operably coupled to the debug interface. | 2015-03-05 |
| 20150067429 | WAFER-LEVEL GATE STRESS TESTING - A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test. | 2015-03-05 |
| 20150067430 | SEMICONDUCTOR INTEGTRATED CIRCUIT INCLUDING TEST PADS - A The semiconductor integrated circuit includes a test input/output port including test pads; an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data and temporary storage data in response to external signals through the test input/output port; and an error detection block configured to determine whether the internal data and the temporary storage data are the same, and output a result through one test pad of the port. The internal input interface includes a data input/output block which generates the internal data and the data input/output block includes a temporary storage part which stores the internal data as the temporary storage data, a data output part which receives the temporary storage data, and a data input part which receives an output of the data output part and outputs it as the internal data. | 2015-03-05 |
| 20150067431 | DATA RECOVERY OF DATA SYMBOLS RECEIVED IN ERROR - In one or more embodiments, a data processing apparatus is configured to receive data symbols transmitted from one or more endpoint devices. Each of the data symbols is transmitted in a respective temporal position assigned for communication by one of the plurality of endpoints. The data processing apparatus is configured to recover data from two or more transmission(s)/retransmission(s) (of the same data) that are received in error and have different temporal positions. The corresponding data symbols in error are phase-aligned per a common reference point and energy is accumulated therefrom. The data processing apparatus discerns correct data values from the accumulated energy. | 2015-03-05 |
| 20150067432 | SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME - A semiconductor device include: a first reception inductor pad through configured to receive data from a first transmission inductor pad; a second reception inductor pad configured to receive a clock from a second transmission inductor pad; and a data recovery unit configured to generate an output data. | 2015-03-05 |
| 20150067433 | Reducing Latency OF Unified Memory Transactions - In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed. | 2015-03-05 |
| 20150067434 | RELAY DEVICE AND RELAY METHOD - A computer receives, using a first communication method, first data transmitted from a first information processing device. The computer transmits, using a second communication method different from the first communication method, the first data to a second information processing device different from the first information processing device. The computer receives, using the second communication method, a reception acknowledgement for the first data from the second information processing device. The computer transmits, using the first communication method, the reception acknowledgement to the first information processing device. The computer detects one of a first error and a second error. The first error is an error in communication between the computer and the first information processing device. The second error is an error in communication between the computer and the second information processing device. The computer retransmits, based on the detected error, one of reception acknowledgements transmitted to the first information processing device. | 2015-03-05 |
| 20150067435 | RESOURCE MAPPING TO HANDLE BURSTY INTERFERENCE - Resource mapping and coding schemes to handle bursty interference are disclosed that provide for spreading the modulated symbols for one or more transmission code words over more symbols in the time-frequency transmission stream. Certain aspects allow for the modulated symbols to be based on bits from more than one code word. Other aspects also provide for re-mapping code word transmission sequences for re-transmissions based on the number of re-transmissions requested by the receiver. Additional aspects provide for layered coding that uses a lower fixed-size constellation to encode/decode transmissions in a layered manner in order to achieve a larger-size constellation encoding. The layered encoding process allows the transmitter and receiver to use different coding rates for each coding layer. The layered encoding process also allows interference from neighboring cells to be canceled without knowledge of the actual constellation used to code the interfering neighboring signal. | 2015-03-05 |
| 20150067436 | Nonvolatile Memory System Compression - Data to be stored in a nonvolatile memory array may be compressed in a manner that provides variable sized portions of compressed data, which is then padded to a predetermined uniform size and then stripped of padding. The encoded compressed data is sent to the memory array where it is stored in a uniform sized area that is exclusive to the encoded compressed data. | 2015-03-05 |
| 20150067437 | APPARATUS, METHOD AND SYSTEM FOR REPORTING DYNAMIC RANDOM ACCESS MEMORY ERROR INFORMATION - Techniques and mechanisms for providing state information describing one or more data errors detected locally at a memory device. In an embodiment, the memory device includes a memory core and error detection circuit logic configured to detect for errors of data stored by the memory core. A die of the memory device includes both the memory core and the error detection circuitry. In another embodiment, state information is stored in a mode register of the memory device in response to the error detection logic detecting an occurrence of a data error. The state information is available for access by a memory controller or other agent which is external to the memory device. | 2015-03-05 |
| 20150067438 | MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller that controls non-volatile memory including a data area and a parity area in which parity for data of a fixed length to be stored in the data area is stored is provided, the memory controller including a coding unit configured to generate parity for each of two or more partial data, each of which has a length less than the fixed length, and the memory controller writing one of the parity generated by the coding unit onto the parity area as first parity, writing the partial data and second parity that is the parity, other than the first parity, generated by the coding unit, onto the data area as the data of the fixed length, and writing the second parity onto a position subsequent to the partial data corresponding to the second parity. | 2015-03-05 |
| 20150067439 | MEMORY CONTROLLER - According to one embodiment, a memory controller according to the embodiments includes an encoder that sequentially calculates parity based on data; a parity buffer that stores completed parity and intermediate parity based on data less than a predetermined size; a write processing unit that writes data and completed parity on a non-volatile memory; a decoder; and a controller that performs a decoding process based on the data read from the non-volatile memory and the intermediate parity in the parity buffer, when receiving a read request to inputted data in a stage in which the a number of inputted data to the encoder is less than the predetermined size. | 2015-03-05 |
| 20150067440 | DECODER FOR LOW-DENSITY PARITY-CHECK CODES - Methods and apparatus for decoding LDPC codes are described. An LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P | 2015-03-05 |
| 20150067441 | COMPUTING DEVICE STORING LOOK-UP TABLES FOR COMPUTATION OF A FUNCTION - A computing device is provide, configured to compute a function of one or more inputs, the device comprising a storage device storing one or more look-up tables used in the computation of said function, the look-up tables mapping input values to output values, the look-up table being constructed with respect to the first error correcting code, a second error correcting code, a first error threshold and a second error threshold, such that any two input values ( | 2015-03-05 |
| 20150067442 | INFORMATION PROCESSING APPARATUS AND DATA REPAIRING METHOD - A processor executes a procedure including performing a repair process including first detecting whether there is any abnormality in data read out from a first storage, repairing abnormal data that is the data in which abnormality is detected as a result of the first detection, and storing the repaired data in a second storage area, second detecting when an address of data changed in the repair process and an address of a read-out source of the abnormal data in the first storage area match, whether there is any abnormality in data read out from an area indicated by the address of data changed in the repair process and the address of the read-out source of the abnormal data in the first storage area, repairing and storing, in the second storage area, the data in which abnormality is found as a result of the second detection. | 2015-03-05 |
| 20150067443 | Method and Device for Recovering Erroneous Data - A method for recovering erroneous data is disclosed, the method includes: when data in a storage block that is included in a solid state disk (SSD) is read, performing a first error check on data on a certain page of the storage block to acquire erroneous data on the page; if a first number of pieces of the erroneous data on the page is smaller than or equal to a preset first threshold, performing an error checking and correction (ECC) recovery on the data on the page; and if the first number is greater than the preset first threshold, acquiring data from spare space according to a storage position of the erroneous data on the page and a fixed entry corresponding to the storage block, and replacing the erroneous data on the page with the acquired data, where the fixed entry includes a storage position of each data stored in the spare space. | 2015-03-05 |
| 20150067444 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device according to the present embodiment comprises a memory cell array including a plurality of memory cells. An output part is configured to output data based on a strobe signal. An error correction part is configured to correct an error in first data read from the memory cell array. The output part fixes level of the strobe signal when outputting the first data, if the number of error bits of the first data exceeds a first number, he error correction part being capable of correcting error of the first number in the first data. | 2015-03-05 |
| 20150067445 | ADJUSTING A DISPERSAL PARAMETER OF DISPERSEDLY STORED DATA - A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust redundancy of the dispersed storage error coding function based on performance of the DSN. When the redundancy of the dispersed storage error coding function is to be adjusted, changing a ratio between the pillar width parameter and the decode threshold parameter and adjusting storage of one or more sets of the plurality of sets of encoded data slices based on the changing of the ratio. | 2015-03-05 |
| 20150067446 | DECODING METHOD, MEMORY STORAGE DEVICE AND REWRITABLE NON-VOLATILE MEMORY MODULE - A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased. | 2015-03-05 |
| 20150067447 | METHOD, APPARATUS AND DEVICE FOR DATA PROCESSING - An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information. | 2015-03-05 |
| 20150067448 | METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE - In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word. | 2015-03-05 |
| 20150067449 | FLASH SUBSYSTEM ORGANIZED INTO PAIRS OF UPPER AND LOWER PAGE LOCATIONS - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 2015-03-05 |
| 20150067450 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 2015-03-05 |
| 20150067451 | System and Method for Optimizing Luby Transform (Lt) Codes To Facilitate Data Transmission Over Communication Network - A system(s), method(s) and computer program product to optimize Luby Transform codes to facilitate a transmission of data over a communication network are disclosed. Demands from various sinks are received and a demand vector is calculated. Various sources are employed with LT codes to encode the data. A Generalized LT code (GLT) is generated for an objective function determined for a given demand vector irrespective of the LT codes employed at the sources. Morphing rules are designed by optimizing a degree distribution of the data and mapping LT codes to the generalized LT codes. The GLT is optimized by using a linear transformation to obtain optimal morphing rules. The LT codes are retargeted by re-encoding an LT encoded data to further obtain an LT re-encoded data. The LT re-encoded data is then transmitted by a relay device to plurality of sinks. | 2015-03-05 |
| 20150067452 | INFORMATION PROCESSING APPARATUS AND METHOD, AND, PROGRAM - The present technique relates to an information processing apparatus and a method, and a program, capable of reducing a delay time. An information processing apparatus according to the present technique is an information processing apparatus including an estimation unit configured to estimate, on the basis of a transmission buffer waiting time which is a time it takes to accumulate encoded data obtained by encoding image data when encoding the image data which are to be transmitted, a reception buffer waiting time which is a time it takes to accumulate the encoded data before the encoded data are decoded at a transmission destination of the encoded data, and a setting unit configured to set a block length which is a processing unit of error correction processing in such a manner that an error correction reception delay time which is a delay time in the error correction processing performed at the transmission destination of the encoded data does not become more than the reception buffer waiting time estimated by the estimation unit. The present technique can be applied to, for example, an information processing apparatus. | 2015-03-05 |
| 20150067453 | MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G | 2015-03-05 |
| 20150067454 | METHOD OF TRANSMITTING A DIGITAL SIGNAL FOR A SEMI-ORTHOGONAL MS-MARC SYSTEM, AND A CORRESPONDING PROGRAM PRODUCT AND RELAY DEVICE - A method for semi-orthogonal transmission of a signal intended for a system with N sources, M relays and a single receiver whereby the simultaneous transmission on a same spectral resource by the relays is successive and not simultaneous to a simultaneous transmission on a same spectral resource by the sources. The includes, by relay: joint iterative detection/decoding of messages transmitted respectively by the sources to obtain decoded messages, detecting errors on the decoded messages, interleaving the detected messages without errors followed by algebraic network coding consisting of a linear combination in a finite group of an order strictly higher than two of the interleaved messages to obtain a coded message, the linear combinations being independent, two by two, between the relays of the system, and formatting including channel coding to generate a signal representative of the network coded message. | 2015-03-05 |
| 20150067455 | COMMUNICATION DEVICE AND COMMUNICATION METHOD - A first communication device calculates a plurality of data error codes for detecting an error in a plurality of data fields by using the plurality of data fields. The first communication device generates a packet comprising the plurality of data fields and the plurality of data error codes, and then transmits the packet which is generated to a second communication device. | 2015-03-05 |
| 20150067456 | IMAGE DISPLAY APPARATUS, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - Provided is an image display apparatus that displays a page image including a plurality of objects on a screen, determines an amount of movement of the end of the object to be displayed from the end of the screen by detecting a user operation on a touch panel, and sets the end position of the object based on the determined amount of movement when the object to be displayed is larger than the screen. | 2015-03-05 |
