| 10th week of 2015 patent applcation highlights part 59 |
| Patent application number | Title | Published |
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| 20150064849 | Lead Frame Strips with Electrical Isolation of Die Paddles - A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead frame, leads directly connected to the periphery of the unit lead frame and projecting toward the die paddle, and an opening in the periphery adjacent the tie bar. The openings in the periphery of the unit lead frames are spanned with an electrically insulating material that connects the tie bar of each unit lead frame to the periphery of the unit lead frame. The direct connections between the tie bars and the periphery of the unit lead frames are severed prior to subsequent processing, so that the tie bars remain connected to the periphery of the unit lead frames by the electrically insulating material and the die paddles are electrically disconnected from the periphery of the unit lead frames. | 2015-03-05 |
| 20150064850 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. First, an interposer is disposed on a carrier. The carrier has a base body and a bonding layer bonded to the base body. The interposer has opposite first and second sides and the first side has a plurality of conductive elements. The interposer is disposed on the carrier with the first side bonded to the bonding layer and the conductive elements embedded in the bonding layer. Then, at least a semiconductor element is disposed on the second side of the interposer. As such, the semiconductor element and the interposer form a semiconductor structure. Since the conductive elements are embedded in the bonding layer instead of the base body, the present invention eliminates the need to form concave portions in the base body for receiving the conductive elements. Therefore, the method of the present invention is applicable to interposers of different specifications. | 2015-03-05 |
| 20150064851 | PRE-APPLIED UNDERFILL - Underfill structures useful as pre-applied underfill materials comprise a polymer layer having a first polymer region and a second polymer region, wherein the second polymer region comprises inorganic filler. Electronic assemblies comprising a chip or die and a substrate are formed using such multi-layer structured pre-applied underfill. | 2015-03-05 |
| 20150064852 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a reverse blocking MOS semiconductor device, a gettering polysilicon layer is formed on a rear surface of an FZ silicon substrate. Then, a p | 2015-03-05 |
| 20150064853 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 2015-03-05 |
| 20150064854 | SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME - A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures. A method to fabricate the structure is also disclosed. | 2015-03-05 |
| 20150064855 | FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION - An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins. | 2015-03-05 |
| 20150064856 | SEMICONDUCTOR STRUCTURE WITH DEEP TRENCH THERMAL CONDUCTION - Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches. | 2015-03-05 |
| 20150064857 | MASK FOR EXPOSURE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING DISPLAY PANEL USING THE MASK - A mask for etching a target layer includes a mask substrate. A phase inversion layer is disposed to correspond to a non-etched area of a pattern target layer. The phase inversion layer is configured to generate inverted light by inverting a phase of incident light and to transmit the inverted light to the non-etched area of a pattern target layer. An inversion offset part is disposed in a center part of the phase inversion layer. The inversion offset part is configured to generate offset light causing destructive interference with the inverted light in the non-etched area and to provide the offset light to the non-etched area. | 2015-03-05 |
| 20150064858 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a substrate including a plurality of red, green, and blue sub-pixel regions, a pixel electrode in each of the plurality of the red, green, and blue sub-pixel regions on the substrate, a Distributed Bragg Reflector (DBR) layer between the substrate and the pixel electrodes, a high-refractive index layer between the substrate and the DBR layer in the blue sub-pixel region, the high-refractive index layer having a smaller area than an area of a corresponding pixel electrode in the blue sub-pixel region, an intermediate layer including an emissive layer on the pixel electrode, and an opposite electrode on the intermediate layer. | 2015-03-05 |
| 20150064859 | NONPLANAR III-N TRANSISTORS WITH COMPOSITIONALLY GRADED SEMICONDUCTOR CHANNELS - A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage. | 2015-03-05 |
| 20150064860 | METHODS OF FORMING SEMICONDUCTOR FILMS AND METHODS OF MANUFACTURING TRANSISTORS INCLUDING SEMICONDUCTOR FILMS - Provided are semiconductor films, methods of forming the same, transistors including the semiconductor films, and methods of manufacturing the transistors. Provided are a semiconductor film including zinc (Zn), nitrogen (N), oxygen (O), and fluorine (F), and a method of forming the semiconductor film. Provided are a semiconductor film including zinc, nitrogen, and fluorine, and a method of forming the semiconductor film. Sputtering, ion implantation, plasma treatment, chemical vapor deposition (CVD), or a solution process may be used in order to form the semiconductor films. The sputtering may be performed by using a zinc target and a reactive gas including fluorine. The reactive gas may include nitrogen and fluorine, or nitrogen, oxygen, and fluorine. | 2015-03-05 |
| 20150064861 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate. | 2015-03-05 |
| 20150064862 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. | 2015-03-05 |
| 20150064863 | MASKLESS DUAL SILICIDE CONTACT FORMATION - Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of the first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; converting a top portion of the second set of epitaxial source/drain regions into a metal silicide and the sacrificial epitaxial layer into a sacrificial silicide layer in a silicidation process wherein the first set of epitaxial source/drain regions underneath the sacrificial epitaxial layer is not affected by the silicidation process; removing selectively the sacrificial silicide layer; and converting a top portion of the first set of epitaxial source/drain regions into another metal silicide. | 2015-03-05 |
| 20150064864 | METHOD AND APPARATUS FOR A DIFFUSION BRIDGED CELL LIBRARY - A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge. | 2015-03-05 |
| 20150064865 | MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME - In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region. | 2015-03-05 |
| 20150064866 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench. | 2015-03-05 |
| 20150064867 | METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer. | 2015-03-05 |
| 20150064868 | Apparatus and Method for Power MOS Transistor - A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench. | 2015-03-05 |
| 20150064869 | Method of forming Fin-FET - The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer. | 2015-03-05 |
| 20150064870 | SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME - In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm. | 2015-03-05 |
| 20150064871 | Forming Source/Drain Zones with a Delectric Plug Over an Isolation Region Between Active Regions - An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry. | 2015-03-05 |
| 20150064872 | TOP CORNER ROUNDING BY IMPLANT-ENHANCED WET ETCHING - When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch. | 2015-03-05 |
| 20150064873 | Controlling ReRam Forming Voltage with Doping - An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode. | 2015-03-05 |
| 20150064874 | DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM - FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC). | 2015-03-05 |
| 20150064875 | METHOD FOR MANUFACTURING SOI WAFER - The present invention provides a method for manufacturing an SOI wafer, in which an insulator film is formed at least on all surfaces of a base wafer, and while protecting a first part of the insulator film on a back surface on the opposite side from a bonded surface of the base wafer, a bonded wafer before separating a bond wafer along a layer of the implanted ion is brought into contact with a liquid capable of dissolving the insulator film or exposed to a gas capable of dissolving the insulator film, and a second part of the insulator film interposed between the bond wafer and the base wafer is etched from an outer circumferential edge of the bonded wafer and toward the center of the bonded wafer. The method can control the terrace width and inhibit warping of the SOI wafer in a bonding process with a base wafer. | 2015-03-05 |
| 20150064876 | SEPARATING DEVICE AND SEPARATING METHOD - A separating device separates a chip mounted on a substrate through a connecting material, from the substrate. The separating device includes a heating unit that heats the substrate at a temperature less than a melting point of the connecting material. | 2015-03-05 |
| 20150064877 | METHODS FOR PROCESSING A SEMICONDUCTOR WAFER - A method for processing a semiconductor wafer in accordance with various embodiments may include: providing a semiconductor wafer including at least one chip and at least one kerf region adjacent to the at least one chip, the kerf region including at least one auxiliary structure; applying a mask layer to the semiconductor wafer; removing the at least one auxiliary structure in the at least one kerf region; removing the applied mask layer; and separating the semiconductor wafer along the at least one kerf region. | 2015-03-05 |
| 20150064878 | WAFER DICING METHOD FOR IMPROVING DIE PACKAGING QUALITY - In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads. | 2015-03-05 |
| 20150064879 | Separation of Chips on a Substrate - Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts. | 2015-03-05 |
| 20150064880 | POST ETCH TREATMENT TECHNOLOGY FOR ENHANCING PLASMA-ETCHED SILICON SURFACE STABILITY IN AMBIENT - Methods for performing post etch treatments on silicon surfaces etched using halogen chemistry are provided. The methods may be performed in-situ a chamber in which the silicon surfaces where etch, ex-situ the chamber, or in a hybrid process that combines both in-situ and ex-situ post etch treatment processes. In one embodiment the post etch treatment process includes exposing a substrate having a silicon surface etched using halogen chemistry to a gas mixture comprising C | 2015-03-05 |
| 20150064881 | METHOD FOR TREATING A GALLIUM NITRIDE LAYER COMPRISING DISLOCATIONS - A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type. | 2015-03-05 |
| 20150064882 | PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate. | 2015-03-05 |
| 20150064883 | METHOD AND SYSTEM FOR MANUFACTURING A SEMI-CONDUCTING BACKPLANE - Methods and systems to manufacture a semi-conducting backplane are described. According to one set of implementations, semi-conducting particles are positioned in a supporting material of the semi-conducting backplane utilizing perforations in the supporting material or perforations in a removable support member upon which the semi-conducting backplane is constructed. For example, semi-conducting particles are deposited in perforations on a supporting member such that a portion of the semi-conducting particles protrudes from the supporting member. Suction is applied to the semi-conducting particles to retain the semi-conducting particles in the perforations and a layer of encapsulant material is applied onto the supporting member to cover the protruding portion. The supporting member is then removed from the semi-conducting particles and the layer of encapsulant material, which together form an assembly of the semi-conducting particles and the layer of encapsulant material. The portion of the semi-conducting particles is then planarized. | 2015-03-05 |
| 20150064884 | TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION - A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures. | 2015-03-05 |
| 20150064885 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING VERTICAL CHANNELS AND SEMICONDUCTOR DEVICES FORMED USING SUCH METHODS - Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate. | 2015-03-05 |
| 20150064886 | METHODS FOR PASSIVATING A CARBONIC NANOLAYER - Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer. | 2015-03-05 |
| 20150064887 | ION IMPLANTATION APPARATUS AND ION IMPLANTATION METHOD - An ion implantation apparatus includes an implantation processing chamber, a high voltage unit, and a high-voltage power supply system. In the implantation processing chamber ions are implanted into a workpiece. The high voltage unit includes an ion source unit for generating the ions, and a beam transport unit provided between the ion source unit and the implantation processing chamber. The high-voltage power supply system applies a potential to the high voltage unit under any one of a plurality of energy settings. The high-voltage power supply system includes a plurality of current paths formed such that a beam current flowing into the workpiece is returned to the ion source unit, and each of the plurality of energy settings is associated with a corresponding one of the plurality of current paths. | 2015-03-05 |
| 20150064888 | ION IMPLANTATION APPARATUS, BEAM PARALLELIZING APPARATUS, AND ION IMPLANTATION METHOD - An ion implantation apparatus includes a beam parallelizing unit and a third power supply unit. The beam parallelizing unit includes an acceleration lens, and a deceleration lens disposed adjacent to the acceleration lens in an ion beam transportation direction. The third power supply unit operates the beam parallelizing unit under one of a plurality of energy settings. The plurality of energy settings includes a first energy setting suitable for transport of a low energy ion, and a second energy setting suitable for transport of a high energy ion beam. The third power supply unit is configured to generate a potential difference in at least the acceleration lens under the second energy setting, and generate a potential difference in at least the deceleration lens under the first energy setting. A curvature of the deceleration lens is smaller than a curvature of the acceleration lens. | 2015-03-05 |
| 20150064889 | Method for Dopant Implantation of FinFET Structures - The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers. | 2015-03-05 |
| 20150064890 | METHOD FOR PRODUCING A SEMICONDUCTOR - A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body. | 2015-03-05 |
| 20150064891 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 2015-03-05 |
| 20150064892 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure. | 2015-03-05 |
| 20150064893 | METHOD FOR FORMING TRENCH MOS STRUCTURE - A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate. | 2015-03-05 |
| 20150064894 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer. | 2015-03-05 |
| 20150064895 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device. One exemplary embodiment involves forming a protective layer over first and second electrodes of a semiconductor device; forming a compensation film on the protective layer and between the first and second electrodes; removing the compensation film from being on the protective layer; and removing the protective layer from over the first electrode and second electrodes. | 2015-03-05 |
| 20150064896 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF | 2015-03-05 |
| 20150064897 | PROCESS VARIABILITY TOLERANT HARD MASK FOR REPLACEMENT METAL GATE FINFET DEVICES - Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall. | 2015-03-05 |
| 20150064898 | FABRICATION METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A first metal layer ( | 2015-03-05 |
| 20150064899 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH-SILICON VIA (TSV) STRUCTURES - Provided is a method of fabricating a semiconductor device. In one embodiment, the method includes forming at least one unit device in a substrate and on a front side of the substrate, forming a through-silicon via (TSV) structure apart from the at least one unit device to substantially vertically penetrate the substrate, the TSV structure having a back end including a concave portion, forming an internal circuit on the front side of the substrate and a front end of the TSV structure to be electrically connected to the at least one unit device and the front end of the TSV structure, forming a front side bump on the front side of the substrate to be electrically connected to the front end of the TSV structure, forming a redistribution layer on a back side of the substrate to be electrically connected to the back end of the TSV structure, and forming a back side bump to be electrically connected to the redistribution layer. | 2015-03-05 |
| 20150064900 | THREE DIMENSIONAL SEMICONDUCTOR DEVICE INCLUDING PADS - A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers. | 2015-03-05 |
| 20150064901 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - According to one embodiment, a method for producing a semiconductor device includes forming a base film above a semiconductor substrate, forming a core above the base film, forming a side wall film on a side face of the core, and replacing at least part of the side wall film with a metal film by performing plating processing. | 2015-03-05 |
| 20150064902 | Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device includes forming a stacked structure in which 2 | 2015-03-05 |
| 20150064903 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL PLANARIZATION TO RECESS METAL - Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench. | 2015-03-05 |
| 20150064904 | STABLE METAL COMPOUNDS AS HARDMASKS AND FILLING MATERIALS, THEIR COMPOSITIONS AND METHODS OF USE - The present invention relates to novel, soluble, multi-ligand-substituted metal oxide compounds to form metal oxide films with improved stability as well as compositions made from them and methods of their use. | 2015-03-05 |
| 20150064905 | SEMICONDUCTOR PROCESS - A semiconductor process including the following steps is provided. A substrate is provided. A nitride layer is formed on the substrate, but exposing a silicon containing area. An oxidation process is performed to oxidize a surface of the silicon containing area to form an oxidized surface. The nitride layer is removed. | 2015-03-05 |
| 20150064906 | Triple Patterning NAND Flash Memory - A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers. | 2015-03-05 |
| 20150064907 | Triple Patterning NAND Flash Memory with Stepped Mandrel - A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers. | 2015-03-05 |
| 20150064908 | SUBSTRATE PROCESSING APPARATUS, METHOD FOR PROCESSING SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus, including: a first gas supply system to supply raw material gas of a film being deposited in at least a portion of the surface of the substrate, and first etching gas which removes the deposited film, from a first gas supply nozzle to the processing chamber; a second gas supply system to supply second etching gas, which removes the deposited film, from a second gas supply nozzle to the processing chamber; and a control device to control the first and second gas supply systems such that the raw material gas is supplied from the first gas supply nozzle and the second etching gas is supplied from the second gas supply nozzle while the substrate is in the processing chamber, and the first etching gas is supplied from the first gas supply nozzle while the substrate is not in the processing chamber. | 2015-03-05 |
| 20150064909 | RESIN MOLD MATERIAL COMPOSITION FOR IMPRINTING - Provided are: a resin mold material and a resin replica mold material composition for imprinting having a superior mold releasability; a resin mold and a resin replica mold resulting from containing the material composition; and a method for producing them. The resin mold material or resin replica mold material composition for imprinting contains 100 parts by weight of a mold resin or replica mold resin for imprinting and 0.1 to 10 parts by weight of a curable fluoropolymer (A). Preferably, the fluoropolymer (A) has a weight-average molecular weight of 3,000 to 20,000 and results from including as repeating units (a1) an α-position substituted acrylate having a fluoroalkyl group having 4 to 6 carbon atoms and (a2) and 5 to 120 parts by weight of a high-softening-point monomer exhibiting a glass transition point or softening point of at least 50° C. in the homopolymer state. | 2015-03-05 |
| 20150064910 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING SYSTEM AND MEMORY MEDIUM - A substrate processing method includes supplying onto a substrate a processing liquid which contains a volatile component and forms a film, vaporizing the volatile component in the processing liquid such that the processing liquid solidifies or cures on the substrate and forms a film on the substrate, and supplying onto the film formed on the substrate a removing liquid which removes the processing liquid. The processing liquid is supplied onto the substrate after dry etching or ashing is applied to the substrate. | 2015-03-05 |
| 20150064911 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND STORAGE MEDIUM - Productivity can be improved. A substrate processing method includes a processing liquid supplying process of supplying a processing liquid, which contains a volatile component and forms a film on a substrate, onto the substrate on which a pre-treatment, which requires atmosphere management or time management after the pre-treatment, is performed; and an accommodating process of accommodating, in a transfer container, the substrate on which the processing liquid is solidified or cured by volatilization of the volatile component. | 2015-03-05 |
| 20150064912 | METHODS OF FORMING INTEGRATED CIRCUITS AND MULTIPLE CRITICAL DIMENSION SELF-ALIGNED DOUBLE PATTERNING PROCESSES - Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space. | 2015-03-05 |
| 20150064913 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device. | 2015-03-05 |
| 20150064914 | METHOD OF ETCHING A BORON DOPED CARBON HARDMASK - In one embodiment, a method is proposed for etching a boron dope hardmask layer. The method includes flowing a process gas comprising at least CH | 2015-03-05 |
| 20150064915 | METHODS FOR PROVIDING SPACED LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - A method is disclosed for forming a row of mutually spaced lithography features on a substrate, such as contact electrodes for a NAND device. The method involves forming and/or using a narrow slot over the substrate defined between the edge of a hard mask layer and a side wall of a trench in a resist layer overlying the edge and the substrate. A self-assemblable block copolymer is deposited and ordered in the trench for use as a further resist for patterning the substrate along the slot. The method allows for a sub-resolution contact array to be formed using UV lithography by overlapping the trench with the hard mask edge to provide the narrow slot in which the contact electrodes may be formed. | 2015-03-05 |
| 20150064916 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate. | 2015-03-05 |
| 20150064917 | UV-Assisted Stripping of Hardened Photoresist to Create Chemical Templates for Directed Self-Assembly - A processing method is disclosed that enables an improved directed self-assembly (DSA) processing scheme by allowing the formation of improved guide strips in the DSA template that may enable the formation of sub-30 nm features on a substrate. The improved guide strips may be formed by improving the selectivity of wet chemical processing between different organic layers or films. In one embodiment, treating the organic layers with one or more wavelengths of ultraviolet light may improve selectivity. The first wavelength of UV light may be less than 200 nm and the second wavelength of UV light may be greater than 200 nm. | 2015-03-05 |
| 20150064918 | Method for Laterally Trimming a Hardmask - Techniques herein include methods for controllable lateral etching of dielectrics in polymerizing fluorocarbon plasmas. Methods can include dielectric stack etching that uses a mask trimming step as part of a silicon etching process. Using a fluorocarbon mixture for dielectric mask trimming provides several advantages, such as being straightforward to apply and providing additional flexibility to the process flow. Thus, techniques herein provide a method to correct or tune CDs on a hardmask. In general, this technique can include using a fluorine-based and a fluorocarbon-based, or fluorohydrocarbon-based, chemistry for creating a plasma, and controlling a ratio of the two chemistries. Without the hardmask trim method disclosed herein, if a hardmask CD is not on target, then a wafer is scrapped. With hard-mask trim capability in silicon etch as disclosed herein, a given CD can be re-targeted to eliminate wafer-scraps. | 2015-03-05 |
| 20150064919 | ASPECT RATIO DEPENDENT ETCH (ARDE) LAG REDUCTION PROCESS BY SELECTIVE OXIDATION WITH INERT GAS SPUTTERING - Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature. | 2015-03-05 |
| 20150064920 | System, Method and Apparatus for Generating Pressure Pulses in Small Volume Confined Process Reactor - A plasma processing system and method includes a processing chamber, and a plasma processing volume included therein. The plasma processing volume having a volume less than the processing chamber. The plasma processing volume being defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of restricting an outlet flow through the at least one outlet port to a first flow rate and capable of increasing the outlet flow through the at least one outlet port to a second flow rate, wherein the conductance control structure restricts the outlet flow rate moves between the first flow rate and the second flow rate corresponding to a selected processing state set by the controller during a plasma process. | 2015-03-05 |
| 20150064921 | LOW TEMPERATURE PLASMA ANNEAL PROCESS FOR SUBLIMATIVE ETCH PROCESSES - Methods for etching a material layer disposed on the substrate using a low temperature etching process along with a subsequent low temperature plasma annealing process are provided. In one embodiment, a method for etching a material layer disposed on a substrate includes transferring a substrate having a material layer disposed thereon into an etching processing chamber, supplying an etching gas mixture into the processing chamber, remotely generating a plasma in the etching gas mixture to etch the material layer disposed on the substrate, and plasma annealing the material layer at a substrate temperature less than 100 degrees Celsius. | 2015-03-05 |
| 20150064922 | METHOD OF SELECTIVELY REMOVING A REGION FORMED OF SILICON OXIDE AND PLASMA PROCESSING APPARATUS - Provided is a method of selectively removing a first region from a workpiece which includes the first region formed of silicon oxide and a second region formed of silicon. The method performs a plurality of sequences. Each sequence includes: forming a denatured region by generating plasma of a processing gas that contains hydrogen, nitrogen, and fluorine within a processing container that accommodates the workpiece so as to denature a portion of the first region, and removing the denatured region within the processing container. In addition, a sequence subsequent to a predetermined number of sequences after a first sequence among the plurality of sequences further includes exposing the workpiece to plasma of a reducing gas which is generated within the processing container, prior to the forming of the denatured region. | 2015-03-05 |
| 20150064923 | PLASMA PROCESSING DEVICE AND PLASMA PROCESSING METHOD - A plasma processing device includes a processing chamber defining a plasma processing space and a stage for mounting thereon a target substrate in the processing chamber. The plasma processing device further includes a gas supply mechanism for introducing a processing gas into the plasma processing space, a plasma generation mechanism for supplying electromagnetic energy into the plasma processing space, and a control unit configured to, if a command to start a plasma process for the target substrate mounted on a substrate carry-in stage is issued, perform a warm-up process for supplying the processing gas into the plasma processing space by the gas supply mechanism and supplying the electromagnetic energy by the plasma generation mechanism in a state where no target substrate is mounted on the stage. | 2015-03-05 |
| 20150064924 | METHOD FOR ETCHING ORGANIC FILM AND PLASMA ETCHING DEVICE - In a method for etching an organic film according to an embodiment, a target object that has an organic film is set in a processing chamber. Then, a processing gas containing COS gas and O | 2015-03-05 |
| 20150064925 | DEPOSIT REMOVING METHOD AND GAS PROCESSING APPARATUS - A deposit removing method includes an exposing process of heating and exposing a substrate to oxygen plasma; and a cycle process in which the substrate is exposed to an atmosphere of a mixture gas of a hydrogen fluoride gas and an alcohol gas, and a first period during which a total pressure of the mixture gas or a partial pressure of the alcohol gas is set to be a first total pressure or a first partial pressure and a second period during which the total pressure or the partial pressure is set to be a second total pressure lower than the first total pressure or a second partial pressure lower than the first partial pressure are repeated multiple cycles. A supply amount of the mixture gas from a first region including a central portion of the substrate is larger than that from a second region outside the first region. | 2015-03-05 |
| 20150064926 | PLASMA PROCESSING METHOD - A plasma processing method can etch regions having different densities at the same etching rates. When etching with surface wave plasma, both of layers contain Si and N, a processing gas includes a hydro fluorocarbon gas, a rare gas, and an oxygen gas, and a high frequency bias potential is applied to a preset location at a side of a substrate. Further, a power per unit area of the substrate, which generates the high frequency bias potential, is set to be about 0 W/m | 2015-03-05 |
| 20150064927 | SURFACE PLANARIZATION METHOD OF THIN FILM AND PREPARING METHOD OF ARRAY SUBSTRATE - A surface planarization method of thin film and a preparing method of an array substrate relate to a display field, and can solve the technical problem that the conventional dry etching severely damages the surface flatness of other film layers below the one being etched, thereby improving the display properties of the LCD. The preparing method of the array substrate comprises patterning a non-metallic layer ( | 2015-03-05 |
| 20150064928 | PHOTORESIST REMOVAL - Among other things, one or more systems and techniques for removing a photoresist from a semiconductor wafer are provided. The photoresist is formed over the semiconductor wafer for patterning or material deposition. Once completed, the photoresist is removed in a manner that mitigates damage to the semiconductor wafer or structures formed thereon. In an embodiment, trioxygen liquid is supplied to the photoresist. The trioxygen liquid is activated using an activator, such as an ultraviolet activator or a hydrogen peroxide activator, to create activated trioxygen liquid used to remove the photoresist. In an embodiment, the activation of the trioxygen liquid results in free radicals that aid in removing the photoresist. In an embodiment, an initial photoresist strip, such as using a sulfuric acid hydrogen peroxide mixture, is performed to remove a first portion of the photoresist, and the activated trioxygen liquid is used to remove a second portion of the photoresist. | 2015-03-05 |
| 20150064929 | METHOD OF GAP FILLING - A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer. | 2015-03-05 |
| 20150064930 | PROCESS OF MANUFACTURING THE GATE OXIDE LAYER - A process of manufacturing the gate oxide layer, which uses the wet oxidation by deuterium to form gate oxide layer, wherein the nitriding treatment is applied to formed gate oxide layer by high temperature annealing process, the stable Si-D bonds is formed on surface of the gate oxide layer to reduce silicon dangling bonds, which reduce the defect of the gate oxide interface and lower the interface defect density of the gate oxide layer and the charge density effectively to avoid NBTI, is provided. | 2015-03-05 |
| 20150064931 | FILM FORMATION METHOD AND FILM FORMATION APPARATUS - Disclosed is a film formation method, including vaporizing a plurality of raw material monomers in respective corresponding vaporizers, supplying the plurality of raw material monomers into a film formation apparatus, causing vapor deposition polymerization of the plurality of raw material monomers in the film formation apparatus to form an organic film on a substrate, and removing an impurity contained in at least one raw material monomer among the plurality of raw material monomers before the vapor deposition polymerization. | 2015-03-05 |
| 20150064932 | Method For Restoring Porous Surface Of Dielectric Layer By UV Light-Assisted ALD - A method for restoring a porous surface of a dielectric layer formed on a substrate, includes: (i) providing in a reaction space a substrate on which a dielectric layer having a porous surface with terminal hydroxyl groups is formed as an outer layer; (ii) supplying gas of a Si—N compound containing a Si—N bond to the reaction space to chemisorb the Si—N compound onto the surface with the terminal hydroxyl groups; (iii) irradiating the Si—N compound-chemisorbed surface with a pulse of UV light in an oxidizing atmosphere to oxidize the surface and provide terminal hydroxyl groups to the surface; and (iv) repeating steps (ii) through (iii) to form a film on the porous surface of the dielectric layer for restoration. | 2015-03-05 |
| 20150064933 | CRYSTALLIZATION OF AMORPHOUS FILMS AND GRAIN GROWTH USING COMBINATION OF LASER AND RAPID THERMAL ANNEALING - A method is disclosed for crystallizing semiconductor material so that it has large grains of uniform size comprising delivering a first energy exposure of high intensity and short duration, and then delivering at least one second energy exposures of low intensity and long duration. The first energy exposure heats the substrate to a high temperature for a duration less than about 0.1 sec. The second energy exposure heats the substrate to a lower temperature for a duration greater than about 0.1 sec. | 2015-03-05 |
| 20150064934 | MULTI CHARGED PARTICLE BEAM WRITING APPARATUS AND MULTI CHARGED PARTICLE BEAM WRITING METHOD - In accordance with one aspect of this invention, a multi charged particle beam writing apparatus includes an aperture member, in which a plurality of openings are formed, configured to form multi-beams by making portions of the charged particle beam pass through the plurality of openings; a plurality of blankers configured to perform blanking-deflect regarding beams corresponding to the multi-beams; a writing processing control unit configured to control writing processing with a plurality of beams having passed through different openings among the plurality of openings being irradiated on the target object at a predetermined control grid interval; and a dose controlling unit configured to variably control a dose of a beam associated with deviation according to a deviation amount when an interval between the plurality of beams irradiated is deviated from the control grid interval. | 2015-03-05 |
| 20150064935 | Connector - The movable portion of the first terminal of the first connector is formed to be larger in the width direction than in the thickness direction, so as to be elastically deformed in the front-back direction of the connector, and the movable portion of the second terminal of the second connector is formed to be larger in the thickness direction than in the width direction, so as to be elastically deformed in the width direction of the connector. Therefore, the movable portions can be formed with an increased cross-sectional area, thereby enabling the allowable current of the terminals to be increased, unlike a configuration in which the movable portion is elastically deformable to a sufficient extent both in the front-back direction and in the width direction of the connector. | 2015-03-05 |
| 20150064936 | ADJUSTABLE LENGTH ELECTRICAL CONNECTOR FOR A TRACTOR TRAILER ASSEMBLY WITH DISCONNECT HANDLE AND METHOD THEREFOR - An electrical connector plug configured for use with tractor-trailers has an elongated housing having a hollow interior. A female electrical connector is coupled to a first end of the housing. An electrical cable is coupled to a second end of the housing. A ridge member is formed on a top surface of the housing. A collar is movable along a length of the housing. A locking mechanism is used to secure the collar at different lengths on the housing. A handle is hingly coupled to the collar to disengage the electrical connector plug from an electrical connector. | 2015-03-05 |
| 20150064937 | OVERPASS GROUNDING SPRING AND INTEGRATED COMPONENT PROTECTION - The described embodiments relate generally to use of an electrically conductive member, such as a grounding spring, used to electrically ground components on a printed circuit board as well as provide mechanical protection to the components. More particularly, a method and apparatus for attaching a grounding spring to multiple locations on the printed circuit board are disclosed. In one embodiment, the grounding spring can act as both a ground and a mechanical protection element for other surface mounted components disposed on the printed circuit board. | 2015-03-05 |
| 20150064938 | PIN MODULE OF RJ CONNECTOR - A pin module of RJ connector includes a circuit board and eight pins, which contain a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin. Each pin includes a turning part and a stretching part. One end of the turning part is extended to form a first end of the pin. The first ends of the pins are arranged in a series. One end of the stretching part is coupled to the other end of the corresponding turning part. The other end of the stretching part is extended to form a second end of the pin, and the second ends of the pins clips the circuit board. | 2015-03-05 |
| 20150064939 | Interface Card Assembly for Use in a Bus Extension System - An interface card assembly of a bus extension system for coupling a solid state drive to a host bus adaptor of a host computer includes a printed circuit board having an edge connector with a plurality of pins and a plurality of first conducting traces. The interface card also includes a plurality of first serially aligned plated holes disposed along a first center-line having a first end and a second and being disposed perpendicularly to the edge connector and a slot. The slot is milled in the printed circuit board so that the slot is parallel and adjacent to the first center-line and extends beyond the first and second ends thereby leaving each of the first plated holes in a semi-circular shape. | 2015-03-05 |
| 20150064940 | CONNECTOR HOUSING, ELECTRIC CONNECTOR AND METHOD OF INSERTING CONNECTOR TERMINAL INTO CONNECTOR HOUSING - The connector housing includes a terminal housing in which at least one connector terminal electrically connecting two printed circuit boards to each other is housed, the terminal housing including a holder for holding the connector terminal therewith, the holder being elastically deformable in accordance with a displacement of the connector terminal. | 2015-03-05 |
| 20150064941 | IC SOCKET AND CONNECTION TERMINAL - An IC socket includes: a socket main body having a flat plate section in which a plurality of through holes are provided; and a first connection terminal and a second connection terminal that are provided with the through holes of the socket main body, and protrude from an upper side and a lower side of the flat plate section, wherein a capacitor is provided within the first connection terminal. | 2015-03-05 |
| 20150064942 | CIRCUIT-TERMINAL CONNECTING DEVICE - A circuit-terminal connecting device comprising a first connector having a first housing attached to a first circuit board provided thereon with first circuit-terminals and a first metallic member, a second connector having a second housing attached to a second circuit board provided thereon with second circuit-terminals and a second metallic member and a manipulatable member mounted on the second housing, wherein an end portion of the manipulatable member is formed into a movable locking portion supported by the second metallic member, the first metallic member is provided thereon with a fixed locking portion, and the manipulatable member is resiliently deformed for causing the movable locking portion to engage with the fixed locking portion so that the second housing is put in mechanical lock to the first housing when the second housing is put in engagement with the first housing for connecting the second circuit-terminals with the first circuit-terminals. | 2015-03-05 |
| 20150064943 | GROUNDING METHOD FOR BASEPLATE SEALED ENCLOSURES - An attachment structure for use with a standalone control unit. The control unit includes a threaded insert located in an enclosed cavity which allows screws to be used for grounding of an EMI/RFI board, along with creating a sealed, enclosed pocket. The attachment structure allows for grounding of the PCB to the sheet metal base plate without creating a leak path to the outside of the control unit. This ground approach encapsulates the screw to prevent the formation of a leak path. | 2015-03-05 |
| 20150064944 | TAMPER-RESISTANT ASSEMBLY WITH WEAR-RESISTANT SHUTTERS - A tamper-resistant assembly for an electrical device, such as an electrical receptacle, includes a housing enclosing movable shutter members, each having a ramped surface protected by an overlying winged cover member engageable by an object, such as a plug blade, inserted in an opening in the electrical device. Each shutter member has a pair of pockets on opposite sides of the ramped surface that anchor the wings of the cover member. The pockets extend laterally outward from the sides of the ramped surface, and the wings of the cover member are configured such that they flex inward during assembly and then snap into the pockets. Other mating features of the cover member and the shutter member help ensure secure anchoring of the cover member. | 2015-03-05 |
| 20150064945 | PRINTED CIRCUIT BOARD CONNECTOR EJECTOR - A printed circuit board connector ejector includes a body extending from a first end to a second end. The body includes an outer surface and a passage extending through the body between the first and second ends. A plurality of threads extend at least partially though the passage. The plurality of threads is configured and disposed to engage with an electrical connector. An actuation member extends radially outwardly from the outer surface. The actuation member is configured and disposed to facilitate rotation of the body relative to an electrical connector. | 2015-03-05 |
| 20150064946 | RADIO FREQUENCY SUBSCRIBER DROP EQUIPMENT HAVING HIGH VOLTAGE PROTECTION CIRCUITS AND RELATED CONTACT ASSEMBLIES - RF subscriber drop units have a housing that has a port aperture therethrough and a connector port that extends outwardly from the housing and surrounds the port aperture. The connector port includes a contact assembly that holds a spring contact, the spring contact including a contact tail that extends through the port aperture. A conductive spark gap unit that has a spark gap aperture is further provided and arranged so that the contact tail extends through the spark gap aperture. | 2015-03-05 |
| 20150064947 | ELECTRONIC DEVICE PROVIDING DATA PROTECTION FOR INSERTED SMARTCARD - An electronic device includes a housing for safely breaking electronic communication with a smart card on removal from the electronic device. A safeguard structure rotates with respect to the housing to cover the smart card when inserted, and a switch breaks communication between the smart card and the electronic device when the safeguard structure is rotated away from the housing to enable removal of the smart card. The breaking of communication safely prevents damage to, or corruption of, data in the smart card upon removal from the electronic device. | 2015-03-05 |
| 20150064948 | CONNECTOR AND CONNECTOR DEVICE - A connector ( | 2015-03-05 |
