| 10th week of 2015 patent applcation highlights part 21 |
| Patent application number | Title | Published |
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| 20150061045 | MEMS Device - A MEMS device includes a first chip and a MEMS chip. The first chip has a mounting surface and includes at least an integrated circuit. The MEMS chip has a main surface on which a first set of contact pads for contacting the MEMS device and a second set of contact pads for contacting the first chip are arranged. The first chip is mechanically attached and electrically connected to the second set of contact pads via the mounting surface facing the main surface. The mounting surface of the first chip is at least 25% smaller than the main surface of the MEMS chip. | 2015-03-05 |
| 20150061046 | WAFER LEVEL METHOD OF SEALING DIFFERENT PRESSURE LEVELS FOR MEMS SENSORS - The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of chambers with different pressures on a substrate, and an associated apparatus. In some embodiments, the method is performed by providing a device wafer having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the device wafer in a first ambient environment having a first pressure. The bonding forms a plurality of chambers abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of chambers. The one or more openings in the one or more of the plurality of chambers are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of chambers to be held at the different pressure. | 2015-03-05 |
| 20150061047 | CAPACITIVE PRESSURE SENSORS AND FABRICATION METHODS THEREOF - A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate. | 2015-03-05 |
| 20150061048 | Packaged MEMS Device - A packaged MEMS device may include an embedding arrangement, a MEMS device disposed in the embedding arrangement, a sound port disposed in the embedding arrangement and acoustically coupled to the MEMS device, and a grille within the sound port. Some embodiments relate to a sound transducer component including an embedding material and a substrate-stripped MEMS die embedded into the embedding material. The MEMS die may comprise a diaphragm for sound transduction. The sound transducer component may further comprise a sound port within the embedding material in fluidic or acoustic contact with the diaphragm. Further embodiments relate to a method for packaging a MEMS device or to a method for manufacturing a sound transducer component. | 2015-03-05 |
| 20150061049 | Micromechanical component for a capacitive sensor device, and manufacturing method for a micromechanical component for a capacitive sensor device - A micromechanical component for a capacitive sensor device includes first and second electrodes. The first electrode is at least partially formed from a first semiconductor layer and/or metal layer, and at least one inner side of the second electrode facing the first electrode is formed from a second semiconductor layer and/or metal layer. A cavity is between the first and second electrodes. Continuous recesses are structured into the inner side of the second electrode and sealed off with a closure layer. At least one reinforcing layer of the second electrode and at least one contact element which is electrically connected to the first electrode, to the layer of the second electrode which forms the inner side, to at least one printed conductor, and/or to a conductive substrate area, are formed from at least one epi-polysilicon layer. Also described is a micromechanical component manufacturing method for a capacitive sensor device. | 2015-03-05 |
| 20150061050 | MAGNETIC RANDOM ACCESS MEMORY WITH SWITABLE SWITCHING ASSIST LAYER - A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element is configured to store a state when electrical current is applied thereto. The perpendicular STTMRAM element includes a magnetization layer having a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL). The direction of magnetization of the first and second free layers each is in-plane prior to the application of electrical current and after the application of electrical current, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer. | 2015-03-05 |
| 20150061051 | Magnetic Tunnel Junction Device - A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer. | 2015-03-05 |
| 20150061052 | Reversed Stack MTJ - An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer. | 2015-03-05 |
| 20150061053 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element is disclosed. The element includes a first magnetic film, a second magnetic film, and a first nonmagnetic layer formed between the first magnetic film and the second magnetic film. The second magnetic film includes a first magnetic layer formed on a side of the first nonmagnetic layer, a second magnetic layer formed on a side opposite to the first nonmagnetic layer, and a second nonmagnetic layer formed between the first magnetic layer and the second magnetic layer and containing TiN. | 2015-03-05 |
| 20150061054 | MAGNETIC MEMORY DEVICE - A magnetic memory device is provided. The magnetic memory device may include a plurality of word lines extending along a direction crossing a plurality of active regions and at least one source line connected to a plurality of first active regions arranged on a level that is lower than the upper surface of a substrate. A plurality of contact pads may be connected to a plurality of second active regions and a plurality of buried contact plugs may be connected to the plurality of second active regions via the plurality of contact pads. Said buried contact pads may further be arranged in a hexagonal array structure. A plurality of variable resistance structures may be connected to the plurality of second active regions and arranged in a hexagonal array structure. | 2015-03-05 |
| 20150061055 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 2015-03-05 |
| 20150061056 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 2015-03-05 |
| 20150061057 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 2015-03-05 |
| 20150061058 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A MTJ for a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 2015-03-05 |
| 20150061059 | MAGNETIC DEVICES HAVING PERPENDICULAR MAGNETIC TUNNEL JUNCTION - Provided are magnetic memory devices with a perpendicular magnetic tunnel junction. The device includes a magnetic tunnel junction including a free layer structure, a pinned layer structure, and a tunnel barrier therebetween. The pinned layer structure may include a first magnetic layer having an intrinsic perpendicular magnetization property, a second magnetic layer having an intrinsic in-plane magnetization property, and an exchange coupling layer interposed between the first and second magnetic layers. The exchange coupling layer may have a thickness maximizing an antiferromagnetic exchange coupling between the first and second magnetic layers, and the second magnetic layer may exhibit a perpendicular magnetization direction, due at least in part to the antiferromagnetic exchange coupling with the first magnetic layer. | 2015-03-05 |
| 20150061060 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device provided with an interlayer insulating film formed on a semiconductor substrate, and a plurality of wiring layers formed on the interlayer insulating film. The method includes forming of a first wiring layer closest to the semiconductor substrate among the plurality of wiring layers, and forming of an alloy of a titanium layer and a metal layer by heating treatment. The forming of the first wiring layer includes: forming of a titanium layer on an interlayer insulating film; forming of a metal layer containing a metal capable of forming an alloy with titanium in the titanium layer; forming of an orientation layer on the metal layer; and forming of an aluminum layer on the orientation layer. | 2015-03-05 |
| 20150061061 | PHOTO DIODE AND METHOD OF FORMING THE SAME - A method for forming a photo diode is provided. The method includes: forming a first pair of electrodes and a second pair of electrodes over a substrate by using a conductive layer; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a color filter layer over the photo conversion layer, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filer layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer, wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second pixel. | 2015-03-05 |
| 20150061062 | MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH DEEP-TRENCH ISOLATION STRUCTURE - Embodiments of mechanisms of for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back surface. The image-sensor device further includes a doped isolation region formed in the substrate and adjacent to the radiation-sensing region. In addition, the image-sensor device includes a deep-trench isolation structure formed in the doped isolation region. The deep-trench isolation structure includes a trench extending from the back surface and a negatively charged film covering the trench. | 2015-03-05 |
| 20150061063 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor may include a substrate having photoelectric conversion regions respectively formed on a plurality of pixels and charge trap regions overlapping with the respective photoelectric conversion regions and having depths or thicknesses that are different, for each of the respective pixel. | 2015-03-05 |
| 20150061064 | IMAGING APPARATUS AND ELECTRONIC SYSTEM - An imaging apparatus includes: a lens group formed of one or more lens elements; and an imaging device having a light receiving surface on which the lens group forms an image of an object, wherein the light receiving surface of the imaging device is a curved surface that is concave toward the lens group, and the light receiving surface of the imaging device has an aspheric shape so shaped that a tangential angle that is an angle between a tangential line circumscribing an edge of the light receiving surface and a plane perpendicular to an optical axis of the lens group is smaller than the tangential angle provided when the light receiving surface has a spherical shape. | 2015-03-05 |
| 20150061065 | OPTICAL SENSING OF NEARBY SCENES WITH TESSELLATED PHASE ANTI-SYMMETRIC PHASE GRATINGS - An array of diffraction-pattern generators employ phase anti-symmetric gratings to projects near-field spatial modulations onto a closely spaced array of photoelements. Each generator in the array of generators produces point-spread functions with spatial frequencies and orientations of interest. The generators are arranged in an irregular mosaic with little or no short-range repetition. Diverse generators are shaped and placed with some irregularity to reduce or eliminate spatially periodic replication of ambiguities to facilitate imaging of nearby scenes. | 2015-03-05 |
| 20150061066 | IMAGING APPARATUS - Provided is an imaging apparatus having a plurality of light receiving parts for each one microlens in order for capturing a three-dimensional image, while being capable of obtaining a more natural image when creating a two-dimensional image. The imaging apparatus includes: a microlens array ( | 2015-03-05 |
| 20150061067 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an epitaxial layer of a first conductive type; an anode electrode and a cathode electrode arranged on the epitaxial layer to be separated from each other; a first drift layer of the first conductive type formed in the epitaxial layer; a Schottky contact area at a region of contact between the anode electrode and the first drift layer; an impurity region of a second conductive type different from the first conductive type at the epitaxial layer; and an insular impurity region formed below the Schottky contact area. | 2015-03-05 |
| 20150061068 | NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING PATTERN ON WAFER AND METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE USING SAME - According to an embodiment, a method for fabricating a pattern includes forming a mask covering a first layer, and a second layer selectively provided on the first layer, and forming a groove dividing the first layer and the second layer using the mask. The mask includes a first portion formed on a region of the first layer on a first side of the second layer, a second portion formed on a region of the first layer on a second side of the second layer opposite to the first side, first extending parts extending over the second layer from the first portion toward the second portion, and second extending parts extending over the second layer from the second portion toward the first portion. Each of the second extending parts is located between the first extending parts adjacent to each other. | 2015-03-05 |
| 20150061069 | INTEGRATING A CAPACITOR IN AN INTEGRATED CIRCUIT - In one aspect, an integrated circuit (IC) includes an isolation trench dividing the IC into a first section and a second section, an active electronic device disposed in the first section of the IC and a capacitor disposed in the second section of the IC and electrically isolated from the active electronic device. | 2015-03-05 |
| 20150061070 | SEMICONDUCTOR DEVICE - A first isolation trench insulates and separates a low-voltage region, a high-voltage region, and a connection region of the semiconductor layer from each other. A low-potential signal processing circuit is in the low-voltage region, and operates at a lower potential. A high-potential signal processing circuit is in the high-voltage region, and operates at a higher potential. A capacitor is on the connection region and transmits the second alternating current signal from the low-potential signal processing circuit to the high-potential signal processing circuit. The capacitor includes a low-potential electrode connected to the low-potential signal processing circuit, and a high-potential electrode connected to the high-potential signal processing circuit. First wiring layers of the low-potential electrode and second wiring layers of the high-potential electrode are capacitively coupled. Side wall surfaces of the first wiring layers and those of the second wiring layers are opposed to each other. | 2015-03-05 |
| 20150061071 | Metal Oxide Semiconductor (MOS) Capacitor with Improved Linearity - A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors. | 2015-03-05 |
| 20150061072 | VARIABLE CAPACITANCE INTEGRATED CIRCUIT - A variable capacitance semiconductor structure is disclosed. Embodiments include a capacitor having three plates, a top plate, a middle plate, and a bottom plate. The top plate serves as a positive plate. The middle and bottom plates serve as ground plates for the capacitor. A switching circuit selects between the middle plate and the bottom plate for use as the ground plate of the capacitor. The middle plate is slotted, allowing electric fields to penetrate through the middle plate to the bottom plate. The slots prevent the electric fields from terminating at the middle plate. A different capacitance value can be selected, depending on whether the middle plate or bottom plate is selected as the ground plate. Logic circuitry is configured to control the selection of plates to achieve a variety of capacitance values. | 2015-03-05 |
| 20150061073 | SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug. | 2015-03-05 |
| 20150061074 | MIM Capacitors with Diffusion-Blocking Electrode Structures and Semiconductor Devices Including the Same - A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration. | 2015-03-05 |
| 20150061075 | METAL TRENCH DE-COUPLING CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME - A metal trench de-coupling capacitor structure includes a vertical trench disposed in a substrate, an insulating layer deposited on the sidewall of the vertical trench, an inter-layer dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the interlayer dielectric layer to fill up the vertical trench. The metal layer is electrically connected to a power source. | 2015-03-05 |
| 20150061076 | HIGH DENSITY RESISTOR - At least one three dimensional semiconductor fin is formed from a top semiconductor material of a substrate. A dielectric material is formed along vertical sidewalls and an upper surface of the at least one three dimensional semiconductor fin. A polysilicon resistor is formed on exposed surfaces of the dielectric material and surrounding the at least one semiconductor fin. An interconnect dielectric material is formed above the polysilicon resistor. The interconnect dielectric material has at least one contact structure that extends through the interconnect dielectric to an upper surface of the polysilicon resistor. | 2015-03-05 |
| 20150061077 | TRENCH SIDEWALL PROTECTION FOR SELECTIVE EPITAXIAL SEMICONDUCTOR MATERIAL FORMATION - A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures. | 2015-03-05 |
| 20150061078 | COMPOUND SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. | 2015-03-05 |
| 20150061079 | Wafer Level Dicing Method - Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer. | 2015-03-05 |
| 20150061080 | GUARD RING STRUCTURE OF SEMICONDUCTOR APPARATUS - A guard ring structure of a semiconductor apparatus includes a base wiring layer located above a semiconductor substrate, a first guard ring configured as a wiring stacked structure of two or more layers adjacent to the side of the device forming region above the base wiring layer, and a second guard ring configured to be stacked with the same number of layers as the first guard ring and separated from the first guard ring, the second guard ring formed adjacent to the side of a scribe lane above the base wiring layer. | 2015-03-05 |
| 20150061081 | CRACK DEFLECTOR STRUCTURE FOR IMPROVING SEMICONDUCTOR DEVICE ROBUSTNESS AGAINST SAW-INDUCED DAMAGE - An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal. | 2015-03-05 |
| 20150061082 | CONTACT PLUG AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening. | 2015-03-05 |
| 20150061083 | METAL TRENCH DE-NOISE STRUCTURE AND METHOD FOR FORMING THE SAME - A metal trench de-noise structure includes a trench disposed in a substrate, an insulating layer deposited on the sidewall of the trench, an Inter-Layer Dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the Inter-Layer Dielectric layer to fill up the trench. The metal layer may be grounded or floating. | 2015-03-05 |
| 20150061084 | SUBSTRATE, METHOD OF FABRICATING THE SAME, AND APPLICATION THE SAME - Provided is a substrate, including a substrate material, two conductive structures, and at least one diode. The two conductive structures extend from a first surface of the substrate material to a second surface of the substrate material via two through holes penetrating through the substrate material. The at least one diode is embedded in the substrate material at a sidewall of one of the through holes. | 2015-03-05 |
| 20150061085 | PACKAGE INTERCONNECTS - A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate. | 2015-03-05 |
| 20150061086 | THREE-DIMENSIONAL SEMICONDUCTOR TEMPLATE FOR MAKING HIGH EFFICIENCY THIN-FILM SOLAR CELLS - A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template. | 2015-03-05 |
| 20150061087 | TRIPLE PATTERNING METHOD - A triple patterning method is provided. The method includes providing a substrate having a first region and a second region; and forming a first material layer. The method also includes forming a second material layer; and forming a plurality of core patterns on the second material layer in the first region. Further, the method includes forming sidewall spacers on side surfaces of the core patterns; and forming first patterns on the first material layer. Further, the method includes forming a third material layer on the first material layer and the first patterns; and forming second patterns on the third material layer in the first region and third patterns on the third material layer in the second region. Further, the method also includes forming fourth patterns; and forming triple patterns on the substrate in the first region and fifth patterns on the substrate in the second region. | 2015-03-05 |
| 20150061088 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer. | 2015-03-05 |
| 20150061089 | Vertical Semiconductor Device and Method of Manufacturing Thereof - A vertical semiconductor device has a semiconductor body with a first surface and a second surface substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. In a sectional plane perpendicular to the first surface, the semiconductor body includes an n-doped first semiconductor region in ohmic contact with the second metallization, a plurality of p-doped second semiconductor regions in ohmic contact with the first metallization, and a plurality of p-doped embedded semiconductor regions. The p-doped second semiconductor regions substantially extend to the first surface, are spaced apart from one another and form respective first pn-junctions with the first semiconductor region. The p-doped embedded semiconductor regions are spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and form respective second pn-junctions with the first semiconductor region. | 2015-03-05 |
| 20150061090 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drift layer having a first conductive type; a first semiconductor layer having a second conductive type and arranged in a surface portion of the drift layer; a second semiconductor layer having the first conductive type, arranged at a position of the drift layer spaced apart from the first semiconductor layer, and having a carrier density larger than the drift layer; a hole injection layer having the second conductive type and arranged selectively in the second semiconductor layer; a first electrode electrically connecting to the first semiconductor layer; a second electrode electrically connecting to the second semiconductor layer and the hole injection layer. The second semiconductor layer has a carrier density smaller than a spatial charge density. | 2015-03-05 |
| 20150061091 | Functionalised redistribution layer - An electronic device which comprises at least one interconnect, a semiconductor chip comprising at least one electric chip pad, an encapsulant structure packaging at least a part of the semiconductor chip, and an electrically conductive redistribution layer arranged between and electrically coupled with the at least one interconnect and the at least one chip pad, wherein the redistribution layer comprises at least one adjustment structure configured for adjusting radio frequency properties of a transition between the semiconductor chip and its periphery. | 2015-03-05 |
| 20150061092 | APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad. | 2015-03-05 |
| 20150061093 | INTERPOSER AND SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD OF MANUFACTURING INTERPOSER - Disclosed herein is an interposer, including: an interposer substrate configured by stacking an insulating layer of one layer or more and interlayer connected through a via; a cavity penetrating through a center of the interposer substrate in a thickness direction; and a connection electrode having a post part which is disposed on at least one of an upper surface and a lower surface of the interposer substrate, thereby increasing electrical characteristics and reducing manufacturing cost and time. | 2015-03-05 |
| 20150061094 | CAVITY PACKAGE WITH PRE-MOLDED CAVITY LEADFRAME - A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow. | 2015-03-05 |
| 20150061095 | PACKAGE-ON-PACKAGE DEVICES, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGES - In a package-on-package (PoP) device according to the inventive concepts, an anisotropic conductive film is disposed between a lower semiconductor package and an upper semiconductor package to remove an air gap between the lower and upper semiconductor packages. Thus, heat generated from a lower semiconductor chip may be rapidly and smoothly transmitted toward the upper semiconductor package, thereby increasing or maximizing a heat exhaust effect of the PoP device. | 2015-03-05 |
| 20150061096 | Semiconductor Package with Multi-Level Die Block - A semiconductor package includes a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region. The semiconductor package further includes a first semiconductor die and a second semiconductor die each having opposing first and second sides. The first semiconductor die is disposed in the recessed region of the block and attached to the thinner part of the block at the first side of the first semiconductor die. The second semiconductor die is attached to the second side of the first semiconductor die at a first side of the second semiconductor die. | 2015-03-05 |
| 20150061097 | EDGE COUPLING OF SEMICONDUCTOR DIES - Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together. | 2015-03-05 |
| 20150061098 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead terminal integrated into the case to be directly connected to the semiconductor elements or an interconnection of the substrate. The lead terminal has a stress relief shape for reliving stress generated in the lead terminal. | 2015-03-05 |
| 20150061099 | DENSE-PITCH SMALL-PAD COPPER WIRE BONDED DOUBLE IC CHIP STACK PACKAGING PIECE AND PREPARATION METHOD THEREFOR - A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner pin are arranged; the upper surface of the lead frame carrier is fixedly connected with a first IC chip; a second IC chip is stacked on the first IC chip; the upper surface of the first IC chip and the upper surface of the second IC chip are respectively provided with a plurality of pads which are arranged as two lines of pad groups in parallel; the two pad groups are respectively a first pad group and a second pad group; a metal ball is implanted on each pad; each metal ball is connected with a first copper bonding ball; and a third copper bonding wire is formed by looping and arching on a corresponding metal ball between the second IC chip and the first IC chip. The preparation process of the present invention comprises thinning, scribing, loading the chip, performing pressure welding, plastic packaging and post-curing, trimming, electroplating, printing, forming and separating, and packaging. The package and the preparation method of the invention avoid the hidden danger of open circuit of a plastic packaging punching wire caused by the crater on the pad, the short circuit of adjacent welding spots, and the easy damage of a previous wire. | 2015-03-05 |
| 20150061100 | Semiconductor Arrangement, Method for Producing a Number of Chip Assemblies, Method for Producing a Semiconductor Arrangement and Method for Operating a Semiconductor Arrangement - A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode. | 2015-03-05 |
| 20150061101 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer. | 2015-03-05 |
| 20150061102 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part. | 2015-03-05 |
| 20150061103 | EMBEDDED DIE PACKAGE - A method of making an electrical assembly includes making a laminate substrate, embedding a plurality of integrated circuit dies in the laminate substrate, forming a plurality of through-holes in the laminate substrate and adding conductive material to the through-holes, and making at least one saw cut extending through the laminate substrate and through the plurality of through-holes and the conductive material therein to form at least one laminate block with a cut face and a plurality of sectioned through-holes. | 2015-03-05 |
| 20150061104 | SEMICONDUCTOR DEVICE - An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other. | 2015-03-05 |
| 20150061105 | SEMICONDUCTOR MODULE - Aspects of the invention provide a semiconductor module that can be manufactured without using a bending jig for bearing the stress in bending process of the terminal and scarcely generates cracks in the resin parts of the semiconductor module. In some aspects of the invention, a semiconductor module can include a casing made of a resin material accommodating a semiconductor chip, a terminal one end of which is electrically connected to the semiconductor chip and the other end of which is projecting out of the casing and bent and a lid made of a resin material fitted on an opening of the casing, a part of end region of the lid being in contact with the terminal and being a thick part with a thickness thicker than a thickness of other parts of the lid. | 2015-03-05 |
| 20150061106 | CAVITY-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SAME | 2015-03-05 |
| 20150061107 | INSULATION SHEET MADE FROM SILICON NITRIDE, AND SEMICONDUCTOR MODULE STRUCTURE USING THE SAME - An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains β-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride. | 2015-03-05 |
| 20150061108 | Packaged Semiconductor Device - A packaged semiconductor device includes a semiconductor component, first and second heat dissipation means disposed between the semiconductor component and the first and second main faces, respectively, encapsulated by an encapsulant, the shape of the packaged semiconductor device being non-rectangular cuboid. | 2015-03-05 |
| 20150061109 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a semiconductor chip and connection terminals, a cooling fin to which the semiconductor element is fixed, and an external cooling body having a passage for cooling medium, the cooling fin being fixed to the external cooling body. The semiconductor element has a protruding cooling block that is inserted and fixed to the cooling fin, which in turn is fixed to the external cooling body such that the cooling fin is in contact with the cooling medium. | 2015-03-05 |
| 20150061110 | STACKED CHIP LAYOUT AND METHOD OF MAKING THE SAME - A stacked chip layout includes a central processing chip has a first area and a first active circuit block over the central processing chip, the first active circuit block has a second area. The stacked chip layout further includes a second active circuit block over the first active circuit block, the second active circuit block has a third area, the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The stacked chip layout further includes a third active circuit block over the second active circuit block, the third active circuit block has a fourth area, the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes a portion of the first active circuit block and the second active circuit block. | 2015-03-05 |
| 20150061111 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a base plate having an upper surface on which the semiconductor element is mounted, a cooling fin disposed on a lower surface of the base plate, a jacket disposed in a sealing manner on the lower surface of the base plate, the jacket surrounding the cooling fin, and a header partition wall formed separately from the jacket and fixed to the jacket on the lower side of the cooling fin in the jacket, the header partition wall forming a header and a flow path for causing a refrigerant flow to the cooling fin. | 2015-03-05 |
| 20150061112 | Power semiconductor device and method for producing a power semiconductor device - A power semiconductor device comprising a power semiconductor module and a heat sink and a method for its manufacture. The heat sink has a first cooling housing component, with a cutout passing therethrough, and a second cooling housing component, with a cooling plate arranged in the cutout. The first and second cooling housing components are configured and arranged relative to one another so that a cavity is formed at the side of the cooling plate facing away from the power semiconductor components. The cooling plate is connected to the first cooling housing component by a first weld seam which extends circumferentially therearound. The first weld seam seals the cooling plate in relation to the first cooling housing component, and the second cooling housing component is connected to the first cooling housing component. The inventive power semiconductor device has good heat conduction from the power semiconductor components to a heat sink. | 2015-03-05 |
| 20150061113 | Semiconductor Dies Having Opposing Sides with Different Reflectivity - A method of processing semiconductor dies is provided. Each semiconductor die has a first side with one or more terminals, a second side opposite the first side and sidewalls extending between the first and the second sides. The semiconductor dies are processed by placing the semiconductor dies on a support substrate so that the first side of each semiconductor die faces the support substrate and the second side faces away from the support substrate. A coating is applied to the semiconductor dies placed on the support substrate. The coating has a lower reflectivity than the first side of the semiconductor dies. The coating covers the second side and at least a region of the sidewalls nearest the second side of each semiconductor die. The semiconductor dies are removed from the support substrate after applying the coating for further processing as loose dies such as taping. | 2015-03-05 |
| 20150061114 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip and a joined member. The semiconductor chip has a semiconductor substrate, a first electrode, and a second electrode. The first electrode is arranged on a first surface of the semiconductor substrate. The second electrode is arranged on a second surface of the semiconductor substrate. The first electrode is joined to the joined member via a joint material. A tensile force in a surface direction of the first surface that is applied to the first surface of the semiconductor substrate from the first electrode due to thermal expansion of the first electrode at a melting temperature of the joint material is at least equal to a tensile force in the surface direction that is applied to the second surface of the semiconductor substrate from the second electrode due to thermal expansion of the second electrode at the melting temperature. | 2015-03-05 |
| 20150061115 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b). | 2015-03-05 |
| 20150061116 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad. | 2015-03-05 |
| 20150061117 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps. | 2015-03-05 |
| 20150061118 | Three-Dimensional Chip Stack and Method of Forming the Same - A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region. | 2015-03-05 |
| 20150061119 | CIRCUIT SUBSTRATE, SEMICONDUTOR PACKAGE STRUCTURE AND PROCESS FOR FABRICATING A CIRCUIT SUBSTRATE - A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided. | 2015-03-05 |
| 20150061120 | STACK PACKAGES AND METHODS OF MANUFACTURING THE SAME - Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed. | 2015-03-05 |
| 20150061121 | METHOD FOR WAFER LEVEL PACKAGING AND A PACKAGE STRUCTURE THEREOF - The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure. | 2015-03-05 |
| 20150061122 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes placing a mask having an opening on an external region of a top face of a substrate to locate an end portion of the opening of the mask just above a concave portion formed on the top face of the substrate, the external region being located outside the concave portion. The manufacturing method further includes: growing a conductive film on part of the top face of the substrate through the mask after the mask is placed on the substrate, the part of the top face containing the concave portion; and removing the mask from the substrate after the conductive film is grown. | 2015-03-05 |
| 20150061123 | Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation - A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer. | 2015-03-05 |
| 20150061124 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 2015-03-05 |
| 20150061125 | INTEGRATED CIRCUIT PACKAGE INCLUDING IN-SITU FORMED CAVITY - A flip chip packaged component includes a die having a first surface and a dielectric barrier disposed on the first surface of the die. The dielectric barrier at least partially surrounds a designated location on the first surface of the die. A plurality of bumps is disposed on the first surface of the die on an opposite side of the dielectric barrier from the designated location. The flip chip packaged component further includes a substrate having a plurality of bonding pads on a second surface thereof. A cavity is defined by the first surface of the die, the dielectric barrier, and the substrate. A molding compound encapsulates the die and at least a portion of the substrate. | 2015-03-05 |
| 20150061126 | MANUFACTURE INCLUDING SUBSTRATE AND PACKAGE STRUCTURE OF OPTICAL CHIP - A manufacture includes a package structure, a first substrate, and a conductive member of a same material. The package structure includes a chip comprising a conductive pad, a conductive structure over the chip, and a passivation layer over the conductive structure. The passivation layer has an opening defined therein, and the opening exposes a portion of a planar portion of the conductive structure. The first substrate includes a first surface defining a first reference plane and a second surface defining a second reference plane. The conductive member extends across the first reference plane and the second reference plane and into the opening. The conductive member is electrically coupled to the exposed portion of the planar portion. | 2015-03-05 |
| 20150061127 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA. | 2015-03-05 |
| 20150061128 | BALL ARRANGEMENT FOR INTEGRATED CIRCUIT PACKAGE DEVICES - An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs. | 2015-03-05 |
| 20150061129 | Bump Electrode, Board Which Has Bump Electrodes, and Method for Manufacturing the Board - A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3. | 2015-03-05 |
| 20150061130 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement may include: a first semiconductor chip having a first side and a second side opposite the first side; a second semiconductor chip having a first side and a second side opposite the first side, the second semiconductor chip disposed at the first side of the first semiconductor chip and electrically coupled to the first semiconductor chip, the first side of the second semiconductor chip facing the first side of the first semiconductor chip; an encapsulation layer at least partially encapsulating the first semiconductor chip and the second semiconductor chip, the encapsulation layer having a first side and a second side opposite the first side, the second side facing in a same direction as the second side of the second semiconductor chip; an interconnect structure disposed at least partially within the encapsulation layer and electrically coupled to at least one of the first and second semiconductor chips, wherein the interconnect structure may extend to the second side of the encapsulation layer; and a third semiconductor chip disposed at at least one of the second side of the second semiconductor chip and the second side of the encapsulation layer, the third semiconductor chip having a first side and a second side opposite the first side, the second side of the third semiconductor chip facing in the same direction as the second side of the second semiconductor chip and the second side of the encapsulation layer. | 2015-03-05 |
| 20150061131 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT. | 2015-03-05 |
| 20150061132 | CONDUCTIVE LINE STRUCTURES AND METHODS OF FORMING THE SAME - Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns. | 2015-03-05 |
| 20150061133 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film. | 2015-03-05 |
| 20150061134 | SEMICONDUCTOR DEVICES INCLUDING AIR GAP SPACERS AND METHODS OF MANUFACTURING THE SAME - A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described. | 2015-03-05 |
| 20150061135 | COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP - A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap. | 2015-03-05 |
| 20150061136 | SEMICONDUCTOR DEVICES HAVING METAL SILICIDE LAYERS AND METHODS OF MANUFACTURING SUCH SEMICONDUCTOR DEVICES - Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device. | 2015-03-05 |
| 20150061137 | PACKAGE AND METHOD FOR INTEGRATION OF HETEROGENEOUS INTEGRATED CIRCUITS - A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip. | 2015-03-05 |
| 20150061138 | METHOD OF FORMING A MEMORY DEVICE - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 2015-03-05 |
| 20150061139 | MICROELECTRONIC PACKAGES CONTAINING OPPOSING DEVICES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of the preformed panel in ohmic contact with or otherwise electrically coupled to the first microelectronic device. Similarly, one or more backside RDL layers are formed over the backside of the preformed panel in ohmic contact with or otherwise electrically coupled to the second microelectronic device. A frontside contact array is produced over the frontside of the preformed panel and electrically coupled to at least the first microelectronic device through the frontside RDL layers. Lastly, the preformed panel is singulated to yield a microelectronic package including a package body in which the first and second microelectronic devices are embedded. | 2015-03-05 |
| 20150061140 | Molded Semiconductor Package with Pluggable Lead - A semiconductor package includes a semiconductor die having a plurality of terminals, a molding compound encapsulating the semiconductor die, and a pluggable lead dimensioned for insertion into an external receptacle. The pluggable lead protrudes from the molding compound and provides a separate electrical pathway for more than one terminal of the semiconductor die. The separate electrical pathways of the pluggable lead can be provided by electrical conductors isolated from one another by electrical insulator such as molding compound or other insulation material/medium. | 2015-03-05 |
| 20150061141 | INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME - A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer. | 2015-03-05 |
| 20150061142 | ULTRA FINE PITCH PoP CORELESS PACKAGE - A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package. | 2015-03-05 |
| 20150061143 | ULTRA FINE PITCH AND SPACING INTERCONNECTS FOR SUBSTRATE - Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer. | 2015-03-05 |
| 20150061144 | Semiconductor Arrangement, Method for Producing a Semiconductor Module, Method for Producing a Semiconductor Arrangement and Method for Operating a Semiconductor Arrangement - A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly. | 2015-03-05 |
