| 10th week of 2015 patent applcation highlights part 20 |
| Patent application number | Title | Published |
|---|
| 20150060945 | TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM - Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm | 2015-03-05 |
| 20150060946 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes a channel layer of first arsenide semiconductor, an electron supply layer of second arsenide semiconductor over the channel layer, a gate electrode, a source electrode and a drain electrode over the channel layer, and a metal film between the gate electrode and the drain electrode, the metal film being insulated from the gate electrode and the drain electrode. | 2015-03-05 |
| 20150060947 | Transistor with Diamond Gate - A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond. | 2015-03-05 |
| 20150060948 | SEMICONDUCTOR DEVICE - A field plate causes excessive gate capacitance that interferes with high-speed transistor switching. To suppress the excessive gate capacitance, an aperture includes a first side wall positioned on the side of a drain electrode, and a second side wall positioned on the side of a source electrode. A gate electrode at the same time includes a first side surface facing opposite the drain electrode as seen from a plan view. The first side surface of the gate electrode is positioned on the inner side of the first side wall and the second side wall as seen from a flat view. Moreover, a portion of a first field plate is embedded between the first side surface and the first side wall. The gate electrode and the first field plate are electrically insulated by a first insulation member. | 2015-03-05 |
| 20150060949 | FET DIELECTRIC RELIABILITY ENHANCEMENT - A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C. | 2015-03-05 |
| 20150060950 | TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region. | 2015-03-05 |
| 20150060951 | IMAGE SENSORS OPERABLE IN GLOBAL SHUTTER MODE AND HAVING SMALL PIXELS WITH HIGH WELL CAPACITY - An image sensor operable in global shutter mode ma include small pixels with high charge storage capacity, low dark current, and no image lag. Storage capacity of a photodiode and a charge storage diode may be increased by placing a p+ type doped layer under the photodiode and the charge storage diode. The p+ type doped layer ma include an opening for allowing photo-generated charge carriers to flow from the silicon bulk to the charge storage well located near the surface of the photodiode. A compensating n− type doped implant may be formed in the opening. Image lag is prevented by placing a p− type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. The p+ type doped layer may extend under the entire pixel array. | 2015-03-05 |
| 20150060952 | FIELD EFFECT TRANSISTOR, DEVICE INCLUDING THE TRANSISTOR, AND METHODS OF FORMING AND USING SAME - The present disclosure provides an improved field effect transistor and device that can be used to sense and characterize a variety of materials. The field effect transistor and/or device including the transistor may be used for a variety of applications, including genome sequencing, protein sequencing, biomolecular sequencing, and detection of ions, molecules, chemicals, biomolecules, metal atoms, polymers, nanoparticles and the like. | 2015-03-05 |
| 20150060953 | ION-SENSITIVE LAYER STRUCTURE FOR AN ION-SENSITIVE SENSOR AND METHOD FOR MANUFACTURING SAME - In a method for manufacturing an ion-sensitive structure for an ion-sensitive sensor, first a semiconductor substrate bearing an oxide layer is provided, whereupon a metal oxide layer and a metal layer are deposited and tempered, in order to obtain a layer sequence having a crystallized metal oxide layer and an oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer. In such case, the metal oxide layer and the metal layer have a compatible metal element, and the coating thickness d | 2015-03-05 |
| 20150060954 | CMOS-MEMS Integrated Flow for Making a Pressure Sensitive Transducer - A sensor is made up of two substrates which are adhered together. A first substrate includes a pressure-sensitive micro-electrical-mechanical (MEMS) structure and a conductive contact structure that protrudes outwardly beyond a first face of the first substrate. A second substrate includes a complementary metal oxide semiconductor (CMOS) device and a receiving structure made up of sidewalls that meet a conductive surface which is recessed from a first face of the second substrate. A conductive bonding material physically adheres the conductive contact structure to the conductive surface and electrically couples the MEMS structure to the CMOS device. | 2015-03-05 |
| 20150060955 | INTEGRATED MEMS MICROPHONE WITH MECHANICAL ELECTRICAL ISOLATION - An integrated MEMS microphone is provided, including, a bonding wafer layer, a bonding layer, an aluminum layer, CMOS substrate layer, an N+ implant doped silicon layer, a field oxide (FOX) layer, a plurality of implant doped silicon areas forming CMOS wells, a two-tier polysilicon layer with selective ion implantation forming a diaphragm, a plurality of implant doped silicon areas forming CMOS source/drain, a gate poly layer forming CMOS transistor gates, said CMOS wells, said CMOS transistor sources/drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with an interconnect contact layer, a plurality of metal layers interleaved with a plurality of via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. Diaphragm is sandwiched between a small top chamber and a small back chamber, and substrate layer includes a large back chamber. | 2015-03-05 |
| 20150060956 | INTEGRATED MEMS PRESSURE SENSOR WITH MECHANICAL ELECTRICAL ISOLATION - An integrated MEMS pressure sensor is provided, including, a CMOS substrate layer, an N+ implant doped silicon layer, a field oxide (FOX) layer, a plurality of implant doped silicon areas forming CMOS wells, a two-tier polysilicon layer with selective ion implantation forming a membrane, including an implant doped polysilicon layer and a non-doped polysilicon layer, a second non-doped polysilicon layer, a plurality of implant doped silicon areas forming CMOS source/drain, a gate poly layer made of polysilicon forming CMOS transistor gates, said CMOS wells, CMOS transistor sources/drains and CMOS gates forming CMOS transistors, an oxide layer embedded with an interconnect contact layer, a plurality of metal layers interleaved with a plurality of via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. N+ implant doped silicon layer and implant doped/un-doped composition polysilicon layer forming a sealed vacuum chamber. | 2015-03-05 |
| 20150060957 | THREE-DIMENSIONAL GATE-WRAP-AROUND FIELD-EFFECT TRANSISTOR - A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved. | 2015-03-05 |
| 20150060958 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers are interlaced. At least one of the conductive layers has a first doping segment having a first doping property and a second doping segment having a second doping property, the second doping property being different from the first doping property. The interface between the first doping segment and the second doping segment has a grain boundary. | 2015-03-05 |
| 20150060959 | Eliminating Fin Mismatch Using Isolation Last - An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin. | 2015-03-05 |
| 20150060960 | METHODS OF FORMING CONTACT STRUCTURES ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - A method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess that have an outer perimeter surface that contacts at least a portion of an interior perimeter surface of the recess and forming at least one source/drain contact structure for each of the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure. The upper surface of each of the buried fin contact structures is positioned below an upper surface of the raised isolation structure and an outer perimeter surface of each of the buried fin contact structures contacts at least a portion of an interior perimeter surface of the recess. | 2015-03-05 |
| 20150060961 | FINFET DEVICE AND METHOD OF FORMING FIN IN THE SAME - A method for manufacturing a fin for a FinFET device includes providing a semiconductor substrate, forming a plurality of implanted regions in the semiconductor substrate, and epitaxially forming fins between two adjacent implanted regions. The method also includes forming an insulating structure between two adjacent fins. | 2015-03-05 |
| 20150060962 | SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD FOR SOLID-STATE IMAGING ELEMENT - Provided are a solid-state imaging element, which suppresses occurrence of a dark current and a white spot and even suppresses occurrence of a residual image, and a manufacturing method for the solid-state imaging element. A solid-state imaging element ( | 2015-03-05 |
| 20150060963 | IMAGE SENSOR DEVICE - An image sensor device comprises an isolation well region within a substrate. A gate stack is over the isolation well region on the first surface of the substrate. The gate stack has an edge. A doped isolation feature is within the substrate between the isolation well region and the gate stack. The doped isolation feature surrounds an active area. The gate stack is over the active area. The doped isolation feature extends from the edge of the gate stack under the gate stack. | 2015-03-05 |
| 20150060964 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE - Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers. | 2015-03-05 |
| 20150060965 | PHOTODETECTING DEVICE HAVING SEMICONDUCTOR REGIONS SEPARATED BY A POTENTIAL BARRIER - Photodetecting device comprising:
| 2015-03-05 |
| 20150060966 | IMAGE SENSORS WITH SILICIDE LIGHT SHIELDS - An image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a semiconductor substrate. Buried light shielding structures may be formed on the substrate to prevent pixel circuitry that is formed in the substrate between two adjacent photodiodes from being exposed to incoming light. The buried light shields may be formed over conductive gate structures. A metal silicide layer may be formed to completely cover these conductive gate structures. Antireflective coating material may optionally be formed over the metal silicide layer. Forming gate structures with a metal silicide liner can help reduce optical pixel crosstalk and enhance global shutter efficiency. | 2015-03-05 |
| 20150060967 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR UNIT - A semiconductor device includes: a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate. | 2015-03-05 |
| 20150060968 | STACK CHIP PACKAGE IMAGE SENSOR - An image sensor cell is divided into two chips, and a capacitor for noise reduction is formed in a bottom wafer in correspondence with a unit pixel of a top wafer in a stack chip package image sensor having a coupling structure of the two chips, so that noise characteristics of the image sensor are improved. A stack chip package image sensor includes: a first semiconductor chip that includes a photodiode, a transmission transistor, and a first conductive pad and outputs image charge, which is output from the photodiode, through the first conductive pad; and a second semiconductor chip that includes a drive transistor, a selection transistor, a reset transistor, and a second conductive pad and supplies a corresponding pixel with an output voltage corresponding to the image charge received from the first semiconductor chip through the second conductive pad. The second semiconductor chip includes a capacitor for noise reduction. | 2015-03-05 |
| 20150060969 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. One of the lower electrode and the upper electrode is connected to an impurity region of the transistor. The second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode. The lower electrode is formed from the same material as the first electrode, the ferroelectric is formed from the same material as the first dielectric, and the upper electrode is formed from the same material as the second electrode. | 2015-03-05 |
| 20150060970 | Semiconductor Device Including Contact Plugs And Conductive Layers Thereon - Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers. | 2015-03-05 |
| 20150060971 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device including a memory cell transistor having a stacked gate structure including a tunnel insulating film, a charge accumulation layer, a memory cell insulating film, and a control gate electrode film are orderly stacked above a semiconductor substrate, and a capacitor in which a first insulating film, a first electrode film, a second insulating film, a second electrode film, a third insulating film, and a third electrode film are orderly stacked above the semiconductor substrate is provided. A material of the second electrode film is same as the charge accumulation layer of the memory cell transistor. The third electrode film includes a material same as the control gate electrode film of the memory cell transistor. | 2015-03-05 |
| 20150060972 | Strained Channel Dynamic Random Access Memory Devices - DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. | 2015-03-05 |
| 20150060973 | ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE USING SAME - An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode. | 2015-03-05 |
| 20150060974 | FLASH MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°. | 2015-03-05 |
| 20150060975 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes first and second memory blocks which are disposed adjacent to each other in a first direction. The first and second memory blocks each include a plurality of bit lines, a plurality of word lines, which are disposed to extend in a second direction, and a memory cell, which is connected to any of the plurality of word lines. The first memory block includes a first selection gate line which is connected to one end of the memory cell, and the second memory block includes a second selection gate line in the same manner. An end portion of one end of the first selection gate line includes an L-shaped portion, and an end portion of one end of the second selection gate line includes a linear portion. A first contact is disposed on the L-shaped portion of the first selection gate. | 2015-03-05 |
| 20150060976 | NON-VOLATILE STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to an embodiment, a solid state storage device includes a first gate; a plurality of conductive layers having insulating layers therebetween, one of the insulating layers located on the first gate, an interconnection region extending inwardly of the first gate, a first semiconductor layer extending through the plurality of conductive layers and insulating layers, a second semiconductor layer extending through the plurality of conductive layers and insulating layers; a third semiconductor layer extending through the interconnection region and electrically connecting the first and second semiconductor layers, and an insulator extending through the plurality of conductive layers and insulating layers at a location intermediate of the first and second semiconductor layers, and also extending inwardly of the interconnection region. | 2015-03-05 |
| 20150060977 | SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL STRUCTURES - Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width. | 2015-03-05 |
| 20150060978 | SEMICONDUCTOR DEVICE - To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell. | 2015-03-05 |
| 20150060979 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel and gate electrodes. The channel extends in a vertical direction with respect to a top surface of a substrate. The gate electrodes are disposed on an outer sidewall of the channel. The gate electrodes includes a ground selection line (GSL), a word line, a string selection line (SSL) and a first dummy word line sequentially stacked from the top surface of the substrate in the vertical direction to be spaced apart from each other. The channel includes an impurity region at a portion adjacent to the SSL. | 2015-03-05 |
| 20150060980 | PROGRAMMABLE DEVICE AND METHOD OF MANUFACTURING THE SAME - A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench. | 2015-03-05 |
| 20150060981 | STACKED NANOWIRE - A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin. | 2015-03-05 |
| 20150060982 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film. | 2015-03-05 |
| 20150060983 | SEMICONDUCTOR STRUCTURE INCLUDING A SPLIT GATE NONVOLATILE MEMORY CELL AND A HIGH VOLTAGE TRANSISTOR, AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a nonvolatile memory stack provided above the active region, a control gate electrode provided above the memory stack, a select gate electrode at least partially provided above the active region adjacent to the memory stack and a select gate insulation layer. The high voltage transistor includes an active region, a gate electrode and a gate insulation layer provided between the active region and the gate electrode. The select gate insulation layer of the nonvolatile memory device and the gate insulation layer of the high voltage transistor are at least partially formed of a same high-k dielectric material. The select gate electrode of the nonvolatile memory device and the gate electrode of the high voltage transistor are at least partially formed of a same metal. | 2015-03-05 |
| 20150060984 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to embodiment, a nonvolatile semiconductor memory device, includes: a memory cell region; and a peripheral region, the memory cell region including: a semiconductor layer including semiconductor regions; control gate electrodes; a first insulating film; a semiconductor-containing layer having a smaller thickness than the first insulating film; and a second insulating film, the peripheral region including: the semiconductor layer; a third insulating film; the semiconductor-containing layer, and a periphery of the semiconductor-containing layer being surrounded by an element isolation region; the first insulating film provided on the semiconductor-containing layer; and a pair of conductive layers extending from a surface of the first insulating film to reach the third insulating film via the semiconductor-containing layer, and the pair of conductive layers being in contact with part of a lower surface of the semiconductor-containing layer. | 2015-03-05 |
| 20150060985 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, nonvolatile semiconductor memory device includes: a semiconductor layer; element regions separated the semiconductor layer, the element regions; and a memory cell including a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode provided above the element regions, a peripheral region including a resistance element including a resistance element layer provided above the semiconductor layer via a first insulating film, a dummy layer provided on a part of the resistance element layer via a second insulating film, a third insulating film provided on the resistance element layer at a first distance from the dummy layer, a fourth insulating film provided on the semiconductor layer at a second distance from the resistance element layer, and a contact piercing the third insulating film, and connected to the resistance element layer, the first distance being shorter than the second distance. | 2015-03-05 |
| 20150060986 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode. | 2015-03-05 |
| 20150060987 | FLASH MEMORY WITH P-TYPE FLOATING GATE - Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer. | 2015-03-05 |
| 20150060988 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer. | 2015-03-05 |
| 20150060989 | Split Gate Nanocrystal Memory Integration - A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates ( | 2015-03-05 |
| 20150060990 | TRANSISTORS, METHODS OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICES INCLUDING THE TRANSISTORS - Provided are transistors, methods of manufacturing the same, and electronic devices including the transistors. A transistor includes a channel layer having a multi-layer structure having first and second layers, the first and second semiconductor layers including a plurality of elements having respective concentrations, and the first layer is disposed closer to a gate than the second layer. The second layer has a higher electrical resistance than the first layer as a result of a combination of the elements and of their respective concentrations. At least one of the first and second layers includes a semiconductor material including zinc, oxygen, and nitrogen. One of the first and second layers includes a semiconductor material including zinc fluoronitride. An oxygen content of the second layer is higher than an oxygen content of the first layer. A fluorine content of the second layer is higher than a fluorine content of the first layer. | 2015-03-05 |
| 20150060991 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film. | 2015-03-05 |
| 20150060992 | SEMICONDUCTOR DEVICE, SYSTEMS AND METHODS OF MANUFACTURE - A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed. | 2015-03-05 |
| 20150060993 | NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND MEMORY MODULE AND SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer. | 2015-03-05 |
| 20150060994 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a non-volatile semiconductor memory device, includes: peripheral transistors including a second element isolation insulating film, a gate electrode, and a diffusion layer region, the second element isolation insulating film being configured to divide the semiconductor layer into at least two second semiconductor regions, the diffusion layer region being formed in the second semiconductor regions to be provided on two sides of the gate electrode; and a sidewall film provided at a side surface of the gate electrode. The second element isolation insulating film has a first portion and a second portion, the second portion is provided on two sides of the first portion, a width of a bottom portion of the first portion in an extension direction of the gate electrode is not more than twice a thickness of the sidewall film at a lower end of the sidewall film. | 2015-03-05 |
| 20150060995 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - Nonvolatile semiconductor storage device provided with first to fourth memory-cell unit each including a first select transistor, a second select transistor series connected to the first select transistor, a third select transistor, and memory-cell transistors series connected between the first and the second select transistors and the third select transistor. The memory-cell transistors have a stack structure including a charge storing layer and a control electrode above the charge storing layer via an insulating film. The first to third select transistors each has a stack structure substantially identical to the aforementioned stack structure. Threshold voltages of the first select transistors in the first and the fourth memory-cell unit and the second transistors in the second and third memory-cell unit differ from the threshold voltages of the second select transistors in the first and the fourth memory-cell unit and the first select transistors in the second and third memory-cell unit. | 2015-03-05 |
| 20150060996 | SEMICONDUCTOR DEVICE WITH SILICIDE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region. | 2015-03-05 |
| 20150060997 | SUSPENDED BODY FIELD EFFECT TRANSISTOR - A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor. | 2015-03-05 |
| 20150060998 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming, on a semiconductor substrate, a sacrificial semiconductor pillar having a pillar-like shape extending in a first direction perpendicular to a main surface of the semiconductor substrate, and being formed of a first semiconductor material. The method further includes forming, around the sacrificial semiconductor pillar, a channel semiconductor layer having a tube-like shape extending in the first direction, and being formed of a second semiconductor material different from the first semiconductor material. The method further includes removing the sacrificial semiconductor pillar after the channel semiconductor layer is formed. The channel semiconductor layer is formed on electrode layers via an insulator, the electrode layers being formed on the semiconductor substrate. | 2015-03-05 |
| 20150060999 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device may include: a drift layer having a first conductivity; a hole accumulating layer formed on the drift layer and having the first conductivity; a well layer formed on the hole accumulating layer and having a second conductivity; an emitter region formed in an internal portion of an upper portion of the well layer and having the first conductivity; and trench gates penetrating through the emitter region, the well layer, and the hole accumulating layer, and having a gate insulating layer formed on a surface thereof. The trench gate may be sequentially divided into a first gate part, a second gate part, and a third gate part from an upper portion thereof depending on a height of a material filled in the trench gate, the first to third gate parts having different resistances from each other. | 2015-03-05 |
| 20150061000 | PROCESS FOR FORMING A SHORT CHANNEL TRENCH MOSFET AND DEVICE FORMED THEREBY - A process for forming a short channel trench MOSFET. The process includes forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant is adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant is n-type material. | 2015-03-05 |
| 20150061001 | SEMICONDUCTOR DEVICE - A semiconductor device which includes a microfabricated transistor with buried gate electrodes. In the semiconductor device, a gate electrode is formed over a substrate, extending in the direction parallel to the first side of a device formation region. The gate electrode lies across the device formation region. A plurality of buried gate electrodes are buried in the device formation region of the substrate and in a plan view, the gate electrode partially overlap them. The buried gate electrodes extend obliquely to the first side of the device formation region and are parallel to each other. In each buried gate electrode, the first end opposite to the first side and the second end opposite to the second end of the device formation region are both parallel to the first side. | 2015-03-05 |
| 20150061002 | TRENCH MOSFET AND METHOD FOR FABRICATING THE SAME - The present disclosure relates to a trench MOSFET and a method for fabricating the same. The method comprises: providing a substrate with an epitaxy layer; forming a trench in the epitaxy layer; forming a first insulating layer, a first gate, a second insulating layer, and a second gate successively in the trench by deposition and etching; forming a well and a source region at both sides of the trench by ion implantation, and forming a trench-type contact and a metal plug. By forming the first gate and the second gate which are separated from each other, the first insulating layer between a lower portion of the first gate and the epitaxy layer has a thickness larger than that of the second insulating layer between the second gate and the well and the source region. The two separate gates are connected with each other by the metal plug. The resultant MOSFET has an increased breakdown voltage and stable performance while its manufacturer cost is lowered because the manufacturer process is simplified. | 2015-03-05 |
| 20150061003 | Power Semiconductor Package - A power semiconductor package includes a housing, a semiconductor chip embedded in the housing, and at least four terminals partially embedded in the housing and partially exposed to the outside of the housing. The semiconductor chip includes a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and a plurality of first trenches that includes gate electrodes and first field electrodes electrically insulated from the gate electrodes. A first terminal of the four terminals is electrically connected to the first metal layer, a second terminal of the four terminals is electrically connected to the second metal layer, a third terminal of the four terminals is electrically connected to the gate electrodes of the first trenches, and a fourth terminal of the four terminals is electrically connected to the first field electrodes of the first trenches. | 2015-03-05 |
| 20150061004 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates. | 2015-03-05 |
| 20150061005 | ASYMMETRIC SEMICONDUCTOR DEVICE - A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region. | 2015-03-05 |
| 20150061006 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region. | 2015-03-05 |
| 20150061007 | HIGH-VOLTAGE SUPER JUNCTION BY TRENCH AND EPITAXIAL DOPING - A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate. | 2015-03-05 |
| 20150061008 | LDMOSFET HAVING A BRIDGE REGION FORMED BETWEEN TWO GATE ELECTRODES - A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a stepped gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the stepped gate oxide layer. The stepped gate oxide layer includes a first gate oxide layer having a first thickness and a second gate oxide layer having a second thickness that is greater than the first thickness. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over the first gate oxide layer and a first portion of a channel region of the substrate, and a second portion forming a static gate formed over the second gate oxide layer and a second portion of the channel region. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate. | 2015-03-05 |
| 20150061009 | HIGH-VOLTAGE FIELD-EFFECT TRANSISTOR AND METHOD OF MAKING THE SAME - The high-voltage transistor device comprises a semiconductor substrate ( | 2015-03-05 |
| 20150061010 | STRUCTURE FOR IMPROVED CONTACT RESISTANCE AND EXTENSION DIFFUSION CONTROL - Semiconductor structures are provided including a raised source region comprising, from bottom to top, a source-side phosphorus doped epitaxial semiconductor material portion and a source-side arsenic doped epitaxial semiconductor material portion and located on one side of a gate structure, and a raised drain region comprising from bottom to top, a drain-side phosphorus doped epitaxial semiconductor material portion and a drain-side arsenic doped epitaxial semiconductor material portion and located on another side of the gate structure. | 2015-03-05 |
| 20150061011 | MOS TRANSISTOR - A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously. | 2015-03-05 |
| 20150061012 | HIGH UNIFORMITY SCREEN AND EPITAXIAL LAYERS FOR CMOS DEVICES - A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control. | 2015-03-05 |
| 20150061013 | LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR - A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer. | 2015-03-05 |
| 20150061014 | FIN PITCH SCALING AND ACTIVE LAYER ISOLATION - A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate. | 2015-03-05 |
| 20150061015 | NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES - Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins. | 2015-03-05 |
| 20150061016 | MULTI-HEIGHT SEMICONDUCTOR STRUCTURES - Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region. | 2015-03-05 |
| 20150061017 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming at least one gate structure over a plurality of fin structures. The method further includes removing dielectric material adjacent to the at least one gate structure using a maskless process, thereby exposing an underlying epitaxial layer formed adjacent to the at least one gate structure. The method further includes depositing metal material on the exposed underlying epitaxial layer to form contact metal in electrical contact with source and drain regions, adjacent to the at least one gate structure. The method further includes forming active areas and device isolation after the formation of the contact metal, including the at least one gate structure. The active areas and the contact metal are self-aligned with each other in a direction parallel to the at least one gate structure. | 2015-03-05 |
| 20150061018 | SPACERLESS FIN DEVICE WITH REDUCED PARASITIC RESISTANCE AND CAPACITANCE AND METHOD TO FABRICATE SAME - A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures. | 2015-03-05 |
| 20150061019 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Embodiments of the present invention provide methods of fabricating features of a semiconductor device array, the method including patterning a dielectric layer deposited on a conductive carrier, wherein patterning comprises forming a trench pattern defining at least one device contact, electrodepositing metal into the patterned trenches, transferring the dielectric layer and the electrodeposited metal to a substrate and removing the conductive carrier, and the method further comprising lithographically fabricating one or more further features of the semiconductor device array overlying the dielectric layer and electrodeposited metal. | 2015-03-05 |
| 20150061020 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate including a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug. | 2015-03-05 |
| 20150061021 | SEMI-CONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE - A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region. | 2015-03-05 |
| 20150061022 | MOS DEVICE HAVING SHALOW TRENCH ISOLATIONS (STI) WITH DIFFERENT TAPERED PORTIONS - A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a semiconductor device. The method includes forming a thermal oxide film and a silicon nitride film over the surface of a silicon substrate; forming an opening to the thermal oxide film and the silicon nitride film in each of the high withstand voltage region and the low withstand voltage region; etching the silicon substrate to form trenches; burying a buried oxide film in each of the trenches; removing the thermal oxide film and the silicon nitride film; and forming a thick gate oxide film and a thin oxide film. The depth of a tapered portion of the trench in the low withstand voltage region is shallower than that in the high withstand voltage region. | 2015-03-05 |
| 20150061023 | On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges - The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater. | 2015-03-05 |
| 20150061024 | Source and Drain Stressors with Recessed Top Surfaces - An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion. | 2015-03-05 |
| 20150061025 | MEMORY DEVICE - A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a plurality of memory elements, and a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned in a pith. The memory device further comprises a second contact positioned in the pith, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line. | 2015-03-05 |
| 20150061026 | Semiconductor Logic Circuits Fabricated Using Multi-Layer Structures - Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer is formed on a substrate and includes a first semiconductor device, the first semiconductor device including a first electrode structure. The second device layer is formed on the first device layer and includes a second semiconductor device, the second semiconductor device including a second electrode structure. The first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first electrode structure and the second electrode structure. | 2015-03-05 |
| 20150061027 | METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS - One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities. | 2015-03-05 |
| 20150061028 | TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate having a first region; and forming a first gate structure on a surface of the semiconductor substrate in the first region. The method also includes forming trenches in the semiconductor substrate at both sides of the first gate structure; and forming a first stress layer with one surface lower than the surface of the semiconductor substrate in the trenches. Further, the method includes forming a second stress layer containing carbon atoms with a surface leveling with or higher than the surface of the semiconductor substrate on the first stress layer; and forming a source region and a drain region in the semiconductor substrate at both sides of the first gate structure. | 2015-03-05 |
| 20150061029 | CMOS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for forming CMOS transistors. The method includes providing a semiconductor substrate having at least one first region and at least one second region; and forming a first gate in the first region and a second gate in the second region. The method also includes forming first offset spacers made of nitrogen-contained material on side surfaces of the first gate and the second gate; and forming dummy spacers on the first offset spacers in the first region and a dummy spacer material layer covering the second gate and the semiconductor substrate in the second region. Further, the method includes forming SiGe stress layers in the semiconductor substrate at both sides of the first gate; and removing the first offset spacers, the dummy spacers and the dummy spacer material layer. Further, the method also includes forming second offset spacers on the first gate and the second gate. | 2015-03-05 |
| 20150061030 | SEMICONDUCTOR STRUCTURE INCLUDING METAL SILICIDE BUFFER LAYERS AND METHODS OF FABRICATING THE SAME - Provided are semiconductor structures and methods of fabricating the same. The semiconductor structure includes a silicon substrate, at least one semiconductor layer that is grown on the silicon substrate and has a lattice constant in a range from about 1.03 to about 1.09 times greater than that of the silicon substrate, and a buffer layer that is disposed between the silicon substrate and the semiconductor layer and includes a metal silicide compound for lattice matching with the semiconductor layer. Related fabrication methods are also discussed. | 2015-03-05 |
| 20150061031 | Integrated High-K/Metal Gate In CMOS Process Flow - A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region. | 2015-03-05 |
| 20150061032 | FABRICATION OF NICKEL FREE SILICIDE FOR SEMICONDUCTOR CONTACT METALLIZATION - A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor. | 2015-03-05 |
| 20150061033 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate, which correspond to the dimensions of a sidewall pattern around a dummy pattern. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. N-type and P-type diffusion layers are in upper portions of the first and second fin-shaped layers, respectively, and in upper and lower portions of the first and second pillar-shaped layers, respectively. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers. | 2015-03-05 |
| 20150061034 | DEVICES HAVING INHOMOGENEOUS SILICIDE SCHOTTKY BARRIER CONTACTS - A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided having a plurality of transistors formed thereon, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region on the silicon including surface. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and n-type surface regions. | 2015-03-05 |
| 20150061035 | Semiconductor Devices, Transistors, and Methods of Manufacture Thereof - Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers. | 2015-03-05 |
| 20150061036 | NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum. | 2015-03-05 |
| 20150061037 | SYSTEM AND METHOD OF VARYING GATE LENGTHS OF MULTIPLE CORES - A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. | 2015-03-05 |
| 20150061038 | SEMICONDUCTOR DEVICE - The reliability of a power MISFET made of a nitride semiconductor material is improved. A strain relaxation film is disposed between a polyimide film and a gate electrode, to suppress a stress exerted on an electron supply layer and a channel layer from the polyimide film, and suppress a stress strain generated in the electron supply layer and the channel layer. As a result, a change in channel electron concentration in the channel layer is suppressed to prevent a threshold voltage or an on-resistance of the power MISFET from fluctuating. | 2015-03-05 |
| 20150061039 | SEMICONDUCTOR DEVICE HAVING SILICIDE ON GATE SIDEWALLS IN ISOLATION REGIONS - Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed. | 2015-03-05 |
| 20150061040 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 2015-03-05 |
| 20150061041 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench. | 2015-03-05 |
| 20150061042 | METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer. | 2015-03-05 |
| 20150061043 | COMPACT SENSOR MODULE - A compact sensor module and methods for forming the same are disclosed herein. In some embodiments, a sensor die is mounted on a sensor substrate. A processor die can be mounted on a flexible processor substrate. In some arrangements, a thermally insulating stiffener can be disposed between the sensor substrate and the flexible processor substrate. At least one end portion of the flexible processor substrate can be bent around an edge of the stiffener to electrically couple to the sensor substrate | 2015-03-05 |
| 20150061044 | SEQUENTIAL WAFER BONDING - Embodiments of methods of fabricating a sensor device includes attaching a first wafer to a sensor wafer with a first bond material, and attaching a second wafer to the sensor wafer with a second bond material, the second bond material having a lower bonding temperature than the first bond material. After attaching the second wafer, an opening (e.g., a trench cut) through the second wafer is formed, and an adhesive material is provided through the opening to further secure the second wafer to the sensor wafer. Embodiments of sensor devices formed using such methods include a first device cavity having a first pressure, and a second device cavity having a second pressure. | 2015-03-05 |
