10th week of 2009 patent applcation highlights part 57 |
Patent application number | Title | Published |
20090061592 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing the semiconductor device includes forming a first polysilicon film on an active region and an element isolation region made of a dielectric material provided in a semiconductor substrate; forming a hard mask on the first polysilicon film; etching the first polysilicon film, the semiconductor substrate in the active region and the dielectric material in the element isolation region by using the hard mask to form first and second gate trenches in the active region and the element isolation region, respectively; and filling the first and second gate trenches with a second polysilicon film before the hard mask is removed. | 2009-03-05 |
20090061593 | Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment - Methods and apparatus for re-using a semiconductor donor wafer in a semiconductor-on-insulator (SOI) fabrication process provide for: (a) subjecting a first implantation surface of a donor semiconductor wafer to an ion implantation process to create a first exfoliation layer of the donor semiconductor wafer; (b) bonding the first implantation surface of the first exfoliation layer to a first insulator substrate; (c) separating the first exfoliation layer from the donor semiconductor wafer, thereby exposing a first cleaved surface of the donor semiconductor wafer, the first cleaved surface having a first damage thickness; and (d) subjecting the first cleaved surface of the donor semiconductor wafer to one or more elevated temperatures over time to reduce the first damage thickness to a sufficient level to produce a second implantation surface. | 2009-03-05 |
20090061594 | METHOD OF DETACHING A THIN FILM BY MELTING PRECIPITATES - A method of fabricating a thin film from a substrate includes implantation into the substrate, for example made of silicon, of ions of a non-gaseous species, for example gallium, the implantation conditions and this species being chosen, according to the material of the substrate, so as to allow the formation of precipitates confined in a certain depth, distributed within a layer, these precipitates being made of a solid phase having a melting point below that of the substrate. The method optionally further including intimate contacting of this face of the substrate with a stiffener, and detachment of a thin film by fracturing the substrate at the layer of precipitates by applying a mechanical and/or chemical detachment stress under conditions in which the precipitates are in the liquid phase. | 2009-03-05 |
20090061595 | METHOD FOR DIVIDING A SEMICONDUCTOR SUBSTRATE AND A METHOD FOR PRODUCING A SEMICONDUCTOR CIRCUIT ARRANGEMENT - A method for dividing a semiconductor substrate involves providing a semiconductor substrate. At least one separating trench is produced at a front side of the semiconductor substrate. A layer is produced at least at the bottom of the at least one separating trench. The semiconductor substrate is thinned at a rear side of the semiconductor substrate at least as far as the layer at the bottom of the at least one separating trench. The layer is severed in order to divide the semiconductor substrate into individual pieces. | 2009-03-05 |
20090061596 | EXPANDING TOOL, EXPANDING METHOD, AND MANUFACTURING METHOD OF UNIT ELEMENTS - There is provided an expanding tool used for dividing a wafer on an expanding tape by applying a radial tensile force to the expanding tape. The expanding tool includes a dividing frame having a first opening, an outer expanding ring having a contact portion that can be made contact with the dividing frame, the contact portion being provided at an outer periphery side of the outer expanding ring, and having a second opening smaller than the first opening, and an inner expanding ring having an outer shape smaller than the second opening. | 2009-03-05 |
20090061597 | SINGULATOR METHOD AND APPARATUS - A method for the singulation of hybrid circuits from a pre-scribed plate containing hybrid circuits or made of other brittle materials. The method includes the steps of providing a platen used to support the hybrid plate and which has a surface comprised of a series of sections each angled downward from its adjacent section, aligning the plate on the platen so that the scribe lines align with the surface discontinuities at the angles between the sections, securing the plate to the platen with vacuum pressure, creating a pressure differential between a space above the plate and a space below the plate, and applying the pressure differential to sequentially break the plate along the pre-scribed lines by forcing the plate against the angles. | 2009-03-05 |
20090061598 | WAFER-LEVEL PACKAGING CUTTING METHOD CAPABLE OF PROTECTING CONTACT PADS - A cutting method for wafer-level packaging capable of protecting the contact pad, in which several cavities and precutting lines are formed at the front surface of a cap wafer, and the depth of each precutting line is lesser than the thickness of the cap wafer, followed by the bonding of the cap wafer to the device wafer, which has several devices and several bonding pads disposed on the surface of the device wafer, followed by performing a wafer dicing process, along the precutting lines cutting through the cap wafer, and after removing a portion of the cap wafer that is not bonded to the device wafer, for exposing the bonding pads at the surface of the device wafer, and finally performing a dicing process for forming many packaged dies. | 2009-03-05 |
20090061599 | SEMICONDUCTOR WAFER PROCESSING METHOD - A semiconductor wafer processing method for planarizing an additional layer formed on the front side of a semiconductor wafer. First, the wafer is held on a chuck table included in a cutting device in the condition where the additional layer is exposed, and a table base supporting the chuck table is moved toward a working position. In concert with the movement of the table base, the exposed surface of the additional layer is cut by a bit of a cutting tool rotationally driven by a spindle motor. Thereafter, the exposed surface of the additional layer is polished by a polishing device to planarize the exposed surface of the additional layer. | 2009-03-05 |
20090061600 | METHOD FOR REUSE OF WAFERS FOR GROWTH OF VERTICALLY-ALIGNED WIRE ARRAYS - Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide. | 2009-03-05 |
20090061601 | METHOD AND APPARATUS FOR IMPROVED PUMPING MEDIUM FOR ELECTRO-OSMOTIC PUMPS - Various embodiments of the present invention comprise systems and methods of fabricating porous silicon. One application of such porous silicon is in the fabrication of electro-osmotic pumps and electro-osmotic pump substrates. The method can comprise operations performed on a silicon wafer. A liner material can be deposited on the silicon wafer, and a photoresist layer can be deposited on the liner material. The photoresist layer can be adapted to define a predetermined pattern on the silicon wafer. Then, porous silicon can be formed on the silicon wafer according to the predefined pattern. As a result, solid silicon can support porous silicon regions of the silicon wafer, providing a support structure for the pumping medium. Other embodiments, aspects, and features are also claimed and described. | 2009-03-05 |
20090061602 | METHOD FOR DOPING POLYSILICON AND METHOD FOR FABRICATING A DUAL POLY GATE USING THE SAME - A method for doping polysilicon improves a doping profile during plasma doping and includes forming a silicon layer using two separate operations. After forming a first silicon layer, thermal annealing is performed to crystallize the first silicon layer, such that the uniformity of a doping concentration according to the depth of a layer inside is improved during plasma doping. Additionally, a doping concentration at the interface between a polysilicon layer and a gate oxide layer is increased. A by-product deposition layer is reduced, which is formed on the surface of a polysilicon layer due to the increase of a doping concentration in a polysilicon layer. As a result, the dopant loss, which is caused by the removing and cleansing of an ion implantation barrier used during doping, is reduced. | 2009-03-05 |
20090061603 | METHOD OF CRYSTALLIZING SEMICONDUCTOR FILM - A method of crystallizing a semiconductor film including splitting a pulse laser beam oscillated from a laser oscillator, and synthesizing the split pulse laser beams after the split pulse laser beams have propagated through optical paths different in optical path length, modulating the synthesized pulse laser beam into a pulse laser beam by a phase modulating element, and irradiating a non-single-crystal film formed on a substrate with the laser beam to crystallize the non-single-crystal film. Splitting the pulse laser beam and synthesizing the split pulse laser beams are performed using at least three optical splitting/synthesizing units arranged in order, and include sequentially splitting one pulse laser beam split by one optical splitting/synthesizing unit by succeeding splitting/synthesizing unit, and synthesizing the other pulse laser beam split by one optical splitting/synthesizing unit with the other pulse laser beam split by preceding splitting/synthesizing unit. | 2009-03-05 |
20090061604 | GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR - Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices. | 2009-03-05 |
20090061605 | PROFILE ADJUSTMENT IN PLASMA ION IMPLANTER - A method to provide a dopant profile adjustment solution in plasma doping systems for meeting both concentration and junction depth requirements. Bias ramping and bias ramp rate adjusting may be performed to achieve a desired dopant profile so that surface peak dopant profiles and retrograde dopant profiles are realized. The method may include an amorphization step in one embodiment. | 2009-03-05 |
20090061606 | METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT - The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well ( | 2009-03-05 |
20090061607 | METHOD OF MANUFACTURING PHOTOMASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a photomask has forming a laminate over a transparent substrate, the laminate having a light-shielding layer and a hard mask layer, forming a negative resist layer over the laminate, exposing and developing the negative resist layer over the laminate to form a first resist pattern having a main pattern in a main exposure area surrounded by an outer area, etching the hard mask layer using the first resist pattern as an etching mask to form a hard mask pattern, removing the first resist pattern from the laminate; forming a positive resist layer covering the hard mask pattern over the transparent substrate, exposing and developing the positive resist layer to form a second resist pattern, the second resist pattern and a light-shielding pattern disposed in the outer area and forming an opening disclosing the hard mask pattern. | 2009-03-05 |
20090061608 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SILICON DIOXIDE LAYER - A method of depositing a silicon dioxide layer for a semiconductor device. The method includes depositing the silicon dioxide layer to have a silicon concentration of greater than 30 atomic percent and a nitrogen concentration of less than 5 atomic percent. The depositing includes flowing nitric oxide gas with a silicon precursor over a substrate. In one example, the silicon precursor and nitric oxide are flowed over a substrate with the substrate being at a temperature in a range of approximately 600 to approximately 900 degrees Celsius. In one example, the silicon dioxide layer is formed on a layer including charge storage memory material. | 2009-03-05 |
20090061609 | METHODS OF FORMING NITRIDE READ ONLY MEMORY AND WORD LINES THEREOF - A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines. | 2009-03-05 |
20090061610 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a plate of semiconductor layer, an insulator layer formed on the plate of semiconductor layer and brought into contact with the plate of semiconductor layer by at least two adjacent faces, a thickness of the insulator layer in the vicinity of a boundary line between the two adjacent faces being larger than that of the insulator layer in a region other than the vicinity of the boundary line, and a band of conductor layer formed facing a middle portion of the plate-like semiconductor layer via the insulator layer. | 2009-03-05 |
20090061611 | FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL - A method for fabricating a dual layer gate electrode having a polysilicon layer and a workfunction metal layer comprises depositing a layer of a workfunction metal on a semiconductor substrate, depositing a layer of polysilicon on the workfunction metal layer, depositing a hard mask layer on the polysilicon layer, etching the hard mask layer to form a hard mask structure defining a gate electrode, etching the polysilicon layer to remove a portion of the polysilicon layer not protected by the hard mask structure, thereby forming a polysilicon structure beneath the hard mask structure, applying a mixture of ozone and water to exposed sidewalls of the polysilicon structure, thereby forming a silicon dioxide layer on the sidewalls, and etching the workfunction metal layer to remove a portion of the workfunction metal layer not protected by the hard mask structure, thereby forming a workfunction metal structure beneath the polysilicon structure. | 2009-03-05 |
20090061612 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench. | 2009-03-05 |
20090061613 | Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same - Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer. | 2009-03-05 |
20090061614 | METHOD FOR FORMING BUMPS ON UNDER BUMP METALLURGY - A method for forming a bump on under bump metallurgy according to the present invention is provided. A bonding pad is first formed on the active surface of a wafer. Subsequently, a passivation layer is formed on the active surface of the wafer and exposes the bonding pad. An under bump metallurgy is formed on the bonding pad. A layer of film is formed on the passivation layer and overlays the under bump metallurgy. Afterward, the portion of the film on the under bump metallurgy is exposed to a UV light and the exposed portion of the film is removed to expose the under bump metallurgy. A solder paste is applied to the under bump metallurgy and the remaining film on the wafer is removed. Finally, the solder paste is reflowed to form a spherical bump. | 2009-03-05 |
20090061615 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate, forming an insulation layer over the substrate, forming a photoresist pattern for a contact hole over the insulation layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD, forming a contact hole by selectively etching the insulation layer using the photoresist pattern, and forming a spacer on a sidewall of the contact hole until a CD of the contact hole whose sidewall is covered by the spacer is reduced to a desired contact CD. | 2009-03-05 |
20090061616 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device capable of minimizing hillocks and voids. The method includes subjecting an interlayer dielectric having a multi-protective dielectric structure including a first barrier metal layer and a first copper line to a plurality of NH | 2009-03-05 |
20090061617 | EDGE BEAD REMOVAL PROCESS WITH ECMP TECHNOLOGY - A method and apparatus for the removal of a deposited conductive layer along an edge of a substrate using a power ring configured to electro polish an edge of the substrate are provided. The electro polishing of the substrate edge may occur simultaneously with the electrochemical mechanical processing of a substrate face. In certain embodiments a method of electrochemically polishing a substrate having a conductive material disposed thereon is provided. A substrate is coupled with a carrier head comprising a power ring which surrounds an edge of the substrate, wherein the edge of the substrate includes the conductive material. A polishing pad is contacted with a face of the substrate. A first voltage is applied to the power ring to remove conductive material from the edge of the substrate. A second voltage different from the first voltage is applied to the polishing pad to remove a portion of the conductive material from the face of the substrate. | 2009-03-05 |
20090061618 | Method of Manufacturing Metal Interconnection - A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal layer. A sacrificial oxide layer can be formed on the IMD layer, and a planarization process can be performed on the sacrificial oxide layer and the IMD layer to substantially eliminate a height difference of the IMD layer. | 2009-03-05 |
20090061619 | METHOD OF FABRICATING METAL LINE - A method of fabricating a metal line of a semiconductor device that prevents formation of serrations in a metal line to thereby increase operational reliability of a semiconductor device. The method includes forming a lower metal line in a semiconductor substrate; and then forming a first nitride layer as an etching stop layer over the semiconductor substrate including the lower metal line; and then forming a first insulating layer over the first nitride layer; and then forming a second nitride layer over the first insulating layer; and then forming a contact hole partially exposing the uppermost surface of the lower metal line by performing a first etching process; and then simultaneously forming a second insulating layer over the second nitride layer and a void in the contact hole; and then forming a trench corresponding spatially to the contact hole and partially exposing the uppermost surface of the lower metal line by performing a second etching process. | 2009-03-05 |
20090061620 | Method of manufacturing a semiconductor device - Exuding of a interconnecting material to a substrate, which occurs because of a thinned state of and a beak in a barrier metal layer is prevented, irrespective of a laminated state of the barrier metal layer. In the present invention, a protective layer is formed on a side wall by using an insulating film or the like after the deposition of the barrier metal layer, whereby the interconnecting material can be prevented from exuding to the substrate due to influence of heat treatment such as alloying, irrespective of the laminated state of the side wall of the contact hole and the barrier metal layer. Further, the formation of the protective layer allows the side wall to be smoother to thereby improve coverage of the interconnecting material at the same time. | 2009-03-05 |
20090061621 | METHOD OF FORMING A METAL DIRECTLY ON A CONDUCTIVE BARRIER LAYER BY ELECTROCHEMICAL DEPOSITION USING AN OXYGEN-DEPLETED AMBIENT - By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices. | 2009-03-05 |
20090061622 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING LIFTING OF AMORPHOUS CARBON LAYER FOR HARD MASK - In a method for manufacturing a semiconductor device, a conductive layer is formed on a semiconductor substrate. A surface of the conductive layer is then treated by plasma. After the conductive layer is treated, an amorphous carbon layer for a hard mask is formed on the surface of the conductive layer that has been treated by the plasma. | 2009-03-05 |
20090061623 | METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE - A method of forming an electrical connection structure is described. A dielectric layer is formed covering a first conductor on a substrate, and then an opening is formed in the dielectric layer exposing the first conductor. A first cleaning step is conducted using fluorine-containing plasma to clean the surfaces of the dielectric layer and the exposed first conductor, and then at least one low-temperature annealing step is conducted. A second cleaning step is conducted using argon plasma to clean the above surfaces. A second conductor is then formed in the opening. | 2009-03-05 |
20090061624 | METHOD OF FABRICATING INTEGRATED CIRCUIT WITH SMALL PITCH - A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls. | 2009-03-05 |
20090061625 | LCD DRIVER IC AND METHOD FOR MANUFACTURING THE SAME - An LCD driver IC and a method for manufacturing the same. In one example embodiment, an LCD driver IC includes first and second main poly patterns formed separately from each other, a connection poly pattern connecting the main poly patterns, and a salicide blocking (SAB) pattern formed on the main poly patterns to block the main poly patterns. | 2009-03-05 |
20090061626 | Method of manunfacturing semiconductor device - Disclosed is a method for manufacturing a semiconductor device comprising forming a hydrophobic interlayer insulating film having a relative dielectric constant of 3.5 or less above a semiconductor substrate, forming a recess in the interlayer insulating film, depositing a conductive material above the interlayer insulating film having the recess to form a conductive layer, selectively removing the conductive material deposited above the interlayer insulating film by polishing to expose a surface of the interlayer insulating film while leaving the conductive material in the recess, and subjecting the surface of the interlayer insulating film having the recess filled with the conductive material to pressure washing using a resin member and an alkaline washing liquid containing an inorganic alkali and exhibiting a pH of more than 9. | 2009-03-05 |
20090061627 | METHOD FOR PRODUCING A METAL BACKSIDE CONTACT OF A SEMICONDUCTOR COMPONENT, IN PARTICULAR, A SOLAR CELL - The present invention relates to a method for manufacturing a backside contact of a semiconductor component, in particular, of a solar cell, comprising a metallic layer on the backside of a substrate in a vacuum treatment chamber, and the use of a vacuum treatment system for performing said method. Through this method and its use, in particular silicon based solar cells, can be provided with a back contact in a simple manner in a continuous process sequence, wherein the process sequence can be provided particularly efficient and economical, since no handling systems for rotating the substrate are required, and in particular silk screening steps can be dispensed with. | 2009-03-05 |
20090061628 | Laser trimming problem suppressing semiconductor device manufacturing apparatus and method - A semiconductor device manufacturing apparatus includes a substrate holding section that holds a semiconductor wafer substrate, a discharge mechanism that discharges liquid drops of metal paste from a discharge nozzle toward a surface of the semiconductor wafer substrate, and a driving mechanism that moves at least one of the substrate holding section and the discharge nozzle. A control section is provided to control the discharge and driving mechanisms so as to adhere the metal paste to the surface. The semiconductor wafer substrate includes a terminal unit formed from two or more electrically separated terminals connected to a device circuit and an insulation layer having an opening in a formation position of the terminal unit. Further, the control section controls the discharge and driving mechanisms to selectively coat the opening of the semiconductor wafer substrate with the metal paste overlying the terminal unit to be electrically connected. | 2009-03-05 |
20090061629 | METHOD OF FORMING A METAL DIRECTLY ON A CONDUCTIVE BARRIER LAYER BY ELECTROCHEMICAL DEPOSITION USING AN OXYGEN-DEPLETED AMBIENT - By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices. | 2009-03-05 |
20090061630 | Method for Chemical Mechanical Planarization of A Metal-containing Substrate - A method using an associated composition for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) is described. This method affords low dishing and local erosion levels on the metal during CMP processing of the metal-containing substrate. | 2009-03-05 |
20090061631 | GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT - Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide. | 2009-03-05 |
20090061632 | METHODS FOR CLEANING ETCH RESIDUE DEPOSITED BY WET ETCH PROCESSES FOR HIGH-K DIELECTRICS | 2009-03-05 |
20090061633 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming an insulating layer comprising silica-based insulating material, processing the insulating layer, hydrophobizing the insulating layer by applying a silane compound to act on the insulating layer; and irradiating the insulating layer with light or an electron beam. | 2009-03-05 |
20090061634 | Method for metallizing a pattern in a dielectric film - A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO | 2009-03-05 |
20090061635 | METHOD FOR FORMING MICRO-PATTERNS - A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed. | 2009-03-05 |
20090061636 | Etching method for nitride semiconductor - The invention discloses etching method for the nitride semiconductor. Firstly dielectric layer is formed on gallium nitride. The line pattern or dot pattern is formed on the dielectric layer by using the exposure, development, and etching processes. The dielectric layer is used as the mask for the epitaxial lateral overgrowth of follow-up gallium nitride layer. The thick gallium nitride film is grown on the dielectric layer. Then the wet etching process is used to remove the dielectric layer, and the thick gallium nitride film on the dielectric layer is etched to form the specific shape as required. | 2009-03-05 |
20090061637 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes: forming a first material film, a second material film, each having a function of preventing metal diffusion, and a third material film of which the etching rate for a first etchant is sufficiently lower than that of the first material film and the etching rate for a second etchant is sufficiently lower than that of the second material film, in this order on the outer peripheral surface of the semiconductor substrate; forming a trench structure; forming a buried insulating film and flattening it; removing the second material film through a wet etching process using the second etchant until the first material film formed on the main surface side is exposed; and removing the first material film on the main surface side through a wet etching process using the first etchant until the semiconductor substrate is exposed on the main surface side. | 2009-03-05 |
20090061638 | METHOD FOR FABRICATING MICROPATTERN OF SEMICONDUCTOR DEVICE - A method for fabricating a micropattern of a semiconductor device is provided. The method includes forming a first hard mask over an etch target layer, forming a first sacrificial layer over the first hard mask, etching the first sacrificial layer to form a sacrificial pattern and forming spacers on both sidewalls of the sacrificial pattern, A second sacrificial layer is formed over the spacers and the first hard mask. A dummy mask is formed in a bent portion of the second sacrificial layer between the adjacent spacers. The sacrificial pattern and the second sacrificial layer are etched using the dummy mask and the spacers as an etch barrier layer to form a dummy pattern between the adjacent spacers. The first hard mask is etched using the spacers and the dummy pattern as an etch barrier layer to form a first hard mask pattern. | 2009-03-05 |
20090061639 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes stacking a spin on carbon (SOC) layer and an multifunction hard mask (MFHM) layer on a substrate, forming a photoresist pattern over the MFHM layer, first etching the MFHM layer using a first amount of a fluorine-based gas, second etching the MFHM layer using a second amount of a fluorine-based gas, wherein the second amount is less than the first amount, etching the SOC layer using the MFHM layer as an etch barrier, and etching the substrate using the SOC layer and the MFHM layer as an etch barrier. | 2009-03-05 |
20090061640 | Alternate gas delivery and evacuation system for plasma processing apparatuses - A gas distribution system for supplying a gas mixture to a plasma process chamber is provided. A first valve arrangement is connected to upstream ends of a first gas line and a second gas line. A second valve arrangement is connected to downstream ends of the first gas line and the second gas line. A first gas distribution outlet line is connected between a gas supply and the first valve arrangement and a first chamber inlet line connected between the second valve arrangement and the plasma process chamber. A first evacuation line is connected to the first gas line at a location between the first valve arrangement and the second valve arrangement. A second evacuation line is connected to the second gas line at a location between the first valve arrangement and the second valve arrangement. The first evacuation line and second evacuation line are in fluid communication with a vacuum line. A controller is operable to actuate the first valve arrangement and second valve arrangement to selectively flow the gas mixture from the gas supply to the plasma process chamber through the first gas line while the second gas is selectively evacuated by the vacuum line; or to selectively flow the gas mixture from the gas supply to the plasma process chamber through the second gas line while the first gas line is selectively evacuated by the vacuum line. | 2009-03-05 |
20090061641 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming micro patterns, an etch target layer, a hard mask layer, a silicon-containing bottom anti-reflective coating (BARC) layer, and first auxiliary patterns are formed over a semiconductor substrate. The silicon-containing BARC layer is etched to form silicon-containing BARC patterns. Insulating layers are formed on a surface of the silicon-containing BARC patterns and the first auxiliary patterns. A second auxiliary layer is formed on the hard mask layer and the insulating layers. An etch process is performed such that the second auxiliary layer remains on the hard mask layer between the silicon-containing BARC patterns thereby forming second auxiliary patterns. The insulating layers on the first auxiliary patterns and between the silicon-containing BARC patterns and the second auxiliary patterns are removed. The hard mask layer is etched thereby forming hard mask patterns. The etch target layer is etched using the hard mask patterns as an etch mask. | 2009-03-05 |
20090061642 | NOZZLE ASSEMBLY, APPARATUS FOR SUPPLYING PROCESSING SOLUTIONS HAVING THE SAME AND METHOD OF SUPPLYING PROCESSING SOLUTIONS USING THE SAME - In a nozzle assembly for supplying processing solutions, the nozzle assembly includes a housing, a plurality of supply units arranged in the housing and through which different processing solutions flow onto the substrate, and a plurality of nozzles connected to the supply units, respectively, in such a configuration that a first nozzle selected from the nozzles is directed to the substrate and the remaining nozzles excluding the first nozzle are directed away from the substrate. Accordingly, the mechanical structure of the nozzle assembly may be simplified and the nozzles directed away from the substrate may be prevented from being contaminated by the processing solutions that are injected onto the substrate through the nozzle directed to the substrate. | 2009-03-05 |
20090061643 | SUBSTRATE PROCESSING METHOD AND RECORDING MEDIUM - A substrate processing method using a substrate processing apparatus including: a process container holding a substrate to be processed therein; first gas supplying means having flow rate adjusting means for supplying a first process gas to the process container; and second gas supplying means supplying a second process gas to the process container, the substrate processing method including: a first step of controlling a flow rate of the first process gas to be a first flow rate by the flow rate adjusting means and supplying the first process gas in a first direction; a second step of discharging the first process gas from the process container; a third step of supplying the second process gas to the process container; and a fourth step of discharging the second process gas from the process container, in a repeated manner, wherein a step of stabilizing the flow rate of the process gas is set between a primary first step and a secondary first step performed subsequently to the primary first step. | 2009-03-05 |
20090061644 | VAPOR BASED COMBINATORIAL PROCESSING - A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings. | 2009-03-05 |
20090061645 | SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS LATERALLY ENCLOSED BY INTERLAYER DIELECTRIC MATERIAL HAVING INCREASED INTRINSIC STRESS - By appropriately treating an interlayer dielectric material above P-channel transistors, the compressive stress may be significantly enhanced, which may be accomplished by expanding the interlayer dielectric material, for instance, by providing a certain amount of oxidizable species and performing an oxidation process. | 2009-03-05 |
20090061646 | VAPOR BASED COMBINATORIAL PROCESSING - A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings. | 2009-03-05 |
20090061647 | CURING METHODS FOR SILICON DIOXIDE THIN FILMS DEPOSITED FROM ALKOXYSILANE PRECURSOR WITH HARP II PROCESS - Methods of curing a silicon oxide layer on a substrate are provided. The methods may include the processes of providing a semiconductor processing chamber and a substrate and forming an silicon oxide layer overlying at least a portion of the substrate, the silicon oxide layer including carbon species as a byproduct of formation. The methods may also include introducing an acidic vapor into the semiconductor processing chamber, the acidic vapor reacting with the silicon oxide layer to remove the carbon species from the silicon oxide layer. The methods may also include removing the acidic vapor from the semiconductor processing chamber. Systems to deposit a silicon oxide layer on a substrate are also described. | 2009-03-05 |
20090061648 | Method of manufacturing semiconductor device and substrate processing apparatus - A method of manufacturing a semiconductor device includes the steps of loading a substrate into a processing chamber; processing the substrate by supplying plural kinds of reaction substances into the processing chamber multiple number of times; and unloading the processed substrate from the processing chamber, wherein at least one of the plural kinds of reaction substances contains a source gas obtained by vaporizing a liquid source by a vaporizing part; in the step of processing the substrate, vaporizing operation of supplying the liquid source to the vaporizing part and vaporizing the liquid source is intermittently performed, and at least at a time other than performing the vaporizing operation of the liquid source, a solvent capable of dissolving the liquid source is flown to the vaporizing part at a first flow rate; and at a time other than performing the vaporizing operation of the liquid source and every time performing the vaporizing operation of the liquid source prescribed number of times, the solvent is flown to the vaporizing part at a second flow rate larger than the first flow rate. | 2009-03-05 |
20090061649 | LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT - A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking —(CH | 2009-03-05 |
20090061650 | SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved. | 2009-03-05 |
20090061651 | Substrate processing apparatus and method for manufacturing semiconductor device - A substrate processing apparatus comprising: a reaction tube that processes a substrate; a support portion that supports the substrate in the reaction tube; a process gas supply line that supplies a process gas into the reaction tube; and an exhaust line that exhausts an inside of the reaction tube, wherein the process gas is supplied into the reaction tube to form a silicon nitride film on the substrate, at least the reaction tube is made of quartz, a plurality of projections are provided on the inner wall of the reaction tube, and the diameter of the projections is larger than 2 μm but smaller than 86 μm. | 2009-03-05 |
20090061652 | Pick up cap for use with socket connector having plug covering opening - A socket connector has a pick up cap ( | 2009-03-05 |
20090061653 | Connector unit and connector thereof - A connector unit comprises a case, a substrate and a connector. The case is formed with an opening. The substrate is installed within the case and is formed with a signal conductive pattern and a ground conductive pattern. The ground conductive pattern is electrically connected to the case. The connector comprises a contact, an outer conductor and a high impedance member. The outer conductor is electrically connected to the ground conductive pattern. The outer conductor is insulated from the contact but covers, at least in part, the contact. The contact is electrically connected to the signal conductive pattern. The high impedance member has high impedance in a high frequency range. The high impedance member is positioned between the outer conductor and the case within the opening of the case. For example, the high impedance member is an electric wave absorber. | 2009-03-05 |
20090061654 | Socket with bolt - A socket, for electrically connecting an IC package and a printed circuit board, comprises a base received with a plurality of contacts, a stiffener surrounding the base and bolts mounting the socket to the printed circuit board. The stiffener has a horizontal plate, which has engaging holes by drawing, so the engaging hole has a sidewall extending beyond the horizontal plate to keep the bolt in the engaging hole of the stiffener. | 2009-03-05 |
20090061655 | CONNECTOR - To provide a connector that enhances the reliability of connection between the ground and a shield constituting a shell. A socket constitutes the connector together with a header which is mounted on a different printed wiring board. The socket includes a socket body which is provided with a connection recess, a plurality of socket contacts which are held by the socket body, and a pitch direction shield and a terminal direction shield constituting the shell which surround the connection recess and which prevents electromagnetic noise from coming in and out. The pitch direction shield and the terminal direction shield are provided with terminals soldered to conductive pattern of the ground. | 2009-03-05 |
20090061656 | BOARD-TO-BOARD CONNECTOR - A thin board-to-board connector with high density in which there is no connection between three-dimensional complex metal springs. The board-to-board connector ( | 2009-03-05 |
20090061657 | HOLDER FOR A FLEXIBLE CIRCUIT BOARD - A holder with a device for holding a flexible circuit board is provided. The holder comprises at least one further device for holding at least one component such that the component may be electrically connected to or disconnected from the circuit board. | 2009-03-05 |
20090061658 | ELECTRICAL CONNECTING APPARATUS - The electrical connecting apparatus comprises: a wiring base plate having a first surface provided with a plurality of first conductive portions; a probe base plate having a second surface provided with a plurality of second conductive portions with its second surface opposed to the lower surface; a plurality of screws for removably coupling the wiring base plate and the probe base plate; and a connecting device for electrically connecting the first and second conductive portions. | 2009-03-05 |
20090061659 | THROUGH-HOLE INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR WAFER - A through-hole interconnection structure for a semiconductor wafer in which plural wafers are bonded together each having a substrate with devices provided thereon, an electrical signal connecting section is provided on a bonding surface of each wafer, the bonding surface being for bonding with other wafers, and the electrical signal connecting section is electrically connected to an electrical signal connecting section provided on another of the oppositely-facing wafers to form a desired semiconductor circuit, the through-hole interconnection structure being provided with: a through-hole interconnection section which has a through-hole protruding section which protrudes from the bonding surface to conduct the opposite surfaces of the wafer, the through-hole interconnection section being one of the oppositely-facing electrical signal connecting sections; and a bump which is the other of the oppositely-facing electrical signal connecting sections, wherein: the through-hole protruding section has an oppositely-placed pair of wiring side walls which extend from the bonding surface toward the another wafer; an end of the through-hole interconnection section is extended to reach an inside of the bump; and the bump is placed between the pair of wiring side walls. | 2009-03-05 |
20090061660 | Connection structure between wired circuit boards - The connection structure between wired circuit boards connects a first wired circuit board and a second wired circuit board. The first wired circuit board includes a metal supporting layer, a first insulating layer formed on the metal supporting layer, and a first conductive pattern formed on the first insulating layer and having a first terminal portion. The metal supporting layer is arranged so as not to be opposed to the first terminal portion in a thickness direction. The first terminal portion and the first insulating layer opposed to the first terminal portion in a thickness direction are folded back into a curved shape. The second wired circuit board includes a second insulating layer, and a second conductive pattern formed on the second insulating layer and having a second terminal portion. The first terminal portion and the second terminal portion are electrically connected to each other. | 2009-03-05 |
20090061661 | MEZZANINE-TYPE ELECTRICAL CONNECTORS - Embodiments of electrical connectors include substantially identical first and second halves. The first and second halves each include insert molded leadframe assemblies that comprise electrical conductors. Each electrical conductor of the first half engages a substantially identical electrical conductor of the second half when the first and second halves are mated. | 2009-03-05 |
20090061662 | CONNECTOR - A connector having a number of SMT pads and a number of in-line package pins is provided. The connector can be applied to both a peripheral component interconnection (PCI) card and a peripheral component interconnection express (PCIE) card. The number of the connectors can be reduced when the connectors are applied to the circuit board, and more space on the circuit board are then available for other electrical elements to be disposed. | 2009-03-05 |
20090061663 | ELECTRONIC DEVICE WITH GROUNDING MECHANISM - A grounding mechanism ( | 2009-03-05 |
20090061664 | GROUNDING ONE OR MORE CABLES - An apparatus is for grounding one or more cables, each cable having a cable jacket surrounding an electrically conductive layer that includes an exposed portion not covered by the cable jacket. The apparatus includes an electrically conductive enclosure coupled to a ground potential and having an opening therethrough, a plurality of electrical conductors disposed across the opening to form a lattice, and an electrically conductive connection. The lattice is configured to receive the one or more cables therethrough such that the exposed portion of the electrically conductive layer of each cable makes electrical contact with at least one of the electrical conductors. The connection is electrical coupled to the lattice and the enclosure such that the electrically conductive layer of each cable received through the lattice is electrically coupled to the ground potential through the lattice, the connection, and the enclosure. | 2009-03-05 |
20090061665 | Powered external serial advancement technology attachment socket - A powered external serial advancement technology attachment (eSATA) socket has a front and a chamber formed in the front of the socket and having multiple eSATA terminals and a power supply assembly. The eSATA terminals are formed on and protrude from the inner surface of the chamber. The power supply assembly has multiple feet formed on and protruding from the inner surface of the chamber and connected electrically to a power source. Therefore, supplementary power wires or plugs are unnecessary when using the powered eSATA socket that is therefore more convenient and promotes widespread application of eSATA technology. | 2009-03-05 |
20090061666 | ELECTRONIC DEVICE HAVING FOLDABLE PLUG - An electronic device includes a casing, a plug, a fixing plate, a circuit board and a first retaining part. The casing has a support member and multiple perforations. The plug has a rotating shaft and multiple pins. The pins are mounted on the rotating shaft. The rotating shaft is pivotally supported on the support member such that the pins are rotatable with respect to the rotating shaft. The pins are substantially perpendicular to the casing when the pins are rotated to a first position. The pins are received in the perforations when the pins are rotated to a second position. The fixing plate is disposed on the support member. The circuit board includes multiple contact elements corresponding to the pins. The first retaining part is engaged with or sustained against an engaging part of the rotating shaft, thereby positioning the pins of the plug in the first position. | 2009-03-05 |
20090061667 | Electrical Plug Adaptor - An electrical plug adapter has a plug body, female receptacles in one surface of the plug body, and male prongs extending from another surface of the plug body. The adapter has a male catch mechanism associated with a latching prong of the male prongs. The male catch mechanism is resiliently biased to a catch position relative to the latching prong. An actuator on the plug body can be moved to selectively move the latch mechanism to a release position closer to the latching prong. The male catch mechanism includes a portion configured to catch on an object in a standard electrical outlet when the male prongs are inserted into corresponding receptacles in the standard electrical outlet. | 2009-03-05 |
20090061668 | Pass-through grounding plug - An electrical connector and a method of use of the electrical connector during installation of an Optical Network Terminal (ONT). The ONT includes a power supply unit having a pass-through grounding plug. The pass-through grounding plug includes an electrically-conductive grounding prong that is operable to engage a ground conductor of an electrical component. For installation purposes, for example, using existing home wiring, the grounding prong may be retractable, removable and foldable into a body of the plug. When installing the ONT, one would determine whether a power source to which a power supply unit of the ONT is to be connected is within a predetermined distance from an installation location of the ONT. Further, one would determine whether the power source includes a ground conductor. In instances where there is not a ground conductor, the grounding prong may be removed, folded, or retracted into the body of the plug. | 2009-03-05 |
20090061669 | Connecting system with direct plug connection - A plug-in connector arrangement includes a terminal block containing a chamber in which are mounted a horizontal bus bar having a transverse wall, and a resilient contact having a fixed horizontal leg portion, an intermediate portion bent upwardly from the first leg portion, and an outwardly biased second leg portion reversely bent back above the first leg portion. The second leg portion contains a clamping end portion that extends through a conductor opening contained in the first leg portion. The clamping portion includes at least two discrete clamping surfaces so arranged that when a bare conductor is inserted into the conductor opening, the conductor circumferential surface is selectively engaged by one or more of the clamping surfaces in accordance with the diametrical size of the conductor. The conductor is biased by the clamping portion toward electrical engagement with the bus bar transverse wall. | 2009-03-05 |
20090061670 | Electrical card connector - An electrical card connector for receiving a card, comprises an insulative housing having a supporting surface with a front end and a rear end; a plurality of contacts assembled in the housing and oriented toward the rear end; a switch terminal arranged in the rear end. Each contact has at least a contact engaging portion extending above the supporting surface; one of the contact engaging portions engaged with the switch terminal when a card is inserted, and electrically separated from each other when the card is removed. | 2009-03-05 |
20090061671 | ELECTRICAL CONNECTOR WITH A PAIR OF IMPROVED DETACTING PINS - An electrical connector includes an insulating housing defining a base portion and a tongue portion extending forwards from a front face of the base portion, a plurality of terminals and a pair of detecting pins having a moveable pin and an immoveable pin. Each terminal defines a contacting portion located on the bottom face of the tongue portion and a solder leg extending towards a bottom face of the base portion. The two pins respectively define a contacting section spaced from and mating with each other and a leg section spaced from each other. The moveable pin defines an arc section projecting forwards beyond the front face of the tongue portion. | 2009-03-05 |
20090061672 | COVER ATTACHING STRUCTURE, HOUSING AND COVER - A cover attaching structure in a connector includes: first and second locking portions provided on a first attaching member; and third and fourth locking portions provided on a second attaching member which is attached to the first attaching member. The first locking portion is locked on the third locking portion from an outer surface side of the connector. The second locking portion is locked on the fourth locking portion from an inner surface side of the connector. | 2009-03-05 |
20090061673 | IC Socket - An IC socket comprises a base, a cover moveably mounted to the base, and an actuating mechanism driving the cover to move between a first position and a second position. The base includes a plurality of passageways and at least a rib extending upwardly from a top surface. The cover defines a hole corresponding to the rib and has a plurality of apertures corresponding to the passageways. | 2009-03-05 |
20090061674 | CARD CONNECTOR - A card connector includes a housing, a base, a slidable member, three of which are provided in the base and define a receiving chamber for receiving a memory card thereamong, and a spring. A tongue is provided on a sidewall of the housing. The memory card has a locating recess formed at one side thereof corresponding to the tongue. The slidable member includes a recession formed on a sidewall thereof corresponding to the tongue, and an opening cut through the sidewall and in communication with the recession. A hooked member is provided in the recession. The recession is provided with a first matching portion, and the hooked member has a second matching portion for joint with the first matching portion. Therefore, the card connector is structurally simple, of secure locking, and can effectively engage and prevent an electronic card inserted therein from falling-off. | 2009-03-05 |
20090061675 | Video signal transmitting device for computer system having analog and digital video signal output functionality - A video signal transmitting device having analog and digital video signal output functionality is adapted to transmit a video signal, and has a cable unit, a digital visual interface integrated input port disposed at one end of the cable unit and adapted to receive the video signal, and a digital visual interface output port and an analog video signal output port disposed at the other end of the cable unit. The digital visual interface integrated input port has a first pin set for digital video signals, and a second pin set for analog video signals. The digital visual interface output port is connected to the first pin set through the cable unit, and the analog video signal output port is connected to the second pin set through the cable unit so as to achieve an effect of respectively outputting digital video signals and analog video signals. | 2009-03-05 |
20090061676 | ELECTRONIC APPARATUS - According to an aspect of the present invention, there is provided an electronic apparatus including: a housing; a circuit board that is housed in the housing; a connector that is mounted on the circuit board and has a jack opening disposed to be exposed from the housing; and an LED unit that is detachably installed on the connector. | 2009-03-05 |
20090061677 | COMPUTER HOUSING CAPABLE OF RETRACTING HEADPHONE CABLE - A computer housing is provided. The computer housing includes a front panel with an opening formed thereon. A cable winding assembly is disposed within the computer housing and includes a stop member, a cable winding member, two support members, and an elastic rope. The cable winding member includes a jack receiving hole and at least one stop member receiving means formed on an outer circumferential surface thereof for accommodating a headphone jack and the stop member respectively. The stop member can be inserted through the opening. The two support members are attached to a bottom panel of the computer housing and include bearing holes formed threreon for supporting the cable winding member and allowing a rotation of the cable winding member. The elastic rope includes two ends fastened respectively to the cable winding member and one of the support members and is capable of being wound when the cable winding member rotates. | 2009-03-05 |
20090061678 | Smart Cables - A smart cable apparatus includes resources that provide for additional functionality such as cable authentication and cable identification. The cable apparatus can be configured for coupling an electronic device such as a media player to other electronic devices such as media player accessories. The cable apparatus includes one or more processing components that can be integrated as part of the cable apparatus. The one or more processing components can be configured to identify the type of signal the cable apparatus is intended to carry, and to communicate that information to the electronic device to which it is connected. The one or more processing components can also be configured to process authentication inquires to indicate whether the cable apparatus is an authorized accessory for the electronic device. | 2009-03-05 |
20090061679 | INSULATING METER JAW GUIDE FOR A WATT-HOUR METER SOCKET - The invention provides an insulating meter jaw guide featuring a loop belt, a retaining fastener, a meter blade receiving slot, and a cavity housing. The insulating meter jaw guide may be positioned on a meter jaw of watt-hour meter socket, effectively covering the receiving end of a meter jaw or a meter jaw assembly, therefore, protecting the meter jaw from accidental contact by a meter cover or the like. | 2009-03-05 |
20090061680 | Adjustable feed through bushing base with lifting means - This invention relates to providing a means to removeably mount a feed through/grounding bushing commonly used to bond together, ground and/or park power distribution cables. Many pieces of power distribution equipment have U brackets for removable attachment of accessories and temporary placed maintenance equipment. The present invention addresses holding the bushing at an angle relative to the U bracket and surrounding surface and adjustability of the bushing height relative to the U bracket for strain relief and adjusting for improved work room. Also addressed is the advantage of cable identification by numbering the wells so that a lineman may readily select the cables even after the bushing may have been set aside for equipment replacement. This is especially useful on but not limited to this invention since the U bracket mounting means is moveable and would not always provide positive identification of one end of a multi well bushing. Also provided is a means to receive a lifting means to assist in lifting and positioning the assembly especially for higher kilovolt applications. Further provided is the method of grounding the lines of a multi phase system on a common bushing in order that a lineman can rely that the entire phase system is grounded and is gives rapid visual confirmation. | 2009-03-05 |
20090061681 | ELECTRICAL RECEPTACLE ASSEMBLY - A receptacle assembly for use in connecting an energy source to an energy delivering device is described herein. The receptacle assembly includes a face plate defining an aperture. The receptacle also includes an adapter assembly including an adapter plate, supporting a terminal that is operatively connected to the energy source. Additionally, the receptacle includes a spacer member interposed between an inner surface of the aperture of the face plate and an outer surface of the adapter plate, wherein the spacer member permits omni-directional movement of the adapter plate and terminal relative to the face plate. | 2009-03-05 |
20090061682 | COAXIAL CONNECTOR HAVING DETACHABLE LOCKING SLEEVE - A connector is provided for terminating coaxial cable. The connector includes a connector body having a cable receiving end and an opposed connection end. A locking sleeve is provided in detachable, re-attachable snap engagement with the insertion end of the connector body for securing the cable in the connector body. The cable may be terminated to the connector by inserting the cable into the locking sleeve or the locking sleeve may be detachably removed from the connector body and the cable inserted directly into the cable body with the locking sleeve detached subsequently. | 2009-03-05 |
20090061683 | EMI SHIELDING/ELECTRICAL GROUNDING MEMBERS - Exemplary embodiments are provided of EMI shielding/electrical grounding members configured to be installed to a substrate for interposition between electrically-conductive surfaces, for establishing electrical grounding contact from the substrate to the electrically-conductive surfaces. In one exemplary embodiment, an EMI shielding/electrical grounding member generally includes first and second generally opposing sides hingedly connected and having respective first and second contact faces configured such that the first and second contact faces are each relatively independently operable and freely compressible upon contact with the respective first and second electrically-conductive surfaces, regardless of whether the other of said first and second contact faces is in contact with the corresponding first or second electrically-conductive surface. | 2009-03-05 |
20090061684 | MIDPLANE ESPECIALLY APPLICABLE TO AN ORTHOGONAL ARCHITECTURE ELECTRONIC SYSTEM - A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line. | 2009-03-05 |
20090061685 | DUAL CONNECTOR FOR AN ANTENNA ELEMENT - Two connection interfaces are combined in a single assembly for high frequency signal propagation of a GPS antenna. At least one connection interface is a constant impedance connector. The connector assembly allows for the application of o-rings and gaskets to be placed circumferentially about the radome to protect against environmental elements, mechanical shock and vibration. The first connection interface has a male plug on a first piece of a dual connector design, and a complementary female plug on a second piece. The second connection interface comprises a plug of any standard industry connector mounted on the second piece opposite the complementary female plug, and is configured to easily mate to a corresponding plug from a cable or other electronic equipment. | 2009-03-05 |
20090061686 | Connector and information processing apparatus - The present invention provides a connector in which countermeasures against external noise and radiation noise are taken, and an information processing apparatus having such a connector, which suppresses both the external noise and radiation noise. The connector is disposed at an opening formed in an outer face of an information processing apparatus such that the connector does not project from the outer face, a shield cable being connected to the connector from the opening. An end face on the side of the opening is made of an insulative material. The connector includes a signal terminal which connects a signal line of the shield cable and a processing circuit of the information processing apparatus with each other and which is provided at a location other than the end face, and a shield conductor which connects a shield of the shield cable and a ground of the information processing apparatus with each other and which is provided at a location other than the end face. | 2009-03-05 |
20090061687 | CONNECTOR PLUG - According to one embodiment, a connector plug includes a plug housing, a head terminal movably attached to a distal end portion of the plug housing, a fixed terminal arranged in the plug housing and electrically connected to a power cord, a cartridge fuse located between the head terminal and the fixed terminal in the plug housing, and a connecting member located between the cartridge fuse and the fixed terminal. The connecting member has a spring portion, which is located between the cartridge fuse and the fixed terminal and urges the cartridge fuse toward the head terminal, and a continuation portion, which extends from an end of the spring portion on the cartridge fuse side, extends straight or in a curve, and is electrically connected to the power cord. | 2009-03-05 |
20090061688 | Card-type peripheral device - A card-type peripheral device includes an electronic component disposed in a case, and a terminal part including connection terminals connectable with a to-be-connected device, wherein a function of the electronic component and the number of terminals of the terminal part are maintained to be compatible with those of the to-be-connected device, and the outside dimensions of the case are set to be smaller than the outside dimensions of the to-be-connected device and greater than the outside dimensions of a predetermined small-size card. | 2009-03-05 |
20090061689 | ELECTRICAL CONNECTOR - An electrical connector for engaging with an electronic card has a insulative housing with a plurality of receiving spaces, a plurality of terminals respectively mounted in the receiving spaces of the insulative housing, and an operating member pivotally connected to the insulative housing. The operating member controls the terminals in the insulative housing to be moved for electrically and mechanically engagement with the electronic card. Each of the terminals has a base portion, an upper arm and a lower arm. The upper arm is connected to the base portion at a joint as a first fulcrum. The lower arm is connected to the base portion at another joint as a second fulcrum. As the operating member pivotally moves to a predetermined position, the upper arm and the lower arm respectively rotate about the first fulcrum and the second fulcrum to securely grasp the electronic card. | 2009-03-05 |
20090061690 | APPARATUS WITH DETACHABLY CONNECTED MEMORY-CARD TYPE ADAPTER - An electronic apparatus is provided at one side with an adapting plate, on at least one side surface of which there is provided connecting lines, and a memory-card type adapter is detachably connected to the apparatus through engagement of a socket provided at a front end of the adapter with the adapting plate on the apparatus. Elastic contact terminals are provided in the socket to electrically connect to the connecting lines on the adapting plate. The apparatus is adapted to plug in any type of memory-card socket provided on a computer through detachable engagement of the adapting plate on the apparatus with one memory-card type adapter that corresponds to the memory-card socket on the computer. | 2009-03-05 |
20090061691 | FUSE MODULE WITH MOVABLE FUSE HOLDER FOR FUSED ELECTRICAL DEVICE - Described herein are various embodiments of a fuse module for fused electrical devices. According to one exemplary embodiment, a fuse module is mounted to the housing of a fused electrical device. The fused electrical device can include at least one power output displaced along the power distribution housing with the at least one power output electrically couplable to at least one power input. The fuse module can be electrically coupled to the at least one power input and electrically couplable to the at least one power outputs. Further, the fuse module can comprise at least one fuse holder that is movable between a first position in which a fuse held by the fuse holder is electrically couplable to the at least one power output and a second position in which a fuse held by the fuse holder not electrically couplable to the at least one power output and is exposed to allow access to the fuse. | 2009-03-05 |