| 10th week of 2009 patent applcation highlights part 25 |
| Patent application number | Title | Published |
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| 20090058389 | CONTROL CIRCUIT FOR MEASURING AND REGULATING OUTPUT CURRENT OF CCM POWER CONVERTER - A switching control circuit is provided for measuring and regulating an output current of a power converter. The power converter is operated under continuous current mode. A detection circuit generates a continuous-current signal and a peak-current signal by detecting a switching current of an inductive device. An integration circuit generates an average-current signal in response to the continuous-current signal, the peak-current signal and an off time of a switching signal. The switching control circuit generates the switching signal in response to the average-current signal. The switching signal is coupled to switch the inductive device and regulate the output current of the power converter. A time constant of the integration circuit is correlated to the switching period of the switching signal, therefore the average-current signal will be proportional to the output current. | 2009-03-05 |
| 20090058390 | SEMICONDUCTOR DEVICE WITH COMPENSATION CURRENT - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a first resistor, a second resistor, and a transistor. The second resistor is configured to receive a current via the first resistor. The transistor is configured to be driven via the first resistor and the second resistor and provide a compensation current. The current includes the compensation current and a reference current and changes in the current are compensated for via the compensation current which limits changes in the reference current. | 2009-03-05 |
| 20090058391 | TEMPERATURE SENSITIVE CIRCUIT - A circuit for use in a current source or a proportional to absolute temperature sensor or in a bandgap regulator, the circuit comprising at least two PTAT cells the operating Voltages of whose components overlap, the PTAT contribution to the output including the sum of the outputs of the two PTAT cells. | 2009-03-05 |
| 20090058392 | REFERENCE VOLTAGE CIRCUIT - A reference voltage circuit that obtains a precisely constant voltage by compensating a temperature variation of a reference voltage circuit using band gap voltage. A p-type MOS transistor (PNP) outputs a reference voltage according to a control voltage, and provides respective PNPs having diode connections with currents corresponding to the reference voltage. A temperature compensation unit adds compensation currents proportional to the second power of absolute current to currents flowing in the respective PNPs, so that both voltages generated corresponding to the currents flowing in the respective PNPs become the same in the case where the band gap unit has temperature characteristics including a peak value. The band gap unit has a differential amplifier for outputting the control voltage. In the case where the band gap unit has a bottom value, the compensation unit subtracts the above compensation currents from the currents flowing in the respective PNPs. | 2009-03-05 |
| 20090058393 | CONSTANT-CURRENT, CONSTANT-VOLTAGE AND CONSTANT-TEMPERATURE CURRENT SUPPLY OF A BATTERY CHARGER - Provided is a current supply for providing a charge current to a load. The current supply includes: a driving transistor, providing the charge current to the load; a sensing transistor, limiting the charge current; a pulling low transistor, pulling low a controlling node which controls the driving transistor and the sensing transistor; a constant voltage controller, pulling up the controlling node, controlling the conduction state of the driving transistor and accordingly maintaining the voltage across the load at the first reference voltage, when a voltage across the load rises up and comes close to a first reference voltage; and a constant current controller, controlling the controlling node and the pulling low transistor to limit the charge current to be constantly provided to the load, when the voltage across the load drops much lower than the first reference voltage. | 2009-03-05 |
| 20090058394 | Device for Supplying Power to Measuring Sensors and Transmitting a Synchronous Clock Signal Thereto - The invention relates to a device for supplying power to measuring sensors and transmitting a synchronous clock signal thereto, in particular, for a low-voltage switchgear, with a power supply unit ( | 2009-03-05 |
| 20090058395 | Method for Determining Anisotropy of 1-D Conductor or Semiconductor Synthesis - A method is provided for determining the anisotropy of alignment of a random array of 1-D conductive elements (e.g., carbon nanotube or silicon nanowire) formed on a substrate. A pattern of a plurality of electrodes are arranged on the substrate containing the 1-D conductive elements and a plurality of electrical property measurements are performed in a plurality of different directions between the plurality of electrodes. The plurality of measurements are combined together to generate a total measurement sum of electrical property measurements between the various electrodes. The measured electrical property is determined between a selected pair of the plurality of electrodes along a selected direction extending between the selected pair of electrodes. The anisotropy of alignment of the 1-D conductive elements on the substrate along the selected direction is determined based on a ratio of the measured electrical property between the selected pair of electrodes versus the total measurement sum. | 2009-03-05 |
| 20090058396 | Electrode configuration for LIMCA - The present invention provides a method and apparatus for reducing electromagnetic noise pick up in a Liquid Metal Cleanliness Analyzer (LiMCA), used to detect and measure particles in molten metal. An first electrode inserted in the molten metal is electrically insulated from second and third electrodes, also inserted in the molten metal. Molten metal and particles pass between the first electrode and the second and third electrodes through a passage in the electrical insulation. The second and third electrodes have a configuration with respect to the first electrode sufficient to establish symmetrical current loops between the first electrode and the second and third electrodes when a current is supplied to the second and third electrodes. The current is supplied from an ultra-capacitor. Electromagnetic noise in the symmetrical current loops is detected and is added in opposition to reduce the amplitude of the electromagnetic noise. | 2009-03-05 |
| 20090058397 | Apparatus for Verifying a Low Noise Block Output Voltage - The present invention relates to system diagnostic circuitry for antenna systems with active antenna components. More specifically, the present invention discloses an apparatus comprising a connection between an antenna and a power supply conducting a first DC voltage, a source of a pulse width modulated signal, a lowpass filter for converting the pulse width modulated signal to a second DC voltage, and a comparator for comparing the first DC voltage and the second DC voltage and generating an output signal responsive to the difference between the first DC voltage and the second DC voltage. | 2009-03-05 |
| 20090058398 | CURRENT/VOLTAGE DETECTION PRINTED BOARD AND CURRENT/VOLTAGE DETECTOR - A printed board, includes: a first shield portion, configured to reduce an influence of an electric field in combination with a casing accommodating the printed board, at least a part of the first shield portion being formed with a plurality of through holes; and a second shield portion, configured to reduce the influence of the electric field in combination with the casing, at least a part of the second shield portion being formed with a plurality of through holes, wherein the second shield portion is arranged alongside of the first shield portion. | 2009-03-05 |
| 20090058399 | CLAMP JAW ASSEMBLY - A method of manufacturing a clamp jaw assembly for a clamp meter is provided. The method includes providing a clamp jaw core and a shield having a channel. The method further includes positioning the clamp jaw core within the channel of the shield such that the shield surrounds a portion of the clamp jaw core. The method also includes enclosing the clamp jaw core and the shield within a clamp jaw housing. | 2009-03-05 |
| 20090058400 | Device for Detecting Absolute Angel of Multiple Rotation and Angle Detection Method - A multiple rotation absolute angle detecting device includes a reduction gear mechanism having an eccentric ring fitted to a rotatable member, an internally threaded member in a stationary member, an externally threaded member engageable with the internally threaded member, and a speed reducing member to which rotation is transmitted from the externally threaded member. The externally threaded member undergoes a speed-reduced rotation at a reduction gear ratio of 1/L (L represents an arbitrarily value exceeding 1) about an axis O′ of rotation of the eccentric ring and the speed reducing member rotates around the rotatable member at a speed equal to that of the externally threaded member. A multiple rotation detecting unit for outputting a sinusoidal or sawtooth wave having one period per rotation includes a to-be-detected member in the speed reducing member and a detecting member in the stationary member that confronts the to-be-detected member. | 2009-03-05 |
| 20090058401 | Machine with a position-sensing system - A machine includes a component. The machine may also include a position-sensing system with a plurality of sensor elements that each generate a signal related to proximity of the sensor element to the component by generating the signal based at least in part on the magnetic permeability of the space adjacent the sensor element and a time-varying magnetic field generated by an electric circuit of the position-sensing system. The machine may also include one or more information-processing devices that determine a positional relationship between the component and the plurality of sensor elements based on a plurality of the signals generated by the sensor elements. | 2009-03-05 |
| 20090058402 | INTEGRATED CIRCUIT INCLUDING MAGNETO-RESISTIVE STRUCTURES - An integrated circuit includes two first adjacent magneto-resistive effect (xMR) structures. Each first xMR structure is configured to sense a first magnetic field direction. The integrated circuit includes two second adjacent xMR structures at a distance from the two first xMR structures. Each second xMR structure is configured to sense a second magnetic field direction. The two first xMR structures and the two second xMR structures are configured for in-plane magnetic field components perpendicular to the first magnetic field and the second magnetic field and phase shifted by approximately 90° from the first magnetic field and the second magnetic field acting on the two first xMR structures and the two second xMR structures. | 2009-03-05 |
| 20090058403 | Magnetic encoder - A magnetic encoder constituting rotation detector in combination with a magnetic sensor, comprising a circular multipolar magnet and a metal reinforcing ring to which the circular multipolar magnet is fixed is disclosed. | 2009-03-05 |
| 20090058404 | Rotation detection sensor - A rotation detection sensor for detecting both rotational position and direction of a rotating body with a gear includes a magnet, multiple magnetic sensors, a rotational position detection circuit, and a rotational direction detection circuit. The magnet produces a magnetic field directed to a gear tooth of the rotating body. When the rotating body rotates, the magnetic sensors output sensor signals shifted in phase from each other. The rotational position detection circuit performs a differential operation on the sensor signals received from at least two magnetic sensors and outputs a rotational position signal. The rotational direction detection circuit outputs a rotational direction signal based on the position signal and the sensor signal received from at least one of the at least two magnetic sensors. | 2009-03-05 |
| 20090058405 | ROTATION ANGLE SENSOR - A rotation angle sensor is provided with a shaft portion having a torsion bar, a rotation angle sensing portion for detecting rotation angle of the shaft portion, and a torque sensing portion for detecting angle of torsion of the torsion bar. The rotation angle sensing portion and the torque sensing portion improve their own detecting accuracies by using each other's detecting result, whereby the rotation angle sensor can detect rotation angle and angle of torsion of a multi-turn rotatable body with high accuracy and high resolution. | 2009-03-05 |
| 20090058406 | NONDESTRUCTIVE INSPECTION METHOD AND DEVICE - The present invention nondestructively analyzes the position or corrosion state of a magnetic material present in the interior of a non-magnetic material structure. The magnetic material is magnetized from the outside of the structure, and magnetic flux density of the thus-magnetized magnetic material is measured at the outside of the structure, to thereby specify the position of the magnetic material or to analyze the corrosion state of the magnetic material. The magnetic material is magnetized in two stages. After the position of the magnetic material magnetized through first-stage magnetization is specified through measurement of magnetic flux density of the magnetic material, the magnetic material is demagnetized through application of an alternating magnetic field. After second-stage magnetization is performed at a position facing the thus-specified magnetic material position, magnetic flux density of the thus-magnetized magnetic material is measured, to thereby analyze the corrosion state of the magnetic material. | 2009-03-05 |
| 20090058407 | PHYSICAL QUANTITY CONVERSION SENSOR AND MOTOR CONTROL SYSTEM USING THE SAME - A first sensor element outputs a first output signal in correspondence to a direction of the magnetic flux lines acting from the outside. A second sensor element outputs a second output signal associated with the first output signal in correspondence to a direction of the magnetic flux lines acting from the outside. A first conversion processing section converts the first output signal output from the first sensor element and the second output signal output from the second sensor element into the second physical quantity. A second conversion processing section converts the first output signal output from the first sensor element and the second output signal output from the second sensor element into a signal representing the rotation angle of the motor. | 2009-03-05 |
| 20090058408 | METHOD AND A DEVICE FOR ELECTROMAGNETIC MEASUREMENT OF THICKNESS AND ELECTRICAL CONDUCTIVITY - A method for non-contact determination of sought properties of an object to be measured by using electromagnetic induction. An electromagnetic field is generated in a transmitter coil placed on one side of the object to be measured. The magnetic field penetrates through the object to be measured and is detected by a receiver coil placed on the other side of the object to be measured. A control coil is placed near the transmitter coil generating a change in the magnetic field of the transmitter coil. A field change in the detecting is detected in the control coil. The field is detected in the receiver coil. The difference in time is determined for the detection of the field change in the control coil and in the receiver coil, respectively. The time of penetration through the object to be measured is determined, and the thickness or electrical conductivity of the object to be measured is determined therefrom. | 2009-03-05 |
| 20090058409 | Method and device for forecasting polishing end point | 2009-03-05 |
| 20090058410 | REED RELAY FOR MAGNETIC FIELD MEASUREMENT - An apparatus for measuring a strength of a magnetic field, including a switch including contacts configured to change position when a switching threshold is reached, wherein the switching threshold is reached by modifying an external magnetic field around the switch, and a coil wound around the switch, wherein the coil is used to modify the external magnetic field, wherein a first current is driven through the coil wound around the switch until a first switching threshold is obtained, wherein a second current is driven through the coil wound around the switch until a second switching threshold is obtained, and wherein a value of the first current when the first switching threshold is reached and a value of the second current when the second switching threshold is reached are used to determine the strength of the magnetic field. | 2009-03-05 |
| 20090058411 | MAGNETIC SENSOR, HALL ELEMENT, HALL IC, MAGNETORESISTIVE EFFECT ELEMENT, METHOD OF FABRICATING HALL ELEMENT, AND METHOD OF FABRICATING MAGNETORESISTIVE EFFECT ELEMENT - An aspect of the present invention provides a magnetic sensor which is operated better at a high temperature range not lower than 300° C. compared with a conventional magnetic sensor. A operating layer having a heterojunction interface is formed by laminating a first layer made of GaN whose electron concentration is not more than 1×10 | 2009-03-05 |
| 20090058412 | Integrated Current Sensor - An integrated current sensor includes a current conductor, a magnetic field transducer, and an electromagnetic shield. The magnetic field transducer includes a sensor die. The electromagnetic shield is disposed proximate to the sensor die. The electromagnetic shield has at least one feature selected to reduce an eddy current in the electromagnetic shield | 2009-03-05 |
| 20090058413 | MAGNETORESISTIVE SENSOR DEVICE AND METHOD OF FABRICATING SUCH MAGNETORESISTIVE SENSOR DEVICE - In order to further develop a magnetoresistive sensor device ( | 2009-03-05 |
| 20090058414 | MEASURING ELECTRIC AND MAGNETIC FIELD - A field detection device such as a micro-strip portion of a transmission line may detect an electric field and a magnetic field induced by current steps injected into the chassis coupled to a ground plane. The shield portions of the transmission line may be coupled to a first and a second port of an I/O connector. A measurement system coupled to the connector may determine the electric field and the magnetic field detected by the micro-strip. The measurement system may determine the electric field and magnetic field based on computing the sum and difference of the signals provided by the first port and the second port. | 2009-03-05 |
| 20090058415 | METHOD AND APPARATUS OF USING CROSSED MAGNETIC FIELDS FOR MEASURING CONDUCTIVITY, PERMEABILITY AND POROSITY - When a static magnetic field and a crossed oscillating field are applied, the deformation rate at a boundary between a fluid and a porous medium depends on the amplitudes of the applied magnetic fields (to be exact, on their product), electric conductivity, porosity, and permeability. Knowing two of the three enables determination of the third. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2009-03-05 |
| 20090058416 | Method and Apparatus for NMR Saturation - Saturation pulse sequences are designed to ensure complete saturation of nuclear spins for dual wait time measurements and saturation recovery measurements in the case of axial motion of a downhole NMR logging tool. Frequency and/ or phase modulation may be used. An auxiliary saturation coil may be used. | 2009-03-05 |
| 20090058417 | Test object for use with diffusion MRI and system and method of synthesizing complex diffusive geometries using novel gradient directions - A test object for use with diffusion MRI and a system and methods of synthesizing complex diffusive geometries. The test object, which includes anisotropic structures, can be used to monitor DTI measures by providing a baseline measurement. Using measurements of the phantom, data characteristic of more complicated diffusive behavior can be “synthesized”, or composed of actual measurements re-arranged into a desired spatial distribution function describing diffusion. Unlike a typical DTI scan, the ADC measurements of the present invention are treated in a “reconstruction” phase as if the gradients were applied in different directions. Given a set of reconstruction directions, a judicious choice of acquisition directions for each reconstruction direction allows for the synthesis of any distribution. | 2009-03-05 |
| 20090058418 | DOUBLE HALF RF PULSES FOR REDUCED SENSITIVITY TO EDDY CURRENTS IN UTE IMAGING - A method for creating a magnetic resonance image of an object with at least a first species and a second species, wherein the first species has a first T | 2009-03-05 |
| 20090058419 | MAGNETIC RESONANCE IMAGING APPARATUS AND MAGNETIC RESONANCE IMAGE DISPLAYING METHOD - A magnetic resonance imaging apparatus includes a scan section which executes a diffusion weighted imaging pulse sequence on an imaging area of a subject within a static magnetic field space thereby to acquire magnetic resonance signals, an image generating part which generates an image with respect to the imaging area, based on the magnetic resonance signals acquired by the scan section, a display unit which displays the image generated by the image generating part on a display screen thereof, and a window setting part which sets a window level and a window width at the time that the display unit displays the image, based on diffusion parameters calculated from the magnetic resonance signals acquired by the scan section. The display unit displays the image on the display screen by the window level and the window width both set by the window setting part. | 2009-03-05 |
| 20090058420 | Magnetic resonance apparatus and control method for the same - A magnetic resonance apparatus includes a coil which receives a magnetic resonance signal from a subject, a transmitting unit which transmits the magnetic resonance signal received by the coil with a radio signal of a frequency band different from that of the magnetic resonance signal, an unit which extracts the magnetic resonance signal from the radio signal, a battery which supplies power to the transmitting unit, a switch unit which turns on and off power supply from the battery to the transmitting unit, a unit which wirelessly transmits a startup signal and a stop signal, a receiving unit which receives the startup signal and the stop signal that have been wirelessly transmitted, and a unit which controls the switch unit to turn on the power supply when the receiving unit receives the startup signal and turn off the power supply when the receiving unit receives the stop signal. | 2009-03-05 |
| 20090058421 | SERVICE TEE MARKER FIXTURE - A service tee marker fixture comprises a disk marker and a cylindrical attachment sleeve fastened concentrically to the disk marker and constructed of a flexible material which provides a releasable friction fit with a service tee cap. For certain sleeve materials a stiffener plate is used to secure an end portion of sleeve adjacent to the disk marker. Detents are formed inside the attachment sleeve to grip matching ribs on the cap. An integrally formed inwardly-extending annular flange at an open end of the sleeve helps retain the sleeve on the cap. When installed the wire coil is horizontal and the marker shields the tee, and is further centered over a centerline of the main pipe. A novel method is also disclosed for using the service tee marker fixtures to survey and locate service line end points. | 2009-03-05 |
| 20090058422 | Fiber optic system for electromagnetic surveying - An electromagnetic survey sensing device includes at least two electrodes disposed at spaced apart locations. An electrical to optical converter is electrically coupled to the at least two electrodes. The converter is configured to change a property of light from a source in response to voltage imparted across the at least two electrodes. The device includes an optical fiber optically coupled to an output of the electrical to optical converter, the optical fiber in optical communication with a detector. | 2009-03-05 |
| 20090058423 | ELECTRONIC APPARATUS AND CONTROLLING METHOD FOR THE SAME - An electronic apparatus which is capable of correctly displaying the remaining usable time even if a discharged current of a battery pack is changed by an unexpected load due to an external apparatus connected. The electronic apparatus has a battery pack with a secondary battery mounted therein. A first remaining usable time of the electronic apparatus is calculated based on a consumed current of the electronic apparatus. A second remaining usable time of the electronic apparatus is calculated based on a discharged current of the secondary battery. The first remaining usable time calculated by the first remaining usable time calculating unit or the second remaining usable time calculated by the second remaining usable time calculating unit, whichever is smaller, is selected, and then a displaying unit displays the selected remaining usable time. | 2009-03-05 |
| 20090058424 | Plasma monitoring method and plasma monitoring system - A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the substrate while being isolated from the substrate; an insulating film formed on the first electrode; a contact hole formed in the insulating film and having a depth from a surface of the insulating film to the first electrode; and a second electrode, the second electrode being a conductive electrode, formed on the surface of the insulating film, and faced to plasma during a plasma process, the plasma monitoring method including measuring and monitoring potentials of the first electrode and the second electrode or a potential difference between the first electrode and the second electrode during the plasma process is disclosed. A plasma monitoring system carrying out the plasma monitoring method is also disclosed. | 2009-03-05 |
| 20090058425 | METHOD AND APPARATUS TO TEST ELECTRICAL CONTINUITY AND REDUCE LOADING PARASITICS ON HIGH-SPEED SIGNALS - An apparatus for testing electrical continuity of a surface mounted (SMT) electrical board includes: a printed wiring board having a first surface and an opposite second surface; a conductive signal line disposed on each of the first and second surfaces of the printed wiring board; an electrical component disposed on and electrically connected to the conductive signal line on the first surface; and a through hole extending through the printed wiring board and the conductive signal line on the second surface of the printed wiring board exposing a surface side of the conductive signal line facing the first surface of the printed wiring board. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board. | 2009-03-05 |
| 20090058426 | Electromagnetic shielding defect monitoring system and method for using the same - An embodiment disclosed herein is directed to a method of monitoring an electromagnetic shield effectiveness comprising transmitting a first electromagnetic field toward a first surface of an electromagnetic shield, detecting a second electromagnetic field transmitted from a second surface of the electromagnetic shield, generating a first signal corresponding to the second electromagnetic field and determining whether a defect exists at the electromagnetic shield by comparing the first signal to a predetermined threshold. | 2009-03-05 |
| 20090058427 | PASSIVE WIRELESS CORROSION SENSOR - A passive wireless corrosion sensor is disclosed. A circuit is configured to provide a signal response when energized. An antenna is configured to wirelessly receive energy for energizing the circuit and to receive the signal response from the circuit and transmit the signal response. A corrosion sensitive connector interposes the circuit and the antenna. The corrosion sensitive connector conducts the energy from the antenna to the circuit and conducts the signal response from the circuit to the antenna when in a substantially non-corroded state. The corrosion sensitive connector creates an effectively non conducting link between the antenna and the circuit when in a substantially corroded state. | 2009-03-05 |
| 20090058428 | Method and device for monitoring and controlling fluid locomotion - A device for monitoring dripping of a fluid from a fluid channel, the device comprises a capacitor, being formed on or integrated with the fluid channel, and electrical contacts, connecting the capacitor to a capacitance measuring device, the capacitor is designed and constructed so that a change in a capacitance thereof represents a formation of a drop near an edge of the fluid channel. | 2009-03-05 |
| 20090058429 | Detecting Closure of an Electronic Device Using Capacitive Sensors - System and method for determining closure of an electronic device. The electronic device may include a top portion and a bottom portion, and may be connecting via a hinge or other closing mechanism. The top portion and/or the bottom portion may include one or more capacitive sensors which provide signals corresponding to physical contact and a controller coupled to the one or more capacitive sensors. The controller may operate to receive the signals from the one or more capacitive sensors, determine if the electronic device has been closed based on the received signals, and initiate a sequence of events corresponding to the closure of the electronic device. The sequence of events may result in the device entering a low power state. | 2009-03-05 |
| 20090058430 | Systems and Methods for Sensing Positions of Components - Systems and methods for sensing positions of components are provided. In this regard, a representative method includes: capacitively coupling the component to a resistive member without electrically connecting the component and the resistive member; moving the component relative to the resistive member while the component is capacitively coupled thereto; and measuring relative electrical impedance with respect to ends of the resistive member such that a position of the component is determined. | 2009-03-05 |
| 20090058431 | ETCH RESISTANT GAS SENSOR - A gas sensor for sensing noxious chemical gases utilizes metal nitrides, metal oxynitrides, metal carbides or metal oxycarbides as the sensing material, which changes its conductivity when exposed to the analyte gas. The change in conductivity is measured for the sensor output. | 2009-03-05 |
| 20090058432 | Ultraviolet light monitoring system - An ultraviolet light monitoring system includes first and second electrodes, an evaluation subject film and a power source. The first and second electrodes are opposingly disposed and attract holes which are generated in accordance with irradiation of ultraviolet light. The evaluation subject film is formed in a vicinity of the first and second electrodes, and is a subject of evaluation of damage caused by the irradiation of ultraviolet light. The power source, at times of monitoring of the ultraviolet light, applies a predetermined bias to a series path formed by the first electrode, a gap between the first and second electrodes, and the second electrode. | 2009-03-05 |
| 20090058433 | METHOD OF TESTING GROUND RESISTANCE BY MAKING USE OF EXISTING TELEPHONE LINES - A fall of potential method of determining earth ground resistance which utilizes an earth ground tester and eliminates the need for utilizing removable ground stakes. Rather than utilizing a “far stake” the method provides connection of the earth ground tester to the telephone wires. Rather than utilizing a “near stake” the method provides for connection of the earth ground tester to the cable shield. | 2009-03-05 |
| 20090058434 | METHOD FOR MEASURING A PROPERTY OF INTERCONNECTIONS AND STRUCTURE FOR THE SAME - A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad. | 2009-03-05 |
| 20090058435 | HIGH-SENSITIVE RESISTANCE MEASURING DEVICE AND MONITORING METHOD OF SOLDER BUMP - According to an aspect of an embodiment, a high-sensitive resistance measuring device of solder bumps comprises a resistance variation detection unit which detects a differential voltage (□V=V | 2009-03-05 |
| 20090058436 | SYSTEM AND METHOD FOR MEASURING A CABLE RESISTANCE IN A POWER OVER ETHERNET APPLICATION - A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port. | 2009-03-05 |
| 20090058437 | Method and apparatus for reviewing defects by detecting images having voltage contrast - A method and apparatus for detecting defects includes irradiating and scanning an electron beam focused on an area of a sample, detecting charged particles generated from the sample by the irradiating and scanning of the electron beam with a first detector which detects charged particles having relatively low energy to obtain a first image of the area and with a second detector which detects charged particles having relatively high energy to obtain a second image of the area, comparing the first inspection image of the area with a first reference image to generate a first difference image, and comparing obtained second image of the area with a second reference image to generate a second difference image, and detecting an open defect or a short defect from at least one of the generated first difference image and the second difference image. | 2009-03-05 |
| 20090058438 | WAFER, TEST SYSTEM THEREOF, TEST METHOD THEREOF AND TEST DEVICE THEREOF - A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer. | 2009-03-05 |
| 20090058439 | ELECTRONIC DEVICE TEST SYSTEM - When the number of DUTs carried on a loader buffer and scheduled to be held by contact arms at the next test is less than N, a DUT at a contact arm corresponding to a missing position at the loader buffer among the N number of DUTs being held for execution of a current test is held as it is without being ejected. While holding this DUT, the DUTs carried at the loader buffer for execution of the next test are picked up and the test is executed in that state. | 2009-03-05 |
| 20090058440 | PROBE ASSEMBLY, METHOD OF PRODUCING IT AND ELECTRICAL CONNECTING APPARATUS - A probe assembly for use in electrical measurement of a device under test. The probe assembly comprises a plate-like probe base plate with bending deformation produced in a free state without load, and a plurality of probes formed on one face of the probe base plate to project from the face. All the tips of the probes are positioned on the same plane parallel to an imaginary reference plane of the probe base plate. | 2009-03-05 |
| 20090058441 | ELECTRICAL TEST PROBE - A probe for electrical test comprises a plate-shaped main portion having a base end to be attached to a support board and a tip end opposite the base end, and a probe tip portion arranged at the tip end of the main portion and having a probe tip to contact an electrode of a device under test, the main portion being made of a tenacity material. The main portion includes a conductive material extending from the base end to the tip end and at least part of which is buried within the tenacity material, and the tenacity material has higher resiliency than that of the conductive material while the conductive material has higher conductivity than that of the tenacity material. As a result, disorder of a signal provided via the probe is decreased without losing elastic deformation. | 2009-03-05 |
| 20090058442 | PROBER FOR TESTING COMPONENTS - A prober for testing components comprises a lower frame, over which a probe holder plate is disposed at a distance therefrom for receiving test probes that make contact with the components to be tested and to which a displacement device is connected. A substrate carrier is disposed in the space between the frame and the probe holder plate, and the probe holder plate is provided with an opening, below which the substrate carrier can be displaced. To expand the scope of application of probers used for testing components, all those components of the prober that surround the substrate are made from a non-magnetic material. | 2009-03-05 |
| 20090058443 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND PROBE CARD USED FOR BURN-IN STRESS AND D/S TESTS - According to one embodiment of the invention, a semiconductor chip includes: a test target circuit to which a given burn-in stress is applied; and a burn-in counter that is configured: to acquire a first parameter indicating a test voltage applied to the test target circuit and a second parameter indicating a temperature of the test target circuit; to estimate the given burn-in stress from the first parameter and the second parameter; and to output burn-in stress information corresponding to the estimated burn-in stress. | 2009-03-05 |
| 20090058444 | METHOD AND APPARATUS FOR RELATIVE TESTING OF INTEGRATED CIRCUIT DEVICES - A method includes loading a plurality of integrated circuit devices into a tester. At least one parameter is determined for each of the integrated circuit devices using the tester. At least one relative acceptance criterion associated with the parameter is determined based on the determined parameters for the plurality of integrated circuit devices. A pass/fail status of each of the integrated circuit devices is determined using the relative acceptance criterion. | 2009-03-05 |
| 20090058445 | CIRCUIT BOARD TESTING USING A PROBE - A test point of a circuit board is probed using an edge probe provided in a fixed orientation when the edge of the probe contacts a solder mound of the test point. The solder mound has an elongated shape. A length of the edge is substantially perpendicular to a length of the solder mound when the edge contacts the solder mound and is maintained in the fixed orientation. | 2009-03-05 |
| 20090058446 | INSPECTION APPARATUS AND INSPECTION METHOD - An inspection apparatus for inspecting electric characteristics of a plurality of devices formed on a target object includes a vertical drive mechanism for lifting and lowering a movable mounting table and a control unit for controlling the vertical drive mechanism. The vertical drive mechanism includes an elevation shaft connected to the mounting table and a servo motor for driving the elevation shaft to lift and lower the mounting table. Further, the control unit has a servo driver which includes a position control part for controlling a position of the servo motor, a torque control part for controlling a torque of the servo motor as a probe card is expanded or contracted by a change in temperature and a switching part for switching the position control part and the torque control part. | 2009-03-05 |
| 20090058447 | FAULT ANALYZER - The objective of the invention is to provide a type of fault analyzer and a method therefore that can easily specify fault locations in semiconductor devices. Fault analyzer | 2009-03-05 |
| 20090058448 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 2009-03-05 |
| 20090058449 | METHOD AND APPARATUS FOR EMPLOYING PREVIOUS TEST INSERTION RESULTS FOR TESTING A DEVICE - A method includes determining at least a first characteristic of a device during a first test insertion and storing the first characteristic. The device is identified during a second test insertion. The first characteristic is retrieved responsive to the identification of the device. A test program for the second insertion is configured based on the first characteristic. The configured test program is executed to test the device during the second test insertion. | 2009-03-05 |
| 20090058450 | METHOD OF AND SYSTEM FOR FUNCTIONALLY TESTING MULTIPLE DEVICES IN PARALLEL IN A BURN-IN-ENVIRONMENT - A method of and a system for testing semiconductor devices heat a plurality of devices to a burn-in temperature, and perform functional tests in parallel on the plurality of devices at the burn-in temperature. Systems include a burn-in oven and a test multiplexer. The burn-in oven is adapted to receive and heat the devices to the burn-in temperature. The test multiplexer is adapted to apply functional test signals to and receive output signals from the devices in the burn-in oven. | 2009-03-05 |
| 20090058451 | Adaptive test time reduction for wafer-level testing - A method is provided for dynamically increasing or decreasing the amount of test data that is applied to die locations on a wafer under test. As on-wafer locations are traversed and tested, the amount of test stimuli applied to subsequent locations is adjusted. This adjustment is based upon the results of previously tested locations. The effect is that the test program detects regions of the wafer that are more likely to fail and applies more complete testing to these areas. Other areas of the wafer may receive reduced testing. By automatically adapting the test mix to suit the potential failure patterns, wafer testing time is reduced. | 2009-03-05 |
| 20090058452 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests fluctuation of a power supply voltage supplied to a device under test, including an oscillator that outputs a clock signal having a frequency that corresponds to the power supply voltage supplied to the power supply input terminal of the device under test, and a measuring section that measures the frequency of the clock signal. For example, the oscillator outputs as the clock signal an output signal of any one negative logic element from among an odd number of negative logic elements connected in a loop, and at least one of the negative logic elements operates using, as a voltage source, a voltage corresponding to the power supply voltage supplied to the power supply input terminal of the device under test. | 2009-03-05 |
| 20090058453 | SEMICONDUCTOR DEVICE - A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals. | 2009-03-05 |
| 20090058454 | DEVICE POWER SUPPLY EXTENSION CIRCUIT, TEST SYSTEM INCLUDING THE SAME AND METHOD OF TESTING SEMICONDUCTOR DEVICES - A test system includes a controller, a power supply circuit and a device power supply (DPS) extension circuit. The controller controls a test operation for a plurality of devices under test (DUTs). The power supply circuit generates a common power voltage in response to a voltage control signal from the controller. The DPS extension circuit includes a plurality of control modules providing a plurality of source currents based on the common power voltage to the DUTs. Each control module blocks a corresponding source current in response to a magnitude of the corresponding source current. | 2009-03-05 |
| 20090058455 | Test structure and test method - The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other. | 2009-03-05 |
| 20090058456 | MANUFACTURING SYSTEM, MANUFACTURING METHOD, MANAGING APPARATUS, MANAGING METHOD AND COMPUTER READABLE MEDIUM - There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages. The manufacturing system includes a manufacturing line that manufactures the electronic device, a manufacturing control section that causes the manufacturing line to manufacture a wafer having therein a test circuit including a plurality of transistors under measurement, a measuring section that measures an electrical characteristic of each of the plurality of transistors under measurement in the test circuit, an identifying section that identifies, among the plurality of manufacturing stages, a manufacturing stage in which a defect is generated, with reference to a distribution, on the wafer, of one or more transistors under measurement whose electrical characteristics do not meet a predetermined standard, and a setting changing section that changes a setting for a manufacturing apparatus that performs a process corresponding to the manufacturing stage in which the defect is generated. | 2009-03-05 |
| 20090058457 | REDUNDANT CRITICAL PATH CIRCUITS TO MEET PERFORMANCE REQUIREMENT - Method, system, IC and design structure for meeting a performance requirement using redundant critical path circuits, are disclosed. In one embodiment, the IC includes a plurality of redundant critical path circuits, wherein at least one of the plurality of redundant critical path circuits meeting a performance requirement is operational and the others are non-operational. | 2009-03-05 |
| 20090058458 | DIGITAL-TO-ANALOG CONVERTING CIRCUIT AND APPARATUS FOR ON-DIE TERMINATION USING THE SAME - A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code. | 2009-03-05 |
| 20090058459 | AUTO-TRIM CIRCUIT - An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits. | 2009-03-05 |
| 20090058460 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 2009-03-05 |
| 20090058461 | Configurable Circuits, IC's, and Systems - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data. | 2009-03-05 |
| 20090058462 | FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NONVOLATILE USER MEMORY AND METHOD FOR PROGRAMMING - An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access. | 2009-03-05 |
| 20090058463 | Sequential Circuit Element Including A Single Clocked Transistor - A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path. | 2009-03-05 |
| 20090058464 | Current mode logic-complementary metal oxide semiconductor converter - A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal. | 2009-03-05 |
| 20090058465 | Circuit Combining Level Shift Function with Gated Reset - A circuit ( | 2009-03-05 |
| 20090058466 | DIFFERENTIAL PAIR CIRCUIT - A differential pair circuit includes a first transistor having a first control terminal, a first input terminal, and a first output terminal; a second transistor having a second control terminal, a second input terminal, and a second output terminal, a first buffer stage including a third transistor having a third control terminal, a third input terminal, and a third output terminal; and a second buffer stage including a fourth transistor having a fourth control terminal, a fourth input terminal, and a fourth output terminal. The first output terminal and the second output terminal are electrically connected; the third output terminal and the first control terminal are electrically connected; the fourth output terminal and the second control terminal are electrically connected; the first input terminal and the fourth input terminal are electrically connected; and the second input terminal and the third input terminal are electrically connected. | 2009-03-05 |
| 20090058467 | PHASE DETECTION APPARATUS - There is provided a phase detection apparatus that can accurately detect a phase difference between an input signal and a reference signal even when the input signal and the reference signal have different duty cycles. A phase detection apparatus according to an aspect of the invention may include: a pulse generation unit generating a first pulse signal on an edge of an input pulse signal, and a second pulse signal based on an edge of a reference pulse signal having a predetermined phase; and a detection unit detecting a phase difference between the first pulse signal and the second pulse signal from the pulse generation unit. | 2009-03-05 |
| 20090058468 | Method of Detecting the Frequency of an Input Clock Signal of an Integrated Circuit and Integrated Circuit - An integrated circuit includes a first switched capacitor element and a second switched capacitor element, which are coupled to form a bridge circuit, the first switched capacitor element being located in a first branch of the bridge circuit and the second switched capacitor element being located in a second branch of the bridge circuit. A detector circuit is coupled to the first branch and to the second branch of the bridge circuit. Switching signals of the first switched capacitor element and of the second switched capacitor element are generated on the basis of an input clock signal of the integrated circuit. | 2009-03-05 |
| 20090058469 | METHODS AND SYSTEMS FOR COMPARING CURRENTS USING CURRENT CONVEYOR CIRCUITRY - Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output. | 2009-03-05 |
| 20090058470 | SELF-STOP CIRCUIT USING NONVOLATILE STORAGE ELEMENT CHARGE AMOUNT AS TIMER - A self-stop circuit has a nonvolatile storage element ( | 2009-03-05 |
| 20090058471 | Rail-to-rail comparator with hysteresis - A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be proportional to a bias current of the current stage. | 2009-03-05 |
| 20090058472 | VOLTAGE COMPARATOR CIRCUIT - A voltage comparator circuit includes a voltage input terminal, a first resistor, a second resistor, a first transistor, a second transistor, and a voltage output terminal connected to the collector of the second transistor. The voltage input terminal is connected to ground via the first and second resistors in turn. A node between the first and second resistors is connected to the base of the first transistor. The emitter of the first transistor is grounded. The collector of the first transistor is connected to a direct current (DC) power supply and the base of the second transistor. The emitter of the second transistor is connected to the DC power supply. | 2009-03-05 |
| 20090058473 | ACTIVE PRE-EMPHASIS FOR PASSIVE RC NETWORKS - An approach that provides active pre-emphasis for a passive RC network is described. In one embodiment, there is a circuit that comprises an RC filter including a resistive divider formed from a first resistor and a second resistor and a filtering capacitor. The first resistor is configured to receive an input voltage and the second resistor and filtering capacitor are in parallel and configured to generate a reference voltage that is a percentage of the input voltage. An operational amplifier is coupled to the RC filter. A first multiplexer controlled by a pulse pre-emphasis signal is coupled to the operational amplifier and the RC filter. A second multiplexer controlled by a sample and hold clocking signal has inputs that are coupled to the first multiplexer and ground. | 2009-03-05 |
| 20090058474 | Output driver of semiconductor memory device - An output driver of a semiconductor memory device is capable of controlling falling and rising edges of an output data. The output driver prevents the first output data form being relatively deteriorated compared with other output data in case that the output data are terminated centering around a predetermined voltage level. The output driver includes a pull-up driver for pull-up driving an output terminal in response to a pull-up control signal, a pull-down driver for pull-down driving the output terminal in response to a pull-down control signal, a first acceleration driver for accelerating the pull-up control signal, and a second acceleration driver for accelerating the pull-down control signal, wherein the first and second acceleration drivers are activated when a first data is outputted. | 2009-03-05 |
| 20090058475 | APPARATUS AND METHOD FOR DIGITAL FREQUENCY UP-CONVERSION - Disclosed is an apparatus and a method for up-converting frequencies of digital Intermediate Frequency (IF) signals input through at least two paths, and then outputting IF signals to which at least two frequencies are allocated in a communication system. The apparatus includes Serializer/Deserializers (SerDeses), down-converters, up-converters, a signal adder, a Digital-to-Analog Converter (DAC), and a Band-Pass Filter (BPF), etc. In relation to digital IF signals respectively input through at least two paths, first, the frequency down-conversion is performed, and then, the up-conversion to relatively low frequencies is performed. | 2009-03-05 |
| 20090058476 | RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT - A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier. | 2009-03-05 |
| 20090058477 | Method and system for reclocking a digital signal - A method and system are disclosed for reclocking a digital time-based signal. An exemplary method includes receiving a digital signal output at a first clock rate. Data transitions of the received digital signal are measured using a master clock having a second clock rate. The digital signal is filtered to determine approximate edge positions of the data transitions. A tolerance is enforced between the approximate edge positions to reconstruct the digital signal. The reconstructed signal is output. The exemplary system for reclocking a digital time-based signal includes an input section, a processor and a reconstruction section. | 2009-03-05 |
| 20090058478 | EFFICIENT CLOCKING SCHEME FOR ULTRA HIGH-SPEED SYSTEMS - There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal. | 2009-03-05 |
| 20090058479 | TIMING CONTROLLERS AND DRIVING STRENGTH CONTROL METHODS - A timing controller receiving image data using an input clock signal and transferring the received image data and an output clock signal to a source driver. The received image data is transferred to the source driver through an output buffer. A frequency detection circuit detects a frequency of the input clock signal. A power supply circuit provides power to the output buffer, wherein power level is determined by the detected frequency. | 2009-03-05 |
| 20090058480 | SCHEME FOR CONTROLLING RISE-FALL TIMES IN SIGNAL TRANSITIONS - A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry. | 2009-03-05 |
| 20090058481 | Semiconductor memory device and method for driving the same - A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock. | 2009-03-05 |
| 20090058482 | Duty detection circuit - Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation. | 2009-03-05 |
| 20090058483 | DUTY CYCLE CORRECTING CIRCUIT AND METHOD - A duty cycle correcting circuit includes a duty detector that detects a duty ratio of an output clock signal to output a duty detection signal, a variable delay unit that outputs a delay clock signal obtained by variably delaying a input signal according to the duty detection signal, and a pulse width modulating unit that generates a first clock signal that is at a high level when both the input clock signal and the delay clock signal are at a high level and generates a second clock signal that is at a high level when any of the input clock signal and the delay clock signal is at a high level, wherein the pulse width modulating unit selectively outputs the first clock signal or the second clock signal as the output clock signal. | 2009-03-05 |
| 20090058484 | Slave latch controlled retention flop with lower leakage and higher performance - In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input. | 2009-03-05 |
| 20090058485 | FLIP-FLOP HAVING LOGIC STATE RETENTION DURING A POWER DOWN MODE AND METHOD THEREFOR - A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch. | 2009-03-05 |
| 20090058486 | MASTER-SLAVE CIRCUIT AND CONTROL METHOD OF THE SAME - A master-slave circuit that includes a master circuit having input data stored therein, a storage unit for receiving the input data in response to receiving a sleep mode setting signal that sets a sleep mode, and for storing the input data, and a first control unit for interrupting the supply of a power supply voltage to the master circuit after the input data is stored in the storage unit. | 2009-03-05 |
| 20090058487 | DELAY CIRCUIT - A delay circuit controls a delay time according to variation of a power supply voltage. In the delay circuit, the capacitance of a capacitor connected in parallel to the delay line is changed according to the change of the power supply voltage. Alternatively, a current is made to flow through one path selected from a plurality of paths having different resistance between the input and the output of the delay line. Accordingly, the delay time can be independently controlled or adjusted by greatly changing the time taken to pass through the delay line according to the change of the power supply voltage. | 2009-03-05 |
| 20090058488 | Delay circuit, semiconductor control circuit, display device, and electronic device - Disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages, and delaying a signal, the delay circuit including an output section configured to output a delayed signal; two power supplies; and a delay inverter; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge, the first transistor and the second transistor being connected in series with each other between the output section and one power supply, and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge, the third transistor being connected in parallel with one of the first transistor and the second transistor. | 2009-03-05 |
