10th week of 2009 patent applcation highlights part 19 |
Patent application number | Title | Published |
20090057789 | PACKAGE STRUCTURE FOR MICRO-SENSOR - The invention discloses a package structure for a micro-sensor including a micro-cantilever for capturing a chemical substance. The package structure, according to the invention, includes a first substrate, a second substrate, and a casing. The first substrate thereon forms a processing circuit. The micro-sensor is bonded to a first upper surface of the first substrate and is electrically connected to the processing circuit capable of outputting a signal relative to the chemical substance sensed by the micro-sensor. The second substrate has a formed-through aperture. The second substrate is bonded to the first substrate such that the micro-sensor is disposed in the formed-through aperture. The casing is bonded to the second substrate and includes a reaction chamber in which the micro-cantilever is installed and a fluid containing the chemical substance flows into. | 2009-03-05 |
20090057790 | PACKAGE FOR A MICRO-ELECTRO MECHANICAL DEVICE - A package for a micro-electromechanical device (MEMS package) includes an inner enclosure having an inner cavity defined therein, and a fill port channel communicating with the inner cavity and of sufficient length to allow a quantity of adhesive to enter the fill port channel while preventing the adhesive from entering the inner cavity. | 2009-03-05 |
20090057791 | MICROCHIP AND SOI SUBSTRATE FOR MANUFACTURING MICROCHIP - A plasma treatment or an ozone treatment is applied to the respective bonding surfaces of the single-crystal Si substrate in which the ion-implanted layer has been formed and the quartz substrate, and the substrates are bonded together. Then, a force of impact is applied to the bonded substrate to peel off a silicon thin film from the bulk portion of single-crystal silicon along the hydrogen ion-implanted layer, thereby obtaining an SOI substrate having an SOI layer on the quartz substrate. A concave portion, such as a hole or a micro-flow passage, is formed on a surface of the quartz substrate of the SOI substrate thus obtained, so that processes required for a DNA chip or a microfluidic chip are applied. A silicon semiconductor element for the analysis/evaluation of a sample attached/held to this concave portion is formed in the SOI layer. | 2009-03-05 |
20090057792 | CHARGE BIASED MEM RESONATOR - A resonator has a vibrating element ( | 2009-03-05 |
20090057793 | SPIN TRANSISTOR AND METHOD OF MANUFACTURING SAME - The spin transistor in accordance with the present invention comprises a magnetoresistive element having a fixed layer, a free layer, and a semiconductor layer provided between the fixed layer and free layer; a source electrode layer electrically connected to one end face in a laminating direction of the magnetoresistive element; a drain electrode layer electrically connected to the other end face in the laminating direction of the magnetoresistive element; and a gate electrode layer laterally adjacent to the semiconductor layer through a gate insulating layer provided on a side face of the semiconductor layer. | 2009-03-05 |
20090057794 | Planar flux concentrator for MRAM devices - The present invention provides an MRAM that includes a conductive line for generating a magnetic field. The latter is enhanced by the addition of a flux concentrator made from a single plane of soft ferromagnetic material, magnetically stabilized by means of an antiferromagnetic layer. This structure, in addition to being very easy to fabricate, facilitates close control over its magnetic properties, including uniformity and domain structure. | 2009-03-05 |
20090057795 | Sensor chip having conductivity film - A sensor chip is provided that includes a sensor element and a control circuit for controlling the sensor element disposed in semiconductor substrate. The control circuit includes a plurality of circuit elements, each of which is isolated by P-N junction separation. The sensor chip further includes a conductivity film disposed on and surrounding at least one of the circuit elements, and having an electric potential fixed to a predetermined value. | 2009-03-05 |
20090057796 | PHOTODIODE BEING MONOLITHICALLY INTEGRATED ONTO A WAVEGUIDE - A waveguide-integrated photodiode for high bandwidths with a semi-insulating monomode supply waveguide monolithically integrated on a substrate, together with an overlying photodiode mesa structure having an electroconducting n-contact layer, an absorption layer, a p+-contact layer and a metallic p-contact, the refraction index of the n-contact layer being greater than the refraction index of the semi-insulating waveguide layer. Lengthening the n-contact layer by a predetermined length L in the direction of the supply waveguide in relation to the overlying layers correspondingly increases at least one factor of the product of quantum efficiency and bandwidth. | 2009-03-05 |
20090057797 | Image Sensor and a Method for Manufacturing the Same - An image sensor and manufacturing method thereof are provided. An insulating layer having a wiring can be provided on a semiconductor substrate. A barrier wiring can be provided in the insulating layer between the wiring of a unit pixel and an adjacent wiring of an adjacent pixel. A device isolating pattern can be provided on the barrier wiring, and a lower electrode can be provided on the insulating layer and the wiring. A photodiode can be provided on the lower electrode, and an upper electrode can be provided on the photodiode. | 2009-03-05 |
20090057798 | Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus - There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks. | 2009-03-05 |
20090057799 | Sensor semiconductor device and method for fabricating the same - A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs. The above arrangement avoids prior-art problems of poor reliability caused by a porous encapsulant and poor signal reception caused by interference of ambient light entering into a conventional chip only encapsulated by a transparent encapsulant. | 2009-03-05 |
20090057800 | SMALL-SIZE MODULE - According to one embodiment, a small-size module an IC chip having leads provided on at least two sides of the IC chip, a circuit substrate having a component mounting face, plural pairs of auxiliary substrates which are disposed between the component mounting face of the circuit substrate and the IC chip so as to nip the leads extending from each of the two sides and mount the IC chip on the component mounting face of the circuit substrate, and a through conductor which is provided in at least one of the pair of the auxiliary substrates and bonded conductively to the nipped leads to connect the leads to the circuit substrate. | 2009-03-05 |
20090057801 | Back-Illuminated, Thin Photodiode Arrays with Trench Isolation - Back-illuminated, thin photodiode arrays with trench isolation. The trenches are formed on one or both sides of a substrate, and after doping the sides of the trenches, are filled to provide electrical isolation between adjacent photodiodes. Various embodiments of the photodiode arrays and methods of forming such arrays are disclosed. | 2009-03-05 |
20090057802 | Image Sensor and Method for Manufacturing the Same - Provided are an image sensor and a manufacturing method thereof. The image sensor can include a first epitaxial layer with a first ion implantation layer, a second epitaxial layer with a second ion implantation layer, and a third epitaxial layer with a third ion implantation layer on a substrate. The first, second, and third ion implantation layers can provide a red, green, and blue photodiode, respectively. A trench can be formed in the third epitaxial layer on the third ion implantation layer to remove the damaged surface of the third epitaxial layer. | 2009-03-05 |
20090057803 | SOLID-STATE IMAGING DEVICE, CAMERA AND METHOD OF PRODUCING THE SOLID-STATE IMAGE DEVICE - A solid-state imaging device in which a first conductive type epitaxial layer is formed on its first surface with an interconnection layer and light is received at a second surface of said epitaxial layer, the solid-state imaging device including: (a) a second conductive type region formed in said epitaxial layer with a first impurity concentration and storing a charge generated by a photoelectrical conversion, and (b) a first conductive type impurity layer formed closer to said second surface side of said epitaxial layer than said second conductive type region and having a second impurity concentration higher than the first impurity concentration; wherein the second impurity concentration has a concentration gradient increasing toward the second surface side. | 2009-03-05 |
20090057804 | THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS - The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor. | 2009-03-05 |
20090057805 | Ultraviolet sensor - The ultraviolet sensor has a ZnO layer composed of an oxide semiconductor including ZnO; a (Ni,Zn)O layer which is provided in contact with the ZnO layer and which is composed of an oxide semiconductor including NiO and ZnO solid-solved therein; a first terminal electrode electrically connected to the ZnO layer, and a second terminal electrode electrically connected to the (Ni,Zn)O layer. The ZnO layer is disposed at an ultraviolet ray receiving side. The (Ni,Zn)O layer is preferably formed of a sintered body. | 2009-03-05 |
20090057806 | SEGMENTED PHOTODIODE - In one embodiment of the present invention, the segmented photodiode includes a p type substrate, a p type epitaxial layer formed on the p type substrate, an n type epitaxial layer formed on the p type epitaxial layer, and p type segmenting region provided in the n type epitaxial layer separately from the p type epitaxial layer and segmenting the photosensitive region, and is configured that a depleted layer (first depleted layer) created in an n type region right under the segmenting section located between the p type segmenting region and the p type epitaxial layer by applying a reverse bias voltage is configured to reach a depleted layer (second depleted layer) formed in a junction surface between the n type epitaxial layer and the p type epitaxial layer so that the photosensitive region is electrically isolated. | 2009-03-05 |
20090057807 | SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF - The invention provides a Schottky barrier diode in which a forward voltage is low, a backward leakage current is small, and a withstanding voltage of an element is high, by improving both the forward voltage VF and the backward leakage current IR. A Schottky barrier diode of the invention includes a semiconductor substrate whose surface is provided with a semiconductor layer of first conduction type, a plurality of semiconductor layers of second conduction type provided as junction barriers at a predetermined depth from the surface of the semiconductor layer of first conduction type, an annular shape guard ring comprised of a semiconductor layer of second conduction type to surround the semiconductor layer of second conduction type on the surface of the semiconductor layer of first conduction type, and a metal layer disposed so as to contact the semiconductor layer of first conduction type and the semiconductor layer of second conduction type. In this Schottky barrier diode, a width of a depletion layer is determined such that an inside of the junction barrier is filled with the depletion layer upon application of a voltage. | 2009-03-05 |
20090057808 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND SUBSTRATE - A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device of the invention has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes. | 2009-03-05 |
20090057809 | STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY PROVIDING A STRESSED DIELECTRIC LAYER ABOVE A STRESS-NEUTRAL DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE - By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor. | 2009-03-05 |
20090057810 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure. | 2009-03-05 |
20090057811 | SIMOX WAFER MANUFACTURING METHOD AND SIMOX WAFER - A SIMOX wafer manufacturing method which is capable of providing etching conditions to prevent surface defects (divots) from being spread. The method includes an oxygen implantation process and a high temperature annealing step for forming a BOX layer, a front surface oxide film etching process to treat a front surface of the wafer at an area in which oxygen is implanted, and a rear surface oxide film etching process to treat a rear surface of the wafer, and oxide film etching conditions in the front and rear oxide film etching processes are controlled differently. | 2009-03-05 |
20090057812 | Semiconductor device having multiple element formation regions and manufacturing method thereof - In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed. | 2009-03-05 |
20090057813 | METHOD FOR SELF-ALIGNED REMOVAL OF A HIGH-K GATE DIELECTRIC ABOVE AN STI REGION - By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material. | 2009-03-05 |
20090057814 | SEMICONDUCTOR MEMORY - A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction. | 2009-03-05 |
20090057815 | FORMING CHANNEL STOP FOR DEEP TRENCH ISOLATION PRIOR TO DEEP TRENCH ETCH - Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed. | 2009-03-05 |
20090057816 | METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 2009-03-05 |
20090057817 | Microelectromechanical System and Process of Making the Same - A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure. | 2009-03-05 |
20090057818 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse. | 2009-03-05 |
20090057819 | ELECTRICAL FUSE DEVICE - The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link. | 2009-03-05 |
20090057820 | ABRUPT METAL-INSULATOR TRANSITION DEVICE WITH PARALLEL CONDUCTING LAYERS - An abrupt MIT (metal-insulator transition) device with parallel conducting layers is provided. The abrupt MIT device includes a first electrode disposed on a certain region of a substrate, a second electrode disposed so as to be spaced a predetermined distance apart from the first electrode, and at least one conducting layer electrically connecting the first electrode with the second electrode and having a width that allows the entire region of the conducting layer to be transformed into a metal layer due to an MIT. Due to this configuration, deterioration of the conducting layer, which is typically caused by current flowing through the conducting layer, is less likely to occur. | 2009-03-05 |
20090057821 | REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL - A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer. | 2009-03-05 |
20090057822 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a leadframe, a discrete passive circuit element, and an active circuit element. The discrete passive circuit element such as, for example, a discrete ferrite core inductor, is mounted either laterally or vertically adjacent to the leadframe. A semiconductor chip is attached to the discrete ferrite core inductor. Bond pads on the semiconductor chip may be electrically coupled to leads from the leadframe or to the discrete ferrite core inductor by wire bonds. The leadframe, discrete ferrite core inductor, semiconductor chip, and wire bonds are protected by an encapsulant such as a mold compound. Other passive circuit elements may be mounted to the discrete ferrite core inductor before encapsulation in the mold compound. | 2009-03-05 |
20090057823 | Semiconductor Structure with a Discontinuous Material Density for Reducing Eddy Currents - A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor. | 2009-03-05 |
20090057824 | INDUCTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An inductor of a semiconductor device and a method for manufacturing the same are disclosed. The inductor has a spiral structure, and includes a semiconductor substrate formed with a sub-structure. At least one metal line layer may be formed over the semiconductor substrate. At least one inductor line layer may be formed over the metal line layer. A space layer may be formed between the inductor line layer and the semiconductor substrate. | 2009-03-05 |
20090057825 | Semiconductor Device and a Method for Fabricating the Same - A semiconductor device including an inductor and a fabricating method thereof are provided. The semiconductor device can include a connection wiring provided on a semiconductor substrate; a metal wiring provided on an insulating layer in a spiral shape and electrically connected to the connection wiring; and holes provided in the insulating layer and between the metal wiring and the silicon substrate. | 2009-03-05 |
20090057826 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a capacitor plate includes a first propeller-shaped portion and a second propeller-shaped portion. A via portion is disposed between the first propeller-shaped portion and the second propeller-shaped portion. | 2009-03-05 |
20090057827 | CAPACITOR EMBEDDED IN INTERPOSER, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING CAPACITOR EMBEDDED IN INTERPOSER - As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes). | 2009-03-05 |
20090057828 | METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor having fast frequency characteristics and a method for manufacturing the same are disclosed. The disclosed MIM capacitor may include a first intermetal insulating film, a lower metal layer formed over the first intermetal insulating film, a second intermetal insulating film formed around the lower metal layer, and a third intermetal insulating film formed over the lower metal layer. A first-capacitor lower metal layer, a first-capacitor insulating film, a first-capacitor upper metal layer, and a first capping layer may be sequentially formed over a portion of the third intermetal insulating film. A first interlayer insulating film, a fourth intermetal insulating film, and a second interlayer insulating film may be sequentially formed over the third intermetal insulating film including the first capping layer. A second-capacitor lower metal layer may extend through the second interlayer insulating film and the first capping layer such that the second-capacitor lower metal layer is connected to the first-capacitor upper metal layer. A first passivation film may be formed over the second-capacitor lower metal layer. A second-capacitor upper metal layer may be formed over a portion of the first passivation film and extending through the first passivation film in a region where the second-capacitor lower metal layer is arranged such that the second-capacitor upper metal layer is connected to the second-capacitor lower metal layer. Second to fourth passivation films may be sequentially formed over the first passivation film including the second-capacitor upper metal layer. | 2009-03-05 |
20090057829 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING THE SAME - A semiconductor device includes a first wiring layer, a second wiring layer and an insulating layer provided between the first wiring layer and the second wiring layer. A capacitor has a first electrode formed on the first wiring layer and a second electrode formed on the second wiring layer in such a manner that the second electrode overlaps with the first electrode. To the first electrode, two connection wirings are connected and, to the second electrode, two connection wirings are connected. The two connection wirings are connected to each other with low DC impedance substantially only through the first electrode. Similarly, the two connection wirings are connected to each other with low DC impedance substantially only through the second electrode. | 2009-03-05 |
20090057830 | Semidoncudtor device and method of manufacturing the same - On a surface of a semiconductor substrate, an epitaxial layer of a conductivity type opposite to a conductivity type of the semiconductor substrate is formed, trenches are formed in portions other than a portion serving as a resistor, and the trenches are filled with an insulating film to three-dimensionally form U-shaped resistors which are separated from each other. | 2009-03-05 |
20090057831 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor. | 2009-03-05 |
20090057832 | Semiconductor device having diode-built-in IGBT and semiconductor device having diode-built-in DMOS - A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode. | 2009-03-05 |
20090057833 | SEMICONDUCTOR DEVICE STRUCTURE AND INTEGRATED CIRCUIT THEREFOR - A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements. | 2009-03-05 |
20090057834 | Method for Chemical Mechanical Planarization of Chalcogenide Materials - A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing. | 2009-03-05 |
20090057835 | Group III nitride semiconductor and a manufacturing method thereof - A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 μm nor more than 10 μm on a substrate made of either one of sapphire, SiC, and Si; forming a metal nitride layer having a plurality of substantially triangular-pyramid-shaped or triangular-trapezoid-shaped microcrystals by performing a heating nitridation process on the metal layer under a mixed gas atmosphere of ammonia; and depositing a group III nitride semiconductor layer on the metal nitride layer. | 2009-03-05 |
20090057836 | Semiconductor device having electrode film in which film thickness of periphery is thinner than film thickness of center - A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on first main face so as to surround first electrode, second electrode is integrated with first electrode by the same conducting material as that of the first electrode, and second electrode has a thinner film thickness than that of the first electrode. | 2009-03-05 |
20090057837 | WAFER WITH EDGE NOTCHES ENCODING WAFER IDENTIFICATION DESCRIPTOR - An apparatus includes a semiconductor wafer having a surface terminating in an edge. A plurality of notches is defined along the edge. The plurality of notches encodes a wafer identification descriptor for the wafer. A system for identifying wafers includes a wafer sorter. The wafer sorter is adapted to scan at least a portion of a wafer including the plurality of notches and decode the scan of the plurality of notches to generate a wafer identification descriptor for the wafer. | 2009-03-05 |
20090057838 | Manufacturing Method for Semiconductor Chips, and Semiconductor Chip - In a manufacturing method for performing plasma etching on a second surface of a semiconductor wafer that has a first surface where an insulating film is placed in dividing regions and the second surface which is opposite from the first surface and on which a mask for defining the dividing regions is placed thereby exposing the insulating film from etching bottom portions by removing portions that correspond to the dividing regions and subsequently continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma thereby removing corner portions put in contact with the insulating film in the device-formation-regions, isotropic etching is performed on the semiconductor wafer at any timing. | 2009-03-05 |
20090057839 | POLYMER-EMBEDDED SEMICONDUCTOR ROD ARRAYS - A structure consisting of well-ordered semiconductor structures embedded in a binder material which maintains the ordering and orientation of the semiconductor structures. Methods for forming such a structure include forming the semiconductor structures on a substrate, casting a binder material onto the substrate to embed the semiconductor structures in the binder material, and separating the binder material from the substrate at the substrate. These methods provide for the retention of the orientation and order of highly ordered semiconductor structures in the separated binder material. | 2009-03-05 |
20090057840 | WAFER MANUFACTURING METHOD, POLISHING APPARATUS, AND WAFER - The present invention provides a wafer manufacturing method and a wafer polishing apparatus which enable control of sags in a periphery of a wafer and improvement of nanotopology values thereof that is strongly required recently, and a wafer. In a polishing process for making a mirror surface of the wafer, a back surface of the wafer is polished to produce a reference plane thereof. | 2009-03-05 |
20090057841 | WAFER - A wafer having a device region, where a plurality of devices is formed, and an outer peripheral surplus region, which surrounds the device region, on the face of a circular wafer substrate is disclosed. A chamfered portion whose cross-sectional shape defines an arc-shaped surface in a range from the face to the back of the wafer substrate is formed in an outer peripheral end portion of the outer peripheral surplus region of the wafer substrate. A flat surface orthogonal to the face and the back is formed in the chamfered portion as a mark showing the crystal orientation of the wafer substrate. An identification code for specifying the wafer substrate is printed on the flat surface. | 2009-03-05 |
20090057842 | SELECTIVE REMOVAL OF ON-DIE REDISTRIBUTION INTERCONNECTS FROM SCRIBE-LINES - Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region. | 2009-03-05 |
20090057843 | SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies. | 2009-03-05 |
20090057844 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device | 2009-03-05 |
20090057845 | APPARATUS TO SAW WAFER AND HAVING NOZZLE TO REMOVE BURRS IN SCRIBE LANES, METHOD OF SAWING WAFER, AND SEMICONDUCTOR PACKAGE FABRICATED BY THE SAME - An apparatus to saw a wafer and having a nozzle to remove burrs in scribe lanes, a method of sawing a wafer, and a semiconductor package fabricated by the same. The apparatus includes a blade to cut scribe lanes of the wafer and a burr removing nozzle disposed spaced apart from the blade. The burr removing nozzle removes metal burrs generated adjacent to the blade during cutting the wafer. | 2009-03-05 |
20090057846 | METHOD TO FABRICATE ADJACENT SILICON FINS OF DIFFERING HEIGHTS - A method to fabricate adjacent silicon fins of differing heights comprises providing a silicon substrate having an isolation layer deposited thereon, patterning the isolation layer to form first and second isolation structures, patterning the silicon substrate to form a first silicon fin beneath the first isolation structure and a second silicon fin beneath the second isolation structure, depositing an insulating layer on the substrate, planarizing the insulating layer to expose top surfaces of the first and second isolation structures, depositing and patterning a masking layer to mask the first isolation structure but not the second isolation structure, applying a wet etch to remove the second isolation structure and expose the second silicon fin, epitaxially depositing a silicon layer on the second silicon fin, and recessing the insulating layer to expose at least a portion of the first silicon fin and at least a portion of the second silicon fin. | 2009-03-05 |
20090057847 | Gallium nitride wafer - A gallium nitride wafer | 2009-03-05 |
20090057848 | REDISTRIBUTION STRUCTURES FOR MICROFEATURE WORKPIECES - Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line. | 2009-03-05 |
20090057849 | INTERCONNECT IN A MULTI-ELEMENT PACKAGE - A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described. | 2009-03-05 |
20090057850 | Surface Mountable Semiconductor Package with Solder Bonding Features - A packaged circuit element such as an LED and a method for making the same are disclosed. The packaged circuit element includes a lead frame, a molded body, and a die containing the circuit element. The lead frame has first and second leads, each lead having first and second portions. The molded body surrounds the first portion of each lead, and the die is connected electrically to the first and second leads on the first portions of the first and second leads. The second portion of each of the first and second leads is substantially parallel to opposing side surfaces of the body and include a feature that inhibits molten solder from wetting a portion of the second section of each lead between the feature and the first portion of that lead while allowing the molten solder to wet the remaining surfaces of the second portions. | 2009-03-05 |
20090057851 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including: arranging multiple dies planarly between a first lead frame plate and a second lead frame plate, which face each other, to connect the multiple semiconductor chips to each of the first lead frame plate and the second lead frame plate; filling a resin between the first lead frame plate and the second lead frame plate to seal the multiple dies; performing a first dicing on a laminated body including the first lead frame plate, the resin, and the second lead frame plate, between the adjacent dies, to separate at least the first lead frame plate by cutting; applying plating to the laminated body with at least the first lead frame plate being separated by cutting; and performing a second dicing on a remainder of the laminated body between the adjacent dies, to separate the laminated body into individual semiconductor devices. | 2009-03-05 |
20090057852 | THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE - A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package. | 2009-03-05 |
20090057853 | Semiconductor power module with flexible circuit leadframe - A semiconductor power module includes a semiconductor chip thermally interfaced to a ceramic substrate and a leadframe defined by a flexible circuit disposed intermediate the chip and the ceramic substrate. The flexible circuit includes a conductor layer that is selectively encased in an insulated jacket to ensure adequate electrical insulation between the conductor layer and adjacent conductive surfaces. Preferably, the module is constructed for double side cooling by sandwiching the chip between a pair of ceramic substrates and providing intermediate flexible circuit leadframes on both sides of the chip for electrically accessing the chip terminals. | 2009-03-05 |
20090057854 | SELF LOCKING AND ALIGNING CLIP STRUCTURE FOR SEMICONDUCTOR DIE PACKAGE - A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure. | 2009-03-05 |
20090057855 | SEMICONDUCTOR DIE PACKAGE INCLUDING STAND OFF STRUCTURES - A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die. | 2009-03-05 |
20090057856 | BONDING-PATTERNED DEVICE AND ELECTRONIC COMPONENT - A bonding-patterned device comprises: a bonding layer provided on a bonding surface to be bonded to a mounting member. The bonding-patterned device has a planar shape which is generally a parallelogram. The bonding-patterned device is separated and cut out from a plate material along a plurality of evenly spaced straight lines, the surface of the plate material provided with the bonding layer being partitioned into a plurality of compartments by a plurality of evenly spaced straight lines parallel to each of the two pairs of opposite sides of the generally parallelogram shape. The plurality of compartments are classified into first compartments and second compartments alternately arranged in a checkerboard configuration, where the bonding layer is provided inside the first compartments, and the bonding layer is not provided in the second compartments and on the contours thereof. x=2nα and y=(2m−1)β, or y=2nβ and x=(2m−1)α where x and y are the lengths of the two pairs of opposite sides of the generally parallelogram shape, α and β are the lengths of two pairs of opposite sides of the compartment parallel to said x and y, respectively, and n and m are natural numbers, planar shapes of each bonding layer provided inside each of the first compartments are congruent each other, and locations of each bonding layer in each of the first compartment are identical. | 2009-03-05 |
20090057857 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lead frame according to one aspect of the present invention is used for a resin-sealed-type semiconductor device and includes a first lead frame having a frame body part and a lead part, and a second lead frame having a frame body part and a lead part. The lead part of the first lead frame and the lead part of the second lead frame do not contact with each other and an inner lead part formed in the lead part of the first lead frame and an inner lead part formed in the lead part of the second lead frame are provided in substantially the same plane when the frame body part of the first lead frame and the frame body part of the second lead frame are laminated together. | 2009-03-05 |
20090057858 | Low cost lead frame package and method for forming same - According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die. | 2009-03-05 |
20090057859 | WINDOW-TYPE BALL GRID ARRAY PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A window-type ball grid array (WBGA) package structure includes a substrate, fingers, traces, a solder mask, a die, a window mold compound and solder balls. The substrate has a first surface and a second surface and a window passing there-through. The fingers are on the first surface near the window, and each trace is on the first surface and connected to each finger. Moreover, the traces and a part of the fingers connected thereto are covered by the solder mask. The die is on the second surface and covers the window, and the window is filled by the window mold compound extendedly covering a part of a top surface of the solder mask. Additionally, the solder balls are on the first surface. Due to the foregoing structure, the stress near the fingers may be reduced and thus the lifetime of WBGA package structure may be efficiently increased. | 2009-03-05 |
20090057860 | Semiconductor memory package - Disclosed is a semiconductor memory package having a thin-film decoupling capacitor that reduces radio frequency noise. The semiconductor memory package in accordance with an embodiment of the present invention includes a substrate, a memory chip being mounted on one side of the substrate and a decoupling capacitor formed in the vicinity one the side of the substrate where the memory chip is mounted. | 2009-03-05 |
20090057861 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING - An integrated circuit package-in-package system includes: mounting a first integrated circuit device over a substrate; mounting an integrated circuit package system having an inner encapsulation over the first integrated circuit device with a first offset; mounting a second integrated circuit device over the first integrated circuit device and adjacent to the integrated circuit package system; connecting the integrated circuit package system and the substrate; and forming a package encapsulation as a cover for the first integrated circuit device, the integrated circuit package system, and the second integrated circuit device. | 2009-03-05 |
20090057862 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH CARRIER INTERPOSER - An integrated circuit package-in-package system includes: mounting an integrated circuit device over a package carrier; forming a subassembly including: providing an integrated circuit package system having a carrier interposer with an integrated circuit die thereover, and mounting a device under the carrier interposer; mounting the subassembly over the integrated circuit device; and encapsulating the subassembly and the integrated circuit device over the package carrier. | 2009-03-05 |
20090057863 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE - An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate; forming a package encapsulation having both a recess and an anti-mold flash feature over the package substrate and the integrated circuit package system including: forming the anti-mold flash feature having an extension width at the bottom of the recess, and partially exposing the mountable substrate in the recess with the anti-mold flash feature over mountable substrate; and mounting an integrated circuit device over the mountable substrate in the recess. | 2009-03-05 |
20090057864 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION - A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect. | 2009-03-05 |
20090057865 | SANDWICHED ORGANIC LGA STRUCTURE - An LGA structure is provided having at least one semiconductor device over a substrate and a mechanical load apparatus over the semiconductor device. The structure includes a load-distributing material between the mechanical load apparatus and the substrate. Specifically, the load-distributing material is proximate a first side of the semiconductor device and a second side of the semiconductor device opposite the first side of the semiconductor device. Furthermore, the load-distributing material completely surrounds the semiconductor device and contacts the mechanical load apparatus, the substrate, and the semiconductor device. The load-distributing material can be thermally conductive and comprises an elastomer and/or a liquid. The load-distributing material comprises a LGA interposer adapted to connect the substrate to a PCB below the substrate and/or a second substrate. Moreover, the load-distributing material comprises compressible material layers and rigid material layers. The load-distributing material comprises a rigid material incased in a compressible material. | 2009-03-05 |
20090057866 | Microelectronic Package Having Second Level Interconnects Including Stud Bumps and Method of Forming Same - A microelectronic package and a method of forming the package. The microelectronic package includes a first level package including: a package substrate having a die side and a carrier side a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects etectrically coupling the die to the package substrate. The microelectronic package further includes: a carrier having a substrate side, the first level package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the first level package to the carrier, each of the second level interconnects including a stud bump made substantially of Au. | 2009-03-05 |
20090057867 | Integrated Circuit Package with Passive Component - The present invention comprises a substrate, an integrated circuit mounted on the substrate, a passive component such as a capacitor mounted on the integrated circuit, and an encapsulation enclosing the integrated circuit and the passive component. The integrated circuit can be mounted in a flip-chip configuration with its active side facing the substrate and the passive component mounted on its backside or with its active side up with its backside on the substrate and the passive component mounted on the active side of the integrated circuit. | 2009-03-05 |
20090057868 | Wafer Level Chip Size Package For MEMS Devices And Method For Fabricating The Same - The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time. | 2009-03-05 |
20090057869 | CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION - A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging. | 2009-03-05 |
20090057870 | STACKED SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME - The stacked semiconductor package includes a substrate having a plurality of connection pads; a first semiconductor chip disposed over the substrate, a plurality of first bonding pads disposed at an first of the first semiconductor chip, redistributions extending from the first bonding pads to the middle of the upper face; wires for electrically connecting the first bonding pads to the connection pads; and a second semiconductor chip disposed over the first semiconductor chip leaving the first bonding pads exposed, and a plurality of second bonding pads disposed over the second semiconductor chip body and connected to the redistributions in a flip-chip manner. The stacked semiconductor package with this structure has a decreased volume, thus making the stacked semiconductor package more compact. | 2009-03-05 |
20090057871 | Ball Grid Array Package Enhanced With a Thermal and Electrical Connector - Ball grid array (BGA) packages are provided. A BGA package includes a substrate that has a surface and a stiffener that has a surface and a protruding portion. The surface of the substrate has an opening therein. The protruding portion is located on the surface of the stiffener. The surface of the stiffener is coupled to the surface of the substrate. The protruding portion extends through the opening. An area of the surface of the stiffener is less than an area of the surface of the substrate. A surface of the protruding portion is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. | 2009-03-05 |
20090057872 | Through-Chip Via Interconnects for Stacked Integrated Circuit Structures - A stacked IC structure has an integrated circuit (IC) having a front IC side, a back IC side, and a first conductive feature formed on the front IC side. A through-chip via connects to the first conductive feature on the front IC side. A substrate has an external circuit formed on a front surface. The IC attaches to the front surface of the substrate and the through-chip via forms a connection between the first conductive feature and the external circuit. | 2009-03-05 |
20090057873 | Packaging substrate structure with electronic component embedded therein and method for manufacture of the same - A packaging substrate structure with an electronic component embedded therein and a fabricating method thereof are disclosed. The packaging substrate structure comprises a core plate; a first built-up structure disposed on a surface of the core plate and comprising a first dielectric layer and a first circuit layer disposed on the first dielectric layer; a second built-up structure disposed on the first built-up structure, wherein a cavity is disposed in the second built-up structure to expose the first built-up structure; an electronic component disposed in the cavity, wherein the electronic component has an active surface having a plurality of electrode pads and an inactive surface facing the first built-up structure; and a solder mask disposed on the surfaces of the second built-up structure and the electronic component, and having a plurality of first openings to expose the electrode pads of the electronic component. | 2009-03-05 |
20090057874 | SEMICONDUCTOR MODULE INCLUDING SEMICONDUCTOR CHIPS IN A PLASTIC HOUSING IN SEPARATE REGIONS - Semiconductor module comprising semiconductor chips in a plastic housing in separate regions and method for producing the same | 2009-03-05 |
20090057875 | Semiconductor device - A highly reliable semiconductor device which is not damaged by local pressing force from the outside and in which unevenness of a portion where an antenna and an element overlap with each other is reduced. The semiconductor device includes a chip and an antenna. The chip includes a semiconductor element layer including a thin film transistor; a conductive resin electrically connected to the semiconductor element layer; and a sealing layer. The sealing layer in which a fiber body is impregnated with an organic resin covers the semiconductor element layer and the conductive resin, and has a thickness of 10 to 100 μm. The antenna has a depressed portion and is electrically connected to the semiconductor element layer through the conductive resin. The chip is embedded inside the depressed portion. The thickness of the chip is equal to the depth of the depressed portion. | 2009-03-05 |
20090057876 | STACKED PACKAGE STRUCTURE FOR REDUCING PACKAGE VOLUME OF AN ACOUSTIC MICRO-SENSOR - A stacked package structure utilizes flip-chip technology to stack an acoustic micro-sensor on an integrated circuit (IC) device having a recess as a back chamber and cover the acoustic micro-sensor using a glass substrate or a planar substrate with an aperture. With the use of the stacked package structure, the package volume of the acoustic micro-sensor can be reduced effectively. | 2009-03-05 |
20090057877 | Semiconductor Device with Gel-Type Thermal Interface Material - Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a catalyst material are applied to the metal layer prior to forming the gel-type thermal interface material layer to facilitate bonding between the gel-type thermal interface material layer and the metal layer. | 2009-03-05 |
20090057878 | SEMICONDUCTOR DIE PACKAGE INCLUDING HEAT SINKS - A semiconductor die package including at least two heat sinks. The semiconductor die package includes a first heat sink, a second heat sink coupled to the first heat sink, and a semiconductor die between the first heat sink and the second heat sink. The semiconductor die is electrically coupled to the first heat sink and the second heat sink. The semiconductor die may also be attached to a lead. | 2009-03-05 |
20090057879 | STRUCTURE AND PROCESS FOR ELECTRICAL INTERCONNECT AND THERMAL MANAGEMENT - A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element. The method supplies a fluid through the entrance through-hole, flows the fluid through the coolant channel between the first substrate and second substrates, and removes the fluid from the coolant channel through the exit through-hole. | 2009-03-05 |
20090057880 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, STACKED MODULE, CARD, SYSTEM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices. | 2009-03-05 |
20090057881 | MICROELECTRONIC PACKAGE AND METHOD OF COOLING SAME - A microelectronic package comprises a chip stack ( | 2009-03-05 |
20090057882 | Fluid cooled semiconductor power module having double-sided cooling - A semiconductor power module includes one or more power semiconductor power devices sandwiched between a fluid conducting base and a fluid conducting cover joined to the base. Fluid coolant entering the base diverges into a first flow path through the base and a second parallel flow path through the cover, and then converges and discharges through an outlet. The semiconductor devices have upper and lower active areas that are thermally coupled to inboard faces of the cover and base for low double-sided thermal resistance, and the devices are electrically accessed through a set of terminals formed on the base. Multiple sets of semiconductor power devices are double-side cooled by joining multiple fluid conducting covers to the base such that the coolant successively diverges and then re-converges at the locations where each cover is joined to the base. Preferably, the flow paths in both the base and cover include integral features for enhancing the surface area in contact with the coolant. | 2009-03-05 |
20090057883 | Method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package - A method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package is disclosed. In one embodiment, a method includes forming a dam structure on an outer area of a substrate surface of a semiconductor package and blocking a flow of a mold material from a mold cavity of the semiconductor package to the outer area of the substrate surface using the dam structure. In another embodiment, a substrate surface of a semiconductor package includes product forming areas to provide mounting spaces of semiconductor chips and staggered offset mesh block areas surrounding the product forming areas to act as dam structures to minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface. | 2009-03-05 |
20090057884 | Multi-Chip Package - Various semiconductor chip packages and package lids are disclosed. In one aspect, a method of manufacturing is provided that includes forming a semiconductor chip package lid with a peripheral wall that defines a first interior space. A first bridge structure is formed in the first interior space. The first bridge structure is adapted to engage a surface of a substrate. | 2009-03-05 |
20090057885 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a semiconductor chip having a main surface, wherein a first molding compound accommodates the semiconductor chip. The first molding compound has a surface that is substantially coplanar to the main surface of the semiconductor chip. A second molding compound is arranged in a space between the first molding compound and the semiconductor chip. | 2009-03-05 |
20090057886 | SEMICONDUCTOR DEVICE AND SUBSTRATE - A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes. | 2009-03-05 |
20090057887 | WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. | 2009-03-05 |
20090057888 | IC Package Having IC-to-PCB Interconnects on the Top and Bottom of the Package Substrate - An integrated circuit package, according to one embodiment, includes a package substrate, an interface stratum and an integrated circuit die. Both the IC die and interface stratum are disposed on the package substrate. The integrated circuit die includes a microelectronic circuit having a plurality of inputs and outputs. A first set of the inputs and outputs are electrically coupled to a plurality of package-to-circuit connection regions on the package substrate. A second set of input and outputs are electrically coupled through the package substrate to package-to-circuit connection regions on the interface stratum. | 2009-03-05 |