| 09th week of 2010 patent applcation highlights part 13 |
| Patent application number | Title | Published |
|---|
| 20100052688 | ELECTROMAGNETIC SURVEYING - A method of determining the nature of subterranean strata. The transmitter antenna is towed by vessel at a distance h above the sea floor. The antenna omits a wave field whose strength is proportional to the current delivered to the antenna and this is monitored. The input voltage to the antenna is also measured and changes in antenna impedance are calculated. Changes in antenna impedance are used together with seismic information to determine the nature of the subsea strata. | 2010-03-04 |
| 20100052689 | Magnetic Field Deflector in an Induction Resistivity Tool - A downhole induction resistivity assembly comprises a mandrel. Disposed around the mandrel are coils of wire disposed circumferentially around magnetic field concentrators. The coils of wire and the magnetic field concentrators are disposed on an outer diameter of the mandrel. A magnetic field deflector, of magnetic permeability greater than the mandrel, is disposed intermediate the coils and the mandrel. | 2010-03-04 |
| 20100052690 | Formation Resistivity Imaging in Conductive Boreholes - An apparatus for providing an image of a resistivity property of an earth formation surrounding a borehole is provided. The apparatus, in one aspect, may include a plurality of measure electrodes that are configured to convey an electrical current into the earth formation. In one aspect, each measure electrode may be substantially surrounded by an associated insulator that extends away from a tool body in a manner that blocks at least a portion of a vertical current flowing in a conductive fluid when the tool is operated to log the borehole. A processor provides an image of the resistivity property of the earth formation using the current in plurality of measure electrodes. | 2010-03-04 |
| 20100052691 | Time Alert Device for Use Together with an Earth Leakage Protection Device - This invention relates to a time alert device ( | 2010-03-04 |
| 20100052692 | CAR BATTERY SYSTEM - The car battery system of the present invention is provided with battery blocks | 2010-03-04 |
| 20100052693 | Method and Apparatus for Measuring Data Rates - A method, computer readable storage medium and apparatus for measuring data rates is disclosed. A method that incorporates the teachings of the present disclosure may include, for example, submitting a signal over a cable from a Time Domain Reflectometry (TDR) element, determining a fault in the cable from a reflection of the signal, determining a length of the cable from the reflection of the signal, determining a location of a bridged tap relative to customer premise equipment (CPE) and determining effective downstream bit rates for the cable according to the fault, the length of the cable and the location of the bridged tap relative to the CPE. Additional steps and embodiments are disclosed. | 2010-03-04 |
| 20100052694 | Test Circuit - A test circuit according to the present invention includes: a synthesis circuit that synthesizes a first test result signal output from a first test target circuit in response to a test instruction, and a second test result signal output from a second test target circuit in response to the test instruction; an inter-block delay generation circuit that delays the second test result signal with respect to the first test result signal; and a test result holding circuit that holds a synthesized test result signal every predetermined timing, the synthesized test result signal being output from the synthesis circuit | 2010-03-04 |
| 20100052695 | SWITCHING DEVICE - The invention relates to a switching device for the alternate connection of at least one first test port or of a second test port to a measuring-device connection, where the measuring-device connection provides at least one test-signal input. The test-signal input is connected to a first signal path and to a second signal path, where the first signal path is connected alternately to the first or to the second test port, and the second signal path is connected at least to the respectively other test port. | 2010-03-04 |
| 20100052696 | Chip Testing Apparatus and Testing Method Thereof - A chip testing apparatus and a chip testing method are provided. The chip testing apparatus includes a command generating module, a transceiving module and a control module. When the command generating module generates a first test command, the transceiving module transmits the first test command to a radio frequency identification (RFID) chip and receives a target test result from the RFID chip. The control module determines whether the target test result complies with a reference test result. When the determination result of the control module is no, the control module controls the command generating module to generate a second test command for retesting the RFID chip. | 2010-03-04 |
| 20100052697 | REPAIRING DEFECTS - Methods and systems for defect repair are disclosed. The methods include: (a) identifying a defect causing an absence of an electrical connection between a first circuit element and a second circuit element, the first and second circuit elements being positioned in or on a substrate and the defect being positioned in the substrate; (b) removing a portion of the substrate to expose the defect, and depositing a conductive material to electrically connect the first and second circuit elements; and (c) verifying that the defect caused the absence of an electrical connection between the first and second circuit elements. | 2010-03-04 |
| 20100052698 | Integrated circuit architecture for testing variable delay circuit - An integrated circuit is provided with first and second variable delay circuits, a test data feeding circuitry, a test control circuit, and a wire-connection line. The test data feeding circuitry feeds first and second test data signals to the first and second variable delay circuits, respectively. The first and second test data signals are complement to each other. The test control circuit feeds first and second drive capability control signals to the first and second variable delay circuits to control drive capabilities of the first and second variable delay circuits. The wire-connection line provides a wire-connection for outputs of the first and second variable delay circuits. | 2010-03-04 |
| 20100052699 | METHOD FOR INSTANTANEOUSLY DETERMINING RATES OF DISTORTION OF SIGNALS ON AN AC ELECTRICAL NETWORK, AND ASSOCIATED DEVICE - A method for instantaneously determining rates of distortion on variable frequency signals, and an associated device, in which a harmonic distortion rate is calculated across the shortest possible temporal window, corresponding to the duration of a period of a given signal's fundamental. Hence, the aim being to precisely determine the signal frequency value, whose HDR is to be calculated, an iteration of certain measurements, achieved at the time of a given calculation, is embodied in order to calculate the HDR on subsequent signals. | 2010-03-04 |
| 20100052700 | CAPACITIVE SENSOR - A shield electrode is provided in parallel with a sensor electrode. A detecting circuit detects a capacitance formed thereby around the sensor electrode. A capacitance-voltage conversion circuit converts the capacitance into a voltage by repeating a predetermined sequence. A shield electrode drive unit switches an electric state of the shield electrode in synchronization with the predetermined sequence. The shield electrode drive unit switches an electric state of the shield electrode in accordance with an electric state of the sensor electrode. | 2010-03-04 |
| 20100052701 | Nanoscale Displacement Transducer - Embodiments of the invention relate to nanoscale measurement of displacement. In one embodiment, a measurement apparatus includes a first plurality of nanoparticles coupled to a first substrate electrically coupled to a second plurality of nanoparticles coupled to a second substrate with a guide or guides disposed between the first substrate and the second substrate that allow for the substrates to move relative to each other. | 2010-03-04 |
| 20100052702 | APPARATUS FOR MEASURING TOTAL ACID NUMBER OF OIL AND ESTIMATING LIFETIME OF OIL, AND METHOD FOR MEASURING TOTAL ACID NUMBER OF OIL AND OIL SENSOR USING THE SAME - Disclosed herein are an apparatus for measuring the total acid number of oil, an apparatus for measuring the lifetime of oil through the measurement of the total acid number of oil, a method for measuring the total acid number of oil, and a method of making measurements using an oil sensor. According to the disclosed invention, measurement accuracy can be increased through the use of a high-sensitivity conductance measuring sensor, the inventive apparatus can be applied to both lubricant oil and insulating oil, the size of the total acid number-measuring apparatus can be reduced. | 2010-03-04 |
| 20100052703 | ICE THICKNESS PROBE, ICE THICKNESS PROBE ASSEMBLY AND ICE THICKNESS MONITORING APPARATUS - An ice thickness probe includes a longitudinally-extending probe rod, an insulator casing and a sleeve. The probe rod is fabricated from an electrically-conductive material. The insulator casing is fabricated from an electrically-insulative material and is wrapped around, is in contact with and extends along the probe rod. The sleeve is fabricated from a stiff yet resilient material and is wrapped around, is in contact with and extends along the insulator casing. The insulator casing and the sleeve are concentrically disposed about the probe rod as viewed in cross-section. An ice thickness probe assembly includes a frame structure, a reference bar and at least one ice thickness probe. An ice thickness monitoring apparatus is used in a thermal storage coil having a tank containing water and a tube disposed in the water so that, when the thermal ice storage coil is energized, ice is produced and accumulates on the tube. | 2010-03-04 |
| 20100052704 | HYBRID RESILIENT AND FRANGIBLE LAYERED STRUCTURAL HEALTH SENSOR - A sensor for monitoring and testing for both possible fractures and corrosion in structural elements is disclosed. A frangible material layer including a thin breakable conductor sense loop and a resilient material layer including a conductive corrosion sense loop bonded on top of the frangible layer form an assembly which is bonded to a structural element to be tested. Portions of the conductive corrosion sense loop are exposed through weep holes in the resilient material layer. A fracture in the bonded structural element induces a disruption in both the frangible membrane and the thin breakable conductor sense loop and corrosion of the conductive corrosion sense loop changes its electrical properties. Measured electrical property changes of the disrupted conductor sense loop and/or the conductive corrosion sense loop reveal possible damage. Both sensor layers may utilize a single shared wireless communications tag to couple to an electrical measuring device. | 2010-03-04 |
| 20100052705 | DEVICE FOR DETECTING THE STATE OF A SWITCH - A device for detecting the state of a switch. The device includes a detection circuit which delivers a signal of specified value (V | 2010-03-04 |
| 20100052706 | CONSISTANT AND QUANTITATIVE METHOD FOR TCO DELAMINATION EVALUATION - A method and apparatus for manufacturing photovoltaic cells is provided. In one embodiment, a method for evaluating transparent conductive oxide (TCO) delamination from a substrate is provided. The method comprises providing a glass substrate with a TCO film laminated on a first surface of the glass substrate, depositing a metal layer on a second surface of the glass substrate opposite the first surface, heating the substrate while applying a bias to the substrate, cooling the substrate in a humidity controlled environment for a fixed time period, dividing the TCO film into a plurality of electrically insulated channels using a laser scribing process, and measuring a resistance of each of the plurality of electrically insulated channels. | 2010-03-04 |
| 20100052707 | Probe Card - A probe card includes probes that come into contact with a semiconductor wafer to receive or output an electric signal; a probe head that holds the probes; a substrate that has a wiring pattern corresponding to a circuit structure for generating a signal for a test; a reinforcing member that reinforces the substrate; an interposer that is stacked on the substrate and includes a housing having connection terminals resilient in an axial direction thereof and hole portions each housing one of the connection terminals; and a space transformer that is stacked between the interposer and the probe head and transforms intervals among the wires. | 2010-03-04 |
| 20100052728 | LOAD SENSE AND ACTIVE NOISE REDUCTION FOR I/O CIRCUIT - An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive. | 2010-03-04 |
| 20100052729 | DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT - An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word. | 2010-03-04 |
| 20100052730 | METHOD AND APPARATUS FOR LATE TIMING TRANSITION DETECTION - Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed. | 2010-03-04 |
| 20100052731 | MULTIPLE CHANNEL BALLAST AND NETWORKABLE TOPOLOGY AND SYSTEM INCLUDING POWER LINE CARRIER APPLICATIONS - Control systems and methods for independent control of power systems, particularly lighting network branches, and separate control of individual branch components. Multi-branch systems comprise independently controllable branches that inter-communicate via PLC communications. In each branch, components such as ballasts, local control units, sensors, actuators, and repeaters, may exchange commands and queries independently of a branch remote control unit (BRCU). Alternatively, a BRCU may manage or arbitrate communications, or interact with other BRCUs, other control units and external management systems. Ballasts include a multi-channel ballast that enables close-loop control of individual fixtures, or of individual dimmable or non-dimmable lamps within a fixture. The close-loop control is facilitated by sampling circuits/sensors co-located with each controlled fixture or lamp. All controllers are preferably implemented using an integrated digital controller. The PLC communication is preferably carried out by a direct spread spectrum method that eliminates side lobes from a cross-correlation function, using an anti-collision protocol. | 2010-03-04 |
| 20100052732 | FREQUENCY DETECTION CIRCUIT - In some preferred embodiments, a switched capacitor circuit configured to change its equivalent resistance depending on the frequency of an input clock signal and a resistor element are connected in series. A power source voltage is divided by the equivalent resistance of the switched capacitor circuit and the resistance of the resistor element, and the divided voltage is inputted to a Schmitt circuit. The Schmitt circuit outputs a high-level signal when the inputted divided voltage is higher than a threshold voltage and a low-level signal when the inputted divided voltage is lower than a threshold voltage. Thus, depending on the frequency of the input clock signal, a high-level signal or a low-level signal is outputted. | 2010-03-04 |
| 20100052733 | COMPARATOR CIRCUIT - A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage. | 2010-03-04 |
| 20100052734 | SYSTEM FOR PROVIDING LARGE RC TIME CONSTANTS IN INTEGRATED CIRCUITS - A peak detector for implementation in a monolithic integrated circuit includes one or more Miller capacitors and one or more transistors for selectively setting large RC time constant values only with components included in the integrated circuit's die. Neither resistors nor capacitors located outside the integrated circuit are used for setting a selected value of a time constant. Some embodiments of the invention include diodes for compensation of amplifier leakage current in the peak detector, thereby increasing a maximum value of a time constant that can be implemented in an integrated circuit. A peak detector in accord with an embodiment of the invention may optionally be configured for either single-ended or differential operation. | 2010-03-04 |
| 20100052735 | SLEW RATE CONTROLLED LEVEL SHIFTER WITH REDUCED QUIESCENT CURRENT - A level shifter circuit includes two parallel current paths respectively controlled by switch transistors, a Wilson current mirror circuit, and a slew rate control circuit to selectively couple an output node either to a high (first) voltage source or to a ground (second voltage) source in response to differential input control signals signal. When the output node reaches a stable (high or low) voltage level, the low voltage on one of the current paths turns off a Wilson current mirror transistor in the other current path, thereby preventing quiescent current during stable periods. An optional cascode transistor is added to facilitate fabrication using low threshold voltage transistors. | 2010-03-04 |
| 20100052736 | SIGNAL GENERATING APPARATUS, TEST APPARATUS AND CIRCUIT DEVICE - There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of data of the pattern data is propagated sequentially in response to the periodic signal, a waveform generating section that generates the output signal whose value varies in accordance with a cycle of the periodic signal, based on data values output from the plurality of flip-flops, and an analog circuit that enhances a predetermined frequency component in a waveform of the output signal generated by the waveform generating section. | 2010-03-04 |
| 20100052737 | SOURCE DRIVING CIRCUIT FOR PREVENTING GAMMA COUPLING - During transition, level shifters in a source driver output logic high signals to PMOS DACs and output logic low signals to NMOS DACs for shutting down current paths in the PMOS DACs and in the NMOS DACs. Therefore, during transition, the PMOS DACs and the NMOS DACs are at high-impedance stage for preventing gamma coupling effect. | 2010-03-04 |
| 20100052738 | FREQUENCY DIVIDER FOR WIRELESS COMMUNICATION SYSTEM AND DRIVING METHOD THEREOF - A frequency divider for a wireless communication system is provided. A frequency divider includes a body bias voltage generator and a divider. The body bias voltage generator generates a body bias voltage including a PMOS body bias voltage and an NMOS body bias voltage whose voltage levels are controlled according to an input signal. The divider includes a plurality of flip-flops whose operation points are determined according to the body bias voltage, and generates an output signal by dividing a frequency of the input signal by N. Each of the flip-flops may include a PMOS logic and an NMOS logic. The PMOS logic may include a plurality of PMOS transistors whose operation points are determined according to the PMOS body bias voltage. The NMOS logic may be connected electrically to the PMOS logic and include a plurality of NMOS transistors whose operation points are determined according to the NMOS body bias voltage. | 2010-03-04 |
| 20100052739 | Device and control method of device - A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed. | 2010-03-04 |
| 20100052740 | CLOCK SIGNAL FREQUENCY DIVIDING CIRCUIT AND CLOCK SIGNAL FREQUENCY DIVIDING METHOD - To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit ( | 2010-03-04 |
| 20100052741 | DUAL INTEGRATOR CIRCUIT FOR ANALOG FRONT END (AFE) - A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter. | 2010-03-04 |
| 20100052742 | LIMIT SIGNAL GENERATOR, PWM CONTROL CIRCUIT, AND PWM CONTROL METHOD THEREOF - A PWM control circuit is disclosed. An oscillator generates a triangular signal, received by a limit signal generator to produce a limit signal accordingly. Corresponding to a rising period of the triangular signal, the limit signal sequentially experiences a first holding period, a rising period and a second holding period, wherein the limit signal has a first predetermined value during the first holding period and a second predetermined value during the second holding period. A compare/control circuit compares the limit signal with a detection signal corresponding to a current through a power switch, and controls the power switch accordingly. | 2010-03-04 |
| 20100052743 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD - The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state. | 2010-03-04 |
| 20100052744 | Multiphase Clock Generator with Enhanced Phase Control - A multi-phase clock generator circuit receives an input clock signal and produces multiple output clock signal, each from a respective delay stage of a multi-stage voltage-controlled delay line (VCDL). The rising edges of the multiple output clock signals produced by the circuit are substantially equidistant in time from one another and have substantially equal phase spacing. | 2010-03-04 |
| 20100052745 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock. | 2010-03-04 |
| 20100052746 | VOLTAGE-CONTROLLED OSCILLATOR, PHASE-LOCKED LOOP (PLL) CIRCUIT, AND CLOCK GENERATOR - A voltage-controlled oscillator includes a voltage regulator, and a delay unit. The voltage regulator independently receives a first oscillation control signal and a second oscillation control signal to provide a regulated voltage signal which is represented by a regular ratio of combination of the first and second oscillation control signals, and the regulated voltage signal is feedback to the voltage regulator. The delay unit generates an output signal having a frequency varying in response to the regulated voltage signal. | 2010-03-04 |
| 20100052747 | PLL FREQUENCY SYNTHESIZER - A PLL frequency synthesizer | 2010-03-04 |
| 20100052778 | Nth Order Tunable Low-Pass Continuous Time Filter for Fiber Optic Receivers - According to one embodiment of the invention, a circuit comprising a plurality of operational transconductance amplifiers (OTAS) is described. The first OTA has differential input and differential output. The second OTA also has differential input, where a first output of the first OTA is coupled to the first differential input of the second OTA, which is an inverting input. A second output of the first OTA is coupled to the second input of the second OTA, which is a non-inverting input. The first differential output being coupled to a first input of the first OTA and the second differential output being coupled to a second input of the first OTA for negative feedback and current biasing. | 2010-03-04 |
| 20100052779 | DOHERTY AMPLIFIER AND SIGNAL AMPLIFICATION SYSTEM HAVING THE SAME, METHOD FOR AMPLIFYING SIGNAL - A Doherty amplifier is provided. The Doherty amplifier includes a first path circuit including a carrier amplifier and a first impedance adjusting circuit connected with the carrier amplifier; and a second path circuit including a peaking amplifier, a second impedance adjusting circuit connected with the peaking amplifier, and a peaking amplifier bias circuit connected with the peaking amplifier. At least one among an impedance of the first impedance adjusting circuit, an impedance of the second impedance adjusting circuit, and a bias of the peaking amplifier bias circuit is adjusted in response to a control signal. | 2010-03-04 |
| 20100052780 | METHOD OF AND CIRCUIT FOR REDUCING DISTORTION IN A POWER AMPLIFIER - An integrated circuit having a circuit for reducing distortion in a power amplifier is disclosed. The integrated circuit comprises a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circuit and an input/output port of the integrated circuit; and an estimator circuit coupled to the sample capture buffers, wherein the estimator circuit generates parameters for the predistortion circuit based upon the output of the predistortion circuit and an output of the power amplifier received at the input/output port of the integrated circuit. A method of reducing distortion in a power amplifier is also disclosed. | 2010-03-04 |
| 20100052781 | Correcting distortions at output of power amplifier - A solution is provided for correcting distortions on a radio frequency output signal of a power amplifier. There is provided an apparatus, comprising: a processor configured to determine at least one correction factor for a distortion on a radio frequency output signal of a power amplifier on the basis of estimated characteristics of a distorted time-varying supply voltage from a power supply to a power amplifier and an interface configured to feed the at least one correction factor to an input signal of the power amplifier. | 2010-03-04 |
| 20100052782 | TRANSFORMER AND STRUCTURE THEREOF AND POWER AMPLIFIER - A transformer and a structure thereof and a power amplifier are provided. The transformer includes a first inductor to a fourth inductor, a first capacitor, and a second capacitor. A first terminal of the first inductor receives a first signal. A first terminal of the second inductor is coupled to the first terminal of the first inductor. A first terminal of the third inductor receives a second signal, and a second terminal of the third inductor is coupled to a second terminal of the first inductor. A first terminal of the fourth inductor is coupled to the first terminal of the third inductor. The first capacitor is coupled between the first terminal of the first inductor and the first terminal of the third inductor. The second capacitor is coupled between a second terminal of the second inductor and a second terminal of the forth inductor. | 2010-03-04 |
| 20100052783 | CLASS-D AMPLIFIER - An amplifier that receives an input signal and outputs an amplified output signal includes an integration stage, a comparison stage, and a full bridge circuit. The integration stage is be used for receiving a constant common mode voltage, for receiving a first signal representing the input signal of the amplifier, and for generating a ramp signal. The comparison stage coupled to the integration stage is used for generating a pulse width modulation signal according to the ramp signal and according to a hysteretic signal. The full bridge circuit coupled to the comparison stage is used for receiving a power supply and the pulse width modulation signal, and for generating the output of the amplifier. | 2010-03-04 |
| 20100052784 | LOW NOISE AMPLIFIER - A low noise amplifier having a wide operating frequency band and a high dynamic range is provided. A transformer having a secondary winding connected between an input terminal to which an input signal is applied and a positive differential output terminal, and a primary winding connected between a negative differential output terminal and an input node is provided as a feedback circuit between a cascode amplifier circuit, which includes transistors and a resistor, and an output circuit, which includes a transistor and a constant current source. Selective use of a transformer whose leakage inductance has an adequate value as the feedback transformer can realize a low noise amplifier which has a wide operating frequency band and a high dynamic range. | 2010-03-04 |
| 20100052785 | DIFFERENTIAL AMPLIFIER, SAMPLE-AND-HOLD CIRCUIT, AND AMPLIFIER CIRCUIT - To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively. | 2010-03-04 |
| 20100052786 | AUTOMATIC GAIN CONTROL APPARATUS AND TECHNIQUE - An amplifier includes steering stages to receive a control signal and collectively provide an output signal. Each steering stage receives an associated input signal and contributes to the output signal based on the control signal. The amplifier includes an attenuator to selectively attenuate the input signals to form different gain control ranges for the amplifier. | 2010-03-04 |
| 20100052787 | LIMITING AMPLIFIERS - A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors. | 2010-03-04 |
| 20100052788 | BROADBAND MICROWAVE DEVICE WITH SWITCHABLE GAIN - The invention relates to a broadband microwave device with switchable gain comprising a microwave signal input E and output S, a distributed amplifier with a plurality of amplifying cells comprising an input transmission line for an input signal applied to the microwave signal input E, said input transmission line having one of its two ends linked to the microwave signal input E, an output transmission line for said amplified input signal having an output end of the distributed amplifier, the cells of the distributed amplifier settable either to an amplifying state or to a blocked state. A switch switches the microwave signal output S either to a non-amplification position linked to the other end of the input transmission line, or to an amplification position linked to the output end of the distributed amplifier. A control unit supplies switch position control and amplifying cell status control signals. | 2010-03-04 |
| 20100052789 | Power Amplifier With Output Power Control - This disclosure relates systems and methods for a power amplifier with output power control. The power amplifier can include multiple stages of amplification. An RF signal is fed to the power amplifier with output control that amplifies the power of the RF signal to meet operational requirements. A first stage of the power amplifier controls the output power via voltage regulation. An isolating device is introduced in the transmission path of the RF signal between the first stage and the following stages of the power amplifier. The isolating device ensures that the load impedance of the first stage remains fixed at a constant value. | 2010-03-04 |
| 20100052790 | AMPLIFIER CIRCUIT - An amplifier circuit includes a first amplifier amplifying an input signal and outputting a first amplified signal, a second amplifier amplifying the first amplified signal and outputting a second amplified signal, and a feedback circuitry feeding back the second amplified signal to the input of the second amplifier. The feedback circuitry includes a feedback transistor that keeps the input level of the second amplifier constant. | 2010-03-04 |
| 20100052791 | AMPLIFIER CIRCUIT - An amplifier circuit including: a multistage amplifier unit including an input-stage transistor and an output-stage transistor and configured to amplify an input signal and to output an amplified signal; and a feedback unit including a first feedback transistor, a second feedback transistor, and a feedback resistor, and configured to feed back the amplified signal to an input of the output-stage transistor in the multistage amplifier unit via the first feedback transistor, the second feedback transistor, and the feedback resistor. | 2010-03-04 |
| 20100052792 | AMPLIFYING APPARATUS, METHOD OF OUTPUT CONTROL AND CONTROL PROGRAM - [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component. | 2010-03-04 |
| 20100052793 | Resonant operating mode for a transistor - The PN junctions of a transistor are biased for operation in the active mode but an initial flow of current reverses the bias of the base-emitter junction causing the transistor to conduct a resonant current with a voltage less than the forward junction voltage of said base-emitter. | 2010-03-04 |
| 20100052794 | METHOD AND SYSTEM FOR IMPROVING EFFICIENCY OVER POWER CONTROL FOR LINEAR AND CLASS AB POWER AMPLIFIERS - Aspects of a system for improving efficiency over power control for linear and class AB power amplifiers may include a current source circuit that enables determination of a bias current level for a PA circuit within an IC die based on an amplitude of an input modulation signal. The PA circuit may enable generation of an output signal based on a differential input signal and the input modulation signal to the current source circuit. A generated bias voltage may be applied to a transformer external to the IC die, but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels may be applied to the PA circuit wherein the amplifier bias voltage levels may be derived from the generated bias voltage level and/or the determined bias current level. | 2010-03-04 |
| 20100052795 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2 | 2010-03-04 |
| 20100052796 | Device Having Digitally Controlled Oscillator - A device includes a digitally controlled oscillator and an interpolator having a data input and a data output coupled to the digitally controlled oscillator. The interpolator may be configured to receive an oscillator control signal at the data input and to provide an interpolated oscillator control signal at the data output. An interpolation rate of the interpolator may depend on the oscillator control signal. Alternatively, a device can include a digitally controlled oscillator having a control input, a sampling unit coupled to the control input of the digitally controlled oscillator, and a timing error detector coupled to an output of the digitally controlled oscillator. The sampling rate of the sampling unit can depend on an output of the timing error detector. | 2010-03-04 |
| 20100052797 | Direct digital synthesizer for reference frequency generation - A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency f | 2010-03-04 |
| 20100052798 | Phase-locked loop circuit - A first exemplary aspect of an embodiment of the present invention is a phase-locked loop circuit including: a voltage-current converter that converts a control voltage into a control current, the control voltage generated according to a phase difference between an input pulse signal and a feedback pulse signal fed back from an output side of a current controlled oscillator; the current controlled oscillator that generates an output pulse signal having a frequency according to the control current; a current detection unit that detects the control current; and a frequency range switch that switches a frequency range of the output pulse signal according to the detected control current. | 2010-03-04 |
| 20100052799 | VOLTAGE CONTROLLED OSCILLATOR, MMIC, AND HIGH FREQUENCY WIRELESS DEVICE - A voltage controlled oscillator having low phase noise and including: a variable resonator including a varactor and a control voltage terminal; and an open-end stub connected in parallel to the variable resonator, the open-end stub having a length shorter than or equal to an odd multiple of one quarter of a wavelength of a harmonic signal plus one sixteenth of the wavelength of the harmonic signal, and longer than or equal to an odd multiple of one quarter of the wavelength of the harmonic signal minus one sixteenth of the wavelength of the harmonic signal. In this structure, a high Q value is realized for a fundamental wave frequency. Fluctuation in a control voltage due to a harmonic signal is controlled. | 2010-03-04 |
| 20100052800 | METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK WITH A FREQUENCY OFFSET FROM AN IC SYSTEM CLOCK - Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop. | 2010-03-04 |
| 20100052801 | TEMPERATURE CONTROL DEVICE - A thermostatic-chamber temperature control device includes: a heating element for heating a thermostatic chamber; a bridge circuit having a temperature sensitive element whose resistance value varies in accordance with the temperature of the heating element; a detection circuit for detecting an unbalanced voltage of the bridge circuit; a PWM signal generating circuit for generating a PWM signal corresponding to the unbalanced voltage detected by the detection circuit; and a switching element that has a current output terminal connected to the heating element and a current input terminal connected to a power supply circuit and is driven on the basis of the PWM signal generated by the PWM signal generating circuit. | 2010-03-04 |
| 20100052802 | Constant-temperature type crystal oscillator - A constant-temperature type crystal oscillator includes: a crystal unit that is installed on one principal surface of a circuit substrate, and chip resistors, which function as heating elements, and which are installed on the other principal surface of the circuit substrate so as to face a principal surface of the crystal unit, the chip resistors heating up the crystal unit to keep an operational temperature of the crystal unit constant. A heating metal film facing the principal surface of the crystal unit is provided on the one principal surface of the circuit substrate. A heat conducting material is interposed between the principal surface of the crystal unit and the heating metal film to perform thermal coupling therebetween. The heating metal film is thermally coupled to electrode terminals of the chip resistors via a plurality of electrode through holes. | 2010-03-04 |
| 20100052803 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency. | 2010-03-04 |
| 20100052804 | PULSE WIDTH MODULATION DEVICE - A pulse width modulation device in which a step form control signal generated by a control signal generating device and a triangular wave carrier signal generated by a carrier generating device are compared by a digital comparator and the comparison signal is supplied to an edge detection device. Also, a top/bottom signal generated by a top/bottom signal generating device is supplied to the edge detection device The edge detection device includes an edge detection function that generates an edge detection signal by detecting change of the comparison signal. The edge detection function is inhibited by the edge detection signal; and inhibition is cancelled by the top/bottom signal so that the edge detection signal is output. A PWM signal is output from the pulse generating device in accordance with the comparison signal, edge detection signal, and top/bottom signal. | 2010-03-04 |
| 20100052805 | HIGH-MODE SELF-OSCILLATING PULSE MODULATOR - The invention relates to a high-mode self-oscillating pulse modulator. According to the invention, a complete rethinking of preconditions for oscillation and modulation in an oscillating modulator as all conventional thinking of how to apply oscillation in a modulator has been set aside. Thus, according to the invention, high-mode oscillation refers to an oscillation at a higher mode than the first mode, which is conventionally regarded as the one and only applicable mode in an oscillating modulator. | 2010-03-04 |
| 20100052806 | MODULATION FOR AMPLITUDE-MODULATING A SIGNAL - Modulators for amplitude-modulating signals defined by phase information and envelope codes are provided with first transistors for receiving the phase information and second transistors for receiving the envelope codes. The first main electrode of one transistor is coupled to the second main electrode of the other transistor and the other second main electrode constitutes an output of the modulator. This modulator can be used in any kind of transistor environment and is simple and low cost. The doped areas of the coupled first and second main electrodes comprise an overlap to reduce cross-talk and to reduce silicon area. Polar transmitters are provided with this modulator and with a circuit for generating a phase/frequency code and the envelope code and with an oscillator for receiving the phase/frequency code and for generating the phase information. A phase shift between the phase information and the envelope code reduce aliases. | 2010-03-04 |
| 20100052807 | ACOUSTIC WAVE FILTER DEVICE - An acoustic wave filter device includes a plurality of acoustic wave filters disposed on the same piezoelectric substrate, and achieves enlargement of out-of-passband attenuation without a large increase in its size. For at least the first acoustic wave filter, ends of second IDTs and of third IDTs connected to first and second balanced terminals, the ends being connected to a ground potential, are connected to a common connection line, the common connection line is connected to a ground terminal by a ground line, and a distance between a connection point, at which the ground line is connected to the common connection line, and the first balanced terminal, and a distance between the connection point and the second balanced terminal, is the same or substantially the same. | 2010-03-04 |
| 20100052818 | MULTI-CHANNEL SURFACE ACOUSTIC WAVE FILTER DEVICE WITH VOLTAGE CONTROLLED TUNABLE FREQUENCY RESPONSE - A multi-channel surface acoustic wave (SAW) filter includes a voltage controlled velocity tunable piezoelectric substrate, an input transducer fabricated on the substrate, and an output transducer fabricated on the substrate. The input transducer further includes multiple input sub-transducers that are electrically and physically connected in parallel. The output transducer further includes multiple output sub-transducers that are electrically and physically connected in parallel. Corresponding pairs of input sub-transducers and output sub-transducers form multiple parallel channels for SAW propagation. The input transducer produces a voltage controlled tunable COMB frequency response that is combined with a voltage controlled tunable COMB frequency response produced by the output transducer to produce a SAW filter voltage controlled tunable frequency response. Further embodiments include a multi-channel SAW resonator, a SAW filter device connecting two novel SAW filters in series, and a SAW filter device connecting two novel SAW resonators in series. | 2010-03-04 |
| 20100052819 | ACOUSTIC WAVE DEVICE AND SYSTEM - An acoustic wave device includes: a piezoelectric substrate; at least five IDTs (InterDigital Transducers) arranged on the substrate in directions of SAW (Surface Acoustic Wave) propagation; and two balanced terminals connected to two first IDTs that are two out of the at least five IDTs and are 180 degrees out of phase. One of a pair of comb electrodes of one of the two first IDTs is connected to one of the two balanced terminals, and one of a pair of comb electrodes of the other one of the two first IDTs being connected to the other one of the two balanced terminals. The other comb electrodes of the two first IDTs are connected in series, and one of a pair of comb electrodes that form an IDT that is included in the at least five IDTs and is not connected to the two first IDTs is grounded. | 2010-03-04 |
| 20100052820 | COMMON MODE FILTERING METHOD AND DEVICE - Provided are common mode filtering method and device for use with a defected ground structure, the device including a substrate, coupled microstrip lines formed on the substrate and a ground plane formed underneath the substrate, the common mode filtering method being characterized by forming at least a defected ground structure on the ground plane and making dual mode signals pass through the coupled microstrip lines, thereby using the defected ground structure to suppress dual model noises within a specific frequency band and prevent signal distortion. | 2010-03-04 |
| 20100052821 | COMPACT FILTERING STRUCTURE - An electromagnetic band gap (EGB) structure includes a substrate made of an isolating material. A plurality of identical planar transmission line segments are formed one under another in conductor layers embedded in the substrate. Vertical transitions connect one by one the plurality of planar transmission line segments. Adjacent ones of the vertical transitions are equally spaced on a predetermined distance in a direction parallel to the transmission line segments, thereby the vertical transitions serve as periodical inclusions forming the EBG structure. | 2010-03-04 |
| 20100052822 | WAVEGUIDE, ANTENNA AND VEHICULAR RADAR APPARATUS - A waveguide, that is improved in size, costs, manufacturing and in durability, has a base having a mounting surface, and a plate member held on the mounting surface of the base for defining a waveguide in cooperation with the base. The mounting surface of the base is a curved surface defined by a sweep of a flexure curve of the plate member when it is loaded along a straight line. The plate member is attached to the base in such a manner that the plate member is pressed against and curved along the mounting surface, and that the plate member has a curvature direction edge portion extending in a curvature direction which is a general extension of the flexure curve and a sweep direction edge portion extending in a direction of the sweep of the curve. | 2010-03-04 |
| 20100052823 | FILTER UNIT - A filter unit comprises a cover and a base. The cover includes a number of first grooves, and the base includes a number of second grooves aligned with the first grooves. At least one of the cover or the base includes an alloy of zinc and aluminum, wherein the weight percentage of zinc is greater than that of aluminum. | 2010-03-04 |
| 20100052824 | Radio Frequency Filter - A radio frequency filter comprising: housing body having input/output connectors and containing space which is divided into spaces by means of diaphragm; at least one resonator rod arranged in the housing; housing cover coupled to the housing body; wherein the housing body and the housing cover are coupled to each other by laser welding. The radio frequency filter according to the present invention can reduce PIMD due to reduce Contact Nonlinearity, and inhibit to erode away because the laser welding method dissolve different metallic materials each other and take a convalent bond, and reduce its manufacturing process time and cost because it is unnecessary drilling a hole and fastening a screw to fasten the housing and the housing cover each other and can simplify its manufacturing process and raise productivity because only irradiate laser beam on irradiated area of the housing cover. | 2010-03-04 |
| 20100052825 | SURFACE-MOUNTABLE WAVEGUIDE ARRANGEMENT - A surface-mountable waveguide arrangement comprising a dielectric carrier material having a first main side and a second main side, the second side comprising a ground plane, and the first side being arranged to form a microwave circuit layout by means of metallization patterns on the respective sides. The microwave circuit layout comprises a footprint for a surface-mountable waveguide part, the waveguide part comprising an open side, a part of the footprint constituting a closing wall arranged for closing the open side. The waveguide part is arranged for being mounted to a footprint solder area comprised in the footprint, having an outer contour and corresponding to a solderable contact area on the waveguide part. A solderstop line is formed on the footprint, at least partly defining a border between the closing wall and the footprint solder area. The present invention also relates to a dielectric carrier. | 2010-03-04 |
| 20100052826 | ISOLATOR WITH COMPLEMENTARY CONFIGURABLE MEMORY - An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary. | 2010-03-04 |
| 20100052827 | Acoustic Waveguide Array - An acoustic (sound or ultrasound) wave transmitter having a plurality of waveguides is described, and a method of making such a transmitter is described. Each waveguide can have a cladded core. The cladded core is capable of transmitting acoustic wave energy from a first end surface to a second end surface of the cladded core. The waveguides can be substantially fixed relative to each other by a binder. The binder can be formed by fusing the claddings together, potting a material between the waveguides and/or mechanically holding the waveguides. | 2010-03-04 |
| 20100052838 | ELECTRONIC COMPONENT - An electronic component is configured to include a laminate disposed between first and second magnetic substrates. The laminate is formed by laminating resin insulating layers, a coil pattern, and a lead pattern. The coil pattern is connected to external electrodes disposed on end surfaces of the laminate by using internal electrodes. The electronic component further includes expansion relaxation portions disposed in the inside of the resin insulating layers and located in the vicinity of connection regions of the internal electrodes and the external electrodes. The expansion relaxation portions are formed by using a magnetic powder resin in which a ferrite powder and a resin material are mixed. | 2010-03-04 |
| 20100052839 | Transformers and Methods of Manufacture Thereof - Transformers and methods of manufacture thereof are disclosed. In one embodiment, a transformer includes a semiconductor workpiece and a packaging system disposed over the semiconductor workpiece. The packaging system includes a redistribution layer. At least a portion of at least one winding of the transformer is disposed in the redistribution layer of the packaging system. | 2010-03-04 |
| 20100052840 | LOW VARIATION RESISTOR - This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature. | 2010-03-04 |
| 20100052841 | MULTILAYER CHIP VARISTOR - A multilayer chip varistor is provided as one capable of suppressing production of cracks and thereby preventing a connection failure between an internal electrode and a through-hole conductor. An internal electrode | 2010-03-04 |
| 20100052842 | THERMISTOR - A thermistor has a sealing portion of glass which seals at least a thermistor element body, first and second electrodes, and ends of the first and second lead wires and an insulating portion which covers portions of the first and second lead wires exposed from the sealing portion. The first and second lead wires are spaced from each other and include respective first portions extending from the aforementioned ends and spaced from each other with a first space, respective second portions spaced from each other with a second space larger than the first space, and respective third portions spaced from each other with a space varying from the first space to the second space, between the first and second portions. The insulating portion covers the first portions of the first and second lead wires together and covers the second and third portions of the first and second lead wires independently for each of the first and second lead wires. | 2010-03-04 |
| 20100052843 | SYSTEMS AND METHODS FOR SAVING AND RESTORING SCENES IN A MULTIMEDIA SYSTEM - Systems and methods for saving and restoring scenes in a multimedia system with minimal configuration are provided. The techniques of the present invention can allow the states of the components in the multimedia system to be captured in a scene. Once the scene has been saved, the scene can be restored at a later time. A remote control system for recommending scenes by comparing states of components in the current scene with states of components in saved scenes is also provided. The remote control system can also recommend scenes based on usage patterns. Moreover, the remote control system can allow users to designate one or more saved scenes as favorite scenes. | 2010-03-04 |
| 20100052844 | SYSTEM AND METHOD FOR DATA ACQUISITION AND PROCESSING - A system and method for data acquisition and processing is described which can form the basis of new and improved business and consumer services. Encoded datagram images are captured using a mobile phone or PDA or fixed line device and processed relative to a stored encoded profile such that the result of the processing can be used to access services remotely by way of a fixed or network connection and or be used to generate encoded local broadcast signals such as those sent by Bluetooth or Infra Red or WLAN or WIMAX or wireless USB and the like. In this way the capturing device becomes an intelligent service access gatekeeper such that data can be differentially extracted from visible images and used to generate encoded signals according to differential service access privileges which can be used for authenticating and granting building access, operating car park barriers, providing additional security for ATM cash point transactions, operating machinery in diverse applications and the like. | 2010-03-04 |
| 20100052845 | Antitheft System For Vehicle - In a keyless entry system, a CPU in an ECU and a CPU in a remote control key change a function formula specified by primary function formula data stored in a memory and a function formula specified by primary function formula data stored in a memory to respective new function formulas. With this structure, function formulas used in the remote control key and the ECU can be changed to respective new function formulas. This makes it possible to enhance the safety of the keyless entry system because it is difficult to predict the function formulas used in the remote control key and the ECU. | 2010-03-04 |
| 20100052846 | Control system for garage door - A control system for garage door includes a motor, a controller controlling operation of the motor, and a keyboard for inputting an instruction into the controller. The keyboard includes a plurality of keys, a plurality of resistors, a divider resistor for sharing voltage, and a voltage signal output circuit. The resistors correspond to the keys. Each key is connected with one of the resistors in series to form a key mapping signal shunt. The key mapping signal shunts are connected in parallel to form a group of key mapping signal shunts. The divider resistor is connected with the group of key mapping signal shunts in series to form a series circuit. A driving voltage is applied on the series circuit. The voltage signal output circuit is for transmitting a voltage on the group of key mapping signal shunts to the controller. | 2010-03-04 |
| 20100052847 | SYSTEMS AND METHODS TO ENHANCE TELEVISION VIEWING - Systems and methods for enabling centralized environmental and television positional control to enhance the viewing experience. In one embodiment, an environmental controller is used to adjust or control lighting, window coverings, etc., and a television positional controller is used to adjust the position of the television. | 2010-03-04 |
| 20100052848 | REMOTE VEHICLE OPERATING SYSTEM - A remote vehicle operating system is provided that basically comprises a vehicle and a portable hand held electronic terminal for remotely operating the vehicle. The vehicle includes a vehicle exterior body, an onboard terminal and at least one onboard device operatively connected to the onboard terminal. The portable hand held electronic terminal includes a miniature vehicle shaped casing with a transmitter that communicates with the onboard terminal of the vehicle to transmit a command to the onboard device. In accordance with one aspect, an operating element is disposed on the casing in a position of the casing such that touching a miniature vehicle component corresponding to the vehicle component of the vehicle results in the operation of the vehicle component. In accordance with one aspect, the miniature vehicle shaped casing corresponds in general appearance to the vehicle exterior body of the vehicle. | 2010-03-04 |
| 20100052849 | SWITCHING DEVICE - The invention relates to a switching device ( | 2010-03-04 |
| 20100052850 | REMOTE VEHICLE ACTIVATION DEVICE - A vehicle activation device may serve as a transmitter and may have at least two function buttons that remotely activate two corresponding functions in an associated vehicle. A cover may be pivoted to a body and may be movable between at least two positions to make the function buttons accessible or inaccessible. | 2010-03-04 |
| 20100052851 | Security System Utilizing Gesture Recognition - Systems and methods are provided for restricting access to an item of interest. A normalization component resamples an input trajectory to produce a resampled trajectory having a standard size. A reference point generator reduces the resampled trajectory to respective values for a set of reference points, each having at least two associated coordinates. The system further includes at least one authentication region. Each of the at least one authentication region represents at least one of the set of reference points. A verification component is configured to determine if the values for the set of reference points from a given input falls within the at least one authentication region. An access restriction mechanism restricts access to the item of interest unless a threshold number of values for the set of reference points from the input falls within their associated authentication regions. | 2010-03-04 |
| 20100052852 | Methods and devices for enrollment and verification of biometric information in identification documents - Methods and devices for the secure encryption, enrollment, verification, and decryption of biometric and biographical identification information. The unique sequence of steps and the use of a combination of visible watermarking, invisible-fragile watermarking decoding, invisible-robust extraction, and decryption watermarking and encryption provides multiple layers of protection with four biometric based keys and makes it practically impossible for the information to be tampered with. | 2010-03-04 |
| 20100052853 | CONTROLLING AN ELECTRONIC DEVICE BY WAY OF A CONTROL DEVICE - A remote control device for a set top box has a biometric reader, such as a fingerprint reader, incorporated therein. During installation of the set top box, fingerprint data is collected from users who are to be authorised by way of the fingerprint reader and is stored in the set top box. When using the remote control device to access programming, fingerprint data is collected from the user and compared with the stored data to determine if the user is authorised. The user has to be authorised to access some, or even all, of the programming. Access to subscription only services and to pay per view programmes is only available to a user identified by the set top box as being authorised. Electronic devices other than set top boxes, for example audio devices and computers, can similarly be controlled by a control device incorporating a biometric reader. | 2010-03-04 |
| 20100052854 | APPARATUS AND METHOD FOR ACTION CONTROL OF RFID SYSTEM - Provided are an apparatus and a method for controlling an operation of an RFID system, that can selectively control communication of the RFID system. In the method for controlling an operation of the RFID system including at least one REID tag storing predetermined data, and an RFID reader transmitting/receiving data to/from the RFID tag, a password is set to at least one of the RFID tag and the RFID reader. A password is received so that data transmission/reception is performed between the RFID tag and the RFID reader. When the received password coincides with the set password, the data transmission/reception is performed. | 2010-03-04 |
| 20100052855 | Method and Apparatus for Cross-Media Use of RFID Readers and RFID Tags - The invention includes a method and apparatus for facilitating cross-media use of object codes and object code readers, such as RFID tags and readers, barcode codes and readers, and the like. In one embodiment, a method includes receiving an object code read request from a user device where the object code read request indicates that an object has been read using an object code reader, determining at least one of a provider of the object code read using the object code reader and a provider of the object code reader used to read the object code, and performing at least one operation in response to the object code read response. The at least one operation performed in response to the object code read response may include one or more of determining an object code read response and determining revenue sharing. In one embodiment, a method includes receiving and storing registration information adapted for use in responding to object code read requests. | 2010-03-04 |
| 20100052856 | Radio Frequency Identification Triangulation Systems for Communications Patching Systems and Related Methods of Determining Patch Cord Connectivity Information - Methods of determining patch cord connectivity information include receiving, at each of a plurality of RFID readers, a signal from an RFID tag that is associated with a first patch cord and then, identifying the one of a plurality of connector ports that the first patch cord is connected to based at least in part on respective strengths of the signals received at each of the plurality of RFID readers. RFID triangulation systems and methods of calibrating such systems are also provided. | 2010-03-04 |
| 20100052857 | Methods and Apparatus for Distance Determination for Radiofrequency Identification Devices - Systems and techniques for reading radio frequency identification (RFID) tags and determining the distance between a reader and a tag being read. A plurality of interrogation signals are transmitted to an RFID tag, with signals at a first frequency being transmitted at a plurality of antenna polarizations and signals at a second frequency being transmitted at a plurality of antenna polarizations. The antenna polarizations are chosen such that return signals resulting from the signals and traveling along reflective paths will sum to zero. Return signals received from the tag are averaged, and phase shift information exhibited by the return signals is determined. The phase shift information for the return signals and frequency information for the interrogation signals is used to compute the distance between the reader and the tag. | 2010-03-04 |
