| 09th week of 2016 patent applcation highlights part 73 |
| Patent application number | Title | Published |
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| 20160065128 | ITERATIVE METHOD OF SOLAR ELECTRICAL SYSTEM OPTIMIZATION - An optimization utility is provided that can receive information regarding a residential property's location along with energy consumption patterns and thereafter, perform calculations to determine an optimum PV system that can be leased by the homeowner of the residential property and installed thereon, thereby providing the homeowner with the greatest amount of financial savings on their electricity bill. The calculations performed for determining the optimum PV system can include multiple calculations that iteratively narrow possible PV system configurations until the optimum PV system is reached. | 2016-03-03 |
| 20160065129 | QUADRATURE LC VCO WITH PASSIVE COUPLING AND PHASE COMBINING NETWORK - A circuit and method for generating a signal is disclosed. The circuit includes a set of wide tuning LC tanks, a set of core transistors cross coupled to the set of wide tuning LC tanks, and a combining network coupled to the set of wide tuning LC tanks and the set of core transistors. The combining network further includes a set of inputs connected to the set of wide tuning LC tanks and the set of core transistors, a set of coupling transistors connected to the set of inputs, a set of source inductors connected to the set of coupling transistors, a coupling capacitor connected to the set of source inductors, a load resistor connected to the coupling capacitor. The combining network combines the set of inputs and the signal is delivered to the load resistor as a fourth order harmonic. | 2016-03-03 |
| 20160065130 | OSCILLATOR WITH DIFFERENTIAL STRUCTURE - An oscillator with a differential structure which is formed in an integrated circuit, including: a first transistor and a second transistor in each of which a drain electrode, a gate electrode, and a source electrode are sequentially arranged, a drain of the first transistor is connected with a gate of the second transistor through a first wiring, a drain of the second transistor is connected with a gate of the first transistor through a second wiring, and a first end of a source of the first transistor and a first end of a source of the second transistor are connected through a third wiring, and a second end of the source of the first transistor and a second end of the source of the second transistor are connected through a fourth wiring. | 2016-03-03 |
| 20160065131 | INTEGRATED CIRCUIT COMPRISING A FREQUENCY DEPENDENT CIRCUIT, WIRELESS DEVICE AND METHOD OF ADJUSTING A FREQUENCY - An integrated circuit comprises a frequency dependent circuit comprising an input node, an output node and a main bank of selectable first capacitive elements that affect a frequency characteristic of the frequency dependent circuit. The frequency dependent circuit further comprises at least one shunt bank of selectable second capacitive elements located between ground and one of the input node or the output node, wherein at least one selectable second capacitive element switched out of the frequency dependent circuit is based on a number of the selectable first capacitive elements that are switched into the frequency dependent circuit. | 2016-03-03 |
| 20160065132 | CRYSTAL OSCILLATION CIRCUIT AND ELECTRONIC TIMEPIECE - To provide a crystal oscillation circuit low in current consumption and stably short in oscillation start time. A crystal oscillation circuit is equipped with a crystal vibrator, a feedback resistor, a bias circuit, a constant voltage circuit, and an oscillation inverter configured by a constant current inverter. The oscillation inverter is configured so as to be controlled by currents based on input signals from the bias circuit and the crystal vibrator and driven by an output voltage of the constant voltage circuit. | 2016-03-03 |
| 20160065133 | POWER-EFFICIENT CHOPPER AMPLIFIER - In an example, an electrical circuit device for amplifying a physiological signal includes a modulation unit configured to receive an input signal, to modulate the input signal to produce a modulated signal. The device also includes an amplification and transconductance unit configured to amplify an amplitude of the modulated signal and increase a transconductance of the modulated signal to produce a transconductance enhanced modulated and amplified signal, where the amplification and transconductance unit comprises at least a first complementary pair of transistors and a second complementary pair of transistors configured to receive the modulated signal and to amplify and increase the transconductance of the modulated signal. The device also includes a demodulation unit configured to receive the transconductance enhanced modulated and amplified signal and to demodulate the signal. | 2016-03-03 |
| 20160065134 | ASYMMETRIC H-BRIDGE IN A CLASS D POWER AMPLIFIER - Disclosed is an amplifier circuit having an output stage that includes an H-bridge circuit. The H-bridge circuit includes sense resistors on one side of the circuit. A current detection circuit can produce an output indicative of current flow through a load based on voltages across the sense resistors. | 2016-03-03 |
| 20160065135 | HIGH-FREQUENCY AMPLIFIER CIRCUIT - A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential. | 2016-03-03 |
| 20160065136 | Modular RF Matrix Switch - An RF matrix switch has a first set of card slots at selected locations on the chassis and a second set of card slots at different selected locations on the chassis as well as input cards and output cards. The input cards, the output cards, the first set of card slots and the second set of card slots are all configured so that the input cards and the output cards fit into all of these slots. Reroute cards can be provided for any unused card slots. The RF matrix switch also may have an active power management system in which there is a power control switch connected to each amplifier that turns the amplifier off when the amplifier is not being used. | 2016-03-03 |
| 20160065137 | REDUCED BANDWIDTH ENVELOPE TRACKING - Envelope power supply circuitry includes an envelope power converter circuitry and envelope tracking circuitry. The envelope power converter circuitry receives an envelope power converter control signal from the envelope tracking circuitry and a supply voltage and provides an envelope power supply signal for an amplifier based thereon. In a first mode of operation, the envelope power converter control signal is provided such that the envelope power supply signal causes the gain of the amplifier to remain substantially constant over a range of input power provided to the amplifier. In a second mode of operation, the envelope power converter control signal is provided such that the envelope power supply signal remains substantially constant for values within the range of input power below a predetermined threshold, and such that the envelope power supply signal causes the gain of the amplifier to remain substantially constant for other values. | 2016-03-03 |
| 20160065138 | RF Amplifier Having A Transition Shaping Filter - A radio frequency (RF) power amplifier system or transmitter includes one or more power amplifiers and a controller that is configured to adjust amplitudes and phases of RF input signals of the one or more power amplifiers and supply voltages applied to the one or more power amplifiers. In embodiments where multiple power amplifiers are used, a combiner may be provided to combine outputs of the power amplifiers. | 2016-03-03 |
| 20160065139 | METHOD AND APPARATUS FOR SUPPLYING POWER TO A RADIO FREQUENCY POWER AMPLIFIER - A method and a supply modulator (SM) are provided for supplying power from a wireless transmitter to a radio frequency (RF) power amplifier. A power control signal input from a modem is received. A reference voltage is determined. An operating mode of the SM is changed by controlling a level of the reference voltage. A voltage is determined based on the level of a reference voltage. When the operating mode of the SM is an ET mode, a first output signal from a linear regulator and a second output signal from a switching regulator are combined to obtain a combined result, and the combined result is output. The first output signal is based on the voltage. When the operating mode of the SM is an APT mode, the voltage based on the reference voltage is output. | 2016-03-03 |
| 20160065140 | CLASS D AMPLIFIER AND ELECTRONIC DEVICES INCLUDING THE SAME - An electronic device includes a waveform generator, a comparator, and an amplifier. The waveform generator receives a voltage from a power supply to the electronic device and outputs a voltage waveform signal. The comparator compares an input signal and the voltage waveform signal to output a first pulse-width-modulated signal. The amplifier receives the first pulse-width-modulated signal and outputs a second pulse-width-modulated signal. | 2016-03-03 |
| 20160065141 | POWER AMPLIFIER - The disclosed power amplifier has: a first amplifying unit and a second amplifying unit provided with a plurality of amplifying circuits connected in parallel in which a bias voltage can be adjusted in accordance with a control signal supplied from outside, the first amplifying unit and the second amplifying unit for amplifying an input signal by each amplifying circuit and combining and outputting the amplified signal; a divider for dividing the input signal to the first amplifying unit and the second amplifying unit; and a combiner for combining and outputting an output signal of the first amplifying unit and an output signal of the second amplifying unit. | 2016-03-03 |
| 20160065142 | PARALLEL COMBINED OUTPUT LINEAR AMPLIFIER AND OPERATING METHOD THEREOF - A parallel output linear amplifier is provided that includes a transconductance amplifier configured to receive an analog input signal from an input terminal and amplify the analog input signal. The parallel output linear amplifier also includes a first pre-amplifier connected to the transconductance amplifier and operated using a floating drive voltage, and a cascode class AB amplifier connected to the first pre-amplifier and configured to provide an amplified signal to an output terminal. The parallel output linear amplifier further includes a second pre-amplifier configured connected to the transconductance amplifier and operated using the floating drive voltage, and a cascade class AB amplifier connected to the second pre-amplifier and configured to provide an amplified signal to the output terminal. | 2016-03-03 |
| 20160065143 | CIRCUIT FOR REDUCING POP NOISE - The invention concerns an amplifier circuit comprising: an amplifier having a first input coupled to an input node of the amplifier circuit via a first resistor and an output coupled to a load via a coupling capacitor, the output being coupled to the first input via a second resistor; and a current ramp generator adapted to supply a current ramp to the first input of the amplifier during a power up phase or power down phase of the amplifier circuit to control the rate of charge or discharge of the coupling capacitor. | 2016-03-03 |
| 20160065144 | METHOD OF MANUFACTURING RF POWER AMPLIFIER MODULE, RF POWER AMPLIFIER MODULE, RF MODULE, AND BASE STATION - The present disclosure relates to a radio frequency (RF) unit of a base station, and more particularly, to a method of manufacturing an RF power amplifier module, an RF power amplifier module, an RF module, and a base station. The RF power amplifier module includes at least a power device, a power circuit board, a heat-dissipation substrate, and input/output ports. A power device die of the power device and the power circuit board are mounted on the heat-dissipation substrate. The power device die is connected to the power circuit board through packaging lead wires. In one exemplary embodiment, a heat-dissipation effect and manufacturing efficiency of the RF power amplifier module are improved and a cost of the RF power amplifier module is reduced. | 2016-03-03 |
| 20160065145 | AMPLIFIER MODULE WITH ENHANCED HEAT DISSIPATING FUNCTION AND SEMICONDUCTOR DEVICE - An amplifier module having a surface-mounting carrier with a base and lid is disclosed. The base in a top surface thereof provides a die pad on which a transistor is mounted, and a back surface thereof provides a back pad electrically and thermally connected to the die pad. The back pad has an area wider than the area of the die pad. The heat conduction from the transistor to the host board on which the amplifier module is mounted is effectively enhanced. | 2016-03-03 |
| 20160065146 | AMPLIFICATION PHASE CORRECTION IN A PULSE BURST - An apparatus having an amplifier and a correction circuit is disclosed. The amplifier may be configured to amplify an intermediate signal to generate an output signal. The amplifier is generally a microwave frequency power amplifier. The correction circuit may be configured to (i) generate a control signal based on a plurality of characteristics of the amplifier, and (ii) adjust a plurality of phases of a plurality of pulses in a pulse burst to generate the intermediate signal. The adjusting may be in response to the control signal. The pulse burst is generally received in an input signal. The phases of the pulses as adjusted in the intermediate signal generally cancel a plurality of phase errors induced by the amplifier in the pulses. | 2016-03-03 |
| 20160065147 | RECEIVERS FOR DIGITAL PREDISTORTION - Aspects of this disclosure relate to a receiver for digital predistortion (DPD). The receiver includes an analog-to-digital converter (ADC) having a sampling rate that is lower than a signal bandwidth of an output of a circuit having an input that is predistorted by DPD. DPD can be updated based on feedback from the receiver. According to certain embodiments, the receiver can be a narrowband receiver configured to observe sub-bands of the signal bandwidth. In some other embodiments, the receiver can include a sub-Nyquist ADC. | 2016-03-03 |
| 20160065148 | ADVANCED CURRENT LIMIT FUNCTION FOR AUDIO AMPLIFIER - A class-D audio amplifier incorporates an overcurrent protection scheme implementing two overcurrent thresholds to avoid a dynamic impedance drop. When output current reaches the first threshold as a result of an impedance drop across the speaker, the overcurrent protection circuitry limits the output current to the value of the first threshold, but does not shut down the circuit. The second threshold is used to detect an overcurrent condition to shut down the circuit. Current limiting logic of a first channel monitors the overcurrent condition of a second channel and controls the first channel output in response thereto. This permits the second channel output current to reach the second threshold if the circuit is experiencing a short-circuit condition. This scheme also allows the output current to drop below the first threshold if the overcurrent condition of the second channel is caused by an impedance drop across the output speaker. | 2016-03-03 |
| 20160065149 | Low Noise Amplifier Method and Apparatus - A low noise amplifier circuit including: at least a first input and first output; at least a first stage of transistor amplification having a transistor input terminal; the circuit further comprising: an input driving circuit interconnecting the first input to the transistor input terminal, the input driving circuit including a parallel resonant circuit interconnected between the transistor input terminal and ground and a series resonant circuit interconnected between the input terminal and the transistor input terminal, the input driving circuit functioning as an input matching network for the circuit in conjunction with an input bias and decoupling network. | 2016-03-03 |
| 20160065150 | LIGHT RECEIVING CIRCUIT AND LIGHT COUPLING DEVICE - A light receiving circuit includes an inverting amplification circuit, a first light receiving element, a first circuit, and a charging circuit. The inverting amplification circuit includes an input terminal and an output terminal. The first light receiving element is connected between the input terminal and a reference potential terminal. The first circuit includes a first resistor, a second resistor, a third resistor and a capacitor. The first resistor second resistor connected through a connection point. The first resistor is connected between the input terminal and the connection point, and the second resistor connected between the output terminal and the connection point. The third resistor is connected between the connection point and connection node, and the capacitor is connected between the connection node and the reference potential terminal. The charging circuit connected between the power supply terminal and the connection node. | 2016-03-03 |
| 20160065151 | AUDIO AMPLIFIER WITH RF INTERFERENCE SUPPRESSION FUNCTION - The present invention is related to an audio amplifier with RF interference suppression function, mainly comprising at least one amplifying unit and a speaker. The amplifying unit comprises a first input end, a second input end and an output end, in which a feedback circuit is presented between the first input end and the output end. The feedback circuit is provided therein with at least one resistor and at least one capacitor, in which the resistor is situated between the first input end and the output end, while one end of the capacitor is connected to the feedback circuit. RF signals entering from the speaker may be filtered out through the provision of the resistor and the capacitor in the feedback circuit. Thereby, interference generated on the audio amplifier due to RF signals is suppressed. | 2016-03-03 |
| 20160065152 | System and Method for Low Distortion Capacitive Signal Source Amplifier - According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage. | 2016-03-03 |
| 20160065153 | INVERTER TYPE POWER AMPLIFIER - The present disclosure relates to an inverter type power amplifier. An exemplary embodiment of the present disclosure provides an inverter type power amplifier including: a first transistor including a gate to which an AC type of input signal is applied through an input port, a first terminal connected a power source voltage, and a second terminal connected to an output port; a second transistor including a gate through which the input signal is applied thereto, a first terminal connected to a ground, and a second terminal connected to the output port; a feedback resistor including a first terminal connected to the input port and a second terminal connected to the output port; and an AC blocking block including a first terminal connected to the output port and a second terminal connected to a DC output port. | 2016-03-03 |
| 20160065154 | TRAVELLING WAVE AMPLIFIER (TWA) FOR DRIVING OPTICAL MODULATOR - A travelling wave amplifier (TWA) with a widened frequency bandwidth is disclosed. The TWA include input transmission lines, amplifier units connected in parallel between the input terminal and the out terminal of the TWA. Each of the amplifier units configures an emitter follower in the front end thereof and an amplifying section. A feature of the TWA is that compensation units that compensates the high frequency performance of the TWA are implemented in the input transmission lines and/or integrated with the amplifier units. | 2016-03-03 |
| 20160065155 | CONTEXTUAL VOLUME CONTROL - Adjustment of volume level of a mobile device, by the mobile device without direct or manual user-input, based on one or more contextual parameters detected by the mobile device, such as ambient noise level. | 2016-03-03 |
| 20160065156 | METHODS AND CIRCUITRY TO PROVIDE COMMON MODE TRANSIENT IMMUNITY - Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals. | 2016-03-03 |
| 20160065157 | METHOD AND APPARATUS FOR GAIN ENHANCEMENT OF DIFFERENTIAL AMPLIFIER - A differential amplifier circuit and method having a feed-in network coupling an input signal to an intermediate signal. An amplifier amplifies the intermediate signal by a gain factor to output an output signal to a load network. A feedback network configured in a negative feedback topology and couples the output signal to the intermediate signal. A gain enhancing network is configured in a positive feedback topology and couples the output signal to the intermediate signal. Preferably, an impedance of the gain enhancing network is approximately equal to an impedance of a parallel connection of the feed-in network and the feedback network times the gain factor minus one. | 2016-03-03 |
| 20160065158 | CLASS D AMPLIFIER CIRCUIT - This application relates to Class D amplifier circuits ( | 2016-03-03 |
| 20160065159 | SOUND-EFFECT SETTING METHOD AND ELECTRONIC DEVICE - A sound-effect setting method and an electronic device are provided. The sound-effect setting method comprises decoding an audio data stream; performing sound-effect processing on the decoded audio data stream according to a sound-effect parameter to obtain sound-effect processed audio data; encoding the sound-effect processed audio data to obtain encoded data and outputting the encoded data and the sound-effect parameter. When the audio playing is switched from the current apparatus to the external apparatus, the sound-effect coordination is achieved, and the problem that the playing effect will become poor if there is no sound-effect coordination is prevented. | 2016-03-03 |
| 20160065160 | TERMINAL DEVICE AND AUDIO SIGNAL OUTPUT METHOD THEREOF - Disclosed is a method whereby a terminal device outputs an audio signal. The audio signal output method comprises the steps of: receiving a broadcast signal including a normalized audio signal having a preset audio signal size; detecting program genre information from the broadcast signal; detecting a preferred audio signal size corresponding to the detected program genre information; and adjusting the size of the normalized audio | 2016-03-03 |
| 20160065161 | FREQUENCY DOMAIN MULTIBAND DYNAMICS COMPRESSOR WITH SPECTRAL BALANCE COMPENSATION - A multiband dynamics compressor implements a solution for minimizing unwanted changes to the long-term frequency response. The solution essentially proposes undoing the multiband compression in a controlled manner using much slower smoothing times. In this regard, the compensation provided acts more like an equalizer than a compressor. What is applied is a very slowly time-varying, frequency-dependent post-gain (make-up gain) that attempts to restore the smoothed long-term level of each compressor band. | 2016-03-03 |
| 20160065162 | ADVANCED THERMALLY COMPENSATED SURFACE ACOUSTIC WAVE DEVICE AND FABRICATION - This disclosure relates to a method of fabrication of a surface acoustic wave device comprising the step (a) of providing a piezoelectric structure, the step (b) of providing a dielectric structure, wherein the step (b) comprises a step (b1) of metalizing the dielectric structure, and the method further comprising the step (c) of bonding the metalized dielectric structure to the piezoelectric structure. | 2016-03-03 |
| 20160065163 | GAIN PEAKING TECHNIQUES IN HIGH-FREQUENCY PASSIVE LOW PASS FILTERS - Techniques to maintain gain flatness in the frequency response of a passband signal over a circuit chain. The techniques may be employed in the receive chain of a millimeter wave band wireless receiver, in the transmit chain of a millimeter wave band wireless transmitter, or in both the receive chain and the transmit chain of a millimeter wave band wireless transceiver. The techniques include mismatching the input and output impedance of a passive low pass filter used in the chain to peak the gain of the passband signal at or near the cutoff frequency (Fc) of the filter. | 2016-03-03 |
| 20160065164 | FILTER COMPONENT WITH WINDINGLESS MAGNETIC TOROIDAL CORE - Filter component having a windingless magnetic toroidal core with an opening, a toroidal core housing in which the toroidal core is fastened using a snap-on mechanism, wherein the filter component is designed such that a conductor can be run windinglessly through the opening of the toroidal core fastened in the toroidal core housing. | 2016-03-03 |
| 20160065165 | TUNABLE FILTER - A tunable filter is a ladder circuit tunable filter including serial arm resonators and a parallel arm resonator. The serial arm resonators and the parallel arm resonator include elastic wave resonators. Variable capacitors are connected in series to the serial arm resonators, a variable capacitor is connected in parallel to the parallel arm resonator, and first inductors are connected in series to the serial arm resonators. When an impedance at a resonant frequency of the serial arm resonators is Zrs and an impedance at a resonant frequency of the parallel arm resonator is Zrp, a ratio Zrs/Zrp is not greater than 1. | 2016-03-03 |
| 20160065166 | SEMICONDUCTOR DEVICE AND ADJUSTMENT METHOD OF FILTER CIRCUIT - A wireless communication device includes a radio frequency integrated circuit (RFIC) which includes a filter circuit operable to pass a desired signal component of a high-frequency signal inputted and operable to attenuate a harmonic component of an integral multiple of the desired signal. The filter circuit includes a first inductor and a second inductor coupled to a signal line transmitting the high-frequency signal. A first input terminal and a second input terminal are operable to receive the high-frequency signal as a differential signal, wherein the first inductor and the second inductor are formed by a first differential inductor and a second differential inductor are coupled between the first input terminal and the second input terminal. | 2016-03-03 |
| 20160065167 | RECONFIGURABLE DIRECTIONAL COUPLER - This disclosure relates generally to directional couplers. In one embodiment, a directional coupler includes a first port, a second port, a third port, a first inductive element, a second inductive element, a first switchable path, and a second switchable path. The first inductive element is coupled between the first port and the second port, while the second inductive element is mutually coupled to the first inductive element. The first switchable path is configured to be opened and closed, wherein the first switchable path is coupled between a first location of the second inductive element and the third port. The second switchable path is configured to be opened and closed, wherein the second switchable path is coupled between a second location of the second inductive element and the third port. In this manner, a directivity of the directional coupler can be switched between a forward direction and a reverse direction. | 2016-03-03 |
| 20160065168 | RESONANCE COUPLER AND TRANSMISSION DEVICE - A resonance coupler according to one aspect of the present disclosure includes first resonance wiring and second resonance wiring. The first resonance wiring includes first open loop wiring, first input/output wiring extending outwardly from a first connection portion of the first open loop wiring, and first stub wiring extending inwardly from a second connection portion of the first open loop wiring. The second resonance wiring includes second open loop wiring, and second input/output wiring extending outwardly from a third connection portion of the second open loop wiring. The first stub wiring includes a first connection end connected to the second connection portion and a first open end on an opposite side. A wiring length from the first connection portion to the first open end is one-quarter of a wavelength of an nth-order harmonic of a radio-frequency signal, where n is an integer not less than 2. | 2016-03-03 |
| 20160065169 | NANO- AND MICRO-ELECTROMECHANICAL RESONATORS - A resonator including a piezoelectric plate and an interdigital electrode is provided. A ratio between a thickness of the plate and a pitch of the interdigital electrode may be from about 0.5 to about 1.5. A radiation detector including a resonator and an absorber layer capable of absorbing at least one of infrared and terahertz radiation is provided. A resonator including a piezoelectric plate and a two-dimensional electrically conductive material is provided. | 2016-03-03 |
| 20160065170 | ELECTRONIC COMPONENT, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - An electronic component includes: an oscillation circuit that is electrically connected to a resonator element; and a substrate that includes a first surface on which the oscillation circuit and wiring that is electrically connected with the resonator element and the oscillation circuit to form an oscillation loop are disposed, and a second surface opposite to the first surface. The substrate includes a conductor layer between the first surface and the second surface. The conductor layer overlaps the wiring in a plan view. A distance between the wiring and the conductor layer in a thickness direction as a direction along a direction intersecting the first surface and the second surface is from 0.35 mm to 0.7 mm. | 2016-03-03 |
| 20160065171 | FILM BULK ACOUSTIC RESONATORS COMPRISING BACKSIDE VIAS - An film bulk acoustic wave resonator (FBAR) structure has an FBAR and a via disposed substantially directly beneath the FBAR. The via is in thermal contact with the FBAR. A plurality of vias may be included. The via(s) serve to dissipate heat generated by the FBAR structure during operation. | 2016-03-03 |
| 20160065172 | MEMBRANE SUBSTRATE STRUCTURE FOR SINGLE CRYSTAL ACOUSTIC RESONATOR DEVICE - A substrate structure for an acoustic resonator device. The substrate has a substrate member comprising a plurality of support members configured to form an array structure. In an example, the substrate member has an upper region, and optionally, has a plurality of recessed regions configured by the support members. The substrate has a thickness of single crystal piezo material formed overlying the upper region. In an example, the thickness of single crystal piezo material has a first surface region and a second surface region opposite of the first surface region. | 2016-03-03 |
| 20160065173 | VIBRATING DEVICE - A vibrating device having tuning fork arms extending in a first direction that are joined to a base portion and are arranged side by side in an second direction. Each of the tuning fork arms has a structure that a silicon oxide layer is laminated on a Si layer made of a degenerate semiconductor, and that an excitation portion is provided on the silicon oxide layer. When a total thickness of the Si layer is denoted by T | 2016-03-03 |
| 20160065174 | LADDER FILTER AND DUPLEXER - A ladder filter includes a plurality of series-arm resonators and parallel-arm resonators including surface acoustic wave resonators. A metallization ratio of the series-arm resonator having the smallest electrostatic capacity among the plurality of series-arm resonators is the smallest among the plurality of series-arm resonators and an electrode finger pitch of the series-arm resonator having the smallest electrostatic capacity is the largest among electrode finger pitches of the plurality of series-arm resonators. | 2016-03-03 |
| 20160065175 | SURFACE ACOUSTIC WAVE FILTER, SURFACE ACOUSTIC WAVE FILTER DEVICE, AND DUPLEXER - A surface acoustic wave filter includes a longitudinally coupled resonator first filter section and a longitudinally coupled resonator second filter section that is electrically connected to the first filter section in parallel or in series and that is provided next to the first filter section in a surface acoustic wave propagation direction. The first filter section includes a first interdigital transducer group arranged in the surface acoustic wave propagation direction. The second filter section includes a second interdigital transducer group arranged in the surface acoustic wave propagation direction. A reflector between the first interdigital transducer group and the second interdigital transducer group is an integrated shared reflector. A number of electrode fingers in reflecting units in the shared reflector is an odd number of no less than nine. | 2016-03-03 |
| 20160065176 | ELASTIC WAVE FILTER DEVICE - An elastic wave filter device includes serial and parallel arms and a plurality of elastic wave resonators. Each elastic wave resonator includes an IDT electrode. In the case where a direction in which electrode fingers extend is taken as a width direction of the IDT electrode, the IDT electrode includes a central area at a center in the width direction, a low acoustic velocity area at an outer side portion of the central area, and a high velocity area at a farther outer side portion thereof. A width of the low acoustic velocity area of at least one elastic wave resonator differs from a width of the low acoustic velocity area of the other elastic wave resonators. | 2016-03-03 |
| 20160065177 | DEVICES AND METHODS FOR CONVERTING DIGITAL SIGNALS - A signal converter directly converts pulse-density-modulated (PDM) signals into pulse-width-modulated (PWM) signals. A noise-shaping loop architecture can be configured to apply a signal transfer function having a low-pass filter effect, and a noise transfer function having a high-pass filter effect. Decimation and interpolation can ensure that the noise-shaping loop architecture operates at a first sampling frequency, while the PWM modulator operates at a second, higher sampling frequency. | 2016-03-03 |
| 20160065178 | DEVICES AND METHODS FOR PULSE-WIDTH MODULATION - Devices and methods convert signals into pulse-width modulated signals. A noise-shaping loop can be clocked at a lower frequency than a PWM modulator, resulting in lower power requirements, and greater ease of synchronization. The delay introduced by the noise-shaping loop can be reduced by implementations using sample-and-hold devices, look-up tables and logic circuitry to predict output signals. | 2016-03-03 |
| 20160065179 | HIGH ACCURACY MILLIMETER WAVE/RADIO FREQUENCY WIDEBAND IN-PHASE AND QUADRATURE GENERATION - Certain aspects of the present disclosure provide circuits for generating high accuracy millimeter wave or radio frequency (RF) wideband in-phase (I) and quadrature (Q) oscillating signals having acceptable amplitude and phase mismatch over process, voltage, and temperature (PVT) variations with reduced cost, area, and power consumption. In one example apparatus, a polyphase filter having a first stage and a second stage is provided. Each stage comprises resistive elements and capacitive elements. Certain aspects of the present disclosure provide for intentional resistive and/or capacitive value mismatch between the resistive or capacitive values of one or multiple stages such that the phase mismatch between the resulting I and Q signals may be reduced without degrading the amplitude mismatch. Certain aspects of the present disclosure provide for replacing the resistive elements in at least one stage with transistors operating in the triode region, where the on-resistance is controlled by a feedback network. | 2016-03-03 |
| 20160065180 | SAMPLING CIRCUIT AND MASTER-SLAVE FLIP-FLOP - A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs. | 2016-03-03 |
| 20160065181 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system includes a first semiconductor device including an offset signal generation circuit configured to compare at least one sensing code and a temperature code and generate an input offset signal, and a second semiconductor device including a temperature code generation circuit configured to be inputted with the input offset signal, compare a reference voltage controlled according to the input offset signal and a temperature signal, and generate the temperature code. | 2016-03-03 |
| 20160065182 | DIGITAL CIRCUIT - A digital circuit comprises a plurality of functional circuits and a finite state machine. Each functional circuit comprises a digital macro, a resistance control device and at least one device with capacitance. The digital macro is coupled to a ground. The resistance control device is electrically connected between the digital macro and an always-on power mesh. The at least one device with capacitance is electrically connected between the resistance control device and the ground. The finite state machine is electrically connected to the resistance control device, and is configured to adjust the resistance of the resistance control device. | 2016-03-03 |
| 20160065183 | One-Shot Circuit - An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input. | 2016-03-03 |
| 20160065184 | FLIP-FLOP CIRCUIT - A flip-flop circuit is provided. The flip-flop circuit includes a first latch, a trigger stage and a second latch. The first latch is configured to latch a selected signal in response to a first state of a clock signal, and provide a first output signal. The trigger stage, connected to the first latch, is configured to provide a trigger signal based on the clock signal and the first output signal. The second latch, connected to the trigger stage, is configured to latch the trigger signal in response to a second state of the clock signal, and provide a second output signal. The first state and the second state of the clock signal are complementary to each other. | 2016-03-03 |
| 20160065185 | MULTI-BIT FLIP-FLOP WITH ENHANCED FAULT DETECTION - A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch. | 2016-03-03 |
| 20160065186 | ADJUSTING THE MAGNITUDE OF A CAPACITANCE OF A DIGITALLY CONTROLLED CIRCUIT - An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements. | 2016-03-03 |
| 20160065187 | MULTI-LEVEL PULSE GENERATOR CIRCUITRY - During operation, a supply voltage and the reference voltage power a novel multi-level pulse generator circuit. The multi-level pulse generator circuit generates voltage pulses of varying magnitude from a respective output port. For example, the multi-level pulse generator circuit produces respective pulses to have magnitudes that fall inside and outside of a range defined by the supply voltage and the reference voltage. Expansion of the pulse magnitudes to be outside of the range as defined by the supply voltage and the reference voltage increases noise immunity and therefore enables a respective transmitter to transmit data at higher bandwidth. The multi-level pulse generator circuit can be fabricated using a set of multiple transistors of only a single type in which each of the multiple transistors in the set has a corresponding oxide breakdown voltage that is substantially less than the respective magnitude that falls outside of the range. | 2016-03-03 |
| 20160065188 | LOW LEAKAGE SHADOW LATCH-BASED MULTI-THRESHOLD CMOS SEQUENTIAL CIRCUIT - Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit. | 2016-03-03 |
| 20160065189 | RECEIVER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical. | 2016-03-03 |
| 20160065190 | CLOCK GATED FLIP-FLOP - Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged. | 2016-03-03 |
| 20160065191 | PULSE CONVERTER CIRCUIT - A pulse converter circuit includes a logic circuit to which a first signal is input and from which a second signal is output. The logic circuit includes a p-channel transistor which determines whether a voltage of the second signal is set to a first voltage depending on a voltage of the gate; and an n-channel transistor which determines whether the voltage of the second signal is set to a second voltage, which is higher than the first voltage, depending on a voltage of the gate. The p-channel transistor includes a semiconductor layer containing an element of a group 14. The n-channel transistor includes an oxide semiconductor layer. | 2016-03-03 |
| 20160065192 | COMPENSATION TIME COMPUTING METHOD and DEVICE FOR CLOCK DIFFERENCE - The present invention provides a method for computing compensation time for clock difference between a first chip and a second chip. The method comprises emitting, by the second chip, a pulse with a fixed pulse length to the first chip; measuring, by the first chip, a pulse length of the pulse; computing the compensation time according to the measure pulse length and the fixed pulse length; and setting the compensation time to the second chip. | 2016-03-03 |
| 20160065193 | LINEAR PROGRESSION DELAY REGISTER - An adjustable delay line includes a series of delay elements for adjusting the accumulative delay. Each element has a plurality of registers indicating to various devices within the delay element to be ‘on’ or ‘off’, thereby changing the time delay through the element. A master control indicates to the delay line whether to go faster (increment) or go slower (decrement). When one of these control signals is applied to the delay line, it is applied to half the elements, either the odd or the even numbered elements. Only one element will have its state changed by the increment or decrement control signal, and it will be the element for which the previous delay's corresponding element is already set or un-set depending upon the applicable case. | 2016-03-03 |
| 20160065194 | DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT - A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller. | 2016-03-03 |
| 20160065195 | MULTIPHASE OSCILLATING SIGNAL GENERATION AND ACCURATE FAST FREQUENCY ESTIMATION - Certain aspects of the present disclosure provide methods and apparatus for generating multiple oscillating signals having different phases. One example multiphase generating circuit generally includes a first phase shifting circuit configured to phase shift an input signal having an input frequency, such that an output signal of the first phase shifting circuit has a first phase difference with respect to the input signal; a first frequency dividing circuit configured to receive the input signal and output a first set of signals having a first frequency less than the input frequency of the input signal; and a second frequency dividing circuit configured to receive the output signal of the first phase shifting circuit and output a second set of signals having a second frequency less than the input frequency of the input signal. The multiphase signals may be used for fast frequency estimation of the input signal or in N-path filters. | 2016-03-03 |
| 20160065196 | MULTI-PHASE CLOCK GENERATION - Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line. | 2016-03-03 |
| 20160065197 | BUTTON DETECTING CIRCUIT - The present disclosure illustrates a button detecting circuit and method thereof. The button detecting circuit includes a determining circuit, a voltage selector and a button module. The voltage selector is electrically connected to the determining circuit. The voltage selector has a plurality of candidate voltages arranged in sequence based on magnitudes of the candidate voltages. The button module which is electrically connected to the determining circuit via a single one pin comprises a threshold unit and a button network. The determining circuit receives the candidate voltage outputted from the voltage selector and outputs the candidate voltage to the button module for testing whether the threshold unit will be conducted to find a threshold voltage. The button module generates a scanning current based upon the threshold voltage. The determining circuit senses the scanning current and determines which one of a plurality of buttons disposed in the button network is pressed. | 2016-03-03 |
| 20160065198 | COMPARATOR - A comparator is disclosed. The comparator has a power input terminal used to input electricity, a first and a second to-be-compared voltage input terminal used to receive the first and second to-be-compared voltage, an offset voltage adjusting circuit used to adjust an offset voltage, a comparative circuit used to compare the first to-be-compared voltage and a third to-be-compared voltage which is a sum of the second to-be-compared voltage and the offset voltage and to generate a comparative result, and a comparative result output terminal used to output the comparative result. | 2016-03-03 |
| 20160065199 | AMPLITUDE DETECTOR - An amplitude detector includes a first amplitude detection transistor and an output terminal. The first amplitude detection transistor receives a first signal by a gate and a second signal that forms a differential pair with the first signal by a drain, and detects an amplitude of the differential pair. The output terminal outputs an amplitude signal in accordance with amplitude detected by the first amplitude detection transistor. | 2016-03-03 |
| 20160065200 | INPUT APPARATUS AND INPUT SYSTEM - An input apparatus may include a pulse width control circuit, a reception circuit, and a latch circuit. The pulse width control circuit may be configured to generate a pulse width control signal by performing a logical operation on a pulse width detection signal and a clock signal. The reception circuit may be configured to selectively provide a received input signal as a period signal on the basis of the clock signal and the pulse width control signal. The latch circuit may be configured to provide an output signal by inverting the period signal, and provide the output signal as the pulse width detection signal in response to the clock signal. | 2016-03-03 |
| 20160065201 | REFERENCE CURRENT SETTING CIRCUIT - A reference current setting circuit according to one embodiment includes a first terminal, a first current mirror circuit, a second current mirror circuit, and a third current mirror circuit. The first terminal is connected to a ground potential via a first resistor. The first current mirror circuit includes a first transistor with a source connected to a reference voltage and a drain serving as a first input terminal, and a second transistor with a source connected to the first terminal and a drain serving as a first output terminal, the drain of the first transistor being connected to a gate of the first transistor and a gate of the second transistor. | 2016-03-03 |
| 20160065202 | Bidirectional Two-Base Bipolar Junction Transitor Operation, Circuits, and Systems with Double Base Short at Initial Turn-Off - Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low. | 2016-03-03 |
| 20160065203 | System and Method for a Switch Having a Normally-on Transistor and a Normally-off Transistor - In accordance with an embodiment, a circuit includes a normally-off transistor, and a normally-on transistor comprising a second load path terminal coupled to a first load path terminal of the normally off transistor, and a control terminal coupled to a second load path terminal of the normally-off transistor. The circuit further includes a driver circuit having an output coupled to a control terminal of the normally off transistor, a first power supply terminal configured to be coupled to a first power supply terminal of a first power supply, and a second power supply terminal configured to be coupled to a second power supply terminal of a second power supply. The second load path terminal of the normally on transistor is further configured to be coupled to a second power supply terminal of the first power supply and to a first power supply terminal of the second power supply. | 2016-03-03 |
| 20160065204 | System and Method for Generating an Auxiliary Voltage - In accordance with an embodiment, a circuit includes a first normally-on transistor having a drain coupled to a first switching output node, a normally-off transistor having a drain coupled to a source of the first normally-on transistor, a driver circuit configured to receive a switching signal, the driver circuit having an output coupled to a gate of the first normally-on transistor, and a second normally-on transistor having a drain terminal coupled to a supply node, a gate terminal coupled to the output of the driver circuit, and a source terminal configured to provide an auxiliary voltage. | 2016-03-03 |
| 20160065205 | GATE DRIVING CIRCUIT OF HIGH-SIDE TRANSISTOR, SWITCHING OUTPUT CIRCUIT, INVERTER DEVICE, AND ELECTRONIC DEVICE - A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse. | 2016-03-03 |
| 20160065206 | SWITCH STAND-BY MODE ISOLATION IMPROVEMENT - Systems, apparatuses and methods are disclosed providing a semiconductor die comprising a semiconductor substrate and a radio-frequency (RF) switch including one or more series field-effect transistors (FETs) and one or more shunt FETs, each of the one or more series FETs and one or more shunt FETs having a respective gate node, the RF switch being configured to receive an RF signal from a power amplifier module and provide the RF signal to an antenna. The semiconductor die may further comprise an internal regulator voltage source configured to provide an internal regulator voltage when the RF switch is in a stand-by mode and shunt arm control circuitry configured to provide the internal regulator voltage to the gate nodes of the one or more shunt FETs when the RF switch is in the stand-by mode. | 2016-03-03 |
| 20160065207 | HIGH VOLTAGE CONTROL CIRCUIT FOR AN ELECTRONIC SWITCH - In one embodiment, the invention can be a control circuit for an electronic switch, the control circuit including a first power switch comprising a first optocoupler, the first power switch configured to (a) receive a common input signal and a first voltage, and (b) switchably connect the first voltage to a common output in response to the common input signal; and a second power switch comprising a first transistor coupled to the common output, and a second transistor connected in series between the first transistor and a second voltage source providing a second voltage, the second power switch configured to (a) receive the common input signal and the second voltage, and (b) switchably connect the second voltage to the common output in response to the common input signal. | 2016-03-03 |
| 20160065208 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPLIANCE - An H-bridge pre-driver is configured as two blocks so as to suit the width of an H-bridge driver Tr. The two blocks are line-symmetrically placed with a bias circuit interposed therebetween. One of the pre-driver blocks is laid out as a rectangle that is long in one direction and is short in a direction perpendicular to that direction. With this configuration, the pre-driver layout area can be reduced, and the cost of IC can be reduced. Furthermore, the symmetric placement enables matching of the impedance of interconnect from the pre-driver to the driver and stabilization of properties to be achieved. | 2016-03-03 |
| 20160065209 | Rapid Cutoff Device and Operation Method for SCR AC Switches - A rapid cutoff device includes a thyristor AC switch for supplying an AC current from a first AC circuit to a second AC circuit. A serially-connected circuit of a first switch and a first capacitor parallel-connects with the first AC circuit. A serially-connected circuit of a second switch and a second capacitor parallel-connects with the second AC circuit. When cutting off the thyristor AC switch, the first switch is operated to conduct the first capacitor in a first direction for the AC current charging to the first capacitor, alternatively, the second switch is operated to conduct the second capacitor in a second direction for the AC current charging to the second capacitor, thereby lowering a current in the thyristor AC switch approaching a zero value and thus rapidly cutting off it. | 2016-03-03 |
| 20160065210 | SEMICONDUCTOR DEVICE - An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable. | 2016-03-03 |
| 20160065211 | LOW POWER DRIVER WITH PROGRAMMABLE OUTPUT IMPEDANCE - A low power programmable driver includes a first driver output, a first programmable driver leg and a second programmable driver leg. The first programmable driver leg has a pull-up half and a pull-down half. The pull-up half is electrically coupled between a supply voltage and the first driver output. The pull-up half is electrically coupled to receive a signal and a first control signal. The pull-down half is electrically coupled between an internal ground and the first driver output. The pull-down half is electrically coupled to receive an inversion of the signal and the first control signal. A second programmable driver leg has a pull-up half and a pull-down half. The pull-up half is electrically coupled between the supply voltage and the first driver output. The pull-up half is electrically coupled to receive the signal and a second control signal. The pull-down half is electrically coupled between the internal ground and the first driver output. The pull-down half is electrically coupled to receive the inversion of the signal and the second control signal. The first programmable driver leg contributes to a termination impedance of the driver when the first control signal is high and does not contribute to the termination impedance when the first control signal is low. The second programmable driver leg contributes to the termination impedance of the driver when the second control signal is high and does not contribute to the termination impedance when the second control signal is low. | 2016-03-03 |
| 20160065212 | METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION - Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level. | 2016-03-03 |
| 20160065213 | LOGIC CELL FOR PROGRAMMABLE LOGIC DEVICE - A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells. | 2016-03-03 |
| 20160065214 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: an inverter gate circuit which inverts and outputs a logic level of an input signal, the inverter gate circuit includes a constant current source and a switch unit which are connected in series between a first power supply wiring and a second power supply wiring, and, according to the control signal, the switch unit switches real values of a gate length and a gate width of a switch transistor configured by a transistor to which a current outputted from the constant current source is applied among a plurality of transistors. | 2016-03-03 |
| 20160065215 | CLOCK MONITOR AND SYSTEM ON CHIP INCLUDING THE SAME - A system on chip includes a plurality of function blocks configured to perform predetermined functions, respectively, a clock control unit configured to generate a plurality of operating clock signals that are provided to the plurality of function blocks, respectively, a clock monitor configured to monitor frequencies of the operating clock signals to generate an interrupt signal, and a processor configured to control the frequencies of the operating clock signals based on the interrupt signal. The clock monitor includes a selector configured to select one of the operating clock signals to provide a selected clock signal, a frequency detector configured to detect a frequency of the selected clock signal to provide a detection frequency, and an interrupt generator configured to generate the interrupt signal based on the detection frequency, where the interrupt signal indicates a frequency abnormality of the operating clock signal corresponding to the selected clock signal. | 2016-03-03 |
| 20160065216 | INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM - An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks. | 2016-03-03 |
| 20160065217 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor device includes a field programmable gate array (FPGA), a controller and a memory. The controller controls the FPGA. The memory stores converted configuration data obtained by converting configuration data of the FPGA, based on defect data of the FPGA. | 2016-03-03 |
| 20160065218 | RECONFIGURABLE LOGIC CIRCUIT DEVICE - According to one embodiment, a reconfigurable logic circuit device includes a memory circuit including a cell group which includes unit cells connected in series, a control circuit connected to the unit cell at one end of the cell group, and an output terminal connected to the unit cell at the other end of the cell group; and a switch circuit connected to the output terminal and controlled by a signal from the memory circuit. Each of the unit cells includes a select element including first and second terminals and a control terminal to which a control signal is input, and a memory element including a third terminal connected to the first terminal and a fourth terminal connected to the second terminal. | 2016-03-03 |
| 20160065219 | DYNAMIC PRESCALING FOR PERFORMANCE COUNTERS - A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate. | 2016-03-03 |
| 20160065220 | CMOS OSCILLATOR HAVING STABLE FREQUENCY WITH PROCESS, TEMPERATURE, AND VOLTAGE VARIATION - A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage. | 2016-03-03 |
| 20160065221 | SYNCHRONIZATION FOR MULTIPLE ARBITRARY WAVEFORM GENERATORS - A system and method synchronizes multi-AWG system, where such systems are of a type having a master arbitrary waveform generator (AWG), one or more slave AWGs, and a sync hub having a sync controller and sync phase detector. The method operates by receiving at the sync hub a divided down clock (SystemRefClock) signal from a master arbitrary waveform generator (AWG). The method then derives a clock signal (SystemClock) from the SystemRefClock signal received from the master AWG and outputs the SystemClock signal to the master AWG and to the one or more slave AWGs Finally, the SystemClock signal is used to clock a synchronous trigger for the master AWG and one or more slave AWGs to play a waveform. In one aspect, the synchronous trigger includes AlignmentFiducial and Run signals to effect trigger and play commands. | 2016-03-03 |
| 20160065222 | SEMICONDUCTOR DEVICE - A semiconductor device includes a synthesizer, a phase locked loop (PLL) circuit, and a clock generating unit which is coupled to a crystal oscillator and generates an oscillation signal, and supplies the oscillation signal to the synthesizer and PLL circuit as a clock signal. | 2016-03-03 |
| 20160065223 | FOREGROUND AND BACKGROUND BANDWIDTH CALIBRATION TECHNIQUES FOR PHASE-LOCKED LOOPS - Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device. | 2016-03-03 |
| 20160065224 | FAST FREQUENCY THROTTLING AND RE-LOCKING TECHNIQUE FOR PHASE-LOCKED LOOPS - Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO. | 2016-03-03 |
| 20160065225 | METHOD FOR RE-CENTERING A VCO, INTEGRATED CIRCUIT AND WIRELESS DEVICE - A method of re-centering a voltage controlled oscillator of a wireless device comprising a phase locked loop circuit is described. The method comprises receiving an input frequency signal at a phase detector of the phase locked loop circuit from a frequency source; generating an oscillator signal based on the received frequency signal; selectably opening a feedback loop of the phase locked loop circuit when in a calibration mode of operation, performing coarse frequency tuning of the oscillator output signal; performing fine frequency tuning of a coarsely adjusted oscillator output signal; and closing the feedback loop. | 2016-03-03 |
| 20160065226 | PLL CIRCUIT, METHOD, AND ELECTRONIC APPARATUS - A PLL circuit includes a frequency divider dividing an oscillation signal to generate a divided signal having a cycle of T/M (M: an integer greater than one); a phase comparator generating M reference signals by sequentially delaying a reference signal having a cycle of T one after another by a predetermined delay time and generating an Exclusive OR calculation result of the M reference signals and the divided signal; a loop filter generating a voltage signal based on the Exclusive OR calculation result input thereto; a voltage-controlled oscillator generating the oscillation signal by oscillating at a frequency in accordance with the voltage signal; and a control circuit adjusting the predetermined delay time to be equal to T/2M based on an Exclusive OR calculation result of at least two of the M reference signals. | 2016-03-03 |
| 20160065227 | ADJUSTING THE MAGNITUDE OF A CAPACITANCE OF A DIGITALLY CONTROLLED CIRCUIT - An apparatus comprises a digitally controlled circuit having a variable capacitance and a controller configured to adjust a magnitude of the variable capacitance of the digitally controlled circuit. The digitally controlled circuit comprises a plurality of gain elements, the plurality of gain elements comprising one or more positive voltage-to-frequency gain elements and one or more negative voltage-to-frequency gain elements. The controller is configured to adjust the magnitude of the capacitance by adjusting the gain provided by respective ones of the gain elements in an alternating sequence of the positive voltage-to-frequency gain elements and the negative voltage-to-frequency gain elements. | 2016-03-03 |
