| 09th week of 2016 patent applcation highlights part 67 |
| Patent application number | Title | Published |
|---|
| 20160064528 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and a hard mask atop the metal gate; and performing a high-density plasma (HDP) process to form a cap layer on the hard mask and the substrate. | 2016-03-03 |
| 20160064529 | METHOD FOR FABRICATING MULTI-GATE STRUCTURE DEVICE WITH SOURCE AND DRAIN HAVING QUASI-SOI STRUCTURE - A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device. | 2016-03-03 |
| 20160064530 | FinFETs with Vertical Fins and Methods for Forming the Same - In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins. | 2016-03-03 |
| 20160064531 | METHOD TO FORM A CYLINDRICAL GERMANIUM NANOWIRE DEVICE ON BULK SILICON SUBSTRATE - A method for manufacturing a semiconductor device includes providing a substrate structure having a substrate and a cavity in the substrate, epitaxially growing a SiGe nanowire in the cavity, and removing a portion of the substrate surrounding the SiGe nanowire to substantially expose a surface of the SiGe nanowire. The method further includes oxidizing the exposed surface of the SiGe nanowire to form an oxide layer, removing the oxide layer by etching, and repeating the oxidizing and removing steps to form a suspended germanium nanowire in the cavity. | 2016-03-03 |
| 20160064532 | MONOLITHIC THREE DIMENSIONAL NAND STRINGS AND METHODS OF FABRICATION THEREOF - Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material. | 2016-03-03 |
| 20160064533 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having mix-loaded therein a nonvolatile memory cell and a field effect transistor at a reduced cost. A method of manufacturing a semiconductor device includes pattering a conductor film by using an additional mask that covers a gate electrode formation region of a memory formation region and exposes a main circuit formation region (field effect transistor formation region) and thereby forming a gate electrode of a nonvolatile memory cell in the memory formation region and then forming an n | 2016-03-03 |
| 20160064534 | Method of Manufacturing a Vertical Junction Field Effect Transistor - A method of manufacturing a vertical junction field effect transistor (JFET) includes forming a drain in a semiconductor substrate, forming a compound semiconductor epitaxial layer on the semiconductor substrate, and forming a source, a gate, a drift region, and a body diode all in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source. | 2016-03-03 |
| 20160064535 | HETEROSECTION TUNNEL FIELD-EFFECT TRANSISTOR (TFET) - A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region. | 2016-03-03 |
| 20160064536 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a first gate electrode, a first region, and a second region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on the third semiconductor region. The first region is provided in the second semiconductor region. The first region is positioned between the first semiconductor region and the third semiconductor region. The second region is provided in the second semiconductor region. The second region is positioned between the first region and the gate electrode. A carrier density of the first conductivity type in the second region is higher than a carrier density of the first conductivity type in the first region. | 2016-03-03 |
| 20160064537 | IGBT USING TRENCH GATE ELECTRODE - An IGBT includes a trench gate electrode that is bent when a semiconductor substrate is seen in a plan view, and an inner semiconductor region of the same conductivity type as an emitter region is formed at a position inside a bent portion of the trench gate electrode and exposed on a front surface of the semiconductor substrate. The trench gate electrode is bent, and therefore, a hole density during operation increases, whereby conductivity modulation phenomenon is accelerated, and an on-state voltage is reduced. When the IGBT is turned off, the inner semiconductor region influences a movement path of the holes so that a moving distance thereof through a body region becomes short. The holes escape easily to a body contact region when the IGBT is turned off. Increase of current density during the operation and prevention of a latchup are both achieved. | 2016-03-03 |
| 20160064538 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity. | 2016-03-03 |
| 20160064539 | SEMICONDUCTOR STRUCTURE AND RECESS FORMATION ETCH TECHNIQUE - A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material. | 2016-03-03 |
| 20160064540 | III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS - III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack. | 2016-03-03 |
| 20160064541 | VERTICAL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor. | 2016-03-03 |
| 20160064542 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a stripe shape between a plurality of the stripe shaped source regions on the semiconductor substrate, an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source regions in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole. | 2016-03-03 |
| 20160064543 | FINFET WITH A SILICON GERMANIUM ALLOY CHANNEL AND METHOD OF FABRICATION THEREOF - A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. | 2016-03-03 |
| 20160064544 | FINFET SEMICONDUCTOR DEVICE WITH ISOLATED FINS MADE OF ALTERNATIVE CHANNEL MATERIALS - One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin. | 2016-03-03 |
| 20160064545 | TECHNIQUES AND CONFIGURATIONS FOR STACKING TRANSISTORS OF AN INTEGRATED CIRCUIT DEVICE - Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed. | 2016-03-03 |
| 20160064546 | EDGE TERMINATION FOR TRENCH GATE FET - A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer. | 2016-03-03 |
| 20160064547 | Semiconductor Device with Field Electrode Structures in a Cell Area and Termination Structures in an Edge Area - A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area. | 2016-03-03 |
| 20160064548 | Semiconductor Device with a Termination Mesa Between a Termination Structure and a Cell Field of Field Electrode Structures - A semiconductor device includes a cell field with a plurality of field electrode structures and cell mesas. The field electrode structures are arranged in lines. The cell mesas separate neighboring ones of the field electrode structures from each other. Each field electrode structure includes a field electrode and a field dielectric separating the field electrode from a semiconductor body. A termination structure surrounds the cell field, extends from a first surface into the semiconductor body, and includes a termination electrode and a termination dielectric separating the termination electrode from the semiconductor body. The termination and field dielectrics have the same thickness. A termination mesa, which is wider than the cell mesas, separates the termination structure from the cell field. | 2016-03-03 |
| 20160064549 | Structure and Method of Forming Semiconductor Device - The present disclosure provides a method for fabricating semiconductor device. The method includes forming a first dielectric layer over a substrate, forming a gate structure over a first portion of the first dielectric layer, forming a sidewall spacer over a second portion of the first dielectric layer and on the gate structure, converting the second portion of the first dielectric layer and an exposed third portion of the first dielectric layer to a first portion of a second dielectric layer and a second portion of the second dielectric layer, respectively, removing the second portion of the second dielectric layer and a portion of the substrate to form a recess in the substrate adjacent the sidewall spacer, forming a source/drain (S/D) feature in the recess and removing the gate electrode and the first portion of the first dielectric layer to form a gate trench. | 2016-03-03 |
| 20160064550 | INSULATED GATE TYPE SWITCHING DEVICE - An insulated gate type switching device includes: a first region being of a first conductivity type; a body region being of a second conductivity type and in contact with the first region; a second region being of the first conductivity type and separated from the first region by the body region; an insulating film being in contact with the first region, the body region and the second region; and a gate electrode facing the body region via the insulating film. The body region includes a first body region and a second body region. The first body region has a theoretical threshold level Vth larger than that of the second body region. | 2016-03-03 |
| 20160064551 | HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES - Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2016-03-03 |
| 20160064552 | LDMOS TRANSISTOR AND FABRICATION METHOD THEREOF - A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region. | 2016-03-03 |
| 20160064553 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a body region of a second conductivity type formed in a semiconductor layer of a first conductivity type in a semiconductor substrate; a gate electrode facing the body region via a gate insulating film; a source region of the first conductivity type formed in the body region, on a first side of the gate electrode; a drain region of the first conductivity type formed in the semiconductor substrate such that a field oxide film is disposed between the drain region and a second side of the gate electrode; and an impurity diffusion region of the first conductivity type having, at least in a partial region thereof between the drain region and the body region, an impurity concentration distribution in which a concentration of impurities becomes higher in accordance with a depth from a main face of the semiconductor substrate. | 2016-03-03 |
| 20160064554 | Field-Effect Semiconductor Device Having Alternating N-Type and P-Type Pillar Regions Arranged in an Active Area - In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions. | 2016-03-03 |
| 20160064555 | III-NITRIDE TRANSISTOR WITH ENHANCED DOPING IN BASE LAYER - A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum. | 2016-03-03 |
| 20160064556 | TRENCH GATE FET WITH SELF-ALIGNED SOURCE CONTACT - A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench. | 2016-03-03 |
| 20160064557 | VERTICAL JUNCTIONLESS TRANSISTOR DEVICE AND MANUFACTURING METHODS - A method for forming a semiconductor device includes forming a fin device structure in a buffer layer on a substrate. The fin device structure includes a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion. The method also includes forming a sacrificial layer disposed over the fin device structure and forming a device semiconductor layer disposed over a surface of the sacrificial layer. A gate dielectric layer is then formed and is disposed over a surface of the device semiconductor layer. A gate electrode layer is formed and disposed over a surface of the gate dielectric layer. The method includes removing a portion of the sacrificial layer to form a cavity surrounding the fin structure and performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure. | 2016-03-03 |
| 20160064558 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure comprises a doped substrate, a gate structure, a source, a drain and a field doped region. The source and the drain are in the doped substrate on opposing sides of the gate structure respectively. The field doped region has a conductivity type opposite to a conductivity type of the source and the drain. The field doped region is extended from the source to be beyond a first gate sidewall of the gate structure but not reach a second gate sidewall of the gate structure opposing to the first gate sidewall. | 2016-03-03 |
| 20160064559 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n | 2016-03-03 |
| 20160064560 | PROCESS DESIGN TO IMPROVE TRANSISTOR VARIATIONS AND PERFORMANCE - The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure. | 2016-03-03 |
| 20160064561 | Method and Apparatus for use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 2016-03-03 |
| 20160064562 | STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS - Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device. | 2016-03-03 |
| 20160064563 | PFET AND CMOS CONTAINING SAME - A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above. | 2016-03-03 |
| 20160064564 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material. | 2016-03-03 |
| 20160064565 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region. | 2016-03-03 |
| 20160064566 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING SPACERS FOR SOURCE/DRAIN CONFINEMENT - A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement. | 2016-03-03 |
| 20160064567 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process. | 2016-03-03 |
| 20160064568 | DISPLAY DEVICE - According to one embodiment, a display device includes a thin-film transistor. The thin-film transistor includes a gate electrode, an insulating layer disposed to superpose the gate electrode, and a semiconductor layer disposed on the insulating layer. The gate electrode is opposed to at least the semiconductor layer in part. The gate electrode includes a laminate including a first layer containing silicon as a main component and a second layer which contains titanium as a main component and which is in contact with the first layer, and is in contact with the insulating layer. | 2016-03-03 |
| 20160064569 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide semiconductor layer, that is, by an interface state between the oxide semiconductor layer and the insulating film. A first oxide semiconductor layer S | 2016-03-03 |
| 20160064570 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×10 | 2016-03-03 |
| 20160064571 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode. | 2016-03-03 |
| 20160064572 | SEMICONDUCTOR DEVICE - An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×10 | 2016-03-03 |
| 20160064573 | SEMICONDUCTOR DEVICE INCLUDING ZENER DIODE AND METHOD OF MANUFACTURING THEREOF - An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. | 2016-03-03 |
| 20160064574 | FERRITIC STAINLESS STEEL FOIL FOR SOLAR CELL - A ferritic stainless steel foil for a solar cell substrate excellent in terms of threading performance. The ferritic stainless steel foil for a solar cell substrate may have a chemical composition containing, by mass %, Cr: 14% or more and 24% or less and Nb: 0.1% or more and 0.6% or less, and optionally further containing Mo: 2.0% or less, a Vickers hardness of Hv250 or more and Hv450 or less, and a Vickers hardness of Hv250 or more and Hv450 or less after the substrate has undergone an optical absorber layer growth process in which the substrate is held in a temperature range of 450° C. or higher and 650° C. or lower for a duration of 1 minute or more. | 2016-03-03 |
| 20160064575 | BACK-CONTACT BACK-SHEET FOR PHOTOVOLTAIC MODULES WITH PASS-THROUGH ELECTRIC CONTACTS - The present invention proposes a back-contact back-sheet for photovoltaic modules comprising back-contact cells and a method of manufacturing thereof. The back-contact back-sheet comprises an insulating substrate upon which a connecting circuit is attached. The back-contact back-sheet further comprises at least a region indented towards the air-side of the photovoltaic module. The indentation is performed is performed in a portion of the back-contact back-sheet comprising the connecting circuit. A through-hole is then formed within the indented region so as to bring into communication the surface of the connecting circuit exposed towards the inside of the photovoltaic module with the face of the back-contact back-sheet facing the air-side of the photovoltaic module. A transport portion of a connecting element, such as the stem of a rivet, may be introduced into the through-hole so that the contact portion of the connecting element, such as the head of the rivet, is attached and electrically connected to the surface of the connecting circuit exposed towards to the inside of the photovoltaic module. The connecting circuit thus permits exchange of an electrical signal between the photovoltaic module in which the back-contact back-sheet is embedded and the outside. | 2016-03-03 |
| 20160064576 | LEAKAGE PATHWAY LAYER FOR SOLAR CELL - Leakage pathway layers for solar cells and methods of forming leakage pathway layers for solar cells are described. | 2016-03-03 |
| 20160064577 | SOLAR PHOTOVOLTAIC MODULE - In the present invention a new solar photovoltaic module is proposed comprising: a silicon based photovoltaic element; an intermediate layer deposited on said photovoltaic element to the incident light side; an interference filter deposited on the incident light side of said intermediate layer; a front element disposed on the incident light side of said interference filter. Said intermediate layer has a transparency of at least 90% for infrared light between 780 nm and 1200 nm and said interference filter is corrugated and composed of a multilayer comprising a plurality of dielectric layers designed to transmit at least 75% of the total incident solar infrared light between 780 nm and 1200 nm, and to reflect and diffuse incident visible solar light such that the perceived color of said reflected and diffused visible light by any observer positioned anywhere to the incident light side of said solar photovoltaic module and looking towards the front element of said solar photovoltaic module is defined by a Y10 tristimulus value not lower than 50 defined by an x value of 0.20 to 0.45 and a y value of 0.20 to 0.45 in a chromaticity diagram of a CIE 1964 Yxy color system using a white light source measured with a D65 light source with a 10-degree angular field. | 2016-03-03 |
| 20160064578 | PHOTOSENSOR - A photosensor, including: first and second photosensitive cells formed next to each other in a semiconductor substrate; first and second dielectric interface layers coating, respectively, the first and second cells; and a resonance grating formed in a third dielectric layer coating the first and second interface layers, wherein the first and second interface layers have different thicknesses, or different refraction indexes, or different thickness and refraction indexes. | 2016-03-03 |
| 20160064579 | SPAD DEVICE WITH RADIATION BLOCKING RINGS AND VIAS AND RELATED ARRAYS AND METHODS - A Single-Photon Avalanche Diode (SPAD) device an active region configured to detect incident radiation, a first radiation blocking ring surrounding the active region, and a radiation blocking cover configured to shield part of the active region from the incident radiation. The radiation blocking cover is configured to define a second radiation blocking ring vertically spaced apart from the first radiation blocking ring. The SPAD device may include radiation blocking vias extending between the first and second radiation blocking rings. | 2016-03-03 |
| 20160064580 | BACK CONTACT SUBSTRATE FOR A PHOTOVOLTAIC CELL OR MODULE - A back contact substrate for a photovoltaic cell includes a carrier substrate and an electrode, the electrode including an alloy thin film based on at least two elements, at least one first element MA chosen among copper (Cu), silver (Ag) and gold (Au), and at least one second element MB chosen among zinc (Zn), titanium (Ti), tin (Sn), silicon (Si), germanium (Ge), zirconium (Zr), hafnium (Hf), carbon (C) and lead (Pb). | 2016-03-03 |
| 20160064581 | BACK CONTACT SUBSTRATE FOR A PHOTOVOLTAIC CELL OR MODULE - A back contact substrate for a photovoltaic cell includes a carrier substrate and an electrode, the electrode including an alloy thin film based: on at least one among copper (Cu) and silver (Ag); and on zinc (Zn). | 2016-03-03 |
| 20160064582 | METHOD FOR MANUFACTURING LIGHT ABSORPTION LAYER - Provided is a method of fabricating a CIGS absorption layer which, may have improved material utilization and productivity and have excellent thin film uniformity even in a large area by depositing and heat treating a precursor having a multilayer structure by a sputtering method using a compound, target of In | 2016-03-03 |
| 20160064583 | Three-Dimensional Metamaterial Devices with Photovoltaic Bristles - A metamaterial of an array of photovoltaic bristles may enable each photovoltaic bristle to have a high probability of photon absorption. The high probability of photon absorption may lead to increased efficiency and more power generation from an array of photovoltaic bristles. A completed photovoltaic device may benefit from further total efficiency gains by implementing a corrugated structure in the metamaterial and/or an assembled solar panel of metamaterials. Various methods to manufacture these metamaterial devices may include utilize stamping methods, photolithographic techniques, etching techniques, deposition techniques, as well as the creation of vias to form arrays of photovoltaic bristles for the metamaterial photovoltaic devices. | 2016-03-03 |
| 20160064584 | SOLAR MODULE REAR SIDE ENCAPSULATION ELEMENT AND SOLAR MODULE - A solar module rear side encapsulation element having a laminate-type layer construction having at least one polymer plate or polymer foil having a laminate surface. The laminate-type layer construction has at least one protective layer having layer openings. The protective layer covers at least 70% of the laminate surface by a covering area, and due to the layer openings at least 15% and maximum 99.9% of the regions of the solar module rear side encapsulation element lying under the protective layer are covered in the covering area, and the protective layer is formed as a structure made of threads, thus being open to diffusion. | 2016-03-03 |
| 20160064585 | Adhesive for Solar Battery Protective Sheets - The present invention provides an adhesive for solar battery protective sheets, comprising a urethane resin obtainable by mixing an acrylic polyol with an isocyanate compound; and a hydroxyphenyltriazine based compound, wherein the acrylic polyol is obtainable by polymerizing polymerizable monomers, the polymerizable monomers comprise a monomer having a hydroxyl group and other monomers, and the other monomers comprise acrylonitrile and (meth)acrylic ester(s). The adhesive for solar battery protective sheets has satisfactory initial adhesion to a film, satisfactory adhesion property to a film after aging, and excellent weatherability and hydrolysis resistance over the long term. The present invention also provides a solar battery protective sheet which is obtainable by using the adhesive. | 2016-03-03 |
| 20160064586 | SOLAR CELL BACK SHEET, AND SOLAR CELL MODULE - To provide a solar cell back sheet having excellent weather resistance and durability in which high adhesiveness to a sealing material for sealing a solar cell element is maintained for a long period of time even under harsh conditions of a high temperature and a high humidity and a solar cell module including the same. | 2016-03-03 |
| 20160064587 | SOLAR CELL MODULE AND METHOD FOR MANUFACTURING SOLAR CELL MODULE - A solar cell module includes a plurality of solar cell elements, a tab wiring, which connects the plurality of solar cell elements with each other, and a resin portion, which bonds the tab wiring and the surface of the solar cell element, the resin portion being nonlinearly provided on the surface of the solar cell element. | 2016-03-03 |
| 20160064588 | CONCENTRATOR LENS FOR DIRECTING LIGHT TO A PHOTOVOLTAIC TARGET OR MIRRORED SURFACE AND A DYNAMIC WINDOW APPARATUS UTILIZING THE SAME - A lens device for concentrating light onto a photovoltaic target or mirrored surface is disclosed. The lens may be configured to receive and reflect at least a portion of incident light onto the photovoltaic target or mirrored surface, and pass a portion of incident light through the lens depending on the received light's particular angle of incidence. The lens may include a lens body having a first surface that extends away from a light incident base at generally a first acute angle relative to the base, and a collector surface extending from a distal end of the first surface toward the base at a second angle. The collector surface may include a photovoltaic target configured to receive a portion of light emitted from the base and to convert the received portion of light into electrical energy, or a mirrored surface configured to reflect light generally back to the origin. | 2016-03-03 |
| 20160064589 | SOLAR CELL MODULE - A solar cell module includes a transparent layer; a plurality of cells disposed on an upper surface of the transparent layer and spaced apart from each other; a reflective layer disposed on the upper surface of the transparent layer and surrounding at least a portion of a peripheral of at least one cell; and a cover plate disposed above, the plurality of cells and the reflective layer. At least a part, opposed to the reflective layer, of a lower surface of the cover plate has a serrate shape. | 2016-03-03 |
| 20160064590 | FABRICATION OF SOLAR CELLS WITH ELECTRICALLY CONDUCTIVE POLYIMIDE ADHESIVE - The present disclosure provides a method of manufacturing a solar cell including: providing a first substrate and a second substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a back metal contact over the bottom subcell; applying a conductive polyimide adhesive to the second substrate; attaching the second substrate on top of the back metal contact; and removing the first substrate to expose the surface of the top subcell. | 2016-03-03 |
| 20160064591 | PASSIVATION METHOD - A solar cell module includes a substrate; an absorber layer formed over the substrate; a porous alumina passivation layer formed on an upper surface of the absorber layer; a buffer layer conformably formed over the passivation layer; and a transparent conducting oxide layer conformably formed over the buffer layer. | 2016-03-03 |
| 20160064592 | A METHOD OF ANODISING A SURFACE OF A SEMICONDUCTOR DEVICE - The present disclosure provides a method of anodising a surface of a semiconductor device comprising a p-n junction. The method comprises exposing a first surface portion of the semiconductor device to an electrolytic solution that is suitable for anodising the first surface portion when an electrical current is directed through a region at the first surface portion. Further, the method comprises exposing a portion of the semiconductor device to electromagnetic radiation in a manner such that the electromagnetic radiation induces the electrical current and the first surface portion anodises. | 2016-03-03 |
| 20160064593 | METHOD AND APPARATUS FOR DEPOSITING COPPER-INDIUM-GALLIUM SELENIDE (CuInGaSe2-CIGS) THIN FILMS AND OTHER MATERIALS ON A SUBSTRATE - An apparatus for deposition of a plurality of elements onto a solar cell substrate that comprises: a housing; a transporting apparatus to transport the substrate in and out of the housing; a first tubing apparatus to deliver powders of a first elements to the housing; a first source material tube located outside of the housing and joined to a feeder tube of the tubing apparatus; a valve located inside of the first source material tube sufficient to block access between the first source material tube and the first feeder tube; a first heating tube located inside of the housing and connected to the first feeder tube; a similar second tubing apparatus to deliver powders of a second elements to the housing; a loading station for loading the substrate onto the transporting apparatus; one or more thermal sources to heat the housing and the first and second heating tube. | 2016-03-03 |
| 20160064594 | LIGHT-EMITTING DIODE - A light-emitting diode (LED) includes a first type semiconductor layer, a second type semiconductor layer, a first current controlling structure, and a first electrode. The second type semiconductor layer is joined with the first type semiconductor layer. The second type semiconductor layer has a first region and a second region, in which the first region has a first threading dislocation density, the second region has a second threading dislocation density, and the first threading dislocation density is greater than the second threading dislocation density. The first current controlling structure is joined with the first type semiconductor layer and has at least one first current-injecting zone therein, in which the vertical projection of the second region on the first current controlling structure at least partially overlaps with the first current-injecting zone. The first electrode is electrically coupled with the first type semiconductor layer. | 2016-03-03 |
| 20160064595 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method for manufacturing a light emitting diode (LED) package, the method includes providing an LED chip and forming electrodes on a top surface of the LED chip; forming a first electric insulation layer on the top surface of the LED chip, the first electric insulation layer adapted to enclose the electrodes therein; etching the first electric insulation layer to define a plurality of second through holes; forming a substrate on a top surface of the first electric insulation layer, the substrate adapted to fill in the plurality of second through holes, the substrate directly contacting the electrodes; dividing the substrate into a plurality of spaced heat dissipation parts; and forming a packaging layer on a bottom surface of the substrate, the packaging layer adapted to enclose the LED chip therein. | 2016-03-03 |
| 20160064596 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device including a substrate; a first conductivity semiconductor layer disposed on the substrate; a first barrier disposed on the first conductivity semiconductor layer; a well disposed on the first barrier and including a first region having a first energy gap and a second region having a second energy gap and closer to the semiconductor layer than the first region; a second barrier disposed on the well; and a second conductivity semiconductor layer disposed on the second barrier; wherein the first energy gap decreases along a stacking direction of the light-emitting device and has a first gradient, the second energy gap increases along the stacking direction and has a second gradient, and an absolute value of the first gradient is smaller than an absolute value of the second gradient. | 2016-03-03 |
| 20160064597 | METHOD FOR MAKING EPITAXIAL STRUCTURE - A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed to expose the epitaxial layer. | 2016-03-03 |
| 20160064598 | ULTRAVIOLET LIGHT-EMITTING DEVICE - Disclosed is an ultraviolet light-emitting device. The light-emitting device includes: an n-type contact layer including a GaN layer; a p-type contact layer including an AlGaN or AlInGaN layer; and an active region of multiple quantum well structure positioned between the n-type contact layer and the p-type contact layer. In addition, the active region of multiple quantum well structure includes a GaN or InGaN layer with a thickness less than 2 nm, radiating an ultraviolet ray with a peak wavelength of 340 nm to 360 nm. | 2016-03-03 |
| 20160064599 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND OPTICAL COUPLING DEVICE - A semiconductor light-emitting element includes a semiconductor stacked body that includes a light emitting layer in which n well layers (where n is, for example, an integer of 1 to 10) formed of In | 2016-03-03 |
| 20160064600 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode. The pn light-emitting body includes a p-type nitride semiconductor layer and an n-type nitride semiconductor layer to emit a light beam having an energy value higher than an electron trapping level existing in the semiconductor stacked body, in which the p-type nitride semiconductor layer of the pn light-emitting body is electrically connected to the gate electrode, and functions as a gate of the transistor. | 2016-03-03 |
| 20160064601 | Deep Ultraviolet Light Emitting Diode - A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure. | 2016-03-03 |
| 20160064602 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATING METHOD THEREOF - A semiconductor light-emitting device including an epitaxial structure, a first electrode structure, a second electrode structure, a light reflective metal layer, a resistivity-enhancing structure and a protection ring is provided. The light-emitting epitaxial structure has a first surface and a second surface. The light-emitting epitaxial structure has a first zone and a second zone. The first electrode structure is disposed within the first zone. The second electrode structure is disposed within the second zone. The light reflective metal layer is disposed adjacent to the second surface. The resistivity-enhancing structure is disposed in contact with a surface of the light reflective metal layer and corresponding to a position of the first electrode structure. The protection ring has a first portion and a second portion. The first portion surrounds a sidewall of the light reflective metal layer. The second portion corresponds to the second electrode structure. | 2016-03-03 |
| 20160064603 | Light Emitting Diodes With Current Confinement - A light emitting diode (LED) assembly with a current blocking layer along the periphery of the LED is disclosed. In one embodiment, the LED assembly includes an LED comprising a light emitting layer disposed between a first layer having a first conductivity type and a second layer having a second conductivity type. The LED assembly further includes a contact electrically coupled to the first layer and a current blocking layer formed along a periphery of the LED at an interface with the contact, and covering a peripheral portion of the first contact. The current blocking layer forms a non-ohmic connection with the contact, thereby limiting the current injection between the contact and the first layer of the LED. In one embodiment, the current blocking layer surrounds a portion of the first layer, defining a portion of the light emitting layer that emits photons. In one embodiment, the current blocking layer comprises a transparent insulating layer between the LED and the contact. In one embodiment, the current blocking layer comprises a plasma treated region of the first layer of the LED. | 2016-03-03 |
| 20160064604 | FLIP CHIP LIGHT EMITTING DIODE PACKAGING STRUCTURE - A flip chip light emitting diode (LED) packaging structure, including a substrate, an LED chip including a P electrode and a N electrode. A protruding platform is formed in a center of the substrate. The protruding platform includes a first connecting portion and a second connecting portion electrically insulating from each other. The P electrode and the N electrode is conductively fixed to the protruding platform by solder, and a bottom edge of the P electrode and the N electrode are beyond a top edge of the protruding platform. | 2016-03-03 |
| 20160064605 | LED DIE AND METHOD OF MANUFACTURING THE SAME - An LED die includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a transparent conductive layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, the second semiconductor layer and the transparent conductive layer are successively formed on the substrate. The first electrode and the second electrode respectively is formed on the first semiconductor layer and the transparent conductive layer. A plurality of grooves defined on the first semiconductor layer, and a plurality of hole groups defined on the second semiconductor layer. The present disclosure also provides a method of manufacturing the LED die. | 2016-03-03 |
| 20160064606 | EPITAXIAL SUBSTRATE, METHOD OF MANUFACTURING THE EPITAXIAL SUBSTRATE AND LIGHT EMITTING DIODE HAVING EPITAXIAL SUBSTRATE - An epitaxial substrate for growing a lighting emitting structure of a light emitting diode, includes a transparent base, a first buffer layer and a second buffer layer formed on the transparent base. The transparent base includes a first surface and a second surface opposite to the first surface. Plural protrusions are formed on the first surface of the transparent base. Each first buffer layer is formed on the outer surfaces of the plural protrusions. The second buffer layer fills in the recesses defined between two adjacent protrusions, and covers the first buffer layer. The refractive index of the first buffer layer is larger than that of the transparent base, and is less than that of the second buffer layer. This disclosure also relates a method for manufacturing the epitaxial substrate and a light emitting diode having the same. | 2016-03-03 |
| 20160064607 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device may include: a base layer formed of a first conductivity-type semiconductor material; an insulating layer disposed on the base layer and having a plurality of openings exposing portions of the base layer; a plurality of nanocores disposed on the exposed portions of the base layer and formed of a first conductivity-type semiconductor material, each of which including a tip portion having a crystal plane different from that of a side surface thereof; a first high resistance layer disposed on the tip portion of the nanocore and formed of an oxide containing an element which is the same as at least one of elements constituting the nanocore; an active layer disposed on the first high resistance layer and the side surface of the nanocore; and a second conductivity-type semiconductor layer disposed on the active layer. | 2016-03-03 |
| 20160064608 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - There is provided a nanostructure semiconductor light emitting device including: a base layer formed of a first conductivity-type nitride semiconductor; and a plurality of light emitting nanostructures disposed to be spaced apart from one another on the base layer, wherein each of the plurality of light emitting nanostructures includes a nanocore formed of a first conductivity-type nitride semiconductor; a stress control layer disposed on a surface of the nanocore and including a nitride semiconductor containing indium; an active layer disposed on the stress control layer; a second conductivity-type nitride semiconductor layer disposed on the active layer; and a defect blocking layer disposed on at least a portion of the stress control layer and including a nitride semiconductor layer having a lattice constant lower than that of the stress control layer. | 2016-03-03 |
| 20160064609 | NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nanostructure semiconductor light emitting device may include a base layer having first and second regions and formed of a first conductivity-type semiconductor material; a plurality of light emitting nanostructures disposed on the base layer, each of which including a nanocore formed of a first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on the nanocore; a contact electrode disposed on the light emitting nanostructures to be connected to the second conductivity-type semiconductor layer; a first electrode connected to the base layer; and a second electrode covering a portion of the contact electrode disposed on at least one of light emitting nanostructures disposed in the second region among the plurality of light emitting nanostructures, wherein light emitting nanostructures disposed in the second region and light emitting nanostructures disposed in the first region among the plurality of light emitting nanostructures have different shapes. | 2016-03-03 |
| 20160064610 | Optoelectronic Device and Method for Producing Same - A method for producing an optoelectronic component is disclosed. A first layer which has a dielectric to the surface of a semiconductor crystal. A photoresist layer is applied and structured on the first layer. The photoresist layer is structured in such a way that the photoresist layer has an opening, The first layer is partially separated in order to expose a lateral region of the surface. A contact area having a first metal is applied in the lateral region of the surface. The photoresist layer is removed. A second layer, which comprises an optically transparent, electrically conductive material, and a third layer, which comprises a second metal, are applied. | 2016-03-03 |
| 20160064611 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a laminated semiconductor structure having a first surface and a second surface opposing each other, a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer respectively forming the first surface and the second surface, and an active layer. First and second electrodes are disposed on the first surface of the laminated semiconductor structure and the second surface of the laminated semiconductor structure, respectively. A connecting electrode extends to the first surface to be connected to the second electrode. A support substrate is disposed on the second electrode, and an insulating layer insulates the connecting electrode from the active layer and the first conductivity-type semiconductor layer. | 2016-03-03 |
| 20160064612 | LIGHT EMITTING DEVICE AND DISPLAY DEVICE USING THE SAME - The disclosure relates to a light emitting device. The light emitting device includes a first electrode, a first semiconductor layer, an active layer, a second semiconductor layer and a second electrode. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. At least one of the first electrode and the second electrode comprises a metal metamaterial layer. The metal metamaterial layer comprises a number of metamaterial units arranged to form a periodic array. A distance between the metal metamaterial layer and the active layer is less than or equal to 100 nanometers. The display device using the light emitting device is also provided. | 2016-03-03 |
| 20160064613 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a first electrode, a second electrode and an epitaxial structure. The epitaxial structure is arranged on the first electrode, and electrically connects with the first electrode and the second electrode. The second electrode surrounds periphery of the epitaxial structure to reflect light from the epitaxial structure to emit out from the top of the epitaxial structure. This disclosure also relates to a method for manufacturing the light emitting diode. The light emitting diode and the method help solve the problem of low light efficiency of the light emitting diode. | 2016-03-03 |
| 20160064614 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A light emitting diode package includes a substrate, a light emitting diode mounted on the substrate by flip chip bonding and a protective layer. The light emitting diode includes an epitaxial layer, a first electrode and a second electrode on the epitaxial layer. The first electrode and the second electrode are spaced apart from each other. The first and second electrodes are embedded in the protective layer. This disclosure also relates to a method for manufacturing the light emitting diode package. | 2016-03-03 |
| 20160064615 | DISPLAY DEVICE - A display device includes a substrate, and a plurality of surface-mounted LEDs which are provided in a matrix pattern on a front surface side of the substrate. A plurality of eave members are provided between rows of the plurality of surface-mounted LEDs on the front surface side of the substrate. A plurality of connecting members are provided between columns of the plurality of surface-mounted LEDs on the front surface side of the substrate. A waterproof resin is provided in a space surrounded by the plurality of eave members and the plurality of connecting members so as to expose front surfaces of the plurality of surface-mounted LEDs and front surfaces of the plurality of connecting members. The plurality of connecting members are formed with a wide width on a front surface side and formed with a narrow width on a rear surface side. | 2016-03-03 |
| 20160064616 | TRANSPARENT CONDUCTIVE STRUCTURE, DEVICE COMPRISING THE SAME, AND THE MANUFACTURING METHOD THEREOF - An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium. | 2016-03-03 |
| 20160064617 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode (LED) structure including a stacked semiconductor layer, a contact layer and a dielectric reflective layer is provided. The stacked semiconductor layer includes a first type doped layer, a second type doped layer and an active layer disposed between the first type doped layer and the second type doped layer, wherein the first type doped layer, the active layer and the second type doped layer are penetrated by a plurality of recesses. The contact layer is disposed on the second type doped layer. The dielectric reflective layer is disposed on the contact layer and extended into the recesses to connect the contact layer and the first type doped layer with a coverage rate equal to or less than 60% from a top view of the LED structure. | 2016-03-03 |
| 20160064618 | OPTOELECTRONIC COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic component includes a plastics housing, wherein a first leadframe section is embedded into the plastics housing, a chip landing face and a soldering contact face of the first leadframe section are at least partly not covered by the plastics housing, the soldering contact face has a groove, and the groove is not covered by the material of the plastics housing. | 2016-03-03 |
| 20160064619 | LIGHT EMITTING DEVICE AND OPTICAL DEVICE - The present invention provides a light emitting device which is capable of enhancing the radiant intensity on a single direction. The light emitting device comprises a substrate, a lens bonded to the substrate, and an LED chip bonded to the substrate and exposed in a gap clipped between the substrate and the lens, wherein the lens has a light output surface which bulges in a direction that is defined from the substrate toward the LED chip and is contained in a thickness direction of the substrate to transmit the light emitted from the LED chip. | 2016-03-03 |
| 20160064620 | LIGHT EMITTING DEVICE FOR ILLUMINATING PLANTS - A spectrally adapted light emitting device for illuminating plants includes at least one semiconductor light-emitting diode (LED), at least one light conversion element for down-converting a portion of light emitted at the first wavelength to at least a second wavelength between 600 nm-680 nm, and at least one scattering device to diffuse light within the light emitting device. The at least one LED is configured to emit at least a first wavelength between 400 nm and 480 nm. The spectral light output from the spectrally adapted light emitting device is bi-modal with wavelengths in a range of 400 nm and 800 nm including a first local maximum between 400 nm and 480 nm and a second local maximum between 600 nm-680 nm with a local minimum between the first local maximum and the second local maximum. | 2016-03-03 |
| 20160064621 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device includes providing a wafer having a substrate and a plurality of semiconductor stacked-layer bodies stacked on the substrate, an upper surface of the substrate being exposed at an outer peripheral region of each of the plurality of semiconductor stack bodies in a plan view, forming a separation layer integrally covering the upper surface of the substrate and an upper surface of the semiconductor stacked-layer body, the separation layer including a separation boundary, forming a support member on the separation layer, removing the substrate, forming a wavelength conversion layer on a side of the semiconductor stack body and the separation layer where the substrate is removed, the wavelength conversion layer made of a resin containing a wavelength conversion member, and removing the wavelength conversion layer located in the outer peripheral region by separating the separation layer at the separation boundary. | 2016-03-03 |
| 20160064622 | SOLID-STATE LIGHT EMITTING DEVICES AND SIGNAGE WITH PHOTOLUMINESCENCE WAVELENGTH CONVERSION AND PHOTOLUMINESCENT COMPOSITIONS THEREFOR - A photoluminescent composition (“phosphor ink”) comprises a suspension of particles of at least one blue light (380 nm to 480 nm) excitable phosphor material in a light transmissive liquid binder in which the weight loading of at least one phosphor material to binder material is in a range 40% to 75%. The binder can be U.V. curable, thermally curable, solvent based or a combination thereof and comprise a polymer resin; a monomer resin, an acrylic, a silicone or a fluorinated polymer. The composition can further comprise particles of a light reflective material suspended in the liquid binder. Photoluminescence wavelength conversion components; solid-state light emitting devices; light emitting signage surfaces and light emitting signage utilizing the composition are disclosed. | 2016-03-03 |
| 20160064623 | LIGHT EMITTING DIODE (LED) COMPONENT COMPRISING A PHOSPHOR WITH IMPROVED EXCITATION PROPERTIES - A light emitting diode (LED) component comprises an LED having a dominant wavelength in a range of from about 425 nm to about 475 nm, and a first phosphor and a second phosphor are in optical communication with the LED. The first phosphor has a peak emission wavelength in the range of from about 600 nm to about 700 nm, and the second phosphor has a peak emission wavelength in the range of from about 500 nm to about 600 nm. An excitation spectrum of the first phosphor includes, at excitation wavelengths longer than 530 nm, no intensities greater than about 60% of a maximum intensity of the excitation spectrum. | 2016-03-03 |
| 20160064624 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - A light emitting device package may include: a package board; a semiconductor light emitting device disposed on the package board; and a color characteristics converting unit having a resin including a wavelength conversion material converting light emitted from the semiconductor light emitting device into light of a different wavelength and glass powder having a glass composition with a rare earth element added thereto and filtering light within a particular wavelength band, and disposed on a path on which light emitted from the semiconductor light emitting device travels. | 2016-03-03 |
| 20160064625 | LIGHT EMITTING DEVICE INCLUDING RGB LIGHT EMITTING DIODES AND PHOSPHOR - A light emitting device includes a plurality light emitting diodes configured to produce a primary light; a wavelength conversion means configured to at least partially convert the primary light into secondary light having peak emission wavelength ranges between 450 nm and 520 nm, between 500 nm and 570 nm, and between 570 nm and 680 nm; and a molded part to enclose the light emitting diodes and the wavelength conversion means. | 2016-03-03 |
| 20160064626 | PHOSPHOR-COATED LIGHT EXTRACTION STRUCTURES FOR PHOSPHOR-CONVERTED LIGHT EMITTING DEVICES - A conformal thin-film phosphor layer is disposed over a surface of a hemispherical lens, a Fresnel lens, or a microlens array, thereby forming a phosphor-coated light extraction structure. Also disclosed is a phosphor-converted photonic crystal light emitting device that incorporates a thin-film phosphor layer. A wafer-level packaging process incorporating a thin-film phosphor layer is also disclosed herein. | 2016-03-03 |
| 20160064627 | LIGHT-EMITTING DEVICE - Disclosed is a light-emitting device ( | 2016-03-03 |
