| 09th week of 2016 patent applcation highlights part 66 |
| Patent application number | Title | Published |
|---|
| 20160064428 | Solid-State Image Capturing Device And Manufacturing Method Thereof - An aspect of the invention is a solid-state image capturing device that includes a P-type well | 2016-03-03 |
| 20160064429 | SOLID-STATE IMAGE SENSOR AND CAMERA - A solid-state image sensor is provided. The sensor includes a semiconductor region having a first conductivity type, and a charge accumulation portion having a second conductivity type. The semiconductor region includes a first semiconductor region, and a second semiconductor region formed below the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region. The charge accumulation portion has a side and a bottom covered with the semiconductor region, and includes at least three regions arranged along a depth direction. A first region formed in a shallowest position has a width larger than that of each of the at least three regions. An impurity concentration of a second region formed in a deepest position is higher than that of each region between the first and second region of the at least three regions. | 2016-03-03 |
| 20160064430 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - An image sensor includes a semiconductor layer, a plurality of light sensing regions, a first pixel isolation layer, a light shielding layer, and a wiring layer. The semiconductor layer has a first surface and a second surface opposite to the first surface. The plurality of light sensing regions is formed in the semiconductor layer. The first pixel isolation layer is disposed between adjacent light sensing regions from among the plurality of light sensing regions. The first pixel isolation layer is buried in an isolation trench formed between the first surface and the second surface. The light shielding layer is formed on the second surface of the semiconductor layer and on some of the adjacent light sensing regions. The wiring layer is formed on the first surface of the semiconductor layer. | 2016-03-03 |
| 20160064431 | INTEGRATED CIRCUIT WITH CAVITY-BASED ELECTRICAL INSULATION OF A PHOTODIODE - An integrated circuit includes a semiconductor substrate, at least one photodiode, which is formed on a surface of the semiconductor substrate, at least one trench, which extends from the surface of the semiconductor substrate into the semiconductor substrate and surrounds a region of the semiconductor substrate on which the photodiode Is arranged, and at least one cavity in the semiconductor substrate, which is located below the surface of the semiconductor substrate. The at least one trench and the at least one cavity form an electrical insulation structure between the region of the semiconductor substrate on which the photodiode is arranged and one or more adjacent regions of the semiconductor substrate. | 2016-03-03 |
| 20160064432 | SOLID-STATE IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions. | 2016-03-03 |
| 20160064433 | BACKSIDE ILLUMINATED IMAGE SENSOR STRUCTURE - Backside illuminated image sensor structures are provided. The backside illuminated image sensor structure includes a device substrate having a frontside and a backside and pixels formed at the frontside of the substrate. The backside illuminated image sensor structure further includes a metal element formed in a dielectric layer over the backside of the substrate and a color filter layer formed over the dielectric layer. In addition, the metal element is configured to form a light blocking area in the device substrate and is made of copper. | 2016-03-03 |
| 20160064434 | Color Filter Array and Image Receiving Method thereof - A color filter array, for an image sensing device, includes a plurality of filter patterns. Each filter pattern includes at least one first filter, corresponding to a first wavelength range of a first color; at least one second filter, corresponding to a second wavelength range of a second color; at least one third filter, corresponding to a third wavelength range of a third color; at least one fourth filter, corresponding to a first infrared wavelength range, wherein the first infrared wavelength range is an intersection of the first wavelength range and the second wavelength range; and at least one fifth filter, corresponding to a second infrared wavelength range, wherein the second infrared wavelength range is an intersection of the first wavelength range and the third wavelength range. | 2016-03-03 |
| 20160064435 | PHOTO SENSOR AND MANUFACTURING METHOD THEREOF - A photo sensor according to an embodiment includes a semiconductor substrate. A plurality of photodiodes are provided on a first surface of the semiconductor substrate. A plurality of photodetective filters corresponding to the photodiodes are provided on a second surface of the semiconductor substrate opposite to the first surface. A plurality of lenses correspond to the photodetective filters so as to respectively cover the photodetective filters. Protruding portions protrude on the second surface between adjacent ones of the photodetective filters. | 2016-03-03 |
| 20160064436 | CIRCUIT-INTEGRATED PHOTOELECTRIC CONVERTER AND METHOD FOR MANUFACTURING THE SAME - A circuit-integrated photoelectric converter in which a dished portion is less likely to be formed in an insulating layer underlying a plasmonic filter portion and the plasmonic filter portion can be accurately and finely processed is provided and a method for manufacturing the same is provided. A metal layer ( | 2016-03-03 |
| 20160064437 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion. | 2016-03-03 |
| 20160064438 | SEMICONDUCTOR DEVICE HAVING RECESS FILLED WITH CONDUCTIVE MATERIAL AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip comprising a first metallic structure and a second semiconductor chip comprising a second metallic structure. The second semiconductor chip is bonded with the first semiconductor chip by a conductive material filled in a through via. The through via connects the first metallic structure and the second metallic structure, wherein a portion of the through via is inside the first semiconductor chip and the second semiconductor chip. | 2016-03-03 |
| 20160064439 | SEMICONDUCTOR AND OPTOELECTRONIC METHODS and DEVICES - A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse. | 2016-03-03 |
| 20160064440 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR UNIT INCLUDING THE SAME - A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer. | 2016-03-03 |
| 20160064441 | SOLID IMAGING DEVICE - A solid imaging device to an embodiment includes a semiconductor substrate and a conductive film. The semiconductor substrate has a plurality of photoelectric conversion elements constituting a plurality of pixels formed therein, the semiconductor substrate having a first surface and a second surface opposite to the first surface and being equipped with a wire layer on a first surface side of the semiconductor substrate. The conductive film is patterned and arranged above a border between pixels of the plurality of pixels on a second surface side of the semiconductor substrate. The conductive film is substantially transparent to visible light. | 2016-03-03 |
| 20160064442 | SOLID-STATE IMAGE PICKUP APPARATUS AND IMAGE PICKUP SYSTEM - Provided is a solid-state image pickup apparatus, including: a pixel region, in which a plurality of pixels each including an amplifier transistor are arranged two-dimensionally in rows and columns, and which includes an n-row signal mixing region in which outputs of n amplifier transistors are mixed, where n is a natural number of 1 or more, and an m-row signal mixing region in which outputs of m amplifier transistors are mixed, where m>n; a column signal line to which a voltage from the amplifier transistor is output; and a clipping circuit, which is configured to clip a voltage in the column signal line, and is arranged at a position that is closer to the n-row signal mixing region than to the m-row signal mixing region. | 2016-03-03 |
| 20160064443 | IMAGING DEVICE AND ELECTRONIC DEVICE - An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. Variation in threshold voltage of an amplifier transistor (the fifth transistor) included in the first circuit can be compensated. | 2016-03-03 |
| 20160064444 | IMAGING DEVICE AND ELECTRONIC DEVICE - An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit, a second circuit and a third circuit. The first circuit includes a photoelectric conversion element, a plurality of transistors including an amplifier transistor, and a plurality of capacitors. The second circuit includes a transistor. The third circuit includes a resistor and a transistor for controlling a current flowing in the resistor. The output signal of the imaging device is determined in accordance with the current flowing in the resistor. Variations in electrical characteristics of the amplifier transistor included in the first circuit can be compensated. | 2016-03-03 |
| 20160064445 | PHOTODIODE ARRAY DETECTOR - A photodiode array detector used for detecting light which has undergone wavelength separation by a spectroscopic element, the photodiode array detector including: a light receiving element array wherein, taking a plurality of light receiving elements which detect light of the same wavelength range as one unit, a plurality of such units are arrayed in the direction of dispersion of said wavelength; and a charge accumulation time setting unit which sets different charge accumulation times for the plurality of light receiving elements within the one unit. | 2016-03-03 |
| 20160064446 | IMAGE SENSOR AND PIXEL OF THE IMAGE SENSOR - A pixel of an image sensor includes a well below a gate and containing a dopant at a first concentration, a shallow trench isolation (STI) configured to electrically isolate the well, and a channel stop adjacent to at least one border between the well and the STI and containing a dopant at a second concentration higher than the first concentration. | 2016-03-03 |
| 20160064447 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - The invention improves performance of a solid-state image sensor in which each of the pixels arranged in a pixel array part includes a microlens and plural photodiodes. The locations of the opposing sides between the photodiodes arranged side by side in each pixel are self-alignedly defined by a gate pattern. The location over wiring where the microlens is to be formed is checked and determined using as a superposition mark a check pattern of the same layer as a gate layer. | 2016-03-03 |
| 20160064448 | IMAGE SENSOR HAVING IMPROVED LIGHT UTILIZATION EFFICIENCY - An image sensor is provided including a photo sensor layer including a plurality of photo-sensing cells; a color separation layer disposed on the photo sensor layer and including color separation elements embedded in a transparent spacer layer; and a micro lens array arranged on the color separation layer, the micro lens array including a plurality of micro lenses. The color separation layer separates light by wavelength. The micro lens array concentrates incident light onto the plurality of color separation elements. The color separation elements include: a first main splitter which transmits light of a first primary color onto first photo-sensing cells which faces the first main splitter and diffracts and/or refracts light of colors other than the first primary color onto photo-sensing cells adjacent to the first photo-sensing cell; and a plurality of first auxiliary splitters which are arranged surrounding the first main splitter. | 2016-03-03 |
| 20160064449 | METHOD OF MANUFACTURING JUNCTION FIELD EFFECT TRANSISTOR, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING IMAGING APPARATUS, JUNCTION FIELD EFFECT TRANSISTOR, AND IMAGING APPARATUS - A method of manufacturing a junction field effect transistor having a channel region disposed in a semiconductor substrate, deeper than one of a source region and a drain region, the method includes a first step of forming a first mask having a first opening portion over the semiconductor substrate in which a first semiconductor region of a first conductivity type is disposed, a second step of forming a second semiconductor region of a second conductivity type defined as the channel region, in the first semiconductor region by implantation of ions of second conductivity type opposite to the first conductivity type using the first mask, and a third step of forming a third semiconductor region of the second conductivity type defined as the one of the source region and the drain region, by implantation of ions of the second conductivity type, using the first mask. | 2016-03-03 |
| 20160064450 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a semiconductor device incorporating a CMOS image sensor, dangling bonds existing at the interface between a semiconductor substrate and an insulating film formed over the semiconductor substrate are selectively terminated with hydrogen. | 2016-03-03 |
| 20160064451 | SEMICONDUCTOR COMPONENT COMPRISING MAGNETIC FIELD SENSOR - The invention relates to a semiconductor component ( | 2016-03-03 |
| 20160064452 | MEMORY DEVICE - A memory device according to an embodiment includes a memory element; and a transistor including a semiconductor layer and a plurality of gates, wherein the plurality of gates include: a first set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, and a second set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, the gates included in the first set is disposed in a manner to separate from the gates included in the second set in a direction along a side surface of the semiconductor layer. | 2016-03-03 |
| 20160064453 | SELF-RECTIFYING RRAM CELL STRUCTURE AND RRAM 3D CROSSBAR ARRAY ARCHITECTURE - The present disclosure provides a self-rectifying RRAM cell structure including a first electrode layer formed of a nitride of a first metal element, a second electrode layer formed of a second metal element that is different from the first metal element, a first resistive switching layer and a second resistive switching layer. The first resistive switching layer is sandwiched between the first electrode layer and the second resistive switching layer, and the second resistive switching layer is sandwiched between the first resistive switching layer and the second electrode layer. The first resistive switching layer has a first bandgap that is lower than the second bandgap of the second resistive switching layer. Furthermore, a RRAM 3D crossbar array architecture is also provided. | 2016-03-03 |
| 20160064454 | 3D VARIABLE RESISTANCE MEMORY DEVICE HAVING JUNCTION FET AND DRIVING METHOD THEREOF - A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer. | 2016-03-03 |
| 20160064455 | ORGANIC PHOTOELECTRONIC DEVICE AND IMAGE SENSOR - An organic photoelectronic device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, the active layer including a heterojunction of a p-type semiconductor and an n-type semiconductor, the p-type semiconductor including a compound represented by Chemical Formula 1. | 2016-03-03 |
| 20160064456 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGE SENSOR HAVING THE SAME - A photoelectric conversion device of an image sensor includes a first transparent electrode layer, an active layer, and a second transparent electrode layer, which are sequentially stacked. A light having a wavelength of about 440 nm-480 nm is absorbed within a depth of about ⅕ of an entire thickness of the active layer from both the top and bottom surfaces of the active layer. | 2016-03-03 |
| 20160064457 | ORGANIC PHOTOELECTRONIC DEVICE AND IMAGE SENSOR - An organic photoelectronic device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, the active layer including a first compound having a maximum absorption wavelength of about 500 nm to about 600 nm in a visible ray region and a transparent second compound in a visible ray region. | 2016-03-03 |
| 20160064458 | TRANSPARENT DISPLAY PANEL AND DRIVING METHOD THEREOF - A transparent display panel including a transparent substrate and a plurality of display units formed on the substrate is provided. Each of the display units includes a color light area and a least one of transparent areas disposed around the color light area. The color light area has a geometric center, a first color pixel structure, a second color pixel structure, and a third color pixel structure. The first, second and third color pixel structures take the geometric center as a center in each display unit and are disposed in a radial way corresponding to the center to form the color light area. | 2016-03-03 |
| 20160064459 | ORGANIC LIGHT-EMITTING DIODE CONTACT IMPEDANCE TESTING DEVICE - An organic light-emitting diode (OLED) contact impedance testing device includes an organic light-emitting diode cathode material layer located in an organic light-emitting diode panel. A plurality of test points is located on an edge of the organic light-emitting diode panel. A plurality of connecting lines connects the organic light-emitting diode cathode material layer to the test points. Each test point is partially superimposed by one of the connecting lines. Each connecting line is partially superimposed by the organic light-emitting diode cathode material layer. The OLED contact impedance testing device can rapidly detect the contact impedances of different components in the OLED panel. Thus, problems in the complicated OLED panel can rapidly be located through measurement of the impedances. | 2016-03-03 |
| 20160064460 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY - An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate comprising an emission area, a sensor area, and an opening area. The display also includes an OLED formed in the emission area of the substrate, wherein the OLED comprises an organic light emitting layer interposed between pixel and opposite electrodes, wherein the opposite electrode is configured to firstly reflect light emitted from the intermediate layer. The display further includes a photo sensor formed in the sensor area of the substrate and a partition wall located adjacent to the photo sensor and at least partially surrounding the photo sensor. The partition wall is configured to secondly reflect at least a portion of the first reflected light, and wherein the photo sensor is configured to at least partially absorb the second reflected light. | 2016-03-03 |
| 20160064461 | Flexible Organic Light Emitting Diode Display Panel - Provided is a flexible organic light emitting diode display panel including: a substrate in which an opening region and a non-opening region are defined; an organic light emitting diode disposed on the substrate; a bank layer disposed in the non-opening region; and a peeling reduction layer having a reverse-tapered shape disposed in the non-opening region. | 2016-03-03 |
| 20160064462 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ORGANIC LIGHT-EMITTING DIODE DISPLAY EMPLOYING THE SAME - A thin film transistor (TFT) array substrate and an organic light-emitting diode display employing the same are disclosed. In one aspect, the substrate includes at least one TFT, the TFT including a substrate and a semiconductor pattern comprising a source region, a channel region, and a drain region. The TFT also includes a gate insulating layer covering the semiconductor pattern, a side gate electrode electrically insulated from the semiconductor pattern and formed over at least one side of the channel region, and a top gate electrode formed over the gate insulating layer so as to partially overlap the semiconductor pattern, the side gate electrode and the top gate electrode electrically connected to each other. | 2016-03-03 |
| 20160064463 | ORGANIC ELECTROLUMINESCENT DEVICE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - An organic electroluminescent device and its manufacturing method, and a display device are provided. The manufacturing method of the organic electroluminescent device includes: forming a first electrode on a predetermined region of an insulating base; conducting a surface treatment to an upper surface of the first electrode and an upper surface of the insulating base which is not covered by the first electrode, so that the upper surface of the first electrode is lyophilic and the upper surface of the insulating base which is not covered by the first electrode is lyophobic; forming an electroluminescent layer on the first electrode; and forming a second electrode on the electroluminescent layer. In the organic electroluminescent device formed by the manufacturing method, the electroluminescent layer has a relatively uniform thickness. | 2016-03-03 |
| 20160064464 | FLEXIBLE DISPLAY PANEL - A flexible display panel includes a bending area and a surrounding area adjacent to the bending area. The barrier layer includes first silicon nitride layers and first silicon oxide layers which are overlapped with the bending area. The first silicon nitride layers and the first silicon oxide layers are stacked alternately. Each of the first silicon nitride layers may have a thickness less than or equal to about 400 Å, and each of the first silicon oxide layers may have a thickness less than or equal to about 650 Å. | 2016-03-03 |
| 20160064465 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - The present invention relates to a thin film transistor substrate having two different types of semiconductor materials on the same substrate, and a display using the same. A disclosed display may include a substrate, a first thin film transistor having a polycrystalline semiconductor material on the substrate and a second thin film transistor having an oxide semiconductor material on the substrate. | 2016-03-03 |
| 20160064466 | Display Device with Micro Cover Layer and Manufacturing Method for the Same - There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. | 2016-03-03 |
| 20160064467 | ORGANIC ELECTROLUMINESCENT DEVICE AND ELECTRONIC APPARATUS - An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line. | 2016-03-03 |
| 20160064468 | SEMICONDUCTOR UNIT, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate. | 2016-03-03 |
| 20160064469 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes a scanning line and a data line intersecting each other, a pixel circuit provided at a position corresponding to an intersection of the scanning line and the data line, and a power supply wiring line that supplies a given potential. The pixel circuit includes a light emitting element and a driving transistor configured to control a current flowing through the light emitting element. A gate electrode of the driving transistor is electrically connected via a first relay electrode to a given node. The first relay electrode is formed in the same layer as the power supply wiring line and the data line. The first relay electrode is surrounded on at least three sides by the power supply wiring line. | 2016-03-03 |
| 20160064470 | MICRO-FABRICATED INTEGRATED COIL AND MAGNETIC CIRCUIT AND METHOD OF MANUFACTURING THEREOF - A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material. | 2016-03-03 |
| 20160064471 | EMBEDDED CAPACITOR - A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor. | 2016-03-03 |
| 20160064472 | INTEGRATED CIRCUITS INCLUDING A MIMCAP DEVICE AND METHODS OF FORMING THE SAME FOR LONG AND CONTROLLABLE RELIABILITY LIFETIME - Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness. | 2016-03-03 |
| 20160064473 | THIN FILM ELECTRONIC COMPONENT - A thin film electronic component includes: a substrate; a thin film electrode layer over the substrate; an inorganic insulation layer formed on the thin film electrode layer; an organic insulation layer formed on the inorganic insulation layer; and a lead-out electrode that electrically connects to the thin film electrode layer. The inorganic insulation layer has a through-hole formed therein, so as to expose a portion of the thin film electrode layer. The organic insulation layer has a through-hole formed therein, so as to expose the through-hole in the inorganic insulation layer. The lead-out electrode is formed in the through-hole in the inorganic insulation layer and the through-hole in the organic insulation layer. A shape of a borderline defining the through-hole at a top surface of the organic insulation layer in a plan view has chamfered corners. | 2016-03-03 |
| 20160064474 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate doped with a first conductive type;
| 2016-03-03 |
| 20160064475 | LATERAL PiN DIODES AND SCHOTTKY DIODES - Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate. | 2016-03-03 |
| 20160064476 | SEMICONDUCTOR DEVICE - A semiconductor device has a reduced an on-voltage and uses a gate resistance to improve the trade-off relationship between turn-on loss Eon and dV/dt, and turn-on dV/dt controllability. A floating p | 2016-03-03 |
| 20160064477 | Semiconductor Device and a Method for Manufacturing a Semiconductor Device - A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure. | 2016-03-03 |
| 20160064478 | SUPER-JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE THEREOF - The present disclosure relates to a super-junction structure, a method for manufacturing the super-junction structure and a semiconductor device including the super-junction structure. The super-junction structure includes an epitaxy layer of a first doping type and a plurality of first pillar regions of a second doping type which are formed in the epitaxy layer and are separated from each other. Each of the first pillar regions has a doping concentration that decreases from bottom to top. A portion of the epitaxy layer between adjacent ones of the first pillar regions is a second pillar region. The first pillar regions and the second pillar region are arranged alternatively to form the super-junction structure. The first pillar regions are characterized by the doping concentration that decreases from bottom to top so that the super-junction structure has a relatively high breakdown voltage and a relatively low on resistance. Moreover, the super-junction structure changes a path of an avalanche current and thus suppresses an avalanche current so that the device is not easily damaged. | 2016-03-03 |
| 20160064479 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first dielectric layer, a first conductive layer, and an isolation structure. The substrate has a trench. The first dielectric layer is disposed on the substrate between two neighboring trenches. The first conductive layer is disposed on the first dielectric layer. The isolation structure, including a step zone and a recessed zone, is disposed in the trench, wherein an upper surface of the step zone is higher than an upper surface of the first dielectric layer. | 2016-03-03 |
| 20160064480 | Semiconductor Constructions, Memory Arrays and Electronic Systems - The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions. | 2016-03-03 |
| 20160064481 | BORON RICH NITRIDE CAP FOR TOTAL IONIZING DOSE MITIGATION IN SOI DEVICES - A semiconductor-on-insulator (SOI) structure that includes a cap layer composed of a boron-rich compound or doped boron nitride located between a top semiconductor layer and a buried insulator layer is provided. The cap layer forms a conductive path between the top semiconductor layer and the buried insulator layer in the SOI structure to dissipate total ionizing dose (TID) accumulated charges, thus advantageously mitigating TID effects in fully depleted SOI transistors. | 2016-03-03 |
| 20160064482 | NANOWIRE TRANSISTOR STRUCTURES WITH MERGED SOURCE/DRAIN REGIONS USING AUXILIARY PILLARS - A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures. | 2016-03-03 |
| 20160064483 | SEMICONDUCTOR STRUCTURE WITH CONTACT OVER SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H | 2016-03-03 |
| 20160064484 | LATERAL BIPOLAR JUNCTION TRANSISTORS ON A SILICON-ON-INSULATOR SUBSTRATE WITH A THIN DEVICE LAYER THICKNESS - Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors. | 2016-03-03 |
| 20160064485 | SUBSTRATE OF SEMICONDUCTOR DEVICE INCLUDING EPITAXAL LAYER AND SILICON LAYER HAVING SAME CRSTALLINE ORIENTATION - A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation. | 2016-03-03 |
| 20160064486 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations. | 2016-03-03 |
| 20160064487 | POWER INTEGRATED DEVICES, ELECTRONIC DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A power integrated device includes a drift region disposed in a substrate, a source region disposed in the substrate spaced apart from the drift region, a drain region disposed in the drift region, a gate insulation layer and a gate electrode sequentially stacked on the substrate between the source region and the drift region, a trench isolation layer disposed in the drift region adjacent to a side of the drain region, and a deep trench field insulation layer disposed in the drift region adjacent to another side of the drain region, wherein a vertical height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer. | 2016-03-03 |
| 20160064488 | NITRIDE BASED SEMICONDUCTOR DEVICE - A nitride based semiconductor device includes: a substrate; a first buffer layer disposed on the substrate; a second buffer layer disposed on the first buffer layer; a third buffer layer disposed on the second buffer layer, the third buffer layer including an AlGaN-based nitride semiconductor; a fourth buffer layer disposed on the third buffer layer, the fourth buffer layer including a GaN-based nitride semiconductor; a barrier layer disposed on the fourth buffer layer, the barrier layer including an AlGaN-based nitride semiconductor; and a source electrode and a drain electrode, each disposed on the barrier layer, and a gate electrode disposed between the source electrode and the drain electrode, wherein the third buffer layer is subjected to lattice relaxation. There can be provided a nitride based semiconductor device capable of reducing a leakage current and improving breakdown capability. | 2016-03-03 |
| 20160064489 | GROWTH OF SEMICONDUCTORS ON HETERO-SUBSTRATES USING GRAPHENE AS AN INTERFACIAL LAYER - Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth. | 2016-03-03 |
| 20160064490 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d | 2016-03-03 |
| 20160064491 | GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 2016-03-03 |
| 20160064492 | Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication - A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening. | 2016-03-03 |
| 20160064493 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 2016-03-03 |
| 20160064494 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A high voltage semiconductor device including a P type substrate, a high voltage N type well, a first P type well, a drift region, and a P type doping layer is provided. The high voltage N type well and the P type doping layer, which is formed in a region located below the first P type well and the drift region, are formed in the P type substrate. The first P type well is formed in the high voltage N type well. A bottom of the first P type well and a bottom of the P type doping layer are separated from a surface of the P type substrate by a first depth and a second depth larger than the first depth, respectively. The drift region is formed in the high voltage N type well and extending down from the surface of the P type substrate. | 2016-03-03 |
| 20160064495 | SEMICONDUCTOR DEVICES WITH INTEGRATED HOLE COLLECTORS - Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons. | 2016-03-03 |
| 20160064496 | Semiconductor Device with Field Electrode and Contact Structure - A semiconductor device includes a field electrode structure with a field electrode and a field dielectric surrounding the field electrode. A semiconductor body includes a transistor section surrounding the field electrode structure and including a source zone, a first drift zone section and a body zone separating the source zone and the first drift zone section. The body zone forms a first pn junction with the source zone and a second pn junction with the first drift zone section. A gate structure surrounds the field electrode structure and includes a gate electrode and a gate dielectric separating the gate electrode and the body zone. A contact structure directly adjoins the source and body zones and surrounds the field electrode structure equably with respect to the field electrode structure. | 2016-03-03 |
| 20160064497 | DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE - N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate). | 2016-03-03 |
| 20160064498 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar. | 2016-03-03 |
| 20160064499 | TRANSISTOR AND MANUFACTURING METHOD THEREOF - A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided. | 2016-03-03 |
| 20160064500 | NANOCRYSTALINE DIAMOND CARBON FILM FOR 3D NAND HARDMASK APPLICATION - A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer. | 2016-03-03 |
| 20160064501 | UNDER-SPACER DOPING IN FIN-BASED SEMICONDUCTOR DEVICES - A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the device and a spacer and a cap formed over a dummy gate line separating a source and drain of the device. The device also includes an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer. | 2016-03-03 |
| 20160064502 | MIS-type Semiconductor Device - The present invention provides a MIS-type semiconductor device having a ZrO | 2016-03-03 |
| 20160064503 | ELECTRONIC DEVICES AND METHOD OF FABRICATING THE SAME - An electronic device includes a substrate. A lower electrode is disposed on the substrate and has a flat portion and protrusions. An intermediate layer is on the lower electrode. An upper electrode is on the intermediate layer. The lower electrode includes an alloy of a first metal and a second metal. The protrusions have a content ratio of the second metal higher than that of the flat portion. | 2016-03-03 |
| 20160064504 | Method of Manufacturing a Device by Locally Heating One or More Metalization Layers and by Means of Selective Etching - A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device. | 2016-03-03 |
| 20160064505 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an impurity introduction method. To manufacture a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption using the transistor. A gate electrode including a tungsten oxide film whose composition is controlled is used. The composition or the like is adjusted by a film formation method of the tungsten oxide film, whereby the work function can be controlled. By using the tungsten oxide film whose work function is controlled as part of the gate electrode, the threshold of the transistor can be controlled. Using the transistor whose threshold voltage is controlled, a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption can be manufactured. | 2016-03-03 |
| 20160064506 | SEMICONDUCTOR DEVICE HAVING METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device including a metal gate structure and formation method thereof. The semiconductor device includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a trench. A diffusion barrier layer is disposed over a bottom surface and sidewall surfaces of the trench in the dielectric layer. The diffusion barrier layer includes at least a titanium-nitride stacked layer. The titanium-nitride stacked layer includes a TiNx layer disposed over the bottom surface and the sidewall surfaces of the trench, a TiN layer on the TiNx layer, and a TiNy layer on the TiN layer, x<1 and y>1. A metal gate is filled in the trench and disposed on the diffusion barrier layer. | 2016-03-03 |
| 20160064507 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a memory cell equipped with a control gate electrode and a memory gate electrode adjacent to each other via a charge storage layer and having improved performance. | 2016-03-03 |
| 20160064508 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar-shaped semiconductor layer formed on a semiconductor substrate; a first first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer; a third first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer and located at a higher position than the first first-conductivity-type semiconductor layer; a first gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; a first gate formed so as to surround the first gate insulating film; a second gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; and a second gate formed so as to surround the second gate insulating film, wherein the first gate and the second gate are mutually connected. | 2016-03-03 |
| 20160064509 | HYDROGEN-FREE SILICON-BASED DEPOSITED DIELECTRIC FILMS FOR NANO DEVICE FABRICATION - Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films. | 2016-03-03 |
| 20160064510 | DEVICE INCLUDING A FLOATING GATE ELECTRODE AND A LAYER OF FERROELECTRIC MATERIAL AND METHOD FOR THE FORMATION THEREOF - An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane. | 2016-03-03 |
| 20160064511 | FINFET WITH A SILICON GERMANIUM ALLOY CHANNEL AND METHOD OF FABRICATON THEREOF - A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. | 2016-03-03 |
| 20160064512 | GROUP III-N NANOWIRE TRANSISTORS - A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions. | 2016-03-03 |
| 20160064513 | INTEGRATED CIRCUITS WITH A BOWED SUBSTRATE, AND METHODS FOR PRODUCING THE SAME - Integrated circuits and methods for manufacturing the same are provided. A method for manufacturing an integrated circuit includes forming a first and second STI insulator in a substrate, and bowing a substrate surface between the first and second STI insulators. A transistor is formed between the first and second STI insulators. | 2016-03-03 |
| 20160064514 | BORDERLESS CONTACT FORMATION THROUGH METAL-RECESS DUAL CAP INTEGRATION - An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s). | 2016-03-03 |
| 20160064515 | METHODS OF MAKING INTEGRATED CIRCUITS AND COMPONENTS THEREOF - One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer. | 2016-03-03 |
| 20160064516 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack positioned over the semiconductor substrate. The semiconductor device structure includes spacers positioned over sidewalls of the gate stack. The semiconductor device structure includes a first protective layer positioned between the gate stack and the spacers and between the spacers and the semiconductor substrate. The semiconductor device structure includes a second protective layer positioned between the spacers and the first protective layer. The first protective layer and the second protective layer include different materials. | 2016-03-03 |
| 20160064517 | Copper Contact Plugs with Barrier Layers - A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer. | 2016-03-03 |
| 20160064518 | Oxidation and Etching Post Metal Gate CMP - A method includes forming a dummy gate of a transistor at a surface of a wafer, removing the dummy gate, and filling a metallic material into a trench left by the removed dummy gate. A Chemical Mechanical Polish (CMP) is then performed on the metallic material, wherein a remaining portion of the metallic material forms a metal gate of the transistor. After the CMP, a treatment is performed on an exposed top surface of the metal gate using an oxidation-and-etching agent comprising chlorine and oxygen. | 2016-03-03 |
| 20160064519 | ULTRAHIGH SELECTIVE POLYSILICON ETCH WITH HIGH THROUGHPUT - Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer. | 2016-03-03 |
| 20160064520 | GERMANIUM-BASED QUANTUM WELL DEVICES - A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric. | 2016-03-03 |
| 20160064521 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer. | 2016-03-03 |
| 20160064522 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer. | 2016-03-03 |
| 20160064523 | SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS - A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron. | 2016-03-03 |
| 20160064524 | VERTICAL TUNNELING FIELD-EFFECT TRANSISTOR CELL AND FABRICATING THE SAME - A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack. | 2016-03-03 |
| 20160064525 | Semiconductor Device And Method For Fabricating The Same - To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first to a third oxide semiconductor layers are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first and the third oxide semiconductor layers are each an amorphous semiconductor film. The second oxide semiconductor layer is a crystalline semiconductor film. | 2016-03-03 |
| 20160064526 | METHODS OF FORMING ALTERNATIVE CHANNEL MATERIALS ON FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin. | 2016-03-03 |
| 20160064527 | UNDER-SPACER DOPING IN FIN-BASED SEMICONDUCTOR DEVICES - A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the device and a spacer and a cap formed over a dummy gate line separating a source and drain of the device. The device also includes an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer. | 2016-03-03 |
