| 09th week of 2016 patent applcation highlights part 65 |
| Patent application number | Title | Published |
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| 20160064328 | MULTI-CHIP SILICON SUBSTRATE-LESS CHIP PACKAGING - Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers. | 2016-03-03 |
| 20160064329 | EMBEDDED COMPONENT PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die. | 2016-03-03 |
| 20160064330 | METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS - Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines. | 2016-03-03 |
| 20160064331 | CHIP WITH PROGRAMMABLE SHELF LIFE - A structure includes a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD), a first top metal layer and a second top metal layer disposed on and in direct electrical connection with the first interconnect, a third top metal layer and a fourth top metal layer disposed on and in direct electrical connection with the second interconnect, a silicon dioxide layer above the first, second, third and fourth top metal layers, the silicon layer is in direct contact with the first and fourth top metal layers, and a barrier layer separating the silicon dioxide layer from each of the second and third top metal layers, a high resistance connection exist between the third top metal layer and the fourth top metal layer due to the presence of the silicon dioxide layer. | 2016-03-03 |
| 20160064332 | Metal Cap Apparatus and Method - A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal. | 2016-03-03 |
| 20160064333 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate and is provided with a first hole, and a contact portion that is formed in the first hole of the interlayer insulating film. The contact portion includes a first silicon film along an inner surface of the first hole of the interlayer insulating film. | 2016-03-03 |
| 20160064334 | FRONT SIDE PACKAGE-LEVEL SERIALIZATION FOR PACKAGES COMPRISING UNIQUE IDENTIFIERS - A method of making a semiconductor device can include providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. The method can include forming a build-up interconnect structure that extends over the active surface of each of the plurality of semiconductor die within the wafer, and forming a unique identifying mark for each of the plurality of semiconductor die as part of a layer within the build-up interconnect structure while simultaneously forming the layer of the build-up interconnect structure. The layer of the build-up interconnect structure can comprise both the unique identifying marks for each of the plurality of semiconductor die and functionality for the semiconductor device. Each unique identifying mark can convey a unique identity of its respective semiconductor die. The method can further include singulating the plurality of semiconductor die into a plurality of semiconductor devices. | 2016-03-03 |
| 20160064335 | Method of positioning elements, particularly optical elements, on the back side of a hybridized-type infrared detector - A method of positioning elements or additional technological levels ( | 2016-03-03 |
| 20160064336 | INVISIBLE DUMMY FEATURES AND METHOD FOR FORMING THE SAME - A plurality of first miniature elements of an overlay mark is formed in a first layer. A plurality of second miniature elements of the overlay mark is formed in a second layer different from the first layer. A plurality of dummy features is formed around the overlay mark. The dummy features are formed such that they each have a dimension below a resolution of an alignment detection tool configured to optically scan the overlay mark in an alignment process. | 2016-03-03 |
| 20160064337 | INTRAMODULE RADIO FREQUENCY ISOLATION - A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices. | 2016-03-03 |
| 20160064338 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate comprising a front surface, side surfaces, a back surface, and a recessed edge between the side surfaces and either the front surface or the back surface, the front surface comprising an active region, the active region comprising at least one contact pad, a polymeric member disposed and contacted with the recessed edge of the substrate, a mold disposed over the front surface of the substrate and the polymeric member, and an interface between the mold and the polymeric member. | 2016-03-03 |
| 20160064339 | METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT RENDERING A REVERSE ENGINEERING OF THE INTEGRATED CIRCUIT MORE DIFFICULT AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks. | 2016-03-03 |
| 20160064340 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure includes a first substrate having a first surface and a second surface opposite to the first surface, a conductive pad at the first surface of the first substrate, and a connector overlying the conductive pad, wherein the connector is configured for electrically connecting with a conductive land of a second substrate, wherein a geometric center of the connector is deviated from a geometric center of the conductive pad and a geometric center of the conductive land. | 2016-03-03 |
| 20160064341 | MICROELECTRONIC PACKAGES HAVING TEXTURIZED SOLDER PADS AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions. | 2016-03-03 |
| 20160064342 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one component, disposed over and connected to the backside redistribution layer; at least one chip adjacent to the at least one component; a molding compound disposed between the at least one chip and the at least one component; a via, disposed in the molding compound and connected to the backside redistribution layer; and a front redistribution layer, disposed over the chip and the via, wherein the chip and the at least one component are connected by using the backside redistribution layer, the via and the front redistribution layer. | 2016-03-03 |
| 20160064343 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved. | 2016-03-03 |
| 20160064344 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - The present invention makes it possible to: reduce the manufacturing cost of a semiconductor device having a redistribution layer; and further improve the reliability of a semiconductor device having a redistribution layer. | 2016-03-03 |
| 20160064345 | Word Line Hook Up with Protected Air Gap - A method of forming a semiconductor device includes forming a plurality of word lines separated by air gaps with contact pad structures connected to the word lines, and forming a dummy structure directly opposite an air gap between neighboring word lines. Subsequently, the contact pad structures are cut into individual contact pads by a contact pad cut that intersects the dummy structure. | 2016-03-03 |
| 20160064346 | SEMICONDUCTOR DEVICE - This invention provides a semiconductor device with improved reliability. A pad includes a slit portion formed so as to pass through the pad, and also includes a bonding portion positioned inside the slit portion in plan view, and an edge portion positioned outside the slit portion in plan view. In plan view, a via encloses the slit portion and is in contact with the bonding portion of the pad and the edge portion of the pad. | 2016-03-03 |
| 20160064347 | Bump on Pad (BOP) Bonding Structure - The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. | 2016-03-03 |
| 20160064348 | Packaging Devices, Packaged Semiconductor Devices, and Packaging Methods - Packaging devices, packaged semiconductor devices, and packaging methods are disclosed. In some embodiments, a packaging device includes a substrate having an integrated circuit die mounting region disposed thereon. Microstructures are disposed proximate a side of the integrated circuit die mounting region of the substrate. | 2016-03-03 |
| 20160064349 | SEMICONDUCTOR DEVICE CONNECTED BY ANISOTROPIC CONDUCTIVE FILM - A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film having a differential scanning calorimeter onset temperature of 60° C. to 85° C., and a elastic modulus change of 30% or less, as calculated by Equation 1, below, | 2016-03-03 |
| 20160064350 | CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT - A connection arrangement includes at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer is arranged adjacent to the connection layer in a bonded manner. The reinforcement layer has a higher modulus of elasticity than the connection layer. A particularly good protective effect is achieved if the reinforcement layer is formed in a frame-like manner by an outer and an inner boundary and, at least with the outer boundary thereof, encloses the connection face of the at least one electric and/or electronic component. | 2016-03-03 |
| 20160064351 | WIRE BONDING USING ELEVATED BUMPS FOR SECURING BONDS - In accordance with some embodiments, the present disclosure relates to improving the integrity of interconnections between electronic components. In some embodiments, a stitch bond can be secured by a ball or bump placed over the stitch bond. This results in forming strong, uniform interconnections and reducing or eliminating weak bonds. Further, in cases when interconnections are not formed correctly, bonding material can be recovered and reused. Efficiency is improved, yields are increased, and cost savings are achieved. | 2016-03-03 |
| 20160064352 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin. | 2016-03-03 |
| 20160064353 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing process. The semiconductor device has a plurality of die pads, IGBTs, diodes, freewheel diodes, an HVIC and LVICs mounted on the plurality of die pads, a plurality of leads, and an encapsulation resin body that covers these component parts. In a manufacturing process, a single-plate lead frame having the above-described plurality of die pads and leads connected together can be prepared. The semiconductor device may be manufactured by using this single-plate lead frame. | 2016-03-03 |
| 20160064354 | METHOD FOR ELECTRONIC CIRCUIT ASSEMBLY ON A PAPER SUBSTRATE - A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate. | 2016-03-03 |
| 20160064355 | CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF - A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at least partially surrounding the at least one second die, the lid having inclined sidewalls spaced apart from and facing the at least one second die. | 2016-03-03 |
| 20160064356 | SEMICONDUCTOR DEVICE PACKAGE WITH ORGANIC INTERPOSER - A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer. | 2016-03-03 |
| 20160064357 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction. | 2016-03-03 |
| 20160064358 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS STACKED OVER SUBSTRATE - According to the present invention, a semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface, a first layer formed over the first surface, a second layer thicker than the first layer formed over the first portion of the first layer, the first and second layers being formed of a same material, a first semiconductor chip mounted over a second portion of the first layer; and a second semiconductor chip commonly mounted over the first semiconductor chip and the second layer. | 2016-03-03 |
| 20160064359 | STACK PACKAGES AND METHODS OF FABRICATING THE SAME - Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip. | 2016-03-03 |
| 20160064360 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad. | 2016-03-03 |
| 20160064361 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin. | 2016-03-03 |
| 20160064362 | Semiconductor Device Package and Methods of Packaging Thereof - An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped region being part of a first semiconductor device. The method includes forming an opening from the first major surface into the semiconductor substrate and attaching a semiconductor die to the semiconductor substrate at the opening. The semiconductor die includes a second semiconductor device, which is a different type of semiconductor device than the first semiconductor device. The method further includes forming a chip isolation region on sidewalls of the opening and surrounding the second semiconductor device, and singulating the semiconductor substrate. | 2016-03-03 |
| 20160064363 | MICRO ASSEMBLED HYBRID DISPLAYS AND LIGHTING ELEMENTS - The disclosed technology relates generally hybrid displays with pixels that include both inorganic light emitting diodes (ILEDs) and organic light emitting diodes (OLEDs). The disclosed technology provides a hybrid display that uses a mixture of ILEDs and OLEDs in each pixel. In certain embodiments, each pixel in the hybrid display includes a red ILED, a blue ILED, and a green OLED. In this instance, the OLED process would not require a high resolution shadow mask, thereby enhancing the manufacturability of OLEDs for larger format displays. Additionally, the OLED process in this example would not require any fine lithography. The OLED subpixel (e.g., green subpixel) can be larger and the ILEDs can be small (e.g., micro-red and micro-blue ILEDs). The use of small ILEDs allows for other functions to be added to the pixel, such as micro sensors and micro integrated circuits. | 2016-03-03 |
| 20160064364 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a display device including features that suppresses threshold voltage variation among the oxide thin-film transistors of an array substrate and a method for manufacturing the same. The display device includes a first COG block including sub-pixels configured to receive an output signal from a first drive integrated circuit positioned in a first COG area; a second COG block including sub-pixels configured to receive an output signal from a second drive integrated circuit positioned in a second COG area; and an equipotential line extended from the first COG area to the second COG area. | 2016-03-03 |
| 20160064365 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate having a lower substrate and an upper substrate disposed on the lower substrate, the package substrate having a first cavity, a first semiconductor chip disposed in the first cavity, and a chip stack disposed to partially cover the first cavity on the upper substrate. | 2016-03-03 |
| 20160064366 | SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER - A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips. | 2016-03-03 |
| 20160064367 | CHIP PACKAGES AND METHODS OF MANUFACTURE THEREOF - Chip packages and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a chip package may include: providing a support structure including: a base; and a stage pivotably attached to the base, the stage having a surface facing away from the base; attaching a first die having at least one second die disposed thereon to the surface of the stage; pivotably tilting the stage; and after the pivotably tilting, dispensing an underfill over the first die and adjacent to the least one second die, the underfill flowing through a first standoff gap disposed between the first die and the at least one second die. | 2016-03-03 |
| 20160064368 | PATTERN DATA CREATING METHOD, TEMPLATE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a pattern data creating method includes a calculation process, a determination process, and a correction process. In the calculation process, it is calculated a stress distribution of stresses that are applied to a template when a distance between the template and a substrate on which resist are disposed is predetermined, the template including a template pattern. In the determination process, it is determined whether or not there is a stress concentration spot in the template pattern at which a stress value larger than a predetermined criterion value is to appear. If the stress concentration spot is present, in the correction process, it is a corrected pattern data of the template pattern such that the stress value at the stress concentration spot becomes a stress value not larger than the predetermined criterion value. | 2016-03-03 |
| 20160064369 | SEMICONDUCTOR DEVICE - A semiconductor device includes a mesh-patterned power source wiring that supplies respective circuits with a power source voltage supplied to a plurality of locations at an outer periphery of the semiconductor device. The semiconductor device also includes a back-biasing wiring supplying, to a semiconductor substrate, a substrate voltage that controls a threshold voltage of a semiconductor element. The back-biasing wiring includes a upper layer mesh wiring that receives a supply of a substrate voltage, and a lower layer mesh wiring that is provided in a different wiring layer from the upper layer mesh wiring. The outer peripheries of the upper layer mesh wiring and the lower layer mesh wiring are connected to each other through plural vias. | 2016-03-03 |
| 20160064370 | ELECTROSTATIC DISCHARGE PROTECTION - A device comprising an electrostatic discharge protection structure, an ion sensitive field effect transistor (ISFET) having a floating gate, and a sensing layer located above the floating gate. The device is configured such that the electrical impedance from the sensing layer to the electrostatic discharge protection structure is less than the electrical impedance from the sensing layer to the floating gate. The device can be fabricated in a standard CMOS process | 2016-03-03 |
| 20160064371 | NON-PLANAR ESD DEVICE FOR NON-PLANAR OUTPUT TRANSISTOR AND COMMON FABRICATION THEREOF - Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit. | 2016-03-03 |
| 20160064372 | ESD SNAPBACK BASED CLAMP FOR FINFET - There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate. | 2016-03-03 |
| 20160064373 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor. | 2016-03-03 |
| 20160064374 | BIASED ESD CIRCUIT - This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground. | 2016-03-03 |
| 20160064375 | SEMICONDUCTOR DEVICES HAVING HIGH-RESISTANCE REGION AND METHODS OF FORMING THE SAME - Provided are an electrostatic discharge (ESD) protection device having a high-resistance region and a method of forming the same. The device includes a well on a substrate. A first impurity region is formed on the well and connected to an input/output pad. A second impurity region is formed on the well, spaced apart from the first impurity region, and connected to a ground (Vss). A third impurity region is formed on the well, spaced apart from the first impurity region, and connected to the ground (Vss). An isolation layer is formed between the first impurity region and the second impurity region. A high-resistance region, which directly contacts the first impurity region and the well and has a resistance higher than the first impurity region, is formed between the first impurity region and the isolation layer. The well and the third impurity region include first conductive type impurities. The first impurity region and the second impurity region include second conductive type impurities different from the first conductive type impurities. | 2016-03-03 |
| 20160064376 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode. | 2016-03-03 |
| 20160064377 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH PROTECTION LAYER - A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate and an isolation structure formed on the substrate. The first fin structure is embedded in the isolation structure, and the first fin structure has an upper portion and a lower portion. The upper portion is above the isolation structure, and the lower portion is below the isolation structure. The FinFET device structure also includes a protection layer formed on the sidewalls of the lower portion of the first fin structure. | 2016-03-03 |
| 20160064378 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other. | 2016-03-03 |
| 20160064379 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHODS THEREOF - A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure overlying on at least one of the plurality of fins; forming a barrier layer covering top and side surfaces of the gate structures, and top and side surfaces of the plurality of fins; performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer to form a remaining barrier layer and to cause the top surfaces of the fins to be flat after subsequent etching processes; performing an etch-back process on the passive layer to form passive sidewalls on side surfaces of the portions of the remaining barrier on the side surfaces of the fins; and removing portions of the remaining barrier layer on the top surfaces of the fins by a wet etching process using the passive sidewalls as an etching mask. | 2016-03-03 |
| 20160064380 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed. | 2016-03-03 |
| 20160064381 | Fin-Like Field Effect Transistor (FinFET) Device And Method Of Manufacturing Same - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer. | 2016-03-03 |
| 20160064382 | SELECTIVE FuSi GATE FORMATION IN GATE FIRST CMOS TECHNOLOGIES - The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process. | 2016-03-03 |
| 20160064383 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased. | 2016-03-03 |
| 20160064384 | MEMORY DEVICE INCLUDING SELECTIVELY DISPOSED LANDING PADS EXPANDED OVER SIGNAL LINE - Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads. | 2016-03-03 |
| 20160064385 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EMBEDDED CAPACITOR - A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device also includes a contact plug in the dielectric layer, and a recess extending from a surface of the dielectric layer towards the contact plug. The semiconductor device further includes a capacitor element in the recess and electrically connected to the contact plug. | 2016-03-03 |
| 20160064386 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration. | 2016-03-03 |
| 20160064387 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises a first fin type active pattern formed on a substrate and extending in a first direction and including first to third parts. At least one dimension of the third part measuring less than the corresponding dimension of the first part. A gate electrode extending in a second direction different from the first direction is at least partially formed on the first part of the fin type active pattern. A first source/drain is formed on the third part of the fin type active pattern. | 2016-03-03 |
| 20160064388 | NONVOLATILE MEMORY DEVICE - The nonvolatile memory device includes a plurality of memory cells being stacked in a direction perpendicular to a substrate. A string select transistor is connected between the memory cells and a bit line. A string select line is connected to the string select transistor. A one directional device is connected between the substrate and the string select line and configured to transmit a bias voltage from the substrate toward the string select line in an erase operation. | 2016-03-03 |
| 20160064389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode. | 2016-03-03 |
| 20160064390 | NON-VOLATILE MEMORY WITH IMPROVED SENSING WINDOW - A semiconductor device may include: a substrate. First and second gate electrode patterns are disposed on first and second fin type active patterns. The first and second fin type active patterns include a first channel region disposed between a first impurity region and a second impurity region. The second gate electrode pattern crosses a first gate-separating region included in the second fin type active region. The first gate-separating region includes a trench and an embedded insulator filling at least a portion of the trench. | 2016-03-03 |
| 20160064391 | DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING A FERROELECTRIC CAPACITOR - A memory cell includes a capacitor that includes a first metal layer and a second metal layer. The capacitor includes a ferroelectric layer disposed between the first metal layer and the second metal layer. The ferroelectric layer is a single layer of a bi-stable asymmetric crystalline material. | 2016-03-03 |
| 20160064392 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a floating gate electrode; a second gate insulating film; and a control gate electrode. The semiconductor layer is provided on a substrate and extends in a certain direction. The first gate insulating film is formed on the semiconductor layer. The floating gate electrode is formed along the semiconductor layer on the first gate insulating film. The second gate insulating film is formed on an upper surface of the floating gate electrode. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. The control gate electrode comprises: a first portion intersecting the certain direction at a first angle; and a second portion intersecting the certain direction at a second angle different from the first angle. | 2016-03-03 |
| 20160064393 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line. | 2016-03-03 |
| 20160064394 | Integrated Circuit for High-Voltage Device Protection - Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET. | 2016-03-03 |
| 20160064395 | SEMICONDUCTOR DEVICE - According to this embodiment, a semiconductor device includes a semiconductor substrate, element formation regions that are formed in a line-and-space pattern in a surface layer portion of the semiconductor substrate to extend in a first direction, a coupling portion that is formed in the surface layer portion of the semiconductor substrate to couple the element formation regions adjacent to each other in a second direction intersecting the first direction, a source line that is disposed in an upper layer of the semiconductor substrate through an insulating film, a source line contact, having a circular shape or an elliptical shape, that is provided to electrically connect a source region pattern and the source lines by passing through the insulating film, when a region including the coupling portion and portions of the element formation regions coupled by the coupling portion is set to the source region pattern, and a bit line contact, having a circular shape or an elliptical shape, that is provided to electrically connect the element formation regions and a wiring layer located in an upper layer by passing through the insulating film. | 2016-03-03 |
| 20160064396 | FLASH MEMORY FABRICATION METHOD - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device. | 2016-03-03 |
| 20160064397 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, using a control gate electrode and a memory gate electrode which are formed over a semiconductor substrate as a mask, n-type impurity ions are implanted from a direction perpendicular to a main surface of the semiconductor substrate. Then, using the control gate electrode, the memory gate electrode, and first and second sidewall spacers as a mask, other n-type impurity ions are implanted from a direction inclined relative to the direction perpendicular to the main surface of the semiconductor substrate. | 2016-03-03 |
| 20160064398 | INTEGRATED CIRCUITS WITH FINFET NONVOLATILE MEMORY - Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection. | 2016-03-03 |
| 20160064399 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral circuit region arranged on a semiconductor substrate. In the peripheral circuit region, a stacked body including a tunnel insulating film, a floating gate electrode film, an inter-electrode insulating film, and a control gate electrode film stacked in this order, a first insulating film and a second insulating film are stacked on the semiconductor substrate. The peripheral circuit region includes a contact region where the stacked body removed a film above the floating gate electrode film, the first insulating film and the second insulating film are stacked. The peripheral circuit region includes contact provided within a region where the contact region is formed, and one end of the contact is in the second insulating film, and the other end of the contact is in the floating gate electrode film. | 2016-03-03 |
| 20160064400 | SEMICONDUCTOR DEVICE - To provide a memory cell for storing multilevel data that is less likely to be affected by variations in characteristics of transistors and that is capable of easily writing multilevel data in a short time and accurately reading it out. In writing, a current corresponding to multilevel data is supplied to the transistor in the memory cell and stored as the gate-drain voltage of the transistor in the memory cell. In reading, a current is supplied to the transistor in the transistor with the stored gate-drain voltage, and the multilevel data is obtained from the voltage supplied to generate a current that is equal to the current. | 2016-03-03 |
| 20160064401 | Method to Control the Common Drain of a Pair of Control Gates and to Improve Inter-Layer Dielectric (ILD) Filling Between the Control Gates - A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided. | 2016-03-03 |
| 20160064402 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element. | 2016-03-03 |
| 20160064403 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention makes it possible to improve the reliability of a semiconductor device. | 2016-03-03 |
| 20160064404 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer. | 2016-03-03 |
| 20160064405 | METHOD FOR FORMING INSULATOR FILM ON METAL FILM - According to one embodiment, forming a metal film on an underlying layer, and depositing an oxide film on the metal film using plasma of a mixed gas induced above the metal film. The mixed gas includes a gaseous material source, a gaseous oxidant, and a gaseous reductant. | 2016-03-03 |
| 20160064406 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers. | 2016-03-03 |
| 20160064407 | SEMICONDUCTOR DEVICES HAVING GATE STACK PORTIONS THAT EXTEND IN A ZIGZAG PATTERN - A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions spaced apart from each other in the first direction, the gate stack portions including gate electrodes spaced apart from each other in a direction perpendicular to the an upper surface of the substrate and having lateral surfaces extended in the second direction to have a zigzag form, channel regions penetrating through the gate stack portions and disposed to form columns having a zigzag form in the second direction, at least two channel regions among the channel regions being linearly arranged in the first direction within the respective gate stack portion, and a source region disposed between the gate stack portions adjacent to each other and extended in the second direction to have a zigzag form. | 2016-03-03 |
| 20160064408 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device comprises: a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer; a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a side surface of the charge accumulation layer. The inter-layer insulating layer comprises: a first silicon oxide layer; a first metal oxide layer; and a first silicon nitride layer. The first metal oxide layer is formed on a first surface facing the conductive layer, of the first silicon oxide layer. The first silicon nitride layer is formed on the first surface via the first metal oxide layer. | 2016-03-03 |
| 20160064409 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a plurality of gate electrodes stacked in a first direction, a channel portion facing the gate electrodes and extending in the first direction, and first and second charge storage layers between the gate electrode and the channel portion in a second direction crossing the first direction, wherein the second charge storage layer has portions that are between the gate electrodes in the first direction. | 2016-03-03 |
| 20160064410 | U-SHAPED COMMON-BODY TYPE CELL STRING - A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source. | 2016-03-03 |
| 20160064411 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS INCLUDING THE SAME - A thin film transistor substrate and a display apparatus including the same are provided. The thin film transistor substrate includes a plurality of pixels each including: a first transistor for receiving a data signal in response to a first gate control signal; a second transistor for outputting a driving current according to the data signal applied to a gate electrode of the second transistor; and a third transistor for initializing a gate node connected to the gate electrode of the second transistor in response to a second gate control signal, wherein first electrodes of the third transistors of at least some adjacent pixels of the plurality of pixels are connected to the gate node, and second electrodes thereof are connected to a shared transistor that applies an initialization voltage to the second electrodes. | 2016-03-03 |
| 20160064412 | DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A display substrate including a lower common electrode disposed on a substrate, an insulating layer disposed on the lower common electrode, a gate pattern including a gate electrode disposed on the insulating layer and a common electrode contact part and a direct contact part spaced apart from the gate electrode, a gate insulating layer disposed on the gate pattern, a semiconductor layer disposed on the gate insulating layer, an etch stopping layer disposed on the gate insulating layer, source and drain electrodes disposed on the etch stopping layer, pixel part extending from the source and drain electrodes, a first conductive layer connected to the common electrode contact part, a second conductive layer connected to the direct contact part, and a passivation layer disposed on the source and drain electrodes, the first conductive layer, and the second conductive layer. | 2016-03-03 |
| 20160064413 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - The present invention provides an arrayed substrate, a method for manufacturing the same and a display device. It relates to a field of display technology. The short-circuit defect between the lead wires may be avoided while reducing a spacing between the adjacent two lead lines in a limited space for wiring. The array substrate comprises a plurality of criss-cross gate lines and data lines within a display area, and the array substrate further comprises a first short-circuiting ring and a second short-circuiting ring within a non-display area, and first data lead wires and second data lead wires connected electrically with the first short-circuiting ring and the second short-circuiting ring respectively; the first data lead wires are provided in the same layer and made from the same material as the gate lines for connecting electrically the first short-circuiting ring with first data lines of the data lines; the second data lead wires are provided in the same layer and made from the same material as the data lines for connecting electrically the second short-circuiting ring with second data lines of the data lines; wherein the first data lines are interleaved with the second data lines. | 2016-03-03 |
| 20160064414 | DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed are a display substrate, of which productivity is improved by decreasing five mask (M) processes utilized for fabricating the display substrate used in a liquid crystal display device in a horizontal field (Plane to Line Switching (PLS)) mode to four mask processes, and a method of fabricating the same. | 2016-03-03 |
| 20160064415 | ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF, DISPLAY PANEL AND DISPLAY APPARATUS - An array substrate and a fabricating method thereof, a display panel and a display apparatus are disclosed. The array substrate includes a base substrate and a gate metal layer, a gate insulating layer, an active layer, a source-drain electrode metal layer, a passivation layer and a common electrode layer which are sequentially formed on the base substrate, as well as a pixel electrode layer which is positioned between the active layer and the source-drain electrode metal layer or between the source-drain electrode metal layer and the passivation layer; the gate metal layer including a gate electrode and a common electrode line. The pixel electrode layer or the source-drain electrode metal layer includes a connecting electrode, the connecting electrode being electrically connected with the common electrode line through a first via hole in the gate insulating layer, and the connecting electrode being electrically connected with the common electrode of the common electrode layer through a second via hole in the passivation layer. | 2016-03-03 |
| 20160064416 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane. | 2016-03-03 |
| 20160064417 | BULK AND DIELECTRIC-ISOLATED FINFET-BASED INTEGRATED CIRCUIT - A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed. | 2016-03-03 |
| 20160064418 | ARRAY SUBSTRATE AND METHOD FOR FABRICATING ARRAY SUBSTRATE, AND DISPLAY DEVICE - The present invention discloses an array substrate, a method for fabricating an array substrate, and a display device, the array substrate includes: a base substrate; a TFT, a gate line, a data line and a pixel electrode formed on the base substrate, the TFT includes: a bottom gate, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate, a gate isolation layer and a source electrode and a drain electrode sequentially formed on the base substrate; wherein, the source electrode and the drain electrode are in contact with the active layer through a first via hole and a second via hole passing through the gate isolation layer and the second insulating layer, respectively; the pixel electrode is in contact with the drain electrode. | 2016-03-03 |
| 20160064419 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE - The present invention discloses an array substrate, a method of manufacturing the array substrate and a display device. Since the respective surfaces of the sources, the drains and the data lines are clad by the respective insulating films, in formation of the patterns of the pixel electrodes above the insulating films by using a patterning process, the insulating films can prevent the sources and the data lines provided under them from being corroded by an etching agent when an etching process is performed to form the patterns of the pixel electrodes, so as to avoid an influence on display quality of a display panel. Furthermore, since the insulating films are formed by curing the insulating material, instead of the photoresist, remained on the patterns of the sources, the drains and the data lines when forming the patterns of the sources, the drains and the data lines by using the insulating material (replacing the photoresist), formation of the insulating films will not increase the number of masks, and a step of peeling off the insulating material is omitted. Furthermore, the respective connecting portions electrically connects the respective drains with the respective pixel electrodes through the respective first via holes A located above the respective drains and passing through the respective insulating films, so that a normal display function of the display panel can be ensured. | 2016-03-03 |
| 20160064420 | DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A display substrate and its fabricating method have been disclosed. In a horizontal-field-mode liquid crystal display device, while maintaining five mask processes, additional direct contact has been formed to implement a narrow bezel. | 2016-03-03 |
| 20160064421 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE USING THE SAME - A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a base substrate, a first TFT having a polycrystalline semiconductor and disposed on the base substrate, and a second TFT having an oxide semiconductor and disposed on the first TFT. The second TFT overlaps at least a portion of the first TFT in a plan view. | 2016-03-03 |
| 20160064422 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having high electric characteristics and in which a capacitor is efficiently formed even if the semiconductor device has a miniaturized structure. In a top-gate (also referred to as staggered) transistor using an oxide semiconductor film as its active layer, a source electrode and a drain electrode has a two-layer structure (a first electrode film and a second electrode film). Then, a capacitor is formed using a film formed using a material and a step similar to those of the first electrode film, a gate insulating film, and a gate electrode. Accordingly, the transistor and the capacitor can be formed through the same process efficiently. Further, the second electrode is connected onto the oxide semiconductor film between a first electrode and a channel formation region of the transistor. Accordingly, resistance between source and drain electrodes can be reduced; therefore, electric characteristics of the semiconductor device can be improved. | 2016-03-03 |
| 20160064423 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device ( | 2016-03-03 |
| 20160064424 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction. | 2016-03-03 |
| 20160064425 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer. | 2016-03-03 |
| 20160064426 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode. | 2016-03-03 |
| 20160064427 | Display Device and Method of Manufacturing the Same - A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel unlike the related art and thus thickness and manufacturing cost are reduced. | 2016-03-03 |
