| 09th week of 2016 patent applcation highlights part 62 |
| Patent application number | Title | Published |
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| 20160064028 | INFORMATION PROCESSING DEVICE, INFORMATION RECORDING MEDIUM, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing device includes: a data processing unit which executes a reproduction process of recorded data of a disc, in which the data processing unit reads disc type information that is recorded on the disc, and ascertains a recorded data configuration of the disc based on the disc type information that is read, and executes data reading-out and reproduction processes according to a reading-out rate corresponding to the ascertained recorded data configuration. | 2016-03-03 |
| 20160064029 | APPARATUS WITH FIRST AND SECOND CLOSE POINTS ON MEDIA-FACING SURFACE OF MAGNETIC HEAD - A magnetic head includes a read transducer and a write transducer at a media-facing surface of the magnetic head. The magnetic head includes at least one heater that causes heat deformation at the media-facing surface in response to different first and second energizing currents. The first energizing current results in a first close point between the media-facing surface and a recording medium. The second energizing current results in a second close point between the media-facing surface and the recording medium. The second close point is at a different location in the media-facing surface than the first close point. | 2016-03-03 |
| 20160064030 | SHINGLED MAGNETIC RECORDING DATA STORE - Implementations disclosed herein provide a method comprising storing data in a two level key-value data store in an SMR storage device, wherein a first level of the data store comprises a journal of incoming host operations and a second level of the data store comprises a plurality of ordered data stores, ordered based on a predetermined ordering criterion. | 2016-03-03 |
| 20160064031 | SYSTEMS AND METHODS FOR ATOMIC FILM DATA STORAGE - The present disclosure provides systems and methods associated with data storage using atomic films, such as graphene, boron nitride, or silicene. A platter assembly may include at least one platter that has one or more substantially planar surfaces. One or more layers of a monolayer atomic film, such as graphene, may be positioned on a planar surface. Data may be stored on the atomic film using one or more vacancies, dopants, defects, and/or functionalized groups (presence or lack thereof) to represent one of a plurality of states in a multi-state data representation model, such as a binary, a ternary, or another base N data storage model. A read module may detect the vacancies, dopants, and/or functionalized groups (or a topographical feature resulting therefrom) to read the data stored on the atomic film. | 2016-03-03 |
| 20160064032 | System And Method For Semantic Trick Play - A semantic based trick play method and system in a media player is provided in which a semantic trick play command is received from a user while the user is experiencing a current content of a media item. Metadata is detected with respect to a current playback position of the media item, and at least one further playback position is determined in the current content of the media item or a related content in another media item. The further playback position is semantically related to the metadata of the current playback position. Playback is then moved to the at least one further playback position, so that the user experiences a media content of the at least one further playback position. | 2016-03-03 |
| 20160064033 | PERSONALIZED AUDIO AND/OR VIDEO SHOWS - One or more techniques and/or systems are provided for providing personalized audio shows and/or video shows. For example, content corresponding to an interest of a user may be identified (e.g., a videogame article, a home renovation blog, etc.). One or more actor templates within a natural language template set may be applied to portions of the content to create audio snippets. For example, text-to-speech synthesis functionality may use a first actor template to convert the videogame article into a videogame snippet and may use a second actor template to convert the home renovation blog into a home renovation snippet. The videogame snippet and the home renovation snippet may be used to generate an audio show (e.g., a dialogue between a first actor persona, defined within the first actor template, reading the videogame snippet and a second actor persona, defined within the second actor template, reading the home renovation snippet). | 2016-03-03 |
| 20160064034 | VIDEO PREVIEW CREATION WITH AUDIO - Providing a method for creating and displaying portions of videos called video previews. The video previews may be associated with audio, such that when the video previews are activated, the audio may play with the video preview. When multiple video previews are organized to play as a playable group or composite of video previews, a corresponding composite audio file can play in response to an activation of the composite. | 2016-03-03 |
| 20160064035 | MULTI-SOURCE VIDEO INPUT - A method of merging video files into a consolidated video file includes receiving, by a computer device, plural video files from plural video capture devices. The method also includes determining, by the computer device, an overlapping portion of the plural video files. The method additionally includes creating, by the computer device, a thumbnail image associated with the determined overlapping portion. The method further includes creating, by the computer device, a single video file from the plural video files. The method also includes displaying, by the computer device, the single video file and a thumbnail image. | 2016-03-03 |
| 20160064036 | CLOUD INFORMATION STORAGE, ACCESS, AND SECURITY - Devices and methods for cloud based management of multi-media files and/or associated data files are presented. Methods for using the device(s) to implement different information management techniques for managing information obtained (e.g., recorded) by a plurality of recording devices are also described. A comprehensive use of multiple distinct surveillance systems in a coordinated manner is described. A set of surveillance devices configured for use by one or more law enforcement agencies or other government agencies may upload and share information using cloud information, storage, access, and security methods. Maintaining information using cloud based techniques allows for sharing access (securely and remotely) without redundant copies of information on physical media and may reduce bandwidth transmission requirements. Further, requirements for both chain of custody of evidence and confidentiality regarding digitally recorded evidence may be complied with. | 2016-03-03 |
| 20160064037 | VIDEO APPARATUS AND CONTROL METHOD OF VIDEO APPARATUS - One embodiment provides a video apparatus including: a recorder configured to record a video content including caption information; a setting register configured to set search parameters including a keyword; and a chapter generator configured to extract chapters each including an interval in which the keyword appears in a caption or captions from the video content. The chapter generator extracts the chapters by setting a start point of a period in which a caption containing the keyword is to be displayed first as a chapter start point, and setting a point that comes first after the end of display of a tail caption containing the keyword among a point when a silent interval starts, a point when a prescribed time elapses, and an end point of a packet concerned of the video content consisting of plural packets as a chapter end point. | 2016-03-03 |
| 20160064038 | METHOD FOR THE REPRODUCTION OF A FILM - The present invention relates to a method for the reproduction, through an audio/visual means, of a film and an apparatus for the reproduction of the same. More particularly, the method according to the present invention allows more viewings of the same film such that the film itself is automatically composed as to be different at each viewing. The method for the reproduction of a film is finalized to the creation of a “multifilm”, i.e. a film that changes its plot in every reproduction. | 2016-03-03 |
| 20160064039 | Thumbnail Generation - Thumbnail generation techniques are described. In one or more implementations, at least one thumbnail is generated by a device from video received at the device. The generation of the at least one thumbnail includes decoding at least one I-picture included in the video when present that is to serve as a basis for the at least one thumbnail and skipping decoding of non-I-pictures that describe differences in relation to the at least one I-picture included in the video such that the non-I-pictures are not utilized in the generating of the at least one thumbnail. For robust thumbnail generation, when at least one I-picture has not been identified in the video in a predetermined time, falling back to decoding subsequent non-I-pictures in the video to generate the thumbnail from non-I-pictures. | 2016-03-03 |
| 20160064040 | SYSTEMS AND METHODS FOR INSERTION OF AN INFORMATION HANDLING RESOURCE IN AN INFORMATION HANDLING SYSTEM - In accordance with embodiments of the present disclosure, a system may include a structural base, a handle mechanically coupled to the structural base, and a cam element mechanically coupled to the handle. The handle may be configured to translate between an open position and a closed position and vice versa relative to the structural base. The cam element may be configured to mechanically couple to a retention structure for retaining the system when the handle is in the closed position and during at least a portion of the translation of the handle, move at least partially in a direction opposite to that of the handle in response to translation of the handle. | 2016-03-03 |
| 20160064041 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate; a memory cell array including a plurality of memory cells stacked on the substrate; an inter-layer insulating layer provided on the memory cell array; and a first control circuit. The first control circuit includes a first transistor and first semiconductor layer, a number of a grain boundary of the first semiconductor layer is not less than a number of a grain boundary of the substrate, and the first control circuit is provided on the inter-layer insulating layer and electrically connected to the memory cells. | 2016-03-03 |
| 20160064042 | SELECTING A VOLTAGE SENSE LINE THAT MAXIMIZES MEMORY MARGIN - A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair. | 2016-03-03 |
| 20160064043 | SELECTING A VOLTAGE SENSE LINE THAT MAXIMIZES MEMORY MARGIN - A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes sequentially passing a voltage signal from each of the voltage sense line pairs to the voltage feedback line, and, for each voltage sense line pair, calculating a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair. Still further, the method includes identifying the voltage sense line pair that provides the greatest memory margin, and then regulating voltage to the memory system responsive to the identified voltage sense line pair. | 2016-03-03 |
| 20160064044 | MEMORY WITH LOCAL-/GLOBAL BIT LINE ARCHITECTURE AND ADDITIONAL CAPACITANCE FOR GLOBAL BIT LINE DISCHARGE IN READING - There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group. | 2016-03-03 |
| 20160064045 | APPARATUSES AND METHODS FOR STORING A DATA VALUE IN MULTIPLE COLUMNS - An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector. | 2016-03-03 |
| 20160064046 | IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY - A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state. | 2016-03-03 |
| 20160064047 | COMPARISON OPERATIONS IN MEMORY - The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel. | 2016-03-03 |
| 20160064048 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 2016-03-03 |
| 20160064049 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A semiconductor device includes a first data input/output unit storing first internal input data in a first cell block in response to a first shift data strobe signal generated by shifting a first data strobe signal in a test mode, a second data input/output unit storing second internal input data in a second cell block in response to a second shift data strobe signal generated by shifting a second data strobe signal in the test mode, and a connector electrically coupling the first data input/output unit to the second data input/output unit in the test mode. | 2016-03-03 |
| 20160064050 | SEMICONDUCTOR DEVICE - A semiconductor device includes a spin array in which a plurality of memory cells are disposed in a matrix configuration, a group of a predetermined number of memory cells is collected in units of spin units, and a plurality of the spin units are disposed with an adjacency; a word line provided in correspondence with rows of the memory cells; a bit line pair provided in correspondence with columns of the memory cells; a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to a word line and simultaneously activate a plurality of word lines; and a bit line driver configured to subject a plurality of memory cells, of the memory cells connected to bit line pairs and arrayed in a column direction, activated by the plurality of the word lines to a write operation or a read operation. | 2016-03-03 |
| 20160064051 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level. | 2016-03-03 |
| 20160064052 | SINGLE NODE POWER MANAGEMENT FOR MULTIPLE MEMORY DEVICES - Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described. | 2016-03-03 |
| 20160064053 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING DEVICE - A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells. | 2016-03-03 |
| 20160064054 | Double Pumped Memory Techniques - A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal. | 2016-03-03 |
| 20160064055 | EVENT CONTROLLED DECODING CIRCUIT - A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits. | 2016-03-03 |
| 20160064056 | SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other. | 2016-03-03 |
| 20160064057 | ADDRESS ALIGNER AND MEMORY DEVICE INCLUDING THE SAME - An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal. | 2016-03-03 |
| 20160064058 | CONFIGURATION AND TESTING FOR MAGNETORESISTIVE MEMORY - Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation. | 2016-03-03 |
| 20160064059 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element, a sense amplifier connected to one side of the memory cell, and a write driver connected to the other side of the memory cell. A write current flows between the sense amplifier and the write driver in a write operation. | 2016-03-03 |
| 20160064060 | METHOD OF FORMING A MAGNETIC DOMAIN WALL IN A NANOWIRE - A method of forming a domain wall in a nanowire, the method comprising the steps of: a) providing a conductive strip orthogonally to a nanowire adjacent a free end of the nanowire, the nanowire having an original magnetization direction; b) pulsing a current through the conductive strip to generate an Oersted field having a direction opposite to the original magnetization direction such that magnetization direction of a portion of the nanowire transversed by the conductive strip becomes opposite to the original magnetization direction, the domain wall being generated in the nanowire at a location defined between the portion of the nanowire transversed by the conductive strip and a second end of the nanowire, wherein no external magnetic field is provided during formation of the domain wall. | 2016-03-03 |
| 20160064061 | SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period. | 2016-03-03 |
| 20160064062 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH OPERATING METHOD - A semiconductor memory device includes a plurality of normal memory mats, one or more of which includes a redundancy word line, a dummy memory mat suitable for performing an operation with an edge memory mat as a pair during an active operation, wherein the edge memory mat is one among the plurality of normal memory mats disposed at an edge, and a refresh control section suitable for controlling refresh operations for the plurality of normal memory mats and the dummy memory mat, and restricting activation of the redundancy word line during a refresh operation for the edge memory mat. | 2016-03-03 |
| 20160064063 | SEMICONDUCTOR DEVICE - A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors. | 2016-03-03 |
| 20160064064 | POWER UP OF SEMICONDUCTOR DEVICE HAVING A TEMPERATURE CIRCUIT AND METHOD THEREFOR - A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit. | 2016-03-03 |
| 20160064065 | APPARATUSES AND METHODS FOR MULTI-MEMORY ARRAY ACCESSES - Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to the pair of input/output lines. The first array is configured to provide data to and receive data from the pair of input/output lines. The example apparatus further includes an access block coupled to the pair of input/output lines. The access block is configured to access a second array responsive to memory access control signals directed to the second array. The access block is configured provide data between the second array and the pair of main input/output lines responsive to the access of the second array. | 2016-03-03 |
| 20160064066 | MAINTENANCE OPERATIONS IN A DRAM - A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. | 2016-03-03 |
| 20160064067 | THREE-PORT BIT CELL HAVING INCREASED WIDTH - An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm). | 2016-03-03 |
| 20160064068 | SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE - A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor. | 2016-03-03 |
| 20160064069 | LOW VOLTAGE SRAM - In some embodiments, an SRAM includes an array of storage cells arranged as rows and columns, each storage cell of the array of storage cells includes a first type of transistor and a second type of transistor. The SRAM also includes a memory controller configured to detect a temperature of the SRAM and apply a body bias to the first type of transistor in each of the storage cells and refrain from an application of a body bias to the second type of transistor in each of the storage cells. | 2016-03-03 |
| 20160064070 | LOW POWER SRAM - A static random access memory (SRAM) that includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to identify consecutive reads from storage cells accessed via a same one of the word lines and precharge the bit lines no more than once during the consecutive reads. | 2016-03-03 |
| 20160064071 | SOLID STATE DRIVE WITH HYBRID STORAGE MODE - A solid state drive (SSD) with a hybrid storage mode includes a flash memory, and a data processing module in information communication with the flash memory. The flash memory includes a first storage sector that stores data by a first potential storage mode, and a second storage sector that stores data by a second potential storage mode. The first storage sector corresponds to physical block addresses P | 2016-03-03 |
| 20160064072 | 3D VARIABLE RESISTANCE MEMORY DEVICE HAVING JUNCTION FET AND DRIVING METHOD THEREOF - A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer. | 2016-03-03 |
| 20160064073 | RESISTANCE CHANGE TYPE MEMORY DEVICE - A resistance change type memory device according to an embodiment includes a plurality of memory elements; a first to a fourth bit lines connected to the plurality of memory elements, respectively; a first to a fourth transistors connected at their one ends to the first to the fourth bit lines, respectively; a fifth transistor connected at its one end to the other ends of the first and second transistors; a sixth transistor connected at its one end to the other ends of the third and fourth transistors; and a fifth bit line connected to the other ends of the fifth and sixth transistors. | 2016-03-03 |
| 20160064074 | SEMICONDUCTOR DEVICE AND INFORMATION READING METHOD - A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states. | 2016-03-03 |
| 20160064075 | MEMORY DEVICE - A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array. | 2016-03-03 |
| 20160064076 | Method and Apparatus for Decoding Memory - A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller. | 2016-03-03 |
| 20160064077 | MEMORY CELL WITH NON-VOLATILE DATA STORAGE - The invention concerns a memory cell comprising first and second resistive elements ( | 2016-03-03 |
| 20160064078 | SYSTEMS, METHODS AND DEVICES FOR PROGRAMMING A MULTILEVEL RESISTIVE MEMORY CELL - Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses. | 2016-03-03 |
| 20160064079 | THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY AND DRAM MEMORY DEVICES ON A SINGLE SUBSTRATE - A three-dimensional NAND stacked non-volatile memory array and a DRAM memory array are provided. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are integrated on a single substrate. | 2016-03-03 |
| 20160064080 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING DEVICE - In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient. | 2016-03-03 |
| 20160064081 | SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE INCLUDING THE SAME - A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (CAM) block, a CAM state information storage block suitable for storing information on whether the setting information loaded on the CAM block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the CAM block is requested, the control logic selectively performs the reloading operation based on the information stored in the CAM state information storage block. | 2016-03-03 |
| 20160064082 | SEMICONDUCTOR MEMORY CELL AND DRIVER CIRCUITRY WITH GATE OXIDE FORMED SIMULTANEOUSLY - The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates. | 2016-03-03 |
| 20160064083 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device of the inventive concept includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line. | 2016-03-03 |
| 20160064084 | Programming Memory With Reduced Short-Term Charge Loss - Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed. | 2016-03-03 |
| 20160064085 | MEMORY DEVICE HAVING A DIFFERENT SOURCE LINE COUPLED TO EACH OF A PLURALITY OF LAYERS OF MEMORY CELL ARRAYS - A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer. | 2016-03-03 |
| 20160064086 | CIRCUIT AND METHOD FOR ADJUSTING SELECT GATE VOLTAGE OF NON-VOLATILE MEMORY - A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well. | 2016-03-03 |
| 20160064087 | Charge Redistribution During Erase In Charge Trapping Memory - Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole. | 2016-03-03 |
| 20160064088 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD - A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein. | 2016-03-03 |
| 20160064089 | PAGE OR WORD-ERASABLE COMPOSITE NON-VOLATILE MEMORY - A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased. | 2016-03-03 |
| 20160064090 | Charge Redistribution During Erase In Charge Trapping Memory - Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole. | 2016-03-03 |
| 20160064091 | PRECHARGE CONTROL SIGNAL GENERATOR AND SEMICONDUCTOR MEMORY DEVICE THEREWITH - A precharge control signal generator and a semiconductor memory device include a precharge control signal generating circuit which generates a precharge control signal and applies the precharge control signal to a sensing circuit, and a sensing circuit configured to precharge a bit line connected to a memory cell according to the precharge control signal and read data stored in the memory cell. The precharge control signal controls the sensing circuit so that a precharge time is adjusted according to operating temperature. | 2016-03-03 |
| 20160064092 | FLASH MEMORY WITH IMPROVED READ PERFORMANCE - A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled to one of the word lines. Each of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of a plurality of subsets of memory cells of the array. Each subset includes a plurality of memory cells. A voltage switch supplies a respective one of a plurality of aged voltages to each of the plurality of subsets of memory cells in the memory array on respective ones of the voltage supply lines. The aged voltage supplied to a first of the plurality of subsets of memory cells is different than the aged voltage supplied to a second of the plurality of subsets of memory cells. | 2016-03-03 |
| 20160064093 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell, a bit line that is electrically connected to the memory cell, a first node that is electrically connected to the bit line, a capacitive element having a first end electrically connected to the first node and a second end electrically connected to a second node, and a transistor having a gate electrically connected to the first node, a first, and a second end, the second end being electrically connected to the second node. | 2016-03-03 |
| 20160064094 | NONCONSECUTIVE SENSING OF MULTILEVEL MEMORY CELLS - Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC. | 2016-03-03 |
| 20160064095 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target. | 2016-03-03 |
| 20160064096 | NONVOLATILE MEMORY SYSTEM THAT USES PROGRAMMING TIME TO REDUCE BIT ERRORS - A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells. | 2016-03-03 |
| 20160064097 | SHIFT REGISTER UNIT, SHIFT REGISTER, DISPLAY PANEL AND DISPLAY - A shift register unit, a shift register, a display panel and a display. The shift register unit comprises a holding module for holding a high level at a pulling up (PU) node when the PU node is at a high level. With the present invention, the level at the PU node may be pulled up rapidly in a charging stage, and a PD node may also be ensured to be at a higher potential in a noise eliminating stage, which may eliminate noises at the PU node and a signal output terminal OUTPUT effectively, so that a picture quality may be enhanced. | 2016-03-03 |
| 20160064098 | SHIFT REGISTER UNIT, METHOD FOR DRIVING THE SAME, SHIFT REGISTER AND DISPLAY DEVICE - According to an embodiment of the present disclosure, a shift register unit may include: a first control module, configured to transmit a start signal to a first node; a second control module, configured to pull a potential of a second node to a potential different from a potential of the first node, under a control of a first clock signal; a carry output module, configured to output a carry signal according to the potential of the first node and the potential of the second node; and a shift output module, configured to output a shift signal according to the potential of the first node and the potential of the second node. | 2016-03-03 |
| 20160064099 | SEMICONDUCTOR DEVICE AND ITS QUALITY MANAGEMENT METHOD - A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results. | 2016-03-03 |
| 20160064100 | System and Method of Simulation for Next Generation Memory Technology - A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design, multiplying an input spectrum with each of the transfer functions to provide a plurality of results, summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal. | 2016-03-03 |
| 20160064101 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. The second semiconductor device may include a selective transfer unit configured to electrically couple the third pad group to the first pad group or to an interface unit electrically coupled to the first pad group, in response to a test mode enable signal. | 2016-03-03 |
| 20160064102 | FAST AUTO SHIFT OF FAILING MEMORY DIAGNOSTICS DATA USING PATTERN DETECTION - Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail. | 2016-03-03 |
| 20160064103 | TEST METHOD FOR MEMORY - A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once. | 2016-03-03 |
| 20160064104 | Relativistic Vacuum Diode for Shock Compression of a Substance - A relativistic vacuum diode (RVD) for shock compression of a substance to a superdense state is provided. The RVD may include an axisymmetric current-conducting vacuum chamber equipped with a demountable hatch for access into its cavity; an axisymmetric electrode assembly fixed in operative position in the central zone of the vacuum chamber; it has a plasma cathode composed of a thin central current-conducting rod and wide dielectric end element, and anode-enhancer shaped as a rod, one butt-end of which is spheroidal and serves as a target for an electron beam, at that the target cross-section area is smaller as the emitting area of said cathode's wide dielectric end element; and a such short-circuiter of reverse current in an earthed circuit of the anode-enhancer that surrounds concentrically with radial clearance said electrode assembly. | 2016-03-03 |
| 20160064105 | DOPPLER REACTIVITY AUGMENTATION DEVICE - A fast neutron nuclear reactor contains a nuclear reactor core having an array of device locations. Some device locations in the nuclear reactor core contain fissile and fertile nuclear fuel assembly devices. One or more other device locations in the nuclear reactor core contain Doppler reactivity augmentation devices that amplify the negativity of the Doppler reactivity coefficient within the nuclear reactor core. In some implementations, a Doppler reactivity augmentation device can also reduce the coolant temperature coefficient within the nuclear reactor core. Accordingly, a Doppler reactivity augmentation device contributes to a more stable nuclear reactor core. | 2016-03-03 |
| 20160064106 | Residual power of UNF - A heat transfer approach to the calculation of residual power of used nuclear fuel (UNF). This application is a conceptual design of an alternative method for determination of residual power of UNF. Our approach is based on the heat transfer analysis of UNF in the transport container with a compact storage cask. To our knowledge, the proposed method for the calculation of residual power of UNF directly in the transport container is unique and can also provide an effective tool to verify the SCALE 6 in order to ensure the safe transport of the UNF. | 2016-03-03 |
| 20160064107 | NUCLEAR POWER GENERATION SYSTEM - Disclosed is a nuclear power generation system that may secure safety even in a case where a failure occurs in a system due to natural disasters or component malfunction. | 2016-03-03 |
| 20160064108 | SYSTEM AND METHOD FOR OPTICAL CONFINEMENT OF ATOMIC PARTICLES - A system and method for controlling atomic particles using projected light are provided. In some aspects, a method includes providing a plurality of atomic particles, and generating light fields using frequencies shifted from at least one atomic resonance. The method also includes forming a two-dimensional (“2D”) optical array using the generated light fields, wherein the 2D optical array comprises linear segments of light, and projecting the 2D optical array on the plurality of atomic particles to control their respective locations in space. | 2016-03-03 |
| 20160064109 | X-RAY IMAGING APPARATUS - An X-ray imaging apparatus includes: a plurality of gratings; a detector which detects X-rays that have been emitted from an X-ray generator and have been transmitted through the plurality of gratings; a first support member which supports the plurality of gratings and the detector; a second support member which supports the X-ray generator and the first support member; and a first vibration-proof member which is disposed between the first support member and the second support member. A natural frequency of the first vibration-proof member in respect of at least vibration in a direction perpendicular to the optical axis of the X-rays is lower than 2 | 2016-03-03 |
| 20160064110 | PLASMONIC ACTIVATED GRAPHENE TERAHERTZ GENERATING DEVICES AND SYSTEMS - Plasmonic activated graphene terahertz (THz) generating devices and generator systems are described based on the excitation of plasma resonances in a graphene element or structure by mixing two signals with a THz difference frequency. The excitation process is the photo-thermo-electric effect which has been demonstrated to be operative at THz frequencies in graphene. An antenna or other electrical component or device, such as an electrical or antenna lead, couples the THz radiation out of the sub-wavelength graphene element. | 2016-03-03 |
| 20160064111 | ELECTRON BEAM IRRADIATION APPARATUS - An electron bears irradiation apparatus that emits am electron beam into a container, the electron beam irradiation apparatus including a vacuum housing constituting a vacuum chamber; an electron generator provided in the vacuum housing; a cylindrical nozzle member that is extended from the vacuum housing so as to be inserted into the container and has exit windows on the distal end of the nozzle member, the exit windows being provided for emission of an electron beard generated by the electron generator into the container; and a magnetic shield member for the vacuum chamber and a magnetic shield member for the nozzle member, the magnetic shield members being respectively provided for the vacuum housing and the nozzle member so as to block variable magnetism generated around an electron beam, trajectory extended from the electron generator to the exit windows. | 2016-03-03 |
| 20160064112 | CONDUCTIVE POLYMER COMPOSITE AND SUBSTRATE - A conductive polymer composite including a π-conjugated polymer and a dopant polymer contain a repeating unit “a” represented by the following formula (1) and has a weight-average molecular weight with range of 1,000 to 500,000, | 2016-03-03 |
| 20160064113 | CONDUCTIVE POLYMER COMPOSITE AND SUBSTRATE - The present invention provides a conductive polymer composite including a π-conjugated polymer and a dopant polymer which contains a repeating unit “a” represented by the following general formula (1) and has a weight-average molecular weight in the range of 1,000 to 500,000, | 2016-03-03 |
| 20160064114 | CONDUCTIVE COMPOSITE MATERIAL AND METHOD FOR PRODUCING SAID CONDUCTIVE COMPOSITE MATERIAL - The invention relates to a conductive material comprising a first phase including a thermoset compound, a second phase, consisting of a smaller volume, including a thermoplastic compound, and a conductive compound, wherein the second phase is dispersed in the first phase, the two phases are bicontinuous, and the conductive compound is situated at the interface between the first and second phases. | 2016-03-03 |
| 20160064115 | WIRE COATING RESIN MATERIAL AND ELECTRIC WIRE - To provide a wire coating resin material comprising an ETFE type copolymer, capable of forming a coating layer which is excellent in thermal stress cracking resistance and has good mechanical properties, and an electric wire having a coating layer which is excellent in thermal stress cracking resistance and has good mechanical properties. | 2016-03-03 |
| 20160064116 | WIRE FOR DEEP WATER TRANSMISSION - An electrically conductive wire for deep water transmission includes a first wire portion and a second wire portion. The first wire portion makes up one end of the wire, and is formed from a first metal. The second wire portion is formed from a second metal. The first metal has a higher ultimate tensile strength than the second metal. The first wire portion is used to support the weight of the second wire portion, thereby allowing the electrically conductive wire to be used in underwater or subsea power cables which may be freely suspended from their origin for providing electricity to electrical devices located in deep water or ultra-deep water. | 2016-03-03 |
| 20160064117 | TRIPLE HELIX DRIVELINE CABLE AND METHODS OF ASSEMBLY AND USE - A power cable having improved durability and associated methods of assembly and use are described herein. In one aspect, the power cable is adapted for use in powering an implantable circulatory pump system. The cable includes one or more conductors of uninsulated wire strands that are loosely packed so as to move relative one another during cable flexure. The driveline cable may include a plurality of conductors, each comprised of multiple uninsulated bundles of uninsulated, loosely packed wire strands of a conductive material, that are wrapped about a central core. The cable may include at least six conductors, each conductor having at least 200 wire strands of a 30 gauge or higher. The cable may include the plurality of wire strands wound in a Litz style configuration to provide improved durability over many cycles of use at reduced cost, improved integrity of the electrical connection and reduced diameter. | 2016-03-03 |
| 20160064118 | WIRE HARNESS - Provided is a wire harness having a shielding structure that can achieve a required shielding effect while sufficiently meeting the requirements of weight reduction and cost reduction. The wire harness includes a wire group constituted by a plurality of wires and a retaining member that surrounds the wire group such that the wire group is retained in the form of a bundle, wherein the wire group is configured to include a first wire composed of a linear conductor that is located toward the center of the wire group, a tube-shaped wire sheathing that surrounds the first wire, and a second wire and a third wire that are composed of an opposing pair of split tube-shaped conductors that are insulated from each other with the first wire and the wire sheathing being interposed therebetween. | 2016-03-03 |
| 20160064119 | COMMUNICATION CABLE INCLUDING A HELICALLY-WRAPPED SHIELDING TAPE - Communication cable including insulated conductors and a composite tape having an insulative layer and a conductive layer. The composite tape includes first and second lateral sections that are folded over each other to form a shielding tape. The shielding tape includes opposite inner and outer sides that are formed from the first and second lateral sections, respectively, and a folded edge that joins the inner and outer sides. The conductive layer defines the inner side, the outer side, and the folded edge. The shielding tape is wrapped helically about the insulated conductors a plurality of times along a length of the communication cable to form a plurality of wraps. The inner side of a subsequent wrap of the shielding tape overlaps a portion of the outer side of a prior wrap of the shielding tape. | 2016-03-03 |
| 20160064120 | WIRE HARNESS - A wire harness having a shield structure that can exhibit a required shield effect and sufficiently meet demands for cost mitigation and weight reduction is provided. The wire harness is provided with an electrical line group that is held in a bundled manner, in which at least a portion of electrical lines that are positioned on the outer circumferential side of the electrical line group each have a metal thin-film for shielding as the outermost layer, the metal thin-film being formed so as to attach to an outer circumferential surface portion of a sheathing that surrounds a conductor of the electrical line, and a drain wire or another ground connection member that is grounded and comes into contact with the metal thin-films of the electrical lines. | 2016-03-03 |
| 20160064121 | WIRING HARNESS PRODUCTION MOUNTING - The wiring harness production mounting, includes: at least one screen for displaying data aiding in the production of wiring harnesses, and at least one attachment surface associated with the at least one display screen, the at least one attachment surface being configured to receive at least one cable-routing element. | 2016-03-03 |
| 20160064122 | Micro-Resistance Structure with High Bending Strength, Manufacturing Method and Semi-Finished Structure Thereof - A micro-resistance structure with high bending strength is disclosed. The micro-resistance structure with high bending strength comprises a multi-layer metallic substrate; a patterned electrode layer disposed on a lower surface of the multi-layer metallic substrate; an encapsulant layer covering a portion of the multi-layer metallic substrate, wherein the encapsulant layer is substantially made of a flexible resin ink; and two external electrodes, which are electrically insulated from each other, covering the exposed portion of the multi-layer metallic substrate. The abovementioned structure is characterized in high bendability and applicable to wearable devices. A manufacturing method and a semi-finished structure of the micro-resistance structure with high bending strength are also disclosed herein. | 2016-03-03 |
| 20160064123 | TEMPERATURE INDEPENDENT RESISTOR - The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method. | 2016-03-03 |
| 20160064124 | ELECTRONIC COMPONENT - An electronic component in which a metal layer is unlikely to be peeled from a substrate includes an insulating ceramic substrate, a ceramic layer diffusion-bonded to the substrate, a metal layer including a first principal surface and a second principal surface opposed to the first principal surface, with the first principal surface diffusion-bonded to the ceramic layer, and a characteristic layer diffusion-bonded to the second principal surface of the metal layer and prepared from a ceramic material, wherein the characteristic layer varies in resistance value with respect to ambient temperature or applied voltage. | 2016-03-03 |
| 20160064125 | POWDER METALLURGICAL METHOD FOR FABRICATING HIGH-DENSITY SOFT MAGNETIC METALLIC MATERIAL - A powder metallurgical method for fabricating a high-density soft magnetic metallic material comprises steps of providing an initial powder; using a spray drying process to fabricate the initial powder into a spray-dried powder; placing the spray-dried powder in a mold and compacting the spray-dried powder under a compacting pressure and a compacting temperature to form a green compact; and sintering the green compact at a sintering temperature to form a soft magnetic metallic material. The spray-dried powder, which is fabricated by the spray drying process, has superior flowability, compactability and compressibility and is suitable for the press-and-sinter process. The soft magnetic metallic material fabricated by the present invention is outstanding in sintered density and magnetic performance. The present invention adopts the inexpensive press-and-sinter process and has a low fabrication cost. | 2016-03-03 |
| 20160064126 | Magnetic Fluid - The present invention is in the field of fluids and the like comprising magnetic particles, such as ferromagnetic particles, anti-ferromagnetic particles, ferrimagnetic particles, synthetic magnetic particles, paramagnetic particles, superparamagnetic particles, such as magnetic fluids, a method of stabilizing magnetic particles, use of these fluids and functionalized particles. Such fluids have a large variety of applications, such as sealants, as a sensor, in biomedics, etc. | 2016-03-03 |
| 20160064127 | SUPERCONDUCTING COIL DEVICE WITH SWITCHABLE CONDUCTOR SECTION AND METHOD FOR SWITCHING - In a coil device with at least one electrical coil winding with superconducting conductor material, the coil winding is part of a self-contained circuit for formation of a continuous current. The closed circuit has a switchable conductor section which can be switched between a superconducting state and a normally conducting state by a magnetic device. | 2016-03-03 |
