| 09th week of 2011 patent applcation highlights part 27 |
| Patent application number | Title | Published |
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| 20110050271 | TEST APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD USING THE SAME - A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating unit for storing a test signal and inactivating a combination signal when the test mode signal is inactivate and for outputting the stored test signal as the combination signal when the test mode signal is activate, and a code signal generating unit for activating a test code signal when one of the test fuse signal and the combination signal is activated. | 2011-03-03 |
| 20110050272 | METHOD AND CIRCUIT FOR TESTING INTEGRATED CIRCUIT - A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode. | 2011-03-03 |
| 20110050273 | FAST TESTABLE WAFER AND WAFER TEST METHOD - A fast testable wafer includes a die group, testing points located on dies, a scribe line located between the dies, and a plurality of testing pads disposed in the scribe line area. The testing points comprise bonding pads or electrodes of internal circuits within the dies. The testing pads and bonding pads may be electrically connected and arranged suitably such that testing probes may be electrically connected to the testing pads and bonding pads easily so as to test the plurality of dies at about the same time. Through suitable circuits on the wafer, different circuit routes may be selected to connect the testing pads and different testing points on the dies so as to test a plurality of dies without moving the testing probes and thereby accelerating the test. | 2011-03-03 |
| 20110050274 | Maintaining A Wafer/Wafer Translator Pair In An Attached State Free Of A Gasket Disposed Therebetween - A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means. | 2011-03-03 |
| 20110050275 | SEMICONDUCTOR WAFER HAVING TEST MODULES INCLUDING PIN MATRIX SELECTABLE TEST DEVICES - A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing. | 2011-03-03 |
| 20110050276 | METHOD AND PROGRAM FOR OPERATING TEST APPARATUS - Disclosed is a method for operating a test apparatus in which the testing efficiency is drastically increased. The test apparatus has a plurality of stages for testing wafers by using operation buttons displayed on the operating screens of each of a plurality of monitors. Exclusion condition buttons for excluding operation buttons are set in at least one monitor using exclusion condition data prepared by combining data required to perform various functions of the test apparatus and an exclusion condition pattern prepared by combining the exclusion condition of the exclusion condition data into data for deciding whether the operating button configured to operate each function can be pressed or not. Also, display of the screen that satisfies the exclusion condition for at least one monitor is prevented. | 2011-03-03 |
| 20110050277 | SYSTEM FOR CONTROLLING AT LEAST ONE ACTUATOR OF THE COWLINGS OF A TURBOJET ENGINE THRUST REVERSER - The control system of the invention includes at least one actuator ( | 2011-03-03 |
| 20110050278 | SYSTEM FOR AND METHOD OF VIRTUAL SIMULTANEOUS SAMPLING WITH A SINGLE ADC CORE - Voltage balancing in multi-cell battery packs is improved by estimating instantaneous voltages on the cells. In accordance with one embodiment, an apparatus for reading voltages from multiple voltage sources includes a first multiplexer coupled to multiple voltage sources and a controller. The controller is programmed to output from the first multiplexer a sequential pair of voltages read from each of the multiple voltage sources. The multiple sequential pairs of voltages all have a common midpoint in time. The multiple sequential pairs of voltages are all read within a small time window, such as 100 microseconds. In one embodiment, the multiple voltage sources are Li-ion or other high-voltage cells, though other types of cells can also be used. | 2011-03-03 |
| 20110050279 | LIGHTWEIGHT SECURE PHYSICALLY UNCLONABLE FUNCTIONS - Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed. | 2011-03-03 |
| 20110050280 | METHODS AND SYSTEMS TO CALIBRATE PUSH-PULL DRIVERS - Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers. | 2011-03-03 |
| 20110050281 | METHOD AND SYSTEM FOR GROUPING LOGIC IN AN INTEGRATED CIRCUIT DESIGN TO MINIMIZE NUMBER OF TRANSISTORS AND NUMBER OF UNIQUE GEOMETRY PATTERNS - A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit. | 2011-03-03 |
| 20110050282 | ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS - An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). | 2011-03-03 |
| 20110050283 | SYNCHRONOUS PHASE DETECTION CIRCUIT - A phase detection circuit arranged as sigma-delta modulator for determining a phase difference between a periodic signal and a reference signal, the periodic signal and the reference signal having a substantially equal frequency, includes: a source input configured to receive the periodic signal whose phase relationship with respect to the reference signal is to be determined; a feedback signal generator configured to provide a feedback signal, the feedback signal and reference signal having substantially the same frequency; a phase difference circuit coupled to the source input node and a second signal input node coupled to the feedback signal generator, and configured to determine an error signal as a function of the phase difference between the periodic signal and the feedback signal; an integrator circuit coupled to the phase difference circuit, configured to receive the error signal and to integrate the error signal to provide an integration signal; a digitizing circuit coupled to the integration circuit, configured to digitize the integration signal; wherein the feedback signal generator is coupled to the digitizing circuit, configured to provide the feedback signal based on the digitized integration signal from the digitizing circuit; and configured to select the phase of the feedback signal from a number of fixed phases, wherein the phase detection circuit is arranged for generating a time-average of the phase of the feedback signal as selected from the plurality of fixed phases. | 2011-03-03 |
| 20110050284 | SENSE AMPLIFIER CIRCUIT AND RELATED CONFIGURATION AND OPERATION METHODS - A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET. | 2011-03-03 |
| 20110050285 | HIGH LINEAR FAST PEAK DETECTOR - A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor. | 2011-03-03 |
| 20110050286 | TEMPERATURE SENSING CIRCUIT - A temperature sensing circuit that does not use an oscillator is presented. The temperature sensing circuit includes a selector and a detector. The selector is configured to select and output a reference voltage from first and second level signals in response to first and second trimming signals. The first and second level signals are relatively insensitive to temperature variations. The detector is configured to generate a detection voltage by comparing the reference voltage with a variable voltage depending on internal temperature. | 2011-03-03 |
| 20110050287 | HIGH SPEED TRACK AND HOLD CIRCUIT - Examples of systems and methods are provided for tracking-and-holding an input signal. The system may produce a pair of differential voltage outputs responsive to a pair of differential voltage inputs. The system may couple, in response to a clock signal, an input amplifier circuit to an output circuit or decouple the input amplifier circuit from the output circuit. The system may couple the input amplifier to an electrical ground. The system may track values of a pair of differential voltage outputs when a switching circuit is in a closed position and to hold the values of the pair of differential voltage outputs constant when the switching circuit is in an open position. | 2011-03-03 |
| 20110050288 | SEMICONDUCTOR SWITCH - A semiconductor switch includes: a first terminal; a second terminal; a switch section including a through FET connected between the first terminal and the second terminal and a shunt FET connected between the second terminal and a first ground terminal; a first control terminal configured to drive the through FET; a second control terminal configured to drive the shunt FET; and a driver provided on a substrate together with the switch section and configured to provide a differential output to the first control terminal and the second control terminal. | 2011-03-03 |
| 20110050289 | INPUT BUFFER - An input buffer includes a driving signal generation unit, a comparison signal generation unit, and a driving unit. The driving signal generation unit is configured to generate first and second driving signals which are selectively enabled in response to a control signal generated depending on a level of an input signal. The comparison signal generation unit is configured to compare the level of the input signal with the level of a reference voltage and generate a comparison signal. The driving unit is configured to buffer the comparison signal and drive an output signal with a drivability determined by the first and second driving signals. | 2011-03-03 |
| 20110050290 | OUTPUT DRIVER CIRCUIT - An output driver circuit includes a pre-driver unit and a first driving unit. The pre-driver unit is configured to generate a driving selection signal and a driving signal from a pre-driving signal in response to a group selection signal and a code signal. The first driving unit is configured to drive a data pad in response to the driving selection signal and the driving signal. | 2011-03-03 |
| 20110050291 | Method and apparatus for adjusting driver output current and electronic apparatus - According to an aspect of the embodiment, a driver outputs a driver current to a reception LSI, and a receiver included in the reception LSI receives an analog voltage signal corresponding to a value of the driver current as a receiver input. An A/D converter converts the voltage signal of the receiver input to a digital value, and transmits the digital value to a driver current controller in a transmission LSI. The driver current controller adjusts a number of PMOS driving stages in the driver or a number of NMOS driving stages in the driver, to make the digital value of the voltage signal of the receiver input belong to a predetermined range. | 2011-03-03 |
| 20110050292 | CORELESS PRINTED-CIRCUIT-BOARD (PCB) TRANSFORMERS AND OPERATING TECHNIQUES THEREFOR - Optimal operating techniques are disclosed for using coreless printed-circuit-board (PCB) transformers under (1) minimum input power conditions and (2) maximum energy efficiency conditions. The coreless PCB transformers should be operated at or near the ‘maximum impedance frequency’ (MIF) in order to reduce input power requirement. For maximum energy efficiency, the transformers should be at or near the “maximum efficiency frequency” (MEF) which is below the MIF. The operating principle has been confirmed by measurement and simulation. The proposed operating techniques can be applied to coreless PCB transformers in many circuits that have to meet stringent height requirements, for example to isolate the gates of power MOSFET and IGBT devices from the input power supply. | 2011-03-03 |
| 20110050293 | Driving circuit of optical gate switch - A driving circuit of a semiconductor optical amplifier type gate switch constituting a matrix optical switch is provided with an operation amplifier into which a driving signal is input and from which a current corresponding to the driving signal is output, an inductance element provided at an output terminal of the operation amplifier, and a circuit composed of a diode element and a resistor element connected in parallel and provided between the inductance element and the semiconductor optical amplifier. | 2011-03-03 |
| 20110050294 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by dividing a frequency of the data clock and to determine whether or not phases of the plurality of multi-phase data frequency division clocks are reversed in response to a frequency division control signal, and a first phase detecting block to detect a phase of the system clock based on a phase of a first selected clock that is predetermined among the plurality of multi-phase data frequency division clocks and to is determine a logic level of the frequency division control signal in response to the detected result. | 2011-03-03 |
| 20110050295 | SEMICONDUCTOR DEVICE - A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result. | 2011-03-03 |
| 20110050296 | DIVIDE-BY-TWO INJECTION-LOCKED RING OSCILLATOR CIRCUIT - A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature. | 2011-03-03 |
| 20110050297 | SYSTEM EMPLOYING SYNCHRONIZED CRYSTAL OSCILLATOR-BASED CLOCK - A synchronized clock system, for use with an electronic system with several system nodes requiring a synchronized clock signal. The clock system includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer. | 2011-03-03 |
| 20110050298 | POWER SUPPLY CIRCUIT FOR SOUTH BRIDGE CHIP - A power supply circuit for a south bridge chip includes a voltage sampling circuit, a control circuit, and an I/O controller. The voltage sampling circuit comprises an input terminal capable of receiving a first voltage, and an output terminal capable of outputting a control signal. The control circuit is capable of receiving the control signal from the voltage sampling circuit and outputting a power good signal when a high voltage level control signal is received. The I/O controller is capable of receiving the power good signal from the control circuit, adjusting time sequence for the power good signal to synchronize with the first voltage, and outputting the adjusted power good signal to provide power for the south bridge chip. | 2011-03-03 |
| 20110050299 | ELECTRICAL INSTRUMENT HAVING A PROTECTION CIRCUIT - A protection circuit suitable for electrical instruments includes a software detecting circuit, a logic AND circuit, a driver and control circuit for engine operating power components, and a hardware detecting circuit connected with the logic AND circuit. Both the software detecting circuit and the hardware detecting circuit monitor the state of an operating switch and provide signals to the logic AND circuit. Only when the state of the switch changes from opened to closed and both detecting circuits determine that this state is correct will the driver and control circuit signal the engine to operate. Furthermore, by connecting two or more power components in serial at the same time, the engine will not work by accident and the machine will not be out of control when any one of the power components is damaged. A circuit using capacitors of suitable specification can also be provided to isolate the controlling pin of a power component in the form of an SCR to thereby avoid failure and damage of the entire system. | 2011-03-03 |
| 20110050300 | Clock Generator - A data processing system comprises a plurality of sub-circuits ( | 2011-03-03 |
| 20110050301 | Phase Locked Loop Circuitry Having Switched Resistor Loop Filter Circuitry, and Methods of Operating Same - Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry. The frequency detection circuitry includes (i) circuitry to generate a signal which is representative of the frequency of the output signal of the phase-locked loop circuitry, (ii) comparison circuitry to compare the signal which is representative of the frequency of the output signal of the phase-locked loop circuitry to a reference input to the phase-locked loop circuitry, and (iii) a switched capacitor network including at least one capacitor. | 2011-03-03 |
| 20110050302 | CHARGE PUMP CIRCUIT AND PLL CIRCUIT USING THE SAME - A charge pump circuit ( | 2011-03-03 |
| 20110050303 | DIE LOCATION COMPENSATION - Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed. | 2011-03-03 |
| 20110050304 | SEMICONDUCTOR APPARATUS - In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. | 2011-03-03 |
| 20110050305 | CENTRALIZING THE LOCK POINT OF A SYNCHRONOUS CIRCUIT - A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is disclosed. The synchronous circuit is configured to selectively use either a reference clock or its inverted version as the clock signal input to the delay line based on a relationship among the phases of the reference clock, the inverted reference clock, and a feedback clock may be used during determination of the phase relationship. The selective use of the opposite phase of the reference clock for the input of the delay line results in centralization of the lock point for most cases as well as improvement in the tuning range and the time to establish the initial lock, without requiring an additional delay line. | 2011-03-03 |
| 20110050306 | TIME CORRECTION CIRCUIT AND ELECTRONIC APPARATUS - A time correction circuit includes: a time-measurement device that measures a time period; a receiver device that receives electromagnetic wave based on a first baseband signal, the first baseband signal including time information concerning time and being encoded by a pulse width modulation method, and outputs a second baseband signal based on the electromagnetic wave received; and an asynchronous circuit that corrects the time based on the second baseband signal, wherein the asynchronous circuit executes a specified process to retrieve the time information from the second baseband signal based on the time period measured, at least one of when the second baseband signal changes from high level to low level and when the second baseband signal changes from low level to high level, and assumes a standby state after executing the specified process. | 2011-03-03 |
| 20110050307 | CIRCUITS AND METHODS FOR CLOCK SIGNAL DUTY-CYCLE CORRECTION - Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion. | 2011-03-03 |
| 20110050308 | STANDBY POWER REDUCTION METHOD AND APPARATUS FOR SWITCHING POWER APPLICATIONS - The present invention discloses a standby power reduction method and apparatus for switching power applications, the method comprising the steps of: performing a hysteresis comparison on a supply voltage to generate a selecting signal having a first state and a second state, wherein the hysteresis comparison has a high threshold voltage compared to the supply voltage when the selecting signal is at the first state, and the hysteresis comparison has a low threshold voltage compared to the supply voltage when the selecting signal is at the second state; and determining a UVLO_ON voltage according to the selecting signal, wherein the UVLO_ON voltage is equal to a first level when the selecting signal is at the first state, and the UVLO_ON voltage is equal to a second level when the selecting signal is at the second state. | 2011-03-03 |
| 20110050309 | DYNAMIC CLOCK FEEDBACK LATCH - A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node. | 2011-03-03 |
| 20110050310 | LEVEL SHIFTER CIRCUIT - The present invention relates to a level shifter circuit ( | 2011-03-03 |
| 20110050311 | FLAG SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal. | 2011-03-03 |
| 20110050312 | MULTI-PHASE CLOCK GENERATION CIRCUIT - A multi-phase clock generation circuit including a phase interpolation circuit that generates and outputs an interpolation signal based on first and second clock signals, the interpolation signal interpolating a phase between output clock signals corresponding to the first and the second clock signals, and a control circuit that generates a first control signal to adjust a phase of the interpolation signal and outputs the first control signal to the phase interpolation circuit, in which the control circuit includes a timing detection circuit that detects a timing of a change in a logic value of the interpolation signal, and a control signal generation circuit that generates the first control signal according to a detection result in the timing detection circuit. | 2011-03-03 |
| 20110050313 | METHODS AND SYSTEMS RELATED TO A CONFIGURABLE DELAY COUNTER USED WITH VARIABLE FREQUENCY CLOCKS - In certain arrangements and methods, a reset-able counter ( | 2011-03-03 |
| 20110050314 | DISPLAY LINK CLOCKING METHOD AND APPARATUS - An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals. | 2011-03-03 |
| 20110050315 | POWER SUPPLY AND DC-DC-CONVERSION - In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator. | 2011-03-03 |
| 20110050316 | POWER TRANSISTOR WITH TURN OFF CONTROL AND METHOD FOR OPERATING - A circuit has a power transistor, a driver control circuit, a variable clamp circuit and a turn-off control circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit, and a control electrode. The driver control circuit has an output coupled to the control electrode of the power transistor for controlling the power transistor during an active mode of the circuit. The variable clamp circuit is coupled between the output of circuit and the first power supply terminal. The turn-off control circuit is coupled to the variable clamp circuit and selects clamping levels of the variable clamp circuit during a transition from the active mode to an inactive mode of the circuit. | 2011-03-03 |
| 20110050317 | BOOTSTRAP CIRCUIT - A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor. | 2011-03-03 |
| 20110050318 | HIGH VOLTAGE DIFFERENTIAL PAIR AND OP AMP IN LOW VOLTAGE PROCESS - A high voltage differential pair and op amp implemented in a low voltage semiconductor process. The high voltage differential pair expands the incoming common mode voltage of a differential pair to multiple times the normal operating voltage of the differential pair through the use of high voltage current sources, current sinks and stacks of transistors. The high voltage op amp includes a high voltage input stage and a high voltage common source amplifier to expand the output voltage range to multiple times the normal operating voltage of the op amp. | 2011-03-03 |
| 20110050319 | Multiplier, Mixer, Modulator, Receiver and Transmitter - A multiplier is provided, for example, for use as a mixer in a modulator of a radio frequency transmitter. The multiplier multiplies a first alternating signal of constant amplitude by a second signal, for example, in the form of a carrier wave from a local oscillator. The multiplier comprises a transconductance stage for converting the first signal to a differential output current and a current switching stage for switching the differential output current in accordance with the second signal. The transconductance stage comprises a plurality of offset pairs of transistors, whose inputs and outputs are connected in parallel. The switching stage comprises cross-coupled pairs of transistors which, together with the transconductance stage, form a Gilbert cell. The relative gains of the transistors of each offset pair are such that a minimum in the third harmonic distortion characteristic of the multiplier occurs substantially at the amplitude of the first signal. | 2011-03-03 |
| 20110050320 | USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING - In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack. | 2011-03-03 |
| 20110050321 | HIGH VOLTAGE SWITCH IN LOW VOLTAGE PROCESS - A high voltage analog switch operable by a binary signal is implemented in a low voltage semiconductor process. The switch has three parallel circuit paths, with each path comprising at least three series connected transistors. Control signals are selectively applied to the control terminals of the transistors to control the switch and selectively turn on or turn off each of the three circuit paths depending on the input voltage range, so that the breakdown voltage of all of the transistors is never exceeded in any mode of operation. | 2011-03-03 |
| 20110050322 | SWITCHING CIRCUIT WITH GATE DRIVER HAVING PRECHARGE PERIOD AND METHOD THEREFOR - A switching circuit includes first and second transistors, and a driver circuit. The first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a control electrode. The driver circuit has an input for receiving an input signal, and an output coupled to the control electrode of the first transistor. The driver circuit precharges the control electrode of the first transistor to a first predetermined voltage, and in response to the input signal transitioning from a first logic state to a second logic state, the driver circuit provides a second predetermined voltage to the control electrode of the first transistor to cause the first transistor to be conductive. | 2011-03-03 |
| 20110050323 | SEMICONDUCTOR SWITCH - A semiconductor switch includes: a switch section, provided on a substrate, switching connection states among a plurality of terminals; a positive voltage generator generating a positive potential higher than a supply potential supplied from a power-supply line; a driver, connected to an output line of the positive voltage generator, supplying a control signal to the switch section in response to a terminal switching signal; and a voltage controller, provided on the same substrate, controlling to connect the output line of the positive voltage generator to the power-supply line for a first period corresponding to a change in the connection states, and controlling to disconnect the output line from the power-supply line after the first period. | 2011-03-03 |
| 20110050324 | INTEGRATED SMART POWER SWITCH - A device including a controllable semiconductor, sensor, and controller is provided. The controllable semiconductor is associated with a first operating parameter and a second operating parameter, wherein at least the first operating parameter is controllable. The sensor is in communication with the controllable semiconductor device and acquires data relating to the second operating parameter of the controllable semiconductor device. The controller is in communication with the controllable semiconductor device and the sensor, and the controller is configured to access device data associated with the controllable semiconductor, control the first operating parameter of the controllable semiconductor, and receive data from the first sensor relating to the second operating parameter. The controller determines a first predicted value dependent on the device data, compares the data relating to the second operating parameter with the first predicted value, and, if a first condition is detected based on this comparison, dynamically modifies the first operating parameter. | 2011-03-03 |
| 20110050325 | Circuit Arrangement for Voltage Supply and Method - The circuit arrangement for the supply of voltage comprises a control arrangement ( | 2011-03-03 |
| 20110050326 | CHARGE PUMP WITH CHARGE FEEDBACK AND METHOD OF OPERATION - A charge pump charges a first capacitor to a predetermined input voltage using a first switch. The first switch is coupled to a first terminal of the first capacitor for coupling the first terminal to an input terminal that receives the predetermined input voltage. A second switch couples a second terminal of the first capacitor to a reference voltage terminal. Charge is sequentially transferred from the first capacitor to an output capacitance by using the first switch. A portion of charge is sequentially removed from the output capacitance to the input terminal using a third switch and a second capacitor. Configuration logic provides control signals to make one or more of a plurality of charge transfer capacitors switch the same as said first capacitor switches. | 2011-03-03 |
| 20110050327 | Semiconductor device - Provided is a semiconductor device including: a first charge pump circuit that generates a first control signal based on electric charge of a first pumping capacitor accumulated through a first drive transistor; a second charge pump circuit that generates a second control signal based on electric charge of a second pumping capacitor accumulated through a second drive transistor; a third charge pump circuit that transfers electric charge between an output terminal and a reference voltage terminal through a third drive transistor; and a fourth charge pump circuit that transfers electric charge between the output terminal and the reference voltage terminal through a fourth drive transistor. Conductive states of the first and third drive transistors are controlled based on the second control signal, and conductive states of the second and fourth drive transistors are controlled based on the first control signal. | 2011-03-03 |
| 20110050328 | Methods and Circuits for a Low Input Voltage Charge Pump - A charge pump circuit comprises a plurality of subcircuits, where the subcircuits are connected to each other in a single or a dual array having a repeating pattern. Each of the subcircuits comprises one or more of the following: an X-channel device having an X-gate terminal, an X-source terminal and an X-drain terminal, a Y-channel device having a Y-gate terminal, a Y-source terminal and a Y-drain terminal, and a capacitor; wherein a first end of the capacitor, the X-drain terminal, and the Y-drain terminal are connected with each other to form the common drain terminal; and wherein a second end of the capacitor is the clock terminal. | 2011-03-03 |
| 20110050329 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a cascode circuit having a transistor, a detector circuit and a bias generator circuit. A bias is applied to a substrate of the transistor. The detector circuit generates a signal related to a threshold voltage of the transistor. The bias generator circuit generates the bias based on the signal generated by the detector circuit. | 2011-03-03 |
| 20110050330 | REFERENCE CURRENT GENERATING CIRCUIT - A reference current generating circuit includes an operational amplifier having one input terminal to receive a reference voltage and a field effect transistor having a gate to receive an output voltage of the operational amplifier. k resistors (k is an integer not less than 2) are connected in series to a drain of the field effect transistor, and a voltage at one of connection points of the resistors is feed backed to the other input terminal of the operational amplifier. A switch selects one of the connection points of the resistors and applies the voltage of the selected connection point as a reference voltage to a gate of a reference transistor to generate a reference current. | 2011-03-03 |
| 20110050331 | HIGH VOLTAGE CURRENT SOURCE AND VOLTAGE EXPANDER IN LOW VOLTAGE PROCESS - A high voltage current source and a voltage expander implemented in a low voltage semiconductor process. The voltage expander extends the operating voltage range of a stack of transistors to multiple times a supply voltage Vdd at the output node of the stack without exceeding the breakdown voltage of any of the transistors in the stack. The voltage expander uses a diode and a voltage divider to detect the output node voltage changes and generates a plurality of voltages that control the gate voltages for the stack of transistors. A high voltage wide swing current source utilizes a transistor to set the output current and the voltage expander to extend the output voltage range of the current setting transistor. An additional transistor and another current source ensure that the output current is constant throughout the entire output voltage range between about 0 V and multiple times the supply voltage Vdd. | 2011-03-03 |
| 20110050332 | SIGNAL REPRODUCING DEVICE - The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular. This signal reproducing device ( | 2011-03-03 |
| 20110050333 | METHOD, APPARATUS, AND SYSTEM FOR OBTAINING TUNING CAPACITANCE FOR Gm-C FILTER - The present invention discloses a method, apparatus and system for obtaining the tuning capacitance of a Gm-C filter. The method includes: integrating a simulated capacitor within a given time via a current, where the simulated capacitor simulates the capacitor of the Gm-C filter which is set to an even capacitor array; and comparing the integral voltage obtained by the integration with the reference voltage, finding a simulated capacitance that makes the integral voltage equal to the reference voltage via gradual approaching by adjusting a control code, and determining the simulated capacitance as the tuning capacitance. The present invention improves the performance of a Gm-C filter without affecting the performance of the Gm-C filter. | 2011-03-03 |
| 20110050334 | Integrated Voltage Regulator with Embedded Passive Device(s) - A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate. | 2011-03-03 |
| 20110050335 | LOW-CAPACITANCE ELECTROSTATIC DISCHARGE PROTECTION DIODES - A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width. | 2011-03-03 |
| 20110050336 | MULTI-CHIP STACK STRUCTURE AND SIGNAL TRANSMISSION METHOD THEREOF - A multi-chip stack structure and a signal transmission method are disclosed in specification and drawing, where the multi-chip stack structure includes first and second chips. The first chip includes a first inductance coil with a first series capacitor, and the second chip includes a second inductance coil with a second series capacitor. The first and second inductance coils are magnetically coupled to each other. The magnetically coupled inductance coils and the capacitors constitute a coupling filter. | 2011-03-03 |
| 20110050337 | SUPPLY VOLTAGE CONTROL DEVICE FOR AMPLIFIER - A supply voltage control device for an amplifier that controls a supply voltage for the amplifier has been improved. The supply voltage control device includes: a supply voltage control circuit including an error amplification circuit that feeds an error current so as to control the supply voltage for the amplifier, and a direct current feed circuit that feeds a direct current (or the direct current and a current of a low-frequency component); a high-frequency component extraction unit that extracts a predetermined high-frequency component contained in a signal resulting from detection of an envelope relevant to a signal to be amplified by the amplifier; a peak hold unit that performs peak hold processing on a signal of the extracted high-frequency component; and an addition unit that adds up a signal based on the result of detection of the envelope relevant to the signal to be amplified by the amplifier, and the signal resulting from the peak hold processing, and inputs a signal resulting from the addition to the supply voltage control circuit. | 2011-03-03 |
| 20110050338 | Modulated Triangular Wave Amplifier - The invention is a power amplifier circuit for providing a signal acceptable for use in audio amplifiers or similar applications without requiring a stable power supply free from fluctuations. An alternating current power supply signal rectified to a direct current signal is processed by two voltage multipliers. A voltage divider establishes a unity gain level, and the variance from this voltage is squared by the first voltage multiplier. This squared voltage is then multiplied with a triangular wave signal to generate a modulated triangular wave signal. The modulated triangular wave signal and a signal to be amplified, typically an audio signal, are processed by an internal comparator to generate a pulse width modulated signal. This modulated signal is processed by a power transistor network and filter to provide an amplified signal to a load device. By modulating the triangle wave signal to compensate for fluctuations in the power supply to the amplifier circuit, noise or ripples present in the power supply are demodulated, eliminating the requirement for a regulated power supply. | 2011-03-03 |
| 20110050339 | POWER SERIES DIGITAL PREDISTORTER AND DISTORTION COMPENSATION CONTROL METHOD THEREFOR - A power series digital predistorter and a distortion compensation control method for the power series digital predistorter are capable of adjusting the coefficients of a frequency characteristic compensator at high speed. A controller in the power series digital predistorter collectively sets adjustment amounts for the phases in bands in an N-th order frequency characteristic compensator; collectively sets adjustment amounts for the amplitudes in the bands in the N-th order frequency characteristic compensator; determines whether an index indicating the degree of cancellation of a distortion component generated in a power amplifier satisfies a preset condition; and, if the index does not satisfy the condition, performs control such that the adjustment amounts for the phases and the adjustment amounts for the amplitudes are set again. | 2011-03-03 |
| 20110050340 | SYSTEM AND METHOD FOR AMPLIFYING A SIGNAL USING MULTIPLE AMPLIFICATION STAGES SHARING A COMMON BIAS CURRENT - An apparatus including cascaded amplification stages adapted to be biased by a common DC current to generate an amplified output signal from an input signal. A first amplification stage includes a routing network to substantially double an input voltage signal, and a first transconductance gain stage to generate a first current signal from the input voltage signal. A second amplification stage includes a resonator to convert the first current signal into a second voltage signal, and a second transconductance gain stage to generate a second current signal from the first current signal. A third amplification stage includes a current gain stage to generate a third current signal from the second current signal, and a load through which the third current signal flows to generate the output signal. | 2011-03-03 |
| 20110050341 | High speed rail to rail phase splitter for providing a symmetrical differential output signal having low skew - A novel high-speed phase splitter circuit ( | 2011-03-03 |
| 20110050342 | Push-pull amplifier circuit and operational amplifier circuit using the same - A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor. | 2011-03-03 |
| 20110050343 | BIAS CIRCUIT AND AMPLIFIER PROVIDING CONSTANT OUTPUT CURRENT FOR A RANGE OF COMMON MODE INPUTS - Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a constant current. One example of a bias circuit is configured to generate a bias signal having a voltage magnitude according to a reference signal. The reference signal is indicative of a common mode input level of an input signal of the amplifier circuit and the bias circuit is further configured to adjust the bias signal over a range of common mode input levels. An amplifier receiving the bias signal is configured to generate an output signal in response to an input signal and drive an output current based on the voltage magnitude of the bias signal provided by the bias circuit. | 2011-03-03 |
| 20110050344 | OUTPUT STAGE FOR A DIGITAL RF TRANSMITTER, METHOD FOR PROVIDING AN RF OUTPUT SIGNAL IN A DIGITAL RF TRANSMITTER, AND DIGITAL RF TRANSMITTER - An output stage ( | 2011-03-03 |
| 20110050345 | Linearization Circuits and Methods for Power Amplification - Linearization circuits of the invention are used in conjunction with power amplification circuits that comprise a power amplifier core. Exemplary linearization circuits comprise a replica of the power amplifier core. In operation, the linearization produces an envelope signal from an RF signal. The envelope signal is used to control the replica to produce an analog output signal which represents the inverse of the AM to AM distortion of the power amplifier core. The linearization circuit then biases the RF signal with the inverted non-linear signal of the replica to control the power amplifier core. The power amplifier core and the replica thereof can be defined on the same semiconductor die so both respond to process variables similarly. | 2011-03-03 |
| 20110050346 | Method and Apparatus for Compensating for Gain Changes in an Amplifier Circuit - In a method and apparatus for compensating for gain changes in an amplifier circuit comprising radio-frequency modules and attenuation elements, a radio-frequency module is driven with a first temperature-dependent monitoring voltage U | 2011-03-03 |
| 20110050347 | Method and System for Amplifier Control - A method is disclosed wherein a power level indicating a level of transmission power from an amplifier is provided. An indication of at least one of channel, channel bandwidth, OOB spectral requirements, spectral mask requirements, EVM, modulation rate, and modulation type is also provided. A control signal for controlling one of a bias current provided to the amplifier and a matching circuit for matching an output port of at least a stage of the amplifier is generated, the control signal determined in dependence upon the power level and the at least an indication. Then the one of the bias current and the matching circuit is adjusted in accordance with the control signal. | 2011-03-03 |
| 20110050348 | RADIO FREQUENCY POWER AMPLIFIER - An RF power amplifier according to an implementation of the present invention includes: a first power amplifier which linearly amplifies a first RF signal of a first frequency band; a second power amplifier which linearly amplifies a second RF signal of a second frequency band lower than the first frequency band; a third power amplifier which nonlinearly amplifies a third RF signal of the first frequency band; a fourth power amplifier which nonlinearly amplifies a fourth RF signal of the second frequency band, and input lines of the respective power amplifiers do not cross each other on semiconductor substrates, and the output lines of the respective power amplifiers do not cross each other on the semiconductor substrates. | 2011-03-03 |
| 20110050349 | BOOSTED-RAIL AMPLIFIER - An amplifier device including an amplifier having an input for receiving an audio input signal and an output for sending an output signal to a load. A boosted-rail circuit is connected to a power source and has a single boosted rail connected to the BTL amplifier. Also, a common-mode circuit is coupled to the boosted-rail circuit and the BTL amplifier. The common-mode circuit sends a common-mode signal to the BTL amplifier that will dynamically track the output voltage supplied from the boosted-rail circuit to the BTL amplifier. In operation, the boosted-rail circuit reacts to the BTL amplifier and switches from a non-boost mode to a boost mode to increase the output voltage supplied to the BTL when the BTL amplifier requires additional voltage. | 2011-03-03 |
| 20110050350 | AMPLIFIER CIRCUIT - An amplifier circuit operating at a fundamental angular frequency • | 2011-03-03 |
| 20110050351 | OSCILLATOR WITH REDUCED PHASE NOISE CHARACTERISTICS - One well known problem associated with voltage controlled oscillators or VCOs is phase noise, and it is desirable to reduce phase noise in order to improve VCO performance. Here, a VCO is provided where gain elements are provided that reduce phase noise. These gain elements are generally comprised of oscillator tanks. | 2011-03-03 |
| 20110050352 | ELECTRIC CIRCUIT, SENSOR SYSTEM EQUIPPED WITH THE ELECTRIC CIRCUIT, AND SENSOR DEVICE EQUIPPED WITH THE ELECTRIC CIRCUIT - An electric circuit includes: a reference signal generation circuit that generates a reference signal based on a first oscillation signal that is an oscillation signal of a first oscillation circuit that vibrates a first vibrator; and a counter circuit that counts a second oscillation signal that is an oscillation signal of a second oscillation circuit that vibrates a second vibrator based on the reference signal, and outputs a count signal, wherein the count signal is a change of the count value in the second oscillation signal. | 2011-03-03 |
| 20110050353 | TEMPERATURE COMPENSATED RC OSCILLATOR FOR SIGNAL CONDITIONING ASIC USING SOURCE BULK VOLTAGE OF MOSFET - A temperature compensated CMOS RC oscillator circuit changes the source-bulk voltage to stabilize the MOSFET's threshold voltage variation over temperature using a resistor and temperature-correlated bias current. The MOSFET's source is connected to ground through a resistor. This temperature-correlated bias current also runs through this resistor. When temperature increases, the bias current also increases, which increases the MOSFET's source-bulk voltage. The increased source-bulk voltage helps to stabilize the threshold voltage of MOSFET at high temperature. A power saving logic is also embedded in this oscillator to achieve higher frequency at lower power consumption. In the present invention, there is no high gain op amp or high speed comparator, which makes the resultant oscillator to be low power design and which can be integrated into a single chip with other system. | 2011-03-03 |
| 20110050354 | VOLTAGE CONTROL OSCILLATOR AND QUADRATURE MODULATOR - A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor. | 2011-03-03 |
| 20110050355 | EMI SUPPRESSOR HAVING BANDPASS FILTERING FUNCTION - An electromagnetic interference (EMI) suppressor having a bandpass filtering function is provided. The EMI suppressor is disposed on a substrate, and includes a signal line, a ground line, an open-circuit line, a first line group, and a second line group. The signal line has an input terminal and an output terminal for feeding in and feeding out electromagnetic wave signals respectively. One terminal of the ground line is connected to the signal line and the other terminal is a ground terminal. One terminal of the open-circuit line is connected to the signal line and the other terminal is an open-circuit terminal. The first line group is formed by a first open-circuit line and a second open-circuit line, and is connected to the signal line. The second line group is formed by a third open-circuit line and a fourth open-circuit line, and is connected to the signal line. | 2011-03-03 |
| 20110050356 | WAVEGUIDE CONVERTER AND MANUFACTURING METHOD FOR THE SAME - A waveguide converter includes a waveguide configured with an opening, a patch disposed inside the opening of the waveguide, a first ground conductor provided substantially along the opening of the waveguide and a port that opens in a side surface of the waveguide through which a signal line connected to the patch extends. | 2011-03-03 |
| 20110050357 | Transformer Signal Coupling for Flip-Chip Integration - Methods and apparatuses for transformer signal coupling for flip-chip circuit assemblies are presented. A device for coupling dies in flip-chip circuit assembly may include a first die associated with a first fabrication process and a first inductor physically coupled to the first die, where the first inductor receives an RF input signal. The device may further include a second die associated with a second fabrication process, and a second inductor physically coupled to the second die, where the second inductor is positioned so the first inductor can inductively couple the RF signal in the second inductor. A method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. | 2011-03-03 |
| 20110050358 | Electromagnetic Interference Noise Separator - Improved performance of a noise separator circuit capable of separating common mode (CM) and differential mode (DM) components of electromagnetic interference (EMI) noise are provided by arrangement of terminating impedances such that the circuit is fully symmetric with respect of a pair of input ports. The noise separator circuit is further improved by perfecting features for canceling effects of parasitic inductances and capacitances, parasitic capacitance and inductance between circuit connections such as printed circuit board traces, minimizing leakage inductance effects of pairs of coupled inductors and mutual inductance effects between pairs of coupled inductors, providing sufficient magnetizing inductance for low frequency response, and preventing saturation of inductors using switched attenuators, providing a plurality of ground planes, choices of terminating resistors and circuit layout. | 2011-03-03 |
| 20110050359 | High-Performance Conversion Between Single-Ended and Differential/Common-Mode Signals - A signal conversion apparatus includes first and second input ports and first and second output ports. A first splitter is coupled to convert a first single-ended signal received on the first input port into a differential signal including first and second opposite-phase components, and to provide the first and second opposite-phase components respectively on the first and second output ports. A second splitter is separate from the first splitter and is coupled to convert a second single-ended signal received on the second input port into a common-mode signal including first and second in-phase components, and to provide the first and second in-phase components respectively on the first and second output ports together with the first and second opposite-phase components. | 2011-03-03 |
| 20110050360 | WIDEBAND ELECTROMAGNETIC CLOAKING SYSTEMS - Arrangement of resonators in an aperiodic configurations are described, which can be used for electromagnetic cloaking of objects. The overall assembly of resonators, as structures, do not all repeat periodically and at least some of the resonators are spaced such that their phase centers are separated by more than a wavelength. The arrangements can include resonators of several different sizes and/or geometries arranged so that each size or geometry corresponds to a moderate or high “Q” response that resonates within a specific frequency range, and that arrangement within that specific grouping of akin elements is periodic in the overall structure. The relative spacing and arrangement of groupings can be defined by self similarity and origin symmetry. Fractal based scatters are described. Further described are bondary condition layer structures that can activate and deactive cloaking/lensing structures. | 2011-03-03 |
| 20110050361 | RADIO FREQUENCY FILTER - Parameters of a radio frequency filter can be changed by changing structure of each component of the filter. Material of each component, diameters of each of magnetic cylinders, density of each of conductive coils, thickness of a dielectric layer, and thickness of an insulation tube can be changed. When any component needs to be replaced, each cover is rotated, with connection partitions move to two slots of a resisting portion, to detach the filter. | 2011-03-03 |
| 20110050362 | RADIO FREQUENCY FILTER AND FILTERING UNIT THEREOF - Parameters of a radio frequency filter can be changed by changing structure of each component of the filter. Material of each component, diameters of each of magnetic cylinders, density of each of conductive coils, thickness of a dielectric layer, and thickness of an insulation tube can be changed. When any component needs to be replaced, each cover is rotated, with connection partitions move to two slots of an insulation portion, to detach the filter. | 2011-03-03 |
| 20110050363 | ACTIVE LOW PASS FILTER - The invention relates to a selective active low-pass filter and to a method for improving the selectivity of such a filter. The method consists in centring, in the centre of the network, the resonant element whose frequency is closest to the cut-off frequency of the filter and in inserting in series with this element a negative resistance of higher value than the parasitic resistance of the filter. | 2011-03-03 |
| 20110050364 | PRINTED MULTILAYER FILTER METHODS AND DESIGNS USING EXTENDED CRLH (E-CRLH) - Printed multilayer filter design techniques and filters based on metamaterial structures including an extended composite left and right handed (E-CRLH) metamaterial unit cell. | 2011-03-03 |
| 20110050365 | SIGNAL TRANSMISSION APPARATUS - A signal transmission apparatus includes a first ground layer, a second ground layer and a band pass filter. The band pass filter includes a first transmission line positioned in a void defined in the first ground layer and a second transmission line positioned in a void defined in the second ground layer. Each of the first transmission line and the second transmission line includes a coil with a plurality of turns spirally extending in the same plane, a gasket extending from the coil and located in the center of the coil, and a signal terminal extending from extremity of the coil. According to employing the band pass filter, the signal transmission apparatus has filtering function, therefore, quality of signals transmitted through the signal transmission apparatus is improved. | 2011-03-03 |
| 20110050366 | MEMS Resonators Having Resonator Bodies Therein with Concave-Shaped Sides that Support High Quality Factor and Low Temperature Coefficient of Resonant Frequency - A microelectromechanical (MEMs) resonator includes a concave bulk acoustic resonator (CBAR). One embodiment of a CBAR includes a substrate and a resonator body suspended over the substrate by a pair of fixed supports that attach to first and second opposing ends of the resonator body. The resonator body has a first concave-shaped side extending between the first and second ends of the resonator body and a second concave-shaped side extending opposite the first concave-shaped side. The resonator body may be configured to have a minimum spacing of λ/2 between the first and second concave-shaped sides, where λ is a wavelength associated with a resonant frequency of said resonator body. | 2011-03-03 |
| 20110050367 | DIELECTRIC RESONATOR FOR NEGATIVE REFRACTIVITY MEDIUM - A dielectric resonator for a negative refractivity medium, which is coupled to a plurality of substrates, comprises at least one crystal unit, at least one first crystal cube and at least one second crystal cube. The crystal units are arrayed on the substrate. On an identical substrate, each crystal unit has a first spacing with respect to one adjacent crystal unit and a second spacing with respect to another adjacent crystal unit. The first spacing is vertical to the second spacing. Each crystal unit has one first crystal cube and one second crystal cube. A third spacing exists between the first and second crystal cubes. The first and second crystal cubes have a permittivity greater than 20. The present invention adopts the negative refractivity medium to achieve lower dielectric loss. Further, the present invention features isotropy and has low fabrication cost and high industrial utility. | 2011-03-03 |
| 20110050368 | HIGH FREQUENCY DEVICE - A high frequency device having a membrane structure with improved mechanical strength is provided. The high frequency device includes: a substrate having an aperture; a first dielectric layer that is formed from a material having etching selectivity in relation to a material of the substrate and is provided on the substrate to cover the aperture; a second dielectric layer on the first dielectric layer; and a high frequency element provided in a position opposed to the aperture on the second dielectric layer. | 2011-03-03 |
| 20110050369 | INTEGRATED CIRCUIT - An integrated circuit comprising: a substrate; a first transmission line arranged on the substrate, the first transmission line having a first termination; a die having a first surface on the substrate and an opposed second surface, the die being spaced from the first termination; a second transmission line arranged on the second surface of the die, the second transmission line having a second termination; and a bond wire connected between the first termination and the second termination configured to have a length half the wavelength of the signal central frequency. | 2011-03-03 |
| 20110050370 | HIGH ELECTROMAGNETIC TRANSMISSION COMPOSITE STRUCTURE - The invention discloses a high electromagnetic transmission composite structure for reducing the transmission loss of an electromagnetic wave. The high electromagnetic transmission composite structure includes a first composite structure layer, a second composite structure layer, and a first buffer layer. The first composite structure layer has a first thickness and a first dielectric constant. The second composite structure layer has a second thickness and a second dielectric constant. The first buffer is disposed between the first composite structure layer and the second composite structure layer and has a third thickness and a third dielectric constant. The transmission loss of the electromagnetism wave can be adjusted by adjusting the first thickness, the first dielectric constant, the second thickness, the second dielectric constant, the third thickness, and the third dielectric constant. | 2011-03-03 |
