09th week of 2011 patent applcation highlights part 21 |
Patent application number | Title | Published |
20110049670 | Semiconductor Device Including Fuse Having Form of Capacitor - A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode. | 2011-03-03 |
20110049671 | BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT CHIP USING SUCH BONDING PAD STRUCTURE - An integrated circuit chip includes a substrate; a topmost metal layer over the substrate; a lower metal layer on or over the substrate and lower than the topmost metal layer; and at least one bonding pad in the lower metal layer. | 2011-03-03 |
20110049672 | SEMICONDUCTOR DEVICE - A semiconductor device has: a signal pad; a power supply line; a ground line; an inductor section whose one end is connected to the signal pad; a terminating resistor connected between the other end of the inductor section and the power supply line or the ground line. The semiconductor device further has: a first ESD protection element connected to a first node in the inductor section; and a second ESD protection element connected to a second node whose position is different from that of the first node in the inductor section. | 2011-03-03 |
20110049673 | Nanopillar Decoupling Capacitor - Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design. | 2011-03-03 |
20110049674 | INTERDIGITATED VERTICAL PARALLEL CAPACITOR - An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor. | 2011-03-03 |
20110049675 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor provided above a substrate including electrodes and a ferroelectric film provided therebetween, a pad electrode electrically connected to one of the electrodes of the capacitor, the pad electrode being formed above the substrate, the pad electrode having a recess on a surface of the substrate, a protective film covering a part of the pad electrode other than the recess on the exposed surface, and a hydrogen absorbing film on the protective film and the recess of the pad electrode. | 2011-03-03 |
20110049676 | METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER - A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output. | 2011-03-03 |
20110049677 | Buried Layer of An Integrated Circuit - Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed. | 2011-03-03 |
20110049678 | LATERAL BIPOLAR TRANSISTOR WITH COMPENSATED WELL REGIONS - Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance. | 2011-03-03 |
20110049679 | METHOD OF PROCESSING OF NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR WAFER, METHOD OF PRODUCING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer. | 2011-03-03 |
20110049680 | DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS - An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat. | 2011-03-03 |
20110049681 | Semiconductor Structure and a Method of Forming the Same - Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate. | 2011-03-03 |
20110049682 | SYSTEM AND METHOD FOR SUBSTRATE WAFER BACK SIDE AND EDGE CROSS SECTION SEALS - Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column. | 2011-03-03 |
20110049683 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 2011-03-03 |
20110049684 | ANTICOUNTERFEITING SYSTEM AND METHOD FOR INTEGRATED CIRCUITS - An integrated circuit die comprises a device layer comprising a plurality of semiconductor devices; an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths. | 2011-03-03 |
20110049685 | SEMICONDUCTOR DEVICE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - In accordance with the present invention, there is provided a quad flat no leads (QFN) semiconductor device or package including a leadframe wherein the leads of the leadframe are selectively formed so that portions one or more prescribed leads are exposed in a package body of the semiconductor package and electrically connected to an electromagnetic interference (EMI) shielding layer applied to the package body. In certain embodiments of the present invention, one or more tie bars of the leadframe may also be formed so as to be exposed in the package body of the semiconductor package and electrically connected to the shielding layer applied to the package body. Thus, in the present invention, the shielding layer may be electrically connected to one or more leads alone or in combination with one or more tie bars of the leadframe. | 2011-03-03 |
20110049686 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package is provided. The semiconductor package includes a carrier, a die, a metal sheet and a molding compound. The die is disposed on the carrier. The metal sheet has a first portion and a second portion, wherein a receiving space is defined by the first portion and the second portion, and the second portion is electrically connected to the carrier. The molding compound covers the die and the receiving space is filled by at least part of the molding compound. | 2011-03-03 |
20110049687 | ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR - A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer. | 2011-03-03 |
20110049688 | TCP-type semiconductor device - A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads. | 2011-03-03 |
20110049689 | SEMICONDUCTOR DEVICE WITH ACENE HEAT SPREADER - A semiconductor device in which an adhesion between a lead and a sealing body (mold sealing body) is improved to prevent the peering is provided. In a semiconductor device having a semiconductor chip, a plurality of leads electrically connected to the semiconductor chip and mainly made of metal and a sealing body for sealing the semiconductor chip, in order to improve the adhesion between the lead and the sealing body (mold sealing body), a material combination with good lattice matching is used as a combination of a surface material of the lead and a material of the sealing body, and the sealing body mainly made of acene is used. | 2011-03-03 |
20110049690 | Direct contract leadless package for high current devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 2011-03-03 |
20110049691 | SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING THE SAME - A semiconductor package includes a chip, a carrier, a bonding wire and a molding compound. The chip includes a pad. The carrier includes a finger and has an upper surface and a lower surface opposite to the upper surface, wherein the upper surface supports the chip. The bonding wire is extended from the finger to the pad for electrically connecting the chip to the carrier, wherein the bonding wire defines a projection portion on the upper surface of the carrier, a straight line is defined to pass through the finger and pad, there is a predetermined angle between the tangent line of the projection portion at the finger and the straight line. The molding compound seals the chip and the bonding wire, and covers the carrier. | 2011-03-03 |
20110049692 | CONNECTION DEVICE BEWTEEN TRANSISTOR AND LEAD FRAME - A connection device includes a transistor, a lead frame, a first connection member and a second connection member. The signal is electronically connected between the transistor and the lead frame by the first and second connection members. The second connection member is located above the first connection member so as to increase the communication area for the signals and reduce the resistance between the transistor and the lead frame. | 2011-03-03 |
20110049693 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME THEREOF - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 2011-03-03 |
20110049694 | Semiconductor Wafer-To-Wafer Bonding For Dissimilar Semiconductor Dies And/Or Wafers - A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes. | 2011-03-03 |
20110049695 | Semiconductor Device and Method of Forming Pre-Molded Semiconductor Die Having Bumps Embedded in Encapsulant - A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure. | 2011-03-03 |
20110049696 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 2011-03-03 |
20110049697 | ELECTRONIC PACKAGE SYSTEM - Disclosed herein is an electronic package system utilizing a module having a liquid contact material to prevent mechanically and thermally induced strains in an electrical joint. The conductivity of the liquid contact material provides electrical communication between the required electronic components of the package system. The ability of the liquid contact material to flow prevents the creation of stresses and affords an electronic package design tolerant of small displacements or torsions. Thus, the liquid contact material enables a floating contact with high electrical reliability. | 2011-03-03 |
20110049698 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal. | 2011-03-03 |
20110049699 | METHOD OF SEMICONDUCTOR DEVICE PROTECTION, PACKAGE OF SEMICONDUCTOR DEVICE - A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device. | 2011-03-03 |
20110049700 | SEMICONDUCTOR ASSEMBLY THAT INCLUDES A POWER SEMICONDUCTOR DIE LOCATED ON A CELL DEFINED BY FIRST AND SECOND PATTERNED POLYMER LAYERS - A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material. | 2011-03-03 |
20110049701 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a substrate; a semiconductor chip mounted over the substrate; resin encapsulating the semiconductor chip; and a heat dissipation material that is arranged over the semiconductor chip and in contact with the resin, wherein the resin includes a first resin region made of a first resin composition, a second resin region made of a second resin composition, and a mixed layer that is formed between the first and second resin regions and obtained by mixing the first resin composition and the second resin composition. | 2011-03-03 |
20110049702 | SEMICONDUCTOR PACKAGE AND METHOD OF PRODUCING THE SAME - A method of producing a semiconductor package includes setting a radiator member on a semiconductor device that is mounted on a wiring board, said radiator member having a convex surface part on at least a part of a first surface thereof opposite to a second surface thereof to be bonded to the semiconductor device, and pressing the convex surface part of the radiator member towards the semiconductor device in order to align the radiator member and the semiconductor device automatically and to become substantially parallel to each other. | 2011-03-03 |
20110049703 | Flip-Chip Package Structure - A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield. | 2011-03-03 |
20110049704 | SEMICONDUCTOR DEVICE PACKAGES WITH INTEGRATED HEATSINKS - In one embodiment, a semiconductor device package includes a circuit substrate, a chip, a plurality of first solder balls, an encapsulant, and a heatsink. The circuit substrate includes a carrying surface and a plurality of first bonding pads thereon. The chip is disposed on the carrying surface and electrically connected to the circuit substrate. The first bonding pads are located outside of the chip. The first solder balls are disposed on the first bonding pads. The encapsulant is disposed on the carrying surface and covers the chip. The encapsulant includes a plurality of openings exposing the first solder balls. The heatsink is disposed over the encapsulant and bonded to the first solder balls, wherein the heatsink includes a plurality of protrusions on a bonding surface facing the encapsulant, and the protrusions are correspondingly embedded into the first solder balls. | 2011-03-03 |
20110049705 | SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer. | 2011-03-03 |
20110049706 | Front Side Copper Post Joint Structure for Temporary Bond in TSV Application - An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via. | 2011-03-03 |
20110049707 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material. | 2011-03-03 |
20110049708 | Semiconductor Chip Interconnection Structure and Semiconductor Package Formed Using the Same - A semiconductor chip interconnection structure and a semiconductor package formed using the same are provided. The semiconductor chip interconnection structure comprises a chip, a bump assembly and an electrical element. The chip comprises a pad and has a pad aperture from which the pad is exposed. The bump assembly comprises a first bump and a second bump. The first bump is disposed on the pad. The second bump is disposed on the first bump. The outer diameter of the second bump is not less than the outer diameter of the first bump. The electrical element is connected to the bump assembly. | 2011-03-03 |
20110049709 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping. | 2011-03-03 |
20110049710 | INTERCONNECT LAYOUTS FOR ELECTRONIC ASSEMBLIES - Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic device being electrically coupled to the substrate using a plurality of interconnect structures, the interconnect structures being arranged on the electronic device based at least in part on a layout of the substrate. Other embodiments may be described and/or claimed. | 2011-03-03 |
20110049711 | ELLIPTIC C4 WITH OPTIMAL ORIENTATION FOR ENHANCED RELIABILITY IN ELECTRONIC PACKAGES - An arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, disclosed is a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip. | 2011-03-03 |
20110049712 | Wafer Level Stacked Die Packaging - A stacked die package in which an adhesive pad separates a bottom die from a top die. The pad may be in the form of a wall of adhesive about a central hollow area. The bottom die is attached to a base with a low temperature curing adhesive or a snap cure adhesive. | 2011-03-03 |
20110049713 | DUAL CONTACT METALLIZATION INCLUDING ELECTROLESS PLATING IN A SEMICONDUCTOR DEVICE - Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials. | 2011-03-03 |
20110049714 | Illuminant - The invention relates to an illuminant ( | 2011-03-03 |
20110049715 | METHOD FOR DEPOSITING METAL OXIDE FILMS - A method for depositing a metal oxide film on a surface of a supporting body for the film, comprising the steps of: —providing a deposition chamber; —providing a pulsed beam of electrons and plasma in the deposition chamber; —supplying a supporting body in the deposition chamber, the supporting body having a deposition surface; —providing a target body made of a material which comprises the metal oxide in the deposition chamber, the target body having a target surface; —forming a plume of metal oxide ablated from the target surface by means of the impact of the pulsed beam of electrons and plasma against the target surface; and —depositing a metal oxide film on the deposition surface by means of the contact of the plume with the deposition surface. | 2011-03-03 |
20110049716 | STRUCTURES OF AND METHODS AND TOOLS FOR FORMING IN-SITU METALLIC/DIELECTRIC CAPS FOR INTERCONNECTS - A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms. | 2011-03-03 |
20110049717 | INTEGRATED CIRCUITS HAVING TSVS INCLUDING METAL GETTERING DIELECTRIC LINERS - An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer. | 2011-03-03 |
20110049718 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC INSTRUMENT, SEMICONDUCTOR MANUFACTURING APPARATUS, AND STORAGE MEDIUM - When a barrier film is formed on an exposed surface of an interlayer insulation film on a substrate, the interlayer insulation film having a recess formed therein, and a metal wiring to be electrically connected to a metal wiring in a lower layer is formed in the recess, a barrier film having an excellent step coverage can be formed and increase of a wiring resistance can be restrained. An oxide film on a surface of the lower copper wiring exposed to a bottom surface of the interlayer insulation film is reduced or edged so as to remove oxygen on the surface of the copper wiring. Then, by supplying an organic metal compound containing manganese and containing no oxygen, generation of manganese oxide as a self-forming barrier film is selectively allowed on an area containing oxygen, such as a sidewall of the recess and a surface of the interlayer insulation film, while generation of the manganese oxide is not allowed on the surface of the copper wiring. Thereafter, copper is embedded in the recess. | 2011-03-03 |
20110049719 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films. | 2011-03-03 |
20110049720 | Refractory metal nitride capped electrical contact and method for frabricating same - According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device. | 2011-03-03 |
20110049721 | METAL DENSITY AWARE SIGNAL ROUTING - Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit. | 2011-03-03 |
20110049722 | Semiconductor Circuit Structure and Layout Method thereof - A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure. | 2011-03-03 |
20110049723 | METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE - Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers. | 2011-03-03 |
20110049724 | BEOL INTERCONNECT STRUCTURES AND RELATED FABRICATION METHODS - Methods for forming voids in BEOL interconnect structures and BEOL interconnect structures. The methods include forming a temporary feature on a top surface of a first dielectric layer and depositing a second dielectric layer on the top surface of the first dielectric layer. The temporary feature is removed from the second dielectric layer to define a void in the second dielectric layer that is laterally adjacent to a conductive feature in the second dielectric layer. The void operates to reduce the effective dielectric constant of the second dielectric layer, which reduces parasitic capacitance between the conductive feature and other conductors in the BEOL interconnect structure. | 2011-03-03 |
20110049725 | Semiconductor Chip with Contoured Solder Structure Opening - Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first dielectric layer over a first conductor structure of a semiconductor chip and forming a first opening in the first dielectric layer to expose at least a portion of the conductor structure. The first opening defines an interior wall that includes plural protrusions. A solder structure is coupled to the first conductor structure such that a portion of the solder structure is positioned in the first opening. | 2011-03-03 |
20110049726 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip. | 2011-03-03 |
20110049727 | RECESSED INTERLAYER DIELECTRIC IN A METALLIZATION STRUCTURE OF A SEMICONDUCTOR DEVICE - In a complex metallization system, the probability of dielectric breakdown may be reduced by vertically separating a critical area of high electric field strength and an area of reduced dielectric strength of the interlayer dielectric material. For this purpose, the interlayer dielectric material may be recessed after forming the metal regions and/or the metal regions may be increased in height and the corresponding recess may be refilled with an appropriate dielectric material. | 2011-03-03 |
20110049728 | METHOD TO PERFORM ELECTRICAL TESTING AND ASSEMBLY OF ELECTRONIC DEVICES - A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package. | 2011-03-03 |
20110049729 | METHOD FOR PRODUCING A HERMETICALLY SEALED, ELECTRICAL FEEDTHROUGH USING EXOTHERMIC NANOFILM - A method generates at least one electrical connection from at least one electronic component, which is positioned on a substrate inside an encapsulation, to outside the encapsulation. The functional capability of the electrical connection is to be provided at ambient temperatures greater than 140° C. and in the event of large power losses and extreme environmental influences. A reactive nanofilm, having targeted reaction, which can be triggered exothermically by laser, is used to produce hermetically sealed electrical connections. Using the nanofilm, an output of an electrical connection and a contact of the electrical connection to at least one further electrical contact can be provided. | 2011-03-03 |
20110049730 | Device Comprising an Encapsulation Unit - A device in accordance with one embodiment comprises a component ( | 2011-03-03 |
20110049731 | MATERIALS AND METHODS FOR STRESS REDUCTION IN SEMICONDUCTOR WAFER PASSIVATION LAYERS - The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. | 2011-03-03 |
20110049732 | Humidification apparatus and disc assembly thereof - Disclosed herein are a humidification apparatus having a disc assembly, and a disc assembly thereof. The disc assembly includes at least one disc member assembled by stacking, a first clamp disposed at one side of the at least one disc member, and a second clamp disposed at the other side of the at least one disc member. Each of the at least one disc member includes at least one recess part indented on the edge thereof, and the first clamp includes at least one recess connection part inserted into the at least one recess part so as to prevent movement of the at least one disc member. | 2011-03-03 |
20110049733 | Cooling Tower - A water cooling tower having an improved water collection system. The cooling tower has an outer shell, legs, and one or more layers of fill material, through which the water to be cooled moves vertically downward. The water is distributed across the upper surface of the fill material by piping and nozzles. A fan underlying the fill material moves air vertically upward through the fill material. The water collection system, which is positioned below the fill material, has upper and lower troughs which receive water flowing vertically downward through the fill material. Preferably, the lower troughs are positioned beneath the spaces between upper troughs, to catch water falling between the upper troughs. A number of hinged baffles close off the spaces between lower troughs, but rotate upward in response to upward air flow and open the spaces between the lower troughs. | 2011-03-03 |
20110049734 | Method for Preparing Sintered Annular Nuclear Fuel Pellet - A method for fabricating a sintered annular nuclear fuel pellet includes molding nuclear fuel powder or granule, an oxide of a fissile element (M), to fabricate an annular nuclear fuel green body. A rod-like shaped structure is inserted into the annular nuclear fuel green body and sintered in a slight oxidizing gas atmosphere such that the oxide of the fissile element has a balanced O/M ratio higher than a desired O/M ratio (oxygen/fissile element) of a final sintered annular nuclear fuel pellet, while being maintained in a cubic phase. The sintered annular nuclear fuel pellet is then reduced in a reductive gas atmosphere so as to have the desired O/M ratio in the state that the rod-like shaped structure is inserted. | 2011-03-03 |
20110049735 | MANUFACTURING METHOD OF PLANAR OPTICAL WAVEGUIDE DEVICE WITH GRATING STRUCTURE - A method for manufacturing a planar optical waveguide device of which a core includes a plurality of alternatively arranged fin portions and valley portions to form a grating structure, in which the core widths of the valley portions vary along the longitudinal direction, the method including: a high refractive index material layer forming step of forming a high refractive index material layer; a photoresist layer forming step of forming a photoresist layer on the high refractive index material layer; a first exposure step of forming shaded portions on the photoresist layer using a phase-shifting photomask; a second exposure step of forming shaded portions on the photoresist layer using a binary photomask; a development step of developing the photoresist layer; and an etching step of etching the high refractive index material layer using the photoresist pattern resulted from the development step. | 2011-03-03 |
20110049736 | INJECTION MOLDING OF PART HAVING NONUNIFORM THICKNESS - Injection molding of a part having a nonuniform thickness is provided. One disclosed embodiment of an injection molding device includes one or more side walls, a first mold surface intersecting the side walls and being stationary with respect to the side walls, and a second mold surface intersecting the side walls so as to define with the side walls and the first mold surface a cavity configured to receive a metered amount of injected molten thermoplastic material. The second mold surface is moveable toward the first mold surface in such a manner that a first end of the second mold surface moves a larger physical travel distance toward the first mold surface than does a second end of the second mold surface during a molding process. | 2011-03-03 |
20110049737 | DEVICE, METHOD AND USE FOR THE FORMATION OF SMALL PARTICLES - The invention relates to a device for producing small particles of a certain substance. The device includes first inlet means ( | 2011-03-03 |
20110049738 | Methods for making dental prosthesis by three-dimensional printing - This invention relates to methods for making a three-dimensional dental prosthesis using ink-jet printing systems. An ink-jet printer is used to discharge light-curable, wax-like polymerizable material in a layer-by-layer manner to build-up the prosthesis. The methods are particularly useful for making integrated dentures containing a set of artificial teeth. The denture base and set of teeth are made of light-curable, wax-like polymerizable materials comprising a mixture of monomer, oligomer, and light sensitizer. The wax-like materials are dimensionally stable in their uncured states. The denture base and artificial teeth are later light-cured to form a polymerized denture product having high flexural modulus and flexural strength. | 2011-03-03 |
20110049739 | APPARATUS AND PROCESS FOR CONTINUOUS GENERATIVE PRODUCTION - The invention concerns a process for producing products of individual geometry, in particular dental prostheses or dental auxiliary parts, comprising the steps of producing a plurality of products on the surface of a substrate plate by means of selective hardening, in particular by means of selective sintering or melting, in which the material is applied in successive layers, after each layer application one or more predetermined regions of the applied layer is selectively hardened by means of an energy-rich radiation and connected to one or more regions of the subjacent layer, wherein the predetermined regions are predetermined on the basis of a cross-sectional geometry of the product in the respective layer. According to the invention the successive layers are applied in layer planes oriented inclinedly relative to the surface of the substrate plate. The invention further concerns an apparatus for carrying out such a process. | 2011-03-03 |
20110049740 | PROCESS FOR PRODUCTION OF COLOURED POWDER COSMETIC PRODUCTS BY MEANS OF FREEZING - An innovative process is described for production of coloured powder cosmetic products. The process comprises forming a “slurry” ( | 2011-03-03 |
20110049741 | METHOD OF MAKING CERAMIC BODIES HAVING REDUCED SHAPE VARIABILITY - A method of making ceramic bodies having reduced shape variability. Such ceramic bodies include extruded-to-shape substrates and diesel particulate filters. Principal components analysis is used to generate a small number of uncorrelated or independent components from a larger set of inter-correlated measurements. The uncorrelated components can then be used during the forming process to control the shape of ceramic bodies and reduce variability of such shapes. A method for quantifying and subsequently reducing the shape variability of is also described. | 2011-03-03 |
20110049742 | METHOD AND DEVICE FOR INSTALLING AND/OR DEINSTALLING BLOW MOULDS - A method for operating a transforming device for transforming plastic preforms into plastic containers may include at least one blow mould carrier and a multi-part blow mould arranged on the blow mould carrier. A holding connection may be provided between the blow mould and the blow mould carrier. The holding connection between the blow mould carrier and the blow mould may be detached or established in an at least partially automated manner. | 2011-03-03 |
20110049743 | Extrusion Die Flow Modification And Use - An extrusion die is processed to alter the flow of extrudable material through the die by collecting data reflecting flow variations across the face of the die, constructing a graded resistance flow restrictor utilizing the data, and forcing an abrasive machining medium through the flow restrictor and die with the flow restrictor being arranged to deliver higher abrasive flow through die portions initially exhibiting low extrusion rates, the resulting die being useful for the manufacture of ceramic honeycomb bodies exhibiting a reduced incidence of shape defects attributable to die flow variations. | 2011-03-03 |
20110049744 | JIG AND METHOD OF MANUFACTURING AIRCRAFT FRAMES IN A COMPOSITE MATERIAL - The present invention relates to a jig for the manufacture, by means of injection and curing processes, of preforms of composite material frames for aircraft fuselages by using the RTM (resin transfer molding) technology. Two preforms are thus manufactured, one with a C shaped section and another with a L shaped section, together with the preforms of the stabilization ribs for stabilizing the web of the frames and the preform of the roving or staple fiber to cover the gap between the C shaped preform and the L shaped preform. Theses preforms are previously manufactured by any known process for manufacturing preforms. According to a second aspect, the present invention relates to a method of manufacturing composite material load frames for aircraft. | 2011-03-03 |
20110049745 | MANUFACTURING METHOD FOR SOLID ELECTROLYTE SHEET - A manufacturing method for a solid electrolyte sheet includes applying slurry, which contains sulfide-based solid electrolyte powder, a sulfur-containing compound and a solvent, onto a base; and forming the slurry into a sheet. | 2011-03-03 |
20110049746 | Method of manufacturing reinforced electrolyte membrane and membrane electrode assembly - To manufacture by a simple method a reinforced electrolyte membrane obtained by directly impregnating a molten electrolyte resin into a porous reinforced membrane. Further, to easily manufacture a membrane electrode assembly including the reinforced electrolyte membrane by slightly changing the method of manufacturing a reinforced electrolyte membrane. A heated and molten electrolyte resin p is extruded from a resin discharge port | 2011-03-03 |
20110049747 | Process for Bonding Metal Frame with Plastic Material - A process includes preparing the metal frame that is overlaid with an adhesive. The adhesive is heated thereafter, and the adhesive becomes solidified and thus engaged securely with the metal frame. The adhesive is injection molded thereafter, and the molten resin is delivered onto the solidified adhesive to melt the adhesive so as to enable the adhesive to adhere the resin, and after the adhesive and the resin become solid, the resin forms a plastic member securely bound with the metal frame, thus forming the finished product. | 2011-03-03 |
20110049748 | METHOD FOR DEBURRING A CERAMIC FOUNDRY CORE - The present invention relates to a method for deburring a ceramic foundry core ( | 2011-03-03 |
20110049749 | Dynamically Controlled Extrusion - A lighting system is presented that includes a replaceable illumination module removably coupled to a base module. The replaceable illumination module includes one or more solid state lighting elements on a printed circuit board electrically and thermally connected to the base module. The base module may include a heat sink, where the heat sink is in thermal contact with the replaceable illumination module, and dissipates heat generated by the one or more solid state lighting elements during operation of the lighting system. The replaceable illumination module may also include one or more beam conditioning elements for generating a specified beam. The lighting system may be connected to an automated control network and may be automatically controlled thereby, or may be used to control some other system. The heat sink may be generated via a dynamically controllable extrusion die. | 2011-03-03 |
20110049750 | Pultrusion Process for Production of a Continuous Profile - The invention relates to a pultrusion process in which a continuous reinforcement profile is formed by canting of at least one prepreg strip composed of a fiber-reinforced plastics material. The first shaping of the profile takes place in a preform device, which is downstream of a pressure-molding device for final shaping and prehardening. The movement of the profile takes place synchronously with respect to the operating cycle of the pressure-molding device by means of a traction device. By using a cutting device, it is possible to cut the profile to length and/or to subject edges to subsequent mechanical operations to ensure that correct dimensions are maintained. A continuous (pultrusion) gusset is inserted between the prepreg strips in a radius region of the profile. The gusset has an approximately triangular cross sectional geometry and it is formed by a plurality of continuous fibers braided with one another. | 2011-03-03 |
20110049751 | Method Of Fabricating A Low Crystallinity Poly(L-Lactide) Tube - Methods of fabricating a low crystallinity polymer tube for polymers subject to strain-induced crystallization. The low crystallinity tube may be further processed to make an implantable medical device. | 2011-03-03 |
20110049752 | Process for Producing Crosslinked Fluororubber - [Problem] To provide a method for producing a polyol-crosslinking, crosslinked fluororubber product which exhibits low tack properties and significantly increased rubber hardness. | 2011-03-03 |
20110049753 | High molecular weight poly(alpha-olefin) solutions and articles made therefrom - A robust process for the continuous preparation of solutions of high molecular weight UHMW PO that is capable of producing strong materials at high production capacity, is conservative of capital and energy requirements, and the articles made therefrom. | 2011-03-03 |
20110049754 | Methods of Creating Soft Formed Hoses and Molds - A method of forming hoses is provided. The method includes generating a virtual design for at least one of a solid durable core and a hollow sacrificial core. At least one of the solid durable core and the hollow sacrificial core is formed using rapid prototyping. A mold cavity is formed using the solid durable core. The hose is formed about the hollow sacrificial core with the hollow sacrificial core in the mold cavity. | 2011-03-03 |
20110049755 | In mold decoration process - An in mold decoration process includes inserting a film with decorations into a first mold tool cavity side. The first mold tool cavity side is then engaged with a first mold tool core side, and the film in the first mold tool cavity side undergoes a high-pressure heat forming procedure. After the forming procedure, the film is formed with a cavity and maintained in the first mold tool cavity side. The first mold tool cavity side is then disengaged from the first mold tool core side and engaged with a second mold tool core side, and the film undergoes an injection molding procedure. The cavity is injected with a molten resin. After the molding procedure, the molten resin becomes a plastic component bound to the film to form a semi-finished product. The semi-finished product is then ejected out of the first mold tool cavity side and trimmed to form a finished product. | 2011-03-03 |
20110049756 | Escape Route Marking for an Aircraft and Method for Producing an Escape Route Marking - Escape route marking for an aircraft comprising photoluminescent pigments in a carrier material, which luminesce in the dark,
| 2011-03-03 |
20110049757 | HEART VALVE PROSTHESIS AND METHOD OF MANUFACTURE - A cardiac valve prosthesis having a frame and two or more leaflets (preferably three) attached to the frame. The leaflets are attached to the frame between posts, with a free edge which can seal the leaflets together when the valve is closed under back pressure. The leaflets are created in a mathematically defined shape allowing good wash-out of the whole leaflet orifice, including the area close to the frame posts, thereby relieving the problem of thrombus deposition under clinical implant conditions. | 2011-03-03 |
20110049758 | APPARATUS AND METHOD FOR MANUFACTURING ABSORBENT BODY - Fluid absorbent fibers are accumulated in a form die without being interfered by a polymer charging member for charging a superabsorbent polymer. There is provided an apparatus for manufacturing an absorbent body in which while a form die is moved in one direction along a predetermined moving path, fluid absorbent fibers are distributed toward the form die and accumulated in the form die, whereby the absorbent body is formed. A polymer charging member for charging superabsorbent polymer into the form die is disposed to intersect at least a part of a distribution path of the fluid absorbent fibers, and a space through which the fluid absorbent fibers are allowed to pass along the distribution path is formed in the polymer charging member. | 2011-03-03 |
20110049759 | VACUUM TRANSITION FOR SOLDER BUMP MOLD FILLING - A bond metal injection tool can include a fill head having a sealed chamber for containing a molten bond metal (e.g., solder) and a gas, and a nozzle for directing a flow of the molten bond metal into cavities in a major surface of a mold. A pressure control device can controllably apply pressure within the chamber to eject the bond metal from the nozzle into the cavities. The pressure control device may also controllably reduce a pressure within the chamber to inhibit the bond metal from being ejected from the nozzle, such as when the fill head is being moved onto the mold surface from a parking location or when the fill head is being moved off the mold surface onto a parking location. | 2011-03-03 |
20110049760 | NANO PATTERN WRITER - A method for manufacturing a nano pattern writer includes forming one or more grooves on a first layer, depositing a substance on the first layer to form a film on the first layer, polishing the film on the first layer to thereby form a patterned film that fills the one or more grooves on the first layer, placing a second layer over the patterned film to thereby form a layered structure interposing the patterned film between the first layer and the second layer, and removing a part of the first layer and the second layer to thereby expose portions of the patterned film. | 2011-03-03 |
20110049761 | Pattern transfer apparatus and pattern forming method - The pattern transfer apparatus includes: a liquid ejection device having liquid ejection ports through which droplets of liquid are ejected and deposited onto a substrate surface while the liquid ejection device relatively moves to scan the substrate surface in a relative scanning direction; and a stamp having a stamp surface on which a pattern is formed, the stamp surface being applied to the droplets of the liquid on the substrate surface in a stamp application direction while the stamp is relatively moved with respect to the substrate, wherein when defining, on the substrate surface, strips which are straight and parallel to the stamp application direction and have widths substantially equal to diameters of the droplets deposited on the substrate surface, at least one of the strips includes the droplets which are ejected respectively from at least different two of the liquid ejection ports of the liquid ejection device. | 2011-03-03 |
20110049762 | INJECTION MOLDING MACHINE AND INJECTION MOLDING METHOD - An injection molding machine is provided with a mold forming a cavity into which a resin is injected, a liquid supplying device which supplies a liquid continuously to an internal flow channel of the mold during a preparation period prior to injection of the resin and an injection period in which the resin after the preparation period is injected, an electricity supplying device which supplies electricity to an electric heater arranged on the mold at least during a part of the preparation period, thereby heating the mold, and a controller which carries out a predetermined procedure for making different a temperature of a liquid in the internal flow channel between the preparation period and the injection period. | 2011-03-03 |
20110049763 | Method and Device for Injection Molding Plastic Material - The present invention relates to a method and to a device for injection molding plastic material, wherein the starting plastic material to be treated is first subjected to a pretreatment, wherein the plastic material is heated in a receiving container at a temperature below the melting temperature while constantly being mixed, and thereby at the same time is crystallized, dried and/or cleaned and/or the intrinsic viscosity thereof is increased. According to the invention, the plastic material pretreated in this way is transferred into a screw injection molding machine ( | 2011-03-03 |
20110049764 | Substrate cutting apparatus and method for cutting substrate using the same - A substrate cutting apparatus includes a stage configured to support a substrate, a first laser generator configured to emit a first laser beam toward the substrate, the first laser beam being a short-pulse laser beam, and a beam swing unit disposed on a beam path of the first laser beam, the beam swing unit being configured to swing the first laser beam in a predetermined light irradiating section on the substrate, the light irradiating section on the substrate including at least one of a curved line section and a straight line section. | 2011-03-03 |
20110049765 | Methods for Laser Cutting Glass Substrates - A method for cutting a glass article from a strengthened glass substrate having a surface compression layer and a tensile layer includes forming an edge defect in the surface compression layer on a first edge of the strengthened glass substrate. The method further includes propagating a through vent through the surface compression and tensile layers at the edge defect. The through vent precedes a region of separation along a cut line between the glass article and the strengthened glass substrate. | 2011-03-03 |
20110049766 | METHODS OF FORMING GRAPHICS ON A SUBSTRATE AND LASER ACTIVE COATINGS - Methods, articles, and systems for forming a graphic on a substrate and laser-active coatings are provided. One method comprises applying a laser beam to a laser-active coating on a surface of an article to mark a graphic in the laser-active coating, the laser active coating comprising a polymer binder and a pigment. | 2011-03-03 |
20110049767 | SYSTEM, APPARATUS, AND METHOD FOR RESIN LEVEL MAINTENANCE IN A STEREO-LITHOGRAPHY DEVICE - A system includes a stereo-lithography device having a primary fluid vessel having an amount of a photo-curable fluid therein. The system includes a leveling reservoir fluidly coupled to the primary fluid vessel, where a fluid level in the leveling reservoir is vertically positionable. The system further includes a controller that maintains a pre-determined level of the photo-curable fluid in the primary fluid vessel by vertically positioning the fluid level in the leveling reservoir. | 2011-03-03 |
20110049768 | LIQUID CRYSTAL ELASTOMERS WITH TWO-WAY SHAPE ;MEMORY EFFECT - The present invention relates to liquid crystal elastomers having two-way shape memory effect and methods of making such LCEs. The method of preparation includes the steps of polymerizing at least two monomers with crosslinking polymer, prealigning the resultant polymer, crosslinking the resultant polymer, and preparing the liquid crystal elastomer. The liquid crystal elastomer can be drawn to fibers. | 2011-03-03 |
20110049769 | METHOD FOR PRODUCTION OF INORGANIC NANOFIBRES THROUGH ELECTROSTATIC SPINNING - The present disclosure relates to the production method of inorganic nanofibres through electrostatic spinning of solution, which comprises alkoxide of metal or of semi-metal or of non-metal dissolved in a solvent system on basis of alcohol. The solution is stabilised by chelating agent, which prevents hydrolysis of alkoxide, and after homogenisation it is mixed with solution of poly(vinylpyrrolidone) in alcohol, after then the resultant solution is brought into electrostatic field, in which the electrostatic spinning is running continually, the result of which is production of organic-inorganic nanofibres, which are after then calcinated outside the spinning device in the air atmosphere at the temperature from 500° C. to 1300° C. | 2011-03-03 |