| 09th week of 2011 patent applcation highlights part 20 |
| Patent application number | Title | Published |
|---|
| 20110049570 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent ohmic contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of In | 2011-03-03 |
| 20110049571 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE - Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent schottky contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of In | 2011-03-03 |
| 20110049572 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode. | 2011-03-03 |
| 20110049573 | GROUP III NITRIDE SEMICONDUCTOR WAFER AND GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of Al | 2011-03-03 |
| 20110049574 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode. | 2011-03-03 |
| 20110049575 | Semiconductor integrated circuit - Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≧2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≧M≧2) times the basic cell length which is appropriate to the single complementary transistor pair. | 2011-03-03 |
| 20110049576 | Homogenous Cell Array - A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column. | 2011-03-03 |
| 20110049577 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 2011-03-03 |
| 20110049578 | ELECTRIC COMPONENT AND METHOD OF MANUFACTURING THE ELECTRIC COMPONENT - According to one embodiment, an electric component includes: a first insulating layer formed on a first wire; a second wire and a functional element formed on the first insulating layer; a second insulating layer formed on the first insulating layer; and a connection wire that connects the second wire and the first wire. In the connection wire, a first via, a second via, and an inter-via wire are integrally formed of the same material. The first via is formed in the second insulating layer. The second via is formed in the first and second insulating layers. | 2011-03-03 |
| 20110049579 | THIN-FILM TRANSISTOR BASED PIEZOELECTRIC STRAIN SENSOR AND METHOD - A piezoelectric strain sensor and method thereof for detecting strain, vibration, and/or pressure. The sensor incorporates a sequence of piezoelectric and semiconductor layers in a thin-film transistor structure. The thin-film transistor structure can be configured on a flexible substrate via a low-cost fabrication technique. The piezoelectric layer generates an electric charge resulting in a modulation of a transistor current, which is a measure of external strain. The sensor can be formed as a single gate field-effect piezoelectric sensor and a dual gate field-effect piezoelectric sensor. The semiconductor layer can be configured from a nanowire array resulting in a metal-piezoelectric-nanowire field effect transistor. The single and dual gate field-effect piezoelectric sensor offer increased sensitivity and device control due to the presence of the piezoelectric layer in the transistor structure and low cost manufacturability on large area flexible substrates. | 2011-03-03 |
| 20110049580 | Hybrid Packaged Gate Controlled Semiconductor Switching Device Using GaN MESFET - A hybrid packaged gate controlled semiconductor switching device (HPSD) has an insulated-gate transistor (IGT) made of a first semiconductor die and a rectifying-gate transistor (RGT) made of a second semiconductor die. The RGT gate and source are electrically connected to the IGT source and drain respectively. The HPSD includes a package base with package terminals for interconnecting the HPSD to external environment. The IGT is die bonded atop the package base. The second semiconductor die is formed upon a composite semiconductor epi layer overlaying an electrically insulating substrate (EIS) thus creating a RGT die. The RGT die is stacked and bonded atop the IGT die via the EIS. The IGT, RGT die and package terminals are interconnected with bonding wires. Thus, the HPSD is a stacked package of IGT die and RGT die with reduced package footprint while allowing flexible placements of device terminal electrodes on the IGT. | 2011-03-03 |
| 20110049581 | SEMICONDUCTOR STRUCTURE AND METHOD - A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer. | 2011-03-03 |
| 20110049582 | ASYMMETRIC SOURCE AND DRAIN STRESSOR REGIONS - A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region. | 2011-03-03 |
| 20110049583 | Recessed contact for multi-gate FET optimizing series resistance - A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h | 2011-03-03 |
| 20110049584 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, may include a semiconductor substrate including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type different from the first conductivity type, the first semiconductor having a resistance value in a range from 100 Ω·cm to 10000 Ω·cm, the second semiconductor layer having a resistance value in a range from 100 Ω·cm to 10000 Ω·cm, the second semiconductor layer provided on the first semiconductor layer, a first region being formed in the second semiconductor layer and including a first conductivity type of well region and a second conductivity type of well region, a first insulating layer formed on the second semiconductor layer; and a wiring layer located in a second region different from the first region and constituting a passive device insulated by the first insulating layer, wherein no well region is formed in the second semiconductor layer located in the second region. | 2011-03-03 |
| 20110049585 | MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATION USING AN OXYGEN PLASMA - In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage. | 2011-03-03 |
| 20110049586 | Device to Detect and Measure Static Electric Charge | 2011-03-03 |
| 20110049587 | Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device - Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method. | 2011-03-03 |
| 20110049588 | Semiconductor Device and Manufacturing Method Thereof - An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion element with excellent characteristics. An object of an embodiment of the disclosed invention is to provide a semiconductor device including a photoelectric conversion device with excellent characteristic through a simple process. A semiconductor device is provided, which includes a light-transmitting substrate; an insulating layer over the light-transmitting substrate; and a photoelectric conversion element over the insulating layer. The photoelectric conversion element includes a single crystal semiconductor layer including a semiconductor region having an effect of photoelectric conversion, a semiconductor region having a first conductivity type, and a semiconductor region having a second conductivity type; a first electrode electrically connected to the semiconductor region having the first conductivity type; and a second electrode electrically connected to the semiconductor region having the second conductivity type. | 2011-03-03 |
| 20110049589 | BACKSIDE ILLUMINATED IMAGE SENSOR HAVING CAPACITOR ON PIXEL REGION - A backside illuminated image sensor includes a semiconductor substrate having a front side and backside, a sensor element formed overlying the frontside of the semiconductor substrate, and a capacitor formed overlying the sensor element. | 2011-03-03 |
| 20110049590 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A solid-state imaging device that includes at least one pixel. The pixel includes a photodiode, a floating diffusion element in a region of the photodiode and a read out gate electrode at least partially surrounding the floating diffusion element in plan view. | 2011-03-03 |
| 20110049591 | SOLID-STATE IMAGING DEVICE, PROCESS OF MAKING SOLID STATE IMAGING DEVICE, DIGITAL STILL CAMERA, DIGITAL VIDEO CAMERA, MOBILE PHONE, AND ENDOSCOPE - A solid-state imaging device includes an array of pixels, each pixel includes: a pixel electrode; an organic layer; a counter electrode; a sealing layer; a color filter; a readout circuit; and a light-collecting unit as defined herein, the photoelectric layer contains an organic p type semiconductor and an organic n type semiconductor, the organic layer further includes a charge blocking layer as defined herein, an ionization potential of the charge blocking layer and an electron affinity of the organic n type semiconductor in the photoelectric layer has a difference of at least 1 eV, and the sealing layer includes a first sealing sublayer formed by atomic layer deposition and a second sealing sublayer formed by physical vapor deposition and containing one of a metal oxide, a metal nitride, and a metal oxynitride. | 2011-03-03 |
| 20110049592 | NONVOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region. | 2011-03-03 |
| 20110049593 | Semiconductor Component - A semiconductor component comprising a semiconductor body, a channel zone in the semiconductor body, a channel control electrode adjacent to the channel zone, and a dielectric layer between the channel zone and the channel control electrode, wherein the dielectric layer has a relative dielectric constant ε | 2011-03-03 |
| 20110049594 | SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION - A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer. | 2011-03-03 |
| 20110049595 | METHOD FOR FORMING MEMORY CELL TRANSISTOR - A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. The formed memory cell transistor thus comprises a hole structure which is formed from the surface of the top first conductive layer, extending downwards through the first conductive layers and the dielectric layers, and reaching the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure. | 2011-03-03 |
| 20110049596 | Semiconductor Device Having Impurity Doped Polycrystalline Layer Including Impurity Diffusion Prevention Layer and Dynamic Random Memory Device Including the Semiconductor Device - Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers. | 2011-03-03 |
| 20110049597 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device including two or more capacitors having different sizes formed in separated regions and operating at a low voltage, the non-volatile memory device including: a conductive semiconductor substrate formed of a first conductive material; a conductive separation layer provided on at least one portion of the first conductive semiconductor substrate and formed of a second conductive material different from the first conductive material, and which separates an inside of the first conductive semiconductor substrate into a first region and a second region; an insulation layer provided on the first region and the second region to contact the first region and the second region; a charge storage layer provided on the insulation layer; a control gate electrically connected to the first region; and a data line electrically connected to the second region. | 2011-03-03 |
| 20110049598 | MANUFACTURING METHOD OF FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE SEMICONDUCTOR DEVICE - A layered film of a three-layer clad foil formed with a first metal layer | 2011-03-03 |
| 20110049599 | SEMICONDUCTOR DEVICE - In Trench-Gate Fin-FET, in order that the advantage which is exerted in Fin-FET can be sufficiently taken even if a transistor becomes finer and, at the same time, decreasing of on-current can be suppressed by saving a sufficiently large contact area in the active region, a fin width | 2011-03-03 |
| 20110049600 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film. | 2011-03-03 |
| 20110049601 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate, conductive members, an interlayer insulating film, and a plurality of contacts. The conductive members are provided in an upper portion of the substrate or above the substrate to extend in one direction. The interlayer insulating film is provided on the substrate and the conductive members. The plurality of contacts is provided in the interlayer insulating film. In a first region on the substrate, the contacts are located at some of lattice points of an imaginary first lattice. In a second region on the substrate, the contacts are located at some of lattice points of an imaginary second lattice. The second lattice is different from the first lattice. Each of the first lattice and the second lattice includes some of the lattice points located on the conductive members or on an extension region extended in the one direction of the conductive members. A position of each of the lattice points located on the conductive members and the extension region in the one direction is periodically displaced based on every n consecutively-arranged conductive members (n is a natural number). | 2011-03-03 |
| 20110049602 | NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A gate insulating film layer, a floating gate electrode layer, an interelectrode insulating film layer, and a control gate electrode layer are stacked on a silicon substrate, and the control gate electrode film layer is etched to form a plurality of the control gate electrodes having the same width with the width of the memory cell. An arbitrary of the plurality of control gate electrodes is a transistor unit, and an interelectrode insulating film, a floating gate electrode, and a gate insulating film are formed in the transistor unit. In the transistor unit, a conductive material is buried into a contact hole to form a transistor, the contact hole is formed along the plurality of control gate electrodes. | 2011-03-03 |
| 20110049603 | Reverse Disturb Immune Asymmetrical Sidewall Floating Gate Devices and Methods - Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed. | 2011-03-03 |
| 20110049604 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area. | 2011-03-03 |
| 20110049605 | SPLIT GATE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SPLIT GATE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A split gate nonvolatile semiconductor storage device includes: a substrate; a floating gate; a control gate; a first source/drain diffusion layer; a second source/drain diffusion layer; and a silicide. The floating gate is formed on the substrate through a gate insulating film. The control gate is formed adjacent to the floating gate through a tunnel insulating film. The first source/drain diffusion layer is formed in a surface region of the substrate on a side of the floating gate. The second source/drain diffusion layer is formed in a surface region of the substrate on a side of the control gate. The silicide contacts the first source/drain diffusion layer. | 2011-03-03 |
| 20110049606 | CHARGE-TRAP BASED MEMORY - Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described. | 2011-03-03 |
| 20110049607 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole. | 2011-03-03 |
| 20110049608 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity. | 2011-03-03 |
| 20110049609 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device has: a first source/drain diffusion region; a second source/drain diffusion region; a channel region between the first source/drain diffusion region and the second source/drain diffusion region; a first charge storage layer formed on the channel region; a second charge storage layer formed in a same layer as the first charge storage layer and electrically isolated from the first charge storage layer; a first gate electrode; and a second gate electrode electrically isolated from the first gate electrode. The first charge storage layer includes a first memory section and a second memory section. The second charge storage layer includes a third memory section and a fourth memory section. The first gate electrode is formed on the first memory section and the third memory section. The second gate electrode is formed on the second memory section and the fourth memory section. | 2011-03-03 |
| 20110049610 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided are a nonvolatile memory device and a method of forming the same. The nonvolatile memory device includes: a semiconductor substrate including a device isolation layer defining an active region; a tunnel insulating layer on the active region; a charge trapping layer on the tunnel insulating layer; a blocking insulating layer on the charge trapping layer and the device isolation layer; a gate electrode on the blocking insulating layer; and a barrier capping layer formed between the device isolation layer and the blocking insulating layer. | 2011-03-03 |
| 20110049611 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked. | 2011-03-03 |
| 20110049612 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer. | 2011-03-03 |
| 20110049613 | ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF - A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer. | 2011-03-03 |
| 20110049614 | SUPER JUNCTION TRENCH POWER MOSFET DEVICES - In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant. | 2011-03-03 |
| 20110049615 | POWER SEMICONDUCTOR DEVICE - According to one embodiment, a power semiconductor device includes a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type periodically disposed repeatedly along a surface of the first semiconductor layer on a first semiconductor layer of the first conductivity type. A first main electrode is provided to electrically connect to the first semiconductor layer. A fourth semiconductor layer of the second conductivity type is provided to connect to the third semiconductor layer. Fifth semiconductor layers of the first conductivity type are selectively provided in the fourth semiconductor layer surface. A second main electrode is provided on a surface of the fourth and fifth semiconductor layers. A control electrode is provided on a surface of the fourth, fifth, and second semiconductor layers via a gate insulating film. First insulating films are provided by filling a trench made in the second semiconductor layer. | 2011-03-03 |
| 20110049616 | SEMICONDUCTOR STRUCTURE FOR A POWER DEVICE AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions. | 2011-03-03 |
| 20110049617 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate and a plurality of material layers. The substrate includes a concave portion having a bottom surface and a side surface, and a protruded portion extended from the side surface. The plurality of material layers have flat portions on the bottom surface and side portions extended over the side surface from the flat portions, and spaced from each other. Here, at least one of the sidewall portions of the material layers has a thickness greater than a thickness of the flat portions of the material layers. | 2011-03-03 |
| 20110049618 | FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE - Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure. | 2011-03-03 |
| 20110049619 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing the semiconductor device forms a recess gate region on a semiconductor substrate, forms an isolation layer isolated from the recess gate region using a high-temperature thermal process, and guarantees a larger channel region by filling the isolation layer with a gate electrode material, so that a cell current is increased and on/off characteristics of a transistor are improved. | 2011-03-03 |
| 20110049620 | Method for fabricating a MOS transistor with source/well heterojunction and related structure - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon. | 2011-03-03 |
| 20110049621 | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. | 2011-03-03 |
| 20110049622 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has an insulating film and an n-type buried layer. The insulating film is formed in a flat-shaped cavity formed inside a p-type semiconductor substrate and in a trench extending from a surface of the semiconductor substrate to the cavity. The buried layer is formed in surrounding regions of the cavity and the trench in the semiconductor substrate. | 2011-03-03 |
| 20110049623 | Short Channel Lateral MOSFET and Method - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region. | 2011-03-03 |
| 20110049624 | MOSFET ON SILICON-ON-INSULATOR REDX WITH ASYMMETRIC SOURCE-DRAIN CONTACTS - A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region. | 2011-03-03 |
| 20110049625 | ASYMMETRICAL TRANSISTOR DEVICE AND METHOD OF FABRICATION - Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region. | 2011-03-03 |
| 20110049626 | ASYMMETRIC EMBEDDED SILICON GERMANIUM FIELD EFFECT TRANSISTOR - A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region. | 2011-03-03 |
| 20110049627 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 2011-03-03 |
| 20110049628 | SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THE SAME, AND PLASMA DOPING SYSTEM - A fin-semiconductor region ( | 2011-03-03 |
| 20110049629 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin. | 2011-03-03 |
| 20110049630 | Stressed Source/Drain CMOS and Method of Forming Same - A complementary metal-oxide semiconductor (CMOS) structure includes a substrate and a P-type field effect transistor (FET) and an N-type FET disposed adjacent to one another on the substrate. Each FET includes a silicon-on-insulator (SOI) region, a gate electrode disposed on the SOI region, a source stressor, and a drain stressor disposed across from the source stressor relative to the gate electrode, wherein proximities of the source stressor and the drain stressor to a channel of a respective FET are substantially equal. | 2011-03-03 |
| 20110049631 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING INSULATED GATE FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor integrated circuit is provided a first well region, a second well region, a first body bias supply unit and a second body bias supply unit. The first well region includes a first transistor having a first threshold voltage. The second well region includes a second transistor having an absolute value of a second threshold voltage higher than an absolute value of the first threshold voltage. The second well region is separated from the first well region. The second well region has the same conductive type as the first well region. The first body bias supply unit supplies a first body bias voltage to the first well region. The second body bias supply unit supplies a second body bias voltage to the second well region. | 2011-03-03 |
| 20110049632 | SEMICONDUCTOR DEVICE - A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad. | 2011-03-03 |
| 20110049633 | LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING THEREOF AND ELECTRONIC APPLIANCE - An object of the invention is to provide a method for manufacturing a light emitting device capable of reducing deterioration of elements due to electrostatic charge caused in manufacturing the light emitting device. Another object of the invention is to provide a light emitting device in which defects due to the deterioration of elements caused by the electrostatic charge are reduced. The method for manufacturing the light emitting device includes a step of forming a top-gate type transistor for driving a light emitting element. In the step of forming the top-gate type transistor, when processing a semiconductor layer, a first grid-like semiconductor layer extending in rows and columns is formed over a substrate. The plurality of second island-like semiconductor layers are formed between the first semiconductor layer. The plurality of second island-like second semiconductor layers serve as an active layer of the transistor. | 2011-03-03 |
| 20110049634 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate ( | 2011-03-03 |
| 20110049635 | HANDSHAKE STRUCTURE FOR IMPROVING LAYOUT DENSITY - A semiconductor device includes a gate on a semiconductor substrate. One side wall of the gate may include at least one protrusion and an opposite side wall of the gate may include at least one depression. A contact is formed through an insulating layer disposed over the gate. The contact at least partially overlaps at least one of the protrusions in the gate. A metal layer is disposed on the insulating layer. The metal layer includes a first structure shifted to a first side of the gate. The first structure at least partially overlaps the contact such that the contact electrically couples the first structure to the gate through the insulating layer. | 2011-03-03 |
| 20110049636 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor memory device includes a semiconductor substrate, and isolation layers formed in a surface of the semiconductor substrate, and separating the semiconductor substrate into active areas, the isolation layers and the active areas being alternately arranged along a predetermined direction parallel to the surface of the semiconductor substrate, a height of upper surfaces of the isolation layers being lower than a height of an upper surface of the semiconductor substrate. The device further includes diffusion layers formed on surfaces of the active areas, and a stress liner formed on upper surfaces and side surfaces of the diffusion layers, and formed of a material having a lattice constant smaller than a lattice constant of a material formed of the semiconductor substrate. | 2011-03-03 |
| 20110049637 | BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES - Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material. | 2011-03-03 |
| 20110049638 | STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS - An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench. | 2011-03-03 |
| 20110049639 | INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT - A method is disclosed of manufacturing an integrated circuit. The method comprises providing a substrate ( | 2011-03-03 |
| 20110049640 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER - In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures. | 2011-03-03 |
| 20110049641 | STRESS ADJUSTMENT IN STRESSED DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY STRESS RELAXATION BASED ON RADIATION - In sophisticated semiconductor devices, an efficient adjustment of an intrinsic stress level of dielectric materials, such as contact etch stop layers, may be accomplished by selectively exposing the dielectric material to radiation, such as ultraviolet radiation. Consequently, different stress levels may be efficiently obtained without requiring sophisticated stress relaxation processes based on ion implantation, which typically leads to significant device failures. | 2011-03-03 |
| 20110049642 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS - In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided. | 2011-03-03 |
| 20110049643 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor device including forming a gate structure includes a metal gate electrode on a semiconductor substrate, forming two first sidewalls of an insulating material on both side surfaces of the gate structure, introducing impurity into the semiconductor substrate using the first sidewalls as a mask, and forming two extension regions of a first conductivity type and two halo regions of a second conductivity type deeper than the extension regions in the semiconductor substrate, forming two recess regions on the semiconductor substrate by etching the semiconductor substrate using the first sidewalls as a mask, forming SiGe layers in the recess regions, forming two second sidewalls of an insulating material on side surfaces of the first sidewalls, and dry etching the mask layer. | 2011-03-03 |
| 20110049644 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions. | 2011-03-03 |
| 20110049645 | STRUCTURE WITH REDUCED FRINGE CAPACITANCE - A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack. | 2011-03-03 |
| 20110049646 | Semiconductor Device and Method of Forming the Same - Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed. | 2011-03-03 |
| 20110049647 | METHOD AND APPARATUS FOR TUNABLE ELECTRICAL CONDUCTIVITY - An embodiment relates a method comprising creating a reversible change in an electrical property by adsorption of a gas by a composition, wherein the composition comprises a noble metal-containing nanoparticle and a single walled carbon nanotube. Another embodiment relates to a method comprising forming a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube and forming a device containing the said composition. Yet another method relates to a device comprising a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube on a silicon wafer, wherein the composition exhibits a reversible change in an electrical property by adsorption of a gas by the composition. | 2011-03-03 |
| 20110049648 | MEMS DEVICE WITH STRESS ISOLATION AND METHOD OF FABRICATION - A MEMS device ( | 2011-03-03 |
| 20110049649 | INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING THE SAME - Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material. | 2011-03-03 |
| 20110049650 | Electro-Mechanical Transistor - An electromechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode. | 2011-03-03 |
| 20110049651 | THREE-DIMENSIONAL MEMS STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a three-dimensional (3D) MEMS structure and a method of manufacturing the same. The method of manufacturing the 3D MEMS structure having a floating structure includes depositing a first etch mask on a substrate, etching at least two regions of the first etch mask to expose the substrate, and forming at least one step in the etched region, partially etching the exposed region of the substrate using the first etch mask, and forming at least two grooves, depositing a second etch mask on a sidewall of the groove, and performing an etching process to connect lower regions of the at least two grooves to each other, and forming at least one floating structure. | 2011-03-03 |
| 20110049652 | METHOD AND SYSTEM FOR MEMS DEVICES - A micro electro-mechanical (MEMS) device assembly is provided. The MEMS device assembly includes a first substrate that has a plurality of electronic devices, a plurality of first bonding regions, and a plurality of second bonding regions. The MEMS device assembly also includes a second substrate that is bonded to the first substrate at the plurality of first bonding regions. A third substrate having a recessed region and a plurality of standoff structures is disposed over the second substrate and bonded to the first substrate at the plurality of second bonding regions. The plurality of first bonding regions provide a conductive path between the first substrate and the second substrate and the plurality of the second bonding regions provide a conductive path between the first substrate and the third substrate. | 2011-03-03 |
| 20110049653 | MEMS SENSOR, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING MEMS SENSOR - An MEMS sensor includes: a fixation frame section; a movable weight section coupled to the fixation frame section via an elastically deformable section; a fixed electrode section extending from the fixation frame section toward the movable weight section; a movable electrode section extending from the movable weight section toward the fixation frame section, and disposed so as to be opposed to the fixed electrode section via a gap; a capacitance section composed mainly of the fixed electrode section and the movable electrode section; and an active element provided to the movable weight section. | 2011-03-03 |
| 20110049654 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer over the MTJ cap layer. The top electrode layer includes a first nitrified metal. | 2011-03-03 |
| 20110049655 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 2011-03-03 |
| 20110049656 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming a top electrode layer over an MTJ structure. The top electrode layer includes a first nitrified metal. | 2011-03-03 |
| 20110049657 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines. | 2011-03-03 |
| 20110049658 | MAGNETIC TUNNEL JUNCTION WITH ELECTRONICALLY REFLECTIVE INSULATIVE SPACER - Magnetic tunnel junctions having a specular insulative spacer are disclosed. The magnetic tunnel junction includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, and an electrically insulating and electronically reflective layer positioned to reflect at least a portion of electrons back into the free magnetic layer. | 2011-03-03 |
| 20110049659 | MAGNETIZATION CONTROL METHOD, INFORMATION STORAGE METHOD, INFORMATION STORAGE ELEMENT, AND MAGNETIC FUNCTION ELEMENT - The present invention provides a magnetization control method controlling, utilizing no current-induced magnetic field or spin transfer torque a magnetization direction with low power consumption, an information storage method, an information storage element, and a magnetic function element. The magnetization control method involves controlling a magnetization direction of a magnetic layer, and includes: forming a structure including (i) the magnetic layer which is an ultrathin film ferromagnetic layer having a film thickness of one or more atomic layers and of 2 nm or less, and (ii) an insulating layer provided on the ultrathin film ferromagnetic layer and working as a potential barrier; and controlling a magnetization direction of the ultrathin film ferromagnetic layer by applying either (i) a voltage to opposing electrodes sandwiching the structure and a base layer or (ii) an electric field to the structure to change magnetic anisotropy of the ultrathin film ferromagnetic layer. The magnetization control method further involves controlling a waveform of the applied voltage or the applied electric field to switch the magnetization direction. | 2011-03-03 |
| 20110049660 | WAVEGUIDE PHOTO-DETECTOR - Provided is a waveguide photodetector that may improve an operation speed and increase or maximize productivity. The waveguide photodetector includes a waveguide layer extending in a first direction, an absorption layer disposed on the waveguide layer, a first electrode disposed on the absorption layer, a second electrode disposed on the waveguide layer, the second electrode being spaced from the first electrode and the absorption layer in a second direction crossing the first direction, and at least one bridge electrically connecting the absorption layer to the second electrode. | 2011-03-03 |
| 20110049661 | SOLID-STATE IMAGING DEVICE AND PROCESS OF MAKING SOLID STATE IMAGING DEVICE - A solid state imaging device includes an array of pixels, each of the pixels includes: a pixel electrode; an organic layer; a counter electrode; a sealing layer; a color filter; and a readout circuit as defined herein, the photoelectric layer contains an organic p type semiconductor and an organic n type semiconductor, an ionization potential of the charge blocking layer and an electron affinity of the organic n type semiconductor in the photoelectric layer have a difference of at least 1 eV, and the solid-state imaging device further includes a transparent partition wall between adjacent color filters of adjacent pixels of the array of pixels, the partition wall being made from a transparent material having a lower refractive index than a material forming the color filters. | 2011-03-03 |
| 20110049662 | Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device - A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias. | 2011-03-03 |
| 20110049663 | Structure of photodiode array - A structure of photodiode array includes a first electrode on which a plurality of second electrodes is arranged in a spaced manner forming an array and a plurality of isolation sections, which is each formed between adjacent ones of the spaced and arrayed second electrodes, whereby in carrying out tests of light currents, correct detection of the light currents can be realized to improve cross-talking between adjacent dodoes so as to effectively suppress interference of noise and alleviate the problem of low S/N ratio. | 2011-03-03 |
| 20110049664 | EPITAXIAL SUBSTRATE FOR BACK-ILLUMINATED IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Provided is an epitaxial substrate for a back-illuminated image sensor and a manufacturing method thereof that is capable of suppressing metal contaminations and reducing occurrence of a white spot defect of the image sensor, by maintaining a sufficient gettering performance in a device process. The present invention includes forming a gettering sink immediately below a surface of a high-oxygen silicon substrate, forming a first epitaxial layer on the surface of the high-oxygen silicon substrate, and forming a second epitaxial layer on the first epitaxial layer, in which the step of forming the gettering sink includes forming an oxygen precipitate region by applying a long-time heat treatment at a temperature of 650-1150° C. to the high-oxygen silicon substrate. | 2011-03-03 |
| 20110049665 | IMAGE PICKUP DEVICE AND IMAGE PICKUP APPARATUS - An image pickup device includes a plurality of first electrodes, a second electrode, a third electrode, a photoelectric conversion layer, a plurality of signal reading portions, at least one of electric potential adjusting portions. The plurality of first electrodes is arranged on an upper side of a substrate in two dimensions with a predetermined gap interposed between one of the first electrodes and another first electrode adjacent to the one of the first electrode. The second electrode is arranged next to the first electrodes arranged on an outermost side of the first electrodes with the predetermined gap interposed between the first electrodes arranged on the outermost side and the second electrode. The third electrode faces both of the plurality of first electrodes and the second electrode. The photoelectric conversion layer is disposed between the plurality of first electrodes and the second electrode and the third electrode. | 2011-03-03 |
| 20110049666 | GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF - A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask. | 2011-03-03 |
| 20110049667 | Semiconductor Component With Dielectric Layer Stack - A semiconductor component has a semiconductor body zone, a first electrically conductive layer adjacent to the semiconductor body zone, a first dielectric layer with first dielectric properties and a second dielectric layer with second dielectric properties. The first dielectric properties differ from the second dielectric properties. The first dielectric layer and the second dielectric layer are arranged between the semiconductor body zone and the first electrically conductive layer. A second electrically conductive layer is applied between the first dielectric layer and the second dielectric layer. A first voltage divider is switched between the first electrically conductive layer and the semiconductor body zone. The second electrically conductive layer is electrically conductively connected only to the voltage divider. | 2011-03-03 |
| 20110049668 | DEEP TRENCH ISOLATION STRUCTURES BETWEEN HIGH VOLTAGE SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - Deep trench isolation structures between high voltage semiconductor devices and fabrication methods thereof are presented. The high voltage semiconductor device includes a semiconductor substrate, pluralities of intersecting deep trench isolation structures defining several high voltage semiconductor device regions, and an island at the center of the intersection between the two deep trench isolation structures, wherein the two intersecting deep trench isolation structures h | 2011-03-03 |
| 20110049669 | METHOD FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE - A method for forming an isolation layer of a semiconductor device includes forming a trench in a substrate, forming a high-density plasma (HDP) oxide layer filling a portion of the trench, forming a spin-on-dielectric (SOD) oxide layer having a certain height over the HDP oxide layer, performing a thermal treatment, and forming an enhanced high-aspect-ratio process (eHARP) oxide layer filling another portion of the trench over the SOD oxide layer. | 2011-03-03 |
