09th week of 2013 patent applcation highlights part 28 |
Patent application number | Title | Published |
20130052727 | COMPOSITIONS AND METHODS FOR AUTOLOGOUS GERMLINE MITOCHONDRIAL ENERGY TRANSFER - Oogonial stem cell (OSC)-derived compositions, such as nuclear free cytoplasm or isolated mitochondria, and uses of OSC-derived compositions in autologous fertility-enhancing procedures are described. | 2013-02-28 |
20130052728 | COMPOSITIONS AND METHODS FOR MAKING AND USING BONE MARROW MESENCHYMAL STEM CELLS AND ERYTHROID PROGENITOR CELLS - The invention provides compositions for making erythroid progenitor cells that comprise in vitro-activated bone marrow mesenchymal stem cells and embryoid bodies (EBs) or pluripotent stem cells, and methods for making and using them, including ameliorating (e.g., preventing or treating) anemia and/or stimulating erythropoiesis. In one embodiment, the invention provides methods of increasing propensity of committed stem cell differentiation towards the erythroid lineage. | 2013-02-28 |
20130052739 | NOVEL FRT RECOMBINATION SITES AND METHODS OF USE - Methods and compositions using populations of randomized modified FRT recombination sites to identify, isolate and/or characterize modified FRT recombination sites are provided. The recombinogenic modified FRT recombination sites can be employed in a variety of methods for targeted recombination of polynucleotides of interest, including methods to recombine polynucleotides, assess promoter activity, directly select transformed organisms, minimize or eliminate expression resulting from random integration into the genome of an organism, such as a plant, remove polynucleotides of interest, combine multiple transfer cassettes, invert or excise a polynucleotide, and identify and/or characterize transcriptional regulating regions are also provided. | 2013-02-28 |
20130052740 | COPPER, STARCH AND IODIDE MOISTURE INDICATOR - The invention relates to a moisture indicator which includes iodide, copper, and starch. | 2013-02-28 |
20130052741 | DYE COMPOSITIONS - Dye compositions comprising rhodizonate dye particles encapsulated within a shearable hydrophobic organic encapsulant composition. | 2013-02-28 |
20130052742 | ANALYSIS REAGENTS AND METHOD - The invention provides a single colorimetric reagent for the measurement of oxidising agents such as free chlorine in a liquid sample which contains a food dye, whereby the oxidising agent undergoes a reaction with said food dye. A preferred food dye is Brilliant Blue FCF. There is also provided a control system for regulating the volume of reagent added to a fixed volume of sample according to a control algorithm to give a chosen excess of a reagent compound beyond that required to stoichiometrically react with the target analyte in the sample. Also disclosed are single reagents for colorimetric determination of total alkalinity and calcium hardness. | 2013-02-28 |
20130052743 | FLOWABLE DRY POWDER COMPOSITION - A flowable dry powder composition comprising a mixture of diphenylcarbazide particles and glass bubbles; kits containing such compositions; methods of filling containers with such compositions; and, methods of using such compositions in the detecting of hexavalent chromium. | 2013-02-28 |
20130052744 | METHODS AND DEVICES FOR DETECTING ISOTHIAZOLONES - Methods for quantitative determination of the presence of isothiazolone compounds in a solution include controlling pH of the solution in a range from about 3 to about 10, combining a known quantity of the pH-adjusted solution with a known quantity of an aromatic thiolate anion, quantitatively determining color intensity of the resultant combined solution; and correlating the color intensity with amount of isothiazolone compounds. The methods may be used in automated systems, including systems utilizing optical sensor devices. | 2013-02-28 |
20130052745 | CHEMOCHROMIC MEMBRANES FOR MEMBRANE DEFECT DETECTION - A method of detecting defects in membranes such as ion exchange membranes of electrochemical cells. The electrochemical cell includes an assembly having an anode side and a cathode side with the ion exchange membrane in between. In a configuration step a chemochromic sensor is placed above the cathode and flow isolation hardware lateral to the ion exchange membrane which prevents a flow of hydrogen (H | 2013-02-28 |
20130052746 | HIGHER ORDER STRUCTURED DYES WITH ENHANCED OPTICAL FEATURES - Organic dyes that are covalently bonded multimers or higher order symmetrical structures where one or more dye units may optionally contain deuterium substitutions are disclosed. The disclosed dyes are particularly useful for optical coatings, new optical nanomaterials, high density storage devices. The structural and optical characteristics of the disclosed dyes provide avenues for increased information-content through surface-enhanced Raman resonance spectroscopy. | 2013-02-28 |
20130052747 | Quantitative Analysis of a Function Group on the Surface of a Solid Material - Disclosed is a method for quantitatively analyzing a functional group on the surface of a solid material. The functional group is carboxylic group while the solid material is carbon nano-tubes. The carboxylic group reacts with sodium hydrogen carbonate, thus turning the carboxylic groups into sodium carboxylate while consuming the sodium ions in the solution. The carbon nano-tubes are separated from the sodium hydrogen carbonate solution. The number of the sodium ions before and after the reaction is analyzed. Moreover, the sodium carboxylate carried on the reacted carbon nano-tubes with reacts with hydrochloric acid solution, thus dissolving the sodium ions in the hydrochloric acid solution. The carbon nanotubes are separated from from the hydrochloric acid solution. The amount of the sodium ions is analyzed before and after the reaction in the hydrochloric acid solution. | 2013-02-28 |
20130052748 | ASSAY DEVICE AND METHOD OF ASSAYING - A device for testing an analyte comprises a pathway allowing passage of analyte from an application zone to a waste zone. The device includes label material that emits or modifies light and which binds to the analyte. Between the application and waste zones there is a capture zone having capture material for binding any analyte traversing the pathway to the pathway. A first optical filter on one surface of the device allows transmission of light emitted or modified by the label and blocks light of at least one other wavelength range. This enables the device to be illuminated from one surface and light emitted or modified by the label to be detected from the opposite surface. The device may include a second filter allowing shorter wavelength light to reach the label. The device may be viewed using an illuminating reader or held up to a light source for viewing. | 2013-02-28 |
20130052749 | METHODS OF TRIGGERING ACTIVATION OF ENCAPSULATED SIGNAL-GENERATING SUBSTANCES AND APPARATUS UTILISING ACTIVATED SIGNAL-GENERATING SUBSTANCES - A method of performing a bioassay comprising activating capsules containing a signal precursor that is hydrolysable from a latent form in which substantially no signal is generated to a form in which it is able to generate a detectable signal, said activating comprising treating said capsules with heat and with an acid or a base catalysing solution, the combination of said heat and the pH of the catalysing solution being such as to hydrolyse said precursor to the form in which it is able to generate a detectable signal. | 2013-02-28 |
20130052750 | DIAGNOSTIC SYSTEM - The present invention provides, among other things, methods of creating an external marker for diagnosis and/or analysis of one or more diseases, disorders, or conditions, which may or may not otherwise have an external marker. | 2013-02-28 |
20130052755 | Automatically adjusting baking process for low-k dielectric material - A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions. | 2013-02-28 |
20130052756 | HEATING DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A heating device is provided according to an embodiment. The heating device comprises a heater, a temperature detecting part, a wafer warpage detecting part and a controlling part. The heater heats a wafer. The temperature detecting part detects a temperature of the wafer. The wafer warpage detecting part detects warpage of the wafer. The controlling part controls the heater based on a detection result of the wafer warpage detecting part before controlling the heater based on a detection result of the temperature detecting part. | 2013-02-28 |
20130052757 | METHODS FOR OPTIMIZING A PLASMA PROCESS - Methods for optimizing a plasma process are provided. The method may include obtaining a measurement spectrum from a plasma reaction in a chamber, calculating a normalized measurement standard and a normalized measurement spectrum of the measurement spectrum, comparing the normalized measurement spectrum with a normalized reference spectrum, and comparing the normalized measurement standard with a normalized reference standard to determine whether to change a process parameter of the plasma process or clean the chamber when the normalized measurement spectrum and the normalized reference spectrum are mismatched. | 2013-02-28 |
20130052758 | REMOVING ALUMINUM NITRIDE SECTIONS - Approaches for substantially removing bulk aluminum nitride (AlN) from one or more layers epitaxially grown on the bulk AlN are discussed. The bulk AlN is exposed to an etchant during an etching process. During the etching process, the thickness of the bulk AlN can be measured and used to control etching. | 2013-02-28 |
20130052759 | VERTICAL SOLID-STATE TRANSDUCERS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS - Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side. | 2013-02-28 |
20130052760 | METHOD OF INSPECTING AND MANUFACTURING A STACK CHIP PACKAGE - In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip. | 2013-02-28 |
20130052761 | METHOD AND DEVICE FOR RESIN COATING - A device for resin coating is used for producing an LED package including an LED element covered with resin containing phosphor. In a state in which a trial coating material | 2013-02-28 |
20130052762 | METHOD OF FORMING AN ARRAY OF HIGH ASPECT RATIO SEMICONDUCTOR NANOSTRUCTURES - A new method for forming an array of high aspect ratio semiconductor nanostructures entails positioning a surface of a stamp comprising a solid electrolyte in opposition to a conductive film disposed on a semiconductor substrate. The surface of the stamp includes a pattern of relief features in contact with the conductive film so as to define a film-stamp interface. A flux of metal ions is generated across the film-stamp interface, and a pattern of recessed features complementary to the pattern of relief features is created in the conductive film. The recessed features extend through an entire thickness of the conductive film to expose the underlying semiconductor substrate and define a conductive pattern on the substrate. The stamp is removed, and material immediately below the conductive pattern is selectively removed from the substrate. Features are formed in the semiconductor substrate having a length-to-width aspect ratio of at least about 5:1. | 2013-02-28 |
20130052763 | METHOD OF MANUFACTURING A NANO-ROD AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - A method of manufacturing a nano-rod and a method of manufacturing a display substrate in which a seed including a metal oxide is formed. A nano-rod is formed by reacting the seed with a metal precursor in an organic solvent. Therefore, the nano-rod may be easily formed, and a manufacturing reliability of the nano-rod and a display substrate using the nano-rod may be improved. | 2013-02-28 |
20130052764 | METHOD FOR PACKAGING LIGHT EMITTING DIODE - A method of packaging a light emitting diode comprising: providing a flexible substrate with a heat-conducting layer, an insulating layer covering on a surface of the heat-conducting layer and an electrically conductive layer positioned on the insulating layer; etching the conductive layer to form a gap in the conductive layer and expose a part of the insulating layer, the conductive layer being separated by the gap into a first electrode and a second electrode isolated from each other; stamping the flexible substrate with a mold at the position of the gap to form a recess in the flexible substrate; positioning a light emitting element on the conductive layer and electrically connecting the light emitting element to the conductive layer; and forming an encapsulation to cover the light emitting element. | 2013-02-28 |
20130052765 | ORGANIC ELECTRO-LUMINESCENCE DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention relates to an organic electro-luminescence display device and a method for fabricating the same, in which damage to a pad portion is prevented for improving yield. | 2013-02-28 |
20130052766 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - Manufacture of a light-emitting device by selectively removing a thin film that is formed outside a light-emitting region by ink application. The light-emitting device includes a supporting substrate and a plurality of organic electroluminescent (EL) elements ( | 2013-02-28 |
20130052775 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided. | 2013-02-28 |
20130052776 | FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate. | 2013-02-28 |
20130052777 | BACK SIDE ALIGNMENT STRUCTURE AND MANUFACTURING METHOD FOR THREE-DIMENSIONAL SEMICONDUCTOR DEVICE PACKAGES - A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel. | 2013-02-28 |
20130052778 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure. | 2013-02-28 |
20130052779 | FABRICATION OF A SEMICONDUCTOR DEVICE WITH EXTENDED EPITAXIAL SEMICONDUCTOR REGIONS - A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed. | 2013-02-28 |
20130052780 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - In a method of fabricating a semiconductor device, isolation structures are formed in a substrate to define active regions. Conductive structures are formed on the substrate to cross over at least two of the active regions and the isolation structures, the conductive structures extending in a first direction. An interfacial layer is conformally formed on the substrate in contact with the conductive structures. A first insulation layer is provided on the interfacial layer, wherein the first insulation layer is formed using a flowable chemical vapor deposition (CVD) process, and wherein the interfacial layer reduces a tensile stress generated at an interface between the conductive structures and the first insulation layer while the first insulation layer is formed. | 2013-02-28 |
20130052781 | Method of Forming Non-planar FET - A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate. | 2013-02-28 |
20130052782 | Implantation of Hydrogen to Improve Gate Insulation Layer-Substrate Interface - Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e | 2013-02-28 |
20130052783 | Methods of Forming Stressed Silicon-Carbon Areas in an NMOS Transistor - Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate. | 2013-02-28 |
20130052784 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth H | 2013-02-28 |
20130052789 | Polysilicon Resistor Formation in a Gate-Last Process - A method includes forming a polysilicon layer over a substrate, forming a hard mask over the polysilicon layer, and doping a first portion of the hard mask with a dopant to form a doped hard mask region, wherein a second portion of the hard mask is not doped with the dopant. An etching step is performed to etch the first and the second portions of the hard mask, wherein the second portion of the hard mask is removed, and wherein at least a bottom portion of the doped hard mask region is not removed. After the etching step, the bottom portion of the doped hard mask region is removed. Electrical connections are formed to connect to a portion of the polysilicon layer in order to form a resistor. | 2013-02-28 |
20130052790 | DOPING APPROACH OF TITANIUM DIOXIDE FOR DRAM CAPACITORS - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a doped material formed from a first dopant in concert with a second dopant wherein the second dopant has a different physical size from the first dopant and the presence of the second dopant influences the solubility of the first dopant in the dielectric material. The dielectric material maintains a high k-value while minimizing the leakage current and the EOT value | 2013-02-28 |
20130052791 | DOPED ELECTRODE FOR DRAM APPLICATIONS - A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode layers are conductive molybdenum oxide. | 2013-02-28 |
20130052792 | HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 2013-02-28 |
20130052795 | TRENCH FILLING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a trench filling method, which includes: forming a silicon oxide liner on a semiconductor substrate with trenches formed therein, the trenches including narrow-width portions having a first minimum isolation width and wide-width portions having a second minimum isolation width being wider than the first minimum isolation width; forming an oxidation-barrier film on the silicon oxide liner; forming a silicon liner on the oxidation-barrier film; filling the narrow-width portions with a first filling material; filling the wide-width portions with a second filling material; and oxidizing the silicon liner. | 2013-02-28 |
20130052796 | METHOD FOR MANUFACTURING A CIRCUIT DEVICE - A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet. | 2013-02-28 |
20130052803 | Method For Generating A Three-Dimensional NAND Memory With Mono-Crystalline Channels Using Sacrificial Material - A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures. | 2013-02-28 |
20130052804 | MULTI-GAS CENTRALLY COOLED SHOWERHEAD DESIGN - A method and apparatus for chemical vapor deposition and/or hydride vapor phase epitaxial deposition are provided. The apparatus generally include a lower bottom plate and an upper bottom plate defining a first plenum. The upper bottom plate and a mid-plate positioned above the upper bottom plate define a heat exchanging channel. The mid-plate and a top plate positioned above the mid-plate define a second plenum. A plurality of gas conduits extend from the second plenum through the heat exchanging channel and the first plenum. The method generally includes flowing a first gas through a first plenum into a processing region, and flowing a second gas through a second plenum into a processing region. A heat exchanging fluid is introduced to a heat exchanging channel disposed between the first plenum and the second plenum. The first gas and the second gas are then reacted to form a film on a substrate. | 2013-02-28 |
20130052805 | METHOD OF PRODUCING A THREE-DIMENSIONAL INTEGRATED CIRCUIT - Method of producing an integrated electronic circuit comprising at least the steps of:
| 2013-02-28 |
20130052806 | DEPOSITION SYSTEMS HAVING ACCESS GATES AT DESIRABLE LOCATIONS, AND RELATED METHODS - Deposition systems include a reaction chamber, and a substrate support structure disposed at least partially within the reaction chamber. The systems further include at least one gas injection device and at least one vacuum device, which together are used to flow process gases through the reaction chamber. The systems also include at least one access gate through which a workpiece substrate may be loaded into the reaction chamber and unloaded out from the reaction chamber. The at least one access gate is located remote from the gas injection device. Methods of depositing semiconductor material may be performed using such deposition systems. Methods of fabricating such deposition systems may include coupling an access gate to a reaction chamber at a location remote from a gas injection device. | 2013-02-28 |
20130052809 | PRE-CLEAN METHOD FOR EPITAXIAL DEPOSITION AND APPLICATIONS THEREOF - A method for fabricating an epitaxizl structure is provided, wherein the method comprises steps as follows: a reactive gas containing nitrogen and fluorine atoms is firstly applied to react with an oxygen-atom-containing residue residing on a surface of a substrate so as to form a solid compound on the surface. Subsequently, an anneal process is performed to sublimate the solid compound. A semiconductor deposition process is then performed on the substrate. | 2013-02-28 |
20130052810 | ENGINEERING OF POROUS COATINGS FORMED BY ION-ASSISTED DIRECT DEPOSITION - In one embodiment, a method of producing a porous semiconductor film on a workpiece includes generating semiconductor precursor ions that comprise one or more of: germanium precursor ions and silicon precursor ions in a plasma of a plasma chamber, in which the semiconductor precursor ions are operative to form a porous film on the workpiece. The method further includes directing the semiconductor precursor ions to the workpiece over a range of angles. | 2013-02-28 |
20130052811 | PLASMA UNIFORMITY CONTROL USING BIASED ARRAY - A technique for processing a workpiece is disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for processing a substrate, where the method may comprise: providing the workpiece in the chamber; providing a plurality of electrodes between a wall of the chamber and the workpiece; generating a plasma containing ions between the plurality of electrodes and the workpiece, ion density in an inner portion of the plasma being greater than the ion density in an outer portion of the plasma portion, the outer portion being between the inner portion and the wall of the chamber; and providing a bias voltage to the plurality of electrodes and dispersing at least a portion of the ions in the inner portion until the ion density in the inner portion is substantially equal to the ion density in the periphery plasma portion. | 2013-02-28 |
20130052812 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion. | 2013-02-28 |
20130052813 | METHOD AND STRUCTURE FOR ADVANCED SEMICONDUCTOR CHANNEL SUBSTRATE MATERIALS - Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material. | 2013-02-28 |
20130052814 | DIFFUSED CAP LAYERS FOR MODIFYING HIGH-K GATE DIELECTRICS AND INTERFACE LAYERS - Method of forming a semiconductor device includes providing a substrate with defined NMOS and PMOS device regions and an interface layer on the NMOS and PMOS device regions, depositing a high-k film on the interface layer, depositing a first cap layer on the high-k film, and removing the first cap layer from the high-k film in the PMOS device region. The method further includes depositing a second cap layer on the first cap layer in the NMOS device region and on the high-k film in the PMOS device region, performing a heat-treating process to diffuse a first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion from the interface layer into the second cap layer, removing the first and second cap layers from the high-k film, and depositing a gate electrode film over the high-k film. | 2013-02-28 |
20130052815 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function. | 2013-02-28 |
20130052816 | METHOD OF PRODUCING SEMICONDUCTOR TRANSISTOR - A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer | 2013-02-28 |
20130052817 | METHOD FOR THE FABRICATION OF BONDING SOLDER LAYERS ON METAL BUMPS WITH IMPROVED COPLANARITY - A method for fabrication of bonding solder layers on metal bumps with improved coplanarity, applicable to the flip-chip bump bonding technique for semiconductor IC packaging. When metal bumps have different sizes, the bonding solders thereon may have different heights after high-temperature reflows. The present invention can improve the coplanarity of bonding solders, and mitigating or even eliminating the difficulties in downstream packaging and testing caused by the inconsistent height of bonding solders. To achieve this purpose, the present invention proposes a two-step fabrication method for controlling the surface areas of the metal bumps and the bonding solder layers thereon separately, and thereby improving the coplanarity of the bonding solders after high-temperature reflows. The two-step fabrication method includes: a first-step process for forming metal bumps on the semiconductor devices; and a second-step process for forming bonding solder layers of different sizes on the metal bumps. | 2013-02-28 |
20130052818 | Methods for Forming Interconnect Structures of Integrated Circuits - A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask. | 2013-02-28 |
20130052819 | Methods of Forming Metal Silicide Regions on Semiconductor Devices Using Different Temperatures - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature. | 2013-02-28 |
20130052820 | METHOD OF FORMING CONDUCTIVE PATTERN - A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other. | 2013-02-28 |
20130052825 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer. | 2013-02-28 |
20130052826 | High Aspect Ratio Grid for Phase Contrast X-ray Imaging and Method of Making the Same - Semiconductor substrates with high aspect ratio recesses formed therein are described. The high aspect ratio recesses have bottom surface profile characteristics that promote formation of initial growth sites of plated metal as compared to the side surfaces of the recesses. Processes for making and plating the recesses are also disclosed. The metal-plated high aspect ratio recesses can be used as X-ray gratings in Phase Contrast X-ray imaging apparatuses. | 2013-02-28 |
20130052827 | SELECTIVE SUPPRESSION OF DRY-ETCH RATE OF MATERIALS CONTAINING BOTH SILICON AND OXYGEN - A method of suppressing the etch rate for exposed silicon-and-oxygen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. Examples of materials whose selectivity is increased using this technique include silicon nitride and silicon. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-oxygen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including a nitrogen-containing precursor and a hydrogen-containing precursor. The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor. | 2013-02-28 |
20130052828 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - In a substrate processing apparatus ( | 2013-02-28 |
20130052831 | METHOD OF PATTERNING HARD MASK LAYER FOR DEFINING DEEP TRENCH - A method of patterning a hard mask layer for defining a deep trench is described. A substrate formed with an isolation structure therein is provided. A hard mask layer is formed over the substrate provided. A patterned photoresist layer is formed over the hard mask layer, having therein a deep-trench opening pattern over the isolation structure. An etching gas not containing hydrogen is used to etch the hard mask layer with the patterned photoresist layer as a mask and thereby transfer the deep-trench opening pattern to the hard mask layer. | 2013-02-28 |
20130052832 | PRODUCING TRANSISTOR INCLUDING SINGLE LAYER REENTRANT PROFILE - A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer. | 2013-02-28 |
20130052833 | METHOD FOR ETCHING HIGH-K DIELECTRIC USING PULSED BIAS POWER - A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm). | 2013-02-28 |
20130052834 | WAFER HOLDER AND TEMPERATURE CONDITIONING ARRANGEMENT AND METHOD OF MANUFACTURING A WAFER - A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a multitude of heater lamp tubes is arranged, which directly acts upon the circular wafer carrier plate. Latter is drivingly rotatable about the central axis. A wafer is held on the circular wafer carrier plate by means of a weight-ring residing upon the periphery of a wafer deposited on the wafer carrier plate. | 2013-02-28 |
20130052835 | PATTERN TRANSFER APPARATUS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A pattern transfer apparatus according to one embodiment includes a transfer region selecting part that performs operation in which when performing pattern transfer from a template provided with N transfer regions (N is an integer of 2 or larger) to a transferring substrate a plurality of times, 1 to N−1 transfer regions, which are to be used to perform the transfer to regions of the transferring substrate corresponding to part of the N transfer regions, are selected such that the number of the transfer to be performed using each of the N transfer regions is evened out. ened out. | 2013-02-28 |
20130052836 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer. | 2013-02-28 |
20130052837 | Apparatus and Methods for Annealing Wafers - A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region. | 2013-02-28 |
20130052838 | ANNEALING METHOD TO REDUCE DEFECTS OF EPITAXIAL FILMS AND EPITAXIAL FILMS FORMED THEREWITH - An annealing method to reduce defects of epitaxial films and epitaxial films formed therewith. The annealing method includes features as follows: apply a pressure ranged from 10 MPa to 6,000 MPa to an epitaxial film grown on a substrate through a vapor phase deposition process and heat the epitaxial film at a temperature lower than the melting temperature of the epitaxial film. Through applying pressure to the epitaxial film, the lattice strain of the epitaxial film is alleviated, and therefore the defect density of the epitaxial film also decreases. | 2013-02-28 |
20130052839 | DETACHABLE CONNECTION STRUCTURE - A connection structure which electrically connects, through a conductive ball, a first contact which is provided at an electrical wiring member and a second contact which is provided at an electrical component, wherein a bottom surface of a case is provided with a ball assembly-use passage, the first contact is provided at the electrical wiring member facing the ball assembly-use passage. | 2013-02-28 |
20130052840 | SOCKET ASSEMBLY - A socket assembly includes a base and a number of sockets. The base includes a bottom wall and two sidewalls. A conductive base is formed on the bottom wall and forms at least two conductive pieces parallel to the sidewalls. An extension plate extends from the top of one of the sidewalls toward the other sidewall. A number of cutouts are defined in the bottom surface of the extension plate. Each socket includes a main body and a fixing member mounted on the top of the main body. The manipulation of the fixing member allows the repositioning of a socket within the base, or the removal of a socket. | 2013-02-28 |
20130052845 | PORTABLE ELECTRONIC DEVICE HAVING A CAM MECHANISM FOR PLUG EXTENSION AND RETRACTION - The present invention relates to a portable electronic device, which includes a housing having a receiving space therein, a core element received in the receiving space and having a plug at a front end thereof and a track adjacent to a rear end thereof, and a cam pivotally connected to the housing at a position adjacent to a first end thereof. When the first end of the cam is turned (e.g., by the user) in a certain direction, a second end of the cam is moved toward a plug opening of the housing. As a result, a pin at a second end of the cam presses against the track and thereby pushes the core element and extends the plug out of the housing through the plug opening. Due to the simple structure, the portable electronic device can be rapidly produced by an automated assembly process. | 2013-02-28 |
20130052846 | LOCKOUT DEVICE - A lockout device configured to be lockingly secured to an external structure includes a housing defining an opening sized to receive the external structure, at least one gripping member disposed within the housing and positioned to receive the external structure, and a driving member assembled with the housing. The at least one gripping member is movable in an axial direction between a first position in which internal surfaces of the housing urge the at least one gripping member into gripping engagement with the external structure, and a second position in which the internal surfaces of the housing allow the at least one gripping member to expand to release the external structure. The driving member is operatively connected with the at least one gripping member for movement of the at least one gripping member between the first and second positions. | 2013-02-28 |
20130052847 | RETRACTION ARM TO EXTRACT A MEZZANINE CIRCUIT BOARD CONNECTOR FROM A MOTHERBOARD CONNECTOR - An information handling system mezzanine circuit board disposed in a parallel configuration over a motherboard is selectively coupled and de-coupled at the motherboard with a retraction and latching device that translates retraction force applied at an accessible actuation portion to push upward from below the mezzanine circuit board. A retraction portion of the retraction and latching device provides an upward force at the bottom surface of the mezzanine circuit board to separate the mezzanine circuit board connector from the motherboard connector so that an end user can lift the mezzanine circuit board away from the motherboard. | 2013-02-28 |
20130052848 | PORTABLE ELECTRONIC DEVICES WITH MOISTURE CONTROL AND MOISTURE INDICATION FEATURES - Connector structures for electronic devices may be provided with moisture indicators. The connector structures may include a connector such as data port connector that has a rear opening. A moisture barrier structure may cover the rear of the data port connector and may have an opening that is aligned with the rear opening. A moisture indicator may cover the opening in the moisture barrier structure. A transparent window structure such as a layer of clear film may be used to prevent moisture from traveling through the rear opening of the data port connector and the opening in the moisture barrier structure to the moisture indicator. An audio port connector may be provided with a moisture indicator and a transparent window structure that helps prevent moisture from reaching the moisture indicator through the audio port connector. | 2013-02-28 |
20130052849 | CARD EDGE CONNECTOR - To satisfy the demand for a reduction in height, provided is a technique for reducing a gap between a motherboard and a daughterboard in the state where the daughterboard is connected to the motherboard. A card edge connector is used to be mounted on a connector mounting surface of a mainboard to connect a memory module to the mainboard. The card edge connector includes a latch portion for pressing the memory module to be displaced in a direction away from the connector mounting surface, toward the connector mounting surface. The latch portion is configured to be elastically displaceable in the direction away from the connector mounting surface. | 2013-02-28 |
20130052850 | CONNECTOR - A connector is provided that may include first and second housings. The first housing may include a first body and a lock arm. The first body may include a first receptacle. The lock arm may be pivotably coupled to the first body. The second housing may include a second body having a second receptacle and a support member. The first and second housings may be engageable with each other in a first position and a second position and movable relative to each other from the first position to the second position. The lock arm may be deflectable relative to the support member when the first and second housings are in the first position. The support member may restrict deflection of the lock arm when the first and second housings are in the second position. | 2013-02-28 |
20130052851 | RECEPTACLE CONNECTOR, PLUG CONNECTOR AND CONNECTOR ASSEMBLY THEREOF WITH IMPROVED LOCKING STRUCTURE - The present invention provides a connector assembly including mateable receptacle connector and plug connector. The plug connector includes a plug insulative housing, a number of plug contacts and a resilient locking member mounted to the plug insulative housing. The locking member includes a front section positioned on the plug insulative housing and a pressing section extending backwardly and upwardly from the front section. The front section includes a first locking protrusion having an inclined first guiding surface and a first locking surface. When the plug connector is inserted in the receptacle connector, the first locking protrusion is downwardly movable under the drive of the pressing section so as to lock with the receptacle connector. | 2013-02-28 |
20130052852 | ELECTRONIC DEVICE CONNECTOR - A connector includes a body and a socket extending from the body. A blocking wall is located on the body. The socket includes a top wall, a resilient piece located on the top wall. The blocking wall is surrounded the resilient piece for preventing the resilient piece from destroying. | 2013-02-28 |
20130052855 | BALL-LOCK CONNECTOR - Provided is a ball-lock connector wherein a connector which has a relatively small diameter and which can be smoothly attached or detached, is realized at low cost. Ball storage holes ( | 2013-02-28 |
20130052856 | ELECTRICAL CONTACT WITH TWO CONTATING PORTIONS AND ELECTRICAL CONNECTOR WITH THE SAME - An electrical connector including: an insulative housing and a plurality of contacts, the insulative housing defining a first mating face, a second mating face and a mounting face opposite to the mating faces, each contact includes a retaining portion for engaging on the insulative housing and a pair of contact portions exposed on the first mating face and the second mating face respectively, wherein the first mating face is higher than the second face in a direction perpendicular to the mating first and second faces. | 2013-02-28 |
20130052863 | CABLE CONNECTOR - A cable connector including a metal terminal having a middle section configured for clamping a center conductor of a coaxial cable, an insulating seat including two positioning seats that are integrally formed by injection molding and have the same configuration, and a metal housing integrally formed by stamping. The positioning seats are assembled together to completely enclose the metal terminal fitted therein. Portions of the metal housing corresponding to the insulating seat, and a shield layer and a jacket of the coaxial cable can be wrapped around and secured to the peripheries of the insulating seat, the shield layer, and the jacket respectively. Thus, the simple configuration of the insulating seat not only increases the assembly efficiency of the cable connector, but also minimizes wall thickness of the insulating seat for allowing the cable connector to be used in various compact mobile electronic devices. | 2013-02-28 |
20130052864 | RUBBER PLUG AND WATERPROOF CONNECTOR - A rubber plug ( | 2013-02-28 |
20130052865 | ANTI-ELECTROMAGNETIC INTERFERENCE ELECTRICAL CONNECTOR AND TERMINAL ASSEMBLY THEREOF - An anti-electromagnetic interference (anti-EMI) electrical connector having a terminal assembly is provided. The anti-EMI electrical connector includes an electrical insulation case, a plurality of first terminals, and a plurality of second terminals. The electrical insulation case includes a slot. Each of the first terminals is respectively disposed in the electrical insulation case, and each of the first terminals respectively includes a contact end located in the slot. Each of the second terminals is respectively disposed in the electrical insulation case, and the second terminals and the first terminals are arranged in a staggered manner. Each of the second terminals respectively includes a connection end located in the slot and adjacent to the contact end of at least one first terminal, in which a sectional area of the connection end of the second terminal is larger than a sectional area of the contact end of the first terminal. | 2013-02-28 |
20130052866 | SHIELDED CONNECTOR - Herein disclosed is a shielded connector that makes it possible to bring a shielded shell into reliable contact with a shielded shell cover while pursing further miniaturization. A shielded connector | 2013-02-28 |
20130052869 | USB CONNECTOR - A universal serial bus (USB) connector includes a housing and a main body received in the housing. The main body includes an insulator, a number of conductive terminals, a number of conductive pieces, and an anti-electromagnetic radiation (EMR) member. The conductive terminals, the conductive pieces, and the anti-EMR member are arranged in the insulator. Each conductive piece connects a corresponding one of the conductive terminals to the anti-EMR member. | 2013-02-28 |
20130052870 | CONNECTION JACK AND ELECTRONIC APPARATUS - A connection jack to which a connection plug having a center terminal and an earth terminal arranged on an outer peripheral side of the center terminal is connected and provided in an electronic apparatus in which a capacitor is disposed inside, includes: a housing made of an insulating material, in which an insertion opening to which the connection plug is inserted is formed; a center electrode to which the center terminal is connected and connected to the capacitor; a first earth electrode arranged on an outer peripheral side of the center electrode, to which the earth terminal is connected, and connected to the capacitor; and a second earth electrode arranged on an outer peripheral side of the center electrode, to which the earth terminal is connected, connected in series to a resistance limiting inrush current and connected to the capacitor through the resistance. | 2013-02-28 |
20130052873 | BACKWARD COMPATIBLE CONTACTLESS SOCKET CONNECTOR, AND BACKWARD COMPATIBLE CONTACTLESS SOCKET CONNECTOR SYSTEM - The invention relates to socket connectors and socket connector systems for electrically connecting a first corresponding plug connector and for capacitively connecting a second corresponding plug connector. Further, the invention relates to a plug connector for capacitively connecting a corresponding socket connector. In order to allow for an electrical connection or a capacitive connection, the invention suggest providing a connecting element, arranged within the housing of the socket connector, including contact portion for contacting a connection area of the first plug connector, and a non-contact portion arranged such that, in the mated state, the surface thereof covers at least parts of a connection area of the second plug connector. | 2013-02-28 |
20130052874 | ELECTRICAL ASSEMBLY CONNECTION OF A MOTOR VEHICLE - An electrical motor connection, in particular of an electrical cooling fan motor for a motor vehicle, has a connected cable harness whose cable ends are connected to a motor-end connecting terminal. A connecting housing has two housing parts, which are joined together in the assembled state to form a cavity, and which hold connection-end cable ends of the cable harness. One of the housing parts has at least one filling opening, which opens into the cavity, for filling with a curable encapsulation compound, and with the cured encapsulation compound surrounding the cable ends in the area of the connecting terminal, and being joined to the housing parts. | 2013-02-28 |
20130052875 | CONNECTOR AND CONNECTOR MODULE, AND ELECTRONIC APPARATUS HAVING THE SAME - There are provided a connector and a connector module which may commonly use mutually different interface schemes, and an electronic apparatus having the same. The connector includes a body having a fixed volume; and at least one coupling hole formed inwardly in a side of the body, and electrically coupled with a pin from the outside, wherein the coupling hole includes a first coupling unit having a predetermined first depth and electrically coupled with the pin from the outside, and a second coupling unit having a second depth deeper than the first depth and electrically coupled with another pin from the outside. | 2013-02-28 |
20130052876 | ELECTRICAL CONNECTOR - An electrical connector is provided in the present invention, including a plurality of electrical terminal groups, a metal housing, a metal positioning seat and a fixing member. The metal housing has a plurality of terminal-receiving grooves, each of which can accommodate two electrical terminal groups. A contact end of the electrical terminal group extends forward within the metal housing, and a connection end of the electrical terminal group extends downward out of the metal housing. The fixing member has a first bending sheet and a second bending sheet, which are perpendicular to each other and respectively connected to the metal housing and the metal positioning seat for fixing the metal positioning seat to the metal housing. The electrical connector of the present invention uses the metal housing to enhance the electromagnetic shielding effect, have a better heat dissipation efficacy and improve the stability of the connection structure. | 2013-02-28 |
20130052879 | ELECTRICAL PLUG CONNECTOR, ELECTRICAL SOCKET CONNECTOR, ELECTRICAL PLUG AND SOCKET CONNECTOR ASSEMBLY - In an electrical plug and socket connector assembly, each conducting terminal of each of the electrical plug connector and electrical socket connector defines two side panels spaced by a gap, two contact end portions respectively forwardly extended from the two side panels, bonding pegs downwardly extended from the bottom edges of the side panels, and radiation fins respectively extended from the topmost edges of the side panels and suspending above the gap. Subject to the design of the gap and radiation fins, waste heat created during operation of the electrical plug and socket connectors can be quick dissipated into the atmosphere, lowering the temperature and smoothing conduction of power supply. | 2013-02-28 |
20130052880 | ELECTRICAL PLUG CONNECTOR, ELECTRICAL SOCKET CONNECTOR, ELECTRICAL PLUG AND SOCKET CONNECTOR ASSEMBLY - An electrical plug and socket connector assembly includes an electrical plug connector and an electrical socket connector each including an electrically insulative housing and conducting terminals inserted into respective insertion slots in the electrically insulative housing, the electrically insulative housing having springy hooks suspending in top and bottom sides in each insertion slot, each conducting terminal of each of the electrical plug connector and electrical socket connector defines two side panels spaced by a gap, multiple fins extended from top and bottom edges of the side panels and suspending in top and bottom sides of the gap and hooked in the insertion slots by the springy hooks, and two contact end portions respectively forwardly extended from respective opposite ends of the two side panels. | 2013-02-28 |
20130052881 | ELECTRICAL PLUG CONNECTOR, ELECTRICAL SOCKET CONNECTOR, ELECTRICAL PLUG AND SOCKET CONNECTOR ASSEMBLY - In an electrical plug and socket connector assembly, each conducting terminal of each of the electrical plug connector and electrical socket connector defines two side panels spaced by a gap, a connection portion connected between one end of each of the two side panels, and two contact end portions respectively forwardly extended from respective opposite ends of the two side panels. Subject to the design of the connection portion, the contact end portions of each conducting terminal of the electrical plug connector can be kept in positive contact with the inner surfaces of the contact end portions and side panels of the mating conducting terminal of the mating electrical socket connector, lowering the impedance and temperature, smoothing conduction of power supply and assuring a high level of safety. | 2013-02-28 |
20130052882 | Electrial Outlet Safety Device - An electrical safety device for updating an existing electrical outlet into a Ground Fault Circuit Interrupter (GFCI)/Arc Fault protected receptacle. The electrical safety device is a surface mounted GFCI/Arc Fault receptacle for converting a grounded or ungrounded electrical receptacle with limited electrocution protection into semi-permanent GFCI/Arc Fault protected outlet that is not easily removed. | 2013-02-28 |
20130052883 | TERMINAL FITTING AND CONNECTOR - A terminal fitting (T) includes a terminal main body ( | 2013-02-28 |
20130052884 | ELECTRIC CONNECTION TERMINAL - An electrical terminal may include a terminal boot, a spring-force element disposed in the terminal boot, and an operating push-piece movably disposed in the terminal boot to operate the spring-force element. The operating push-piece may include, on a front surface, a labeling surface for marking the operating push-piece. | 2013-02-28 |
20130052885 | ADAPTER FOR A CLAMPING DEVICE - An adapter for a clamping device for the electrical connection of a cable or line is disclosed. The clamping device includes an electrical contact point and a height-adjustable clamping plate, and the clamping plate is designed to press the cable or line mechanically against the electrical contact point of the clamping device. In at least one embodiment, the adapter is designed to be able to be fastened to the clamping plate of the clamping device, so that using the adapter it is possible to carry out an adaptation to the cross-section of the cable or line to be clamped, to carry out an adaptation to the elevation of the height-adjustable clamping plate of the clamping device or to adjust the width of the clamping plate. | 2013-02-28 |
20130052886 | UNIVERSAL POWER SOCKET ADAPTOR - The invention relates to power sockets and, more particularly, relates to universal power sockets capable of receiving, and electrically engaging with, different types of plugs having pins. Even more particularly, the invention relates to a universal power socket having sprung contacts. There are universal adapters already in existence, however some are unable to connect accurate and stably with a plug. Some may require a different pin clasp to hold it in place, whereas some adapters may be too big, or are not cost effective, and will still be unable to hold a vast range of power plugs. My invention has resolved all of these problems, something which has never previously been done. The creation of my universal adapter has enabled the use of only one clasp in order to hold 9 different pins. It is accurate and will hold power plugs stably in place, with the convenience of being able to connect to a majority of power plugs worldwide. My invention has safely adapted the power plug to be much smaller and convenient with the ease of having a low cost. It can be used for travel as a power adapter, as well as being used as an indoor power socket. The ability to be implanted indoors is beneficial to airports and hotels, where it will be of convenience for their customers who have arrived from a different country. | 2013-02-28 |