09th week of 2014 patent applcation highlights part 13 |
Patent application number | Title | Published |
20140054509 | SULFONATION OF CONDUCTING POLYMERS AND OLED, PHOTOVOLTAIC, AND ESD DEVICES - Conducting polymer systems for hole injection or transport layer applications including a composition comprising: a water soluble or water dispersible regioregular polythiophene comprising (i) at least one organic substituent, and (ii) at least one sulfonate substituent comprising sulfonate sulfur bonding directly to the polythiophene backbone. The polythiophene can be water soluble, water dispersible, or water swellable. They can be self-doped. The organic substituent can be an alkoxy substituent, or an alkyl substituent. OLED, PLED, SMOLED, PV, and ESD applications can be used. | 2014-02-27 |
20140054510 | Y-TYPE OXOTITANIUM PHTHALOCYANINE NANOPARTICLES, PREPARATION, AND USE THEREOF - Oxotitanium phthalocyanine nanoparticles in the crystal form of phase-Y (Y-TiOPc) having particle diameters of 2˜4 nm, preparation, and applications thereof are disclosed. The preparation method comprises the following steps: mixing a concentrated sulfuric acid solution of TiOPc with water or dilute sulfuric acid, or water or dilute sulfuric acid with a surfactant dissolved therein, or an aqueous solution of a low molecular weight organic compound to form a suspension or hydrosol; adding into the resulting suspension or hydrosol chlorinated hydrocarbons to extract TiOPc into an organic phase, so as to form a colloidal solution of Y-TiOPc nanoparticles; and then, washing and drying the above nanoparticles to give rise to a powder of the Y-TiOPc nanoparticles. Such a nanoparticle powder can disperse in chlorinated hydrocarbons to form stable colloidal solutions, thereby providing an alternative approach for solving the problem of poor dispersibility for Y-type TiOPc. | 2014-02-27 |
20140054511 | Method for transferring phases of nanoparticles - The present invention provides a method for transferring phases of nanoparticles, which use a polymer with a molecular weight greater than 5,000 as a dispersant. The first step of the method of the present invention is to synthesize nanoparticles in the polymer aqueous solution. Next, an amphiphilic phase-transfer agent is added into the solution to coat the surface of nanoparticles with bipolar molecules, and then the mixture is added into an organic solvent to form a homogeneous solution. Finally, a salt and an alcohol are added into the homogeneous solution, and then an organic phase layer and an aqueous phase layer through a centrifugal method. The method of the present invention combines the advantages of aqueous process for preparing nanoparticles and transfers the same with a simple phase transferring process to obtain oil-phase nanoparticles, which can be applied to various fields. | 2014-02-27 |
20140054512 | CONDUCTIVE FULL VULCANIZED THERMOPLASTIC ELASTOMER AND ITS PREPARATION METHOD - The invention provides a conductive full vulcanized thermoplastic elastomer and its preparation method, and relates to the technical field of full vulcanized thermoplastic elastomer. The full vulcanized thermoplastic elastomer is obtained by melt-blending components including rubber particles having crosslinking structure with mean particle diameter of 0.02 to 1 μm, carbon nanotubes as conductive fillers and thermoplastic plastics once, wherein the weight ratio of the rubber particles and the thermoplastic plastics is from 30:70 to 75:25 and the content of conductive fillers is from 0.3 to 10 weight parts based on the total weight of rubber particles and thermoplastic plastics of 100 weight parts. The resulting conductive full vulcanized thermoplastic elastomers have low content of conductive fillers and excellent combination performances. It can be prepared by conventional rubber processing methods and can be used to produce electronic production equipment, means, electronic instrument, instrument housing and decorative materials of clean production workshop having static resistance, electro magnetic interference resistance and clean requirement. | 2014-02-27 |
20140054513 | Catalytic Composition for Synthesizing Carbon Nanotubes - The present invention relates to a catalytic composition for the synthesis of carbon nanotubes, comprising an active catalyst and a catalytic support, the active catalyst comprising a mixture of iron and cobalt in any oxidation form and the catalytic support comprising exfoliated vermiculite. | 2014-02-27 |
20140054514 | CONDUCTIVE PASTE FOR INTERNAL ELECTRODES, MULTILAYER CERAMIC ELECTRONIC COMPONENT USING THE SAME, AND METHOD OF MANUFACTURING THE SAME - There are provided a conductive paste for internal electrodes, a multilayer ceramic electronic component including the same, and a method of manufacturing the same. The conductive paste for internal electrodes including: a nickel (Ni) powder; a nickel oxide (NiO) powder having a content of 5.0 to 15.0 parts by weight based on 100 parts by weight of the nickel powder; and an organic vehicle. | 2014-02-27 |
20140054515 | Metallic Nanowire Ink Composition for a Substantially Transparent Conductor - An exemplary printable composition comprises a liquid or gel suspension of a plurality of metallic nanofibers or nanowires; a first solvent; and a viscosity modifier, resin, or binder. In various embodiments, an exemplary metallic nanowire ink which can be printed to produce a substantially transparent conductor comprises a plurality of metallic nanowires at least partially coated with a first polymer comprising polyvinyl pyrrolidone having a molecular weight less than about 50,000; one or more solvents such as 1-butanol, ethanol, 1-pentanol, n-methylpyrrolidone, cyclohexanone, cyclopentanone, 1-hexanol, acetic acid, cyclohexanol, and mixtures thereof; and a second polymer or polymeric precursor such as polyvinyl pyrrolidone or a polyimide, having a molecular weight greater than about 500,000. | 2014-02-27 |
20140054516 | NANO WIRE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a nanowire is provided. A solvent is heated. A catalyst is added to the solvent. A metal compound is added to the solvent to form a metal nanowire. The metal nanowire is refined. In the refining of the metal nanowire, the catalyst and a refinement material to converting an insoluble material generated by the catalyst into a soluble material may be added to the solvent. The catalyst may include NaCl and at least one selected from the group consisting of Mg, K, Zn, Fe, se, Mn, P, Br and I. | 2014-02-27 |
20140054517 | CATHODE ACTIVE MATERIAL - A cathode active material is provided by which excellent charge and discharge properties in a high-current range can be obtained when used in non-aqueous electrolyte secondary batteries. The cathode active material consists of a mixed metal fluoride represented by the general formula Fe( | 2014-02-27 |
20140054518 | DRY-IN-PLACE CORROSION-RESISTANT COATING FOR ZINC OR ZINC-ALLOY COATED SUBSTRATES - A process for making a corrosion-resistant metal component. The process having the steps of: combining water, at least one zinc phosphate compound and at least one chromium compound, being chromium (III) or chromium (IV) compounds, to form a first solution; separately combining at least one silicate compound with water to form a second solution; combining the first solution with the second solution such as to form a mixed aqueous solution; optionally combining the mixed aqueous solution with at least one acrylic resin to form a coating mixture; and, applying the coating mixture to a metal substrate having a zinc or zinc-alloy surface to form a coating on the metal substrate, the coating providing chemical resistance for at least 150 hours in accordance with ASTM B 117 standards where the zinc or zinc-alloy coating of the metal substrate has a weight of 0.04 oz/ft | 2014-02-27 |
20140054519 | VEGETABLE DIELECTRIC FLUID FOR ELECTRICAL TRANSFORMERS - Composition of one or more vegetable oils intended as triglycerides of natural origin with an oleic acid (C18:1) content less than 75%, preferably less than or equal to 74% which composition can be used for preparing dielectric fluids to be used in electrical transformers. | 2014-02-27 |
20140054520 | CHROMENE COMPOUND - A novel photochromic compound which develops a color of a neutral tint and has high color optical density, high fading speed and excellent durability. | 2014-02-27 |
20140054521 | METHOD FOR CONTINUOUS PREPARATION OF INDIUM-TIN COPRECIPITATES AND INDIUM-TIN-OXIDE NANOPOWDERS WITH SUBSTANTIALLY HOMOGENEOUS INDIUM/TIN COMPOSITION, CONTROLLABLE SHAPE AND PARTICLE SIZE - Disclosed herein are indium-tin-oxide nanoparticles and a method for continuously producing precipitated indium-tin nanoparticles having a particle size range of substantially from about 10 nm to about 200 nm and a substantially consistent ratio of indium to tin in the resultant nanoparticles across the duration of the continuous process, based on the ratio of indium to tin in a seeding solution. The method comprises preparing intermediate indium and tin compounds of the general formula [M(OH) | 2014-02-27 |
20140054522 | MOUNTING PLATE AND LIFTING COLUMN INCLUDING A MOUNTING PLATE - A mounting plate for mounting a lifting unit in a lifting column which lifting column includes at least two guide tube segments that are insertable substantially concentrically one-into-another and that are movable with respect to one another along their direction of extension in order to change the length of the lifting column. The mounting plate includes a motor-accommodating structure for a drive motor of the lifting unit and an accommodating structure, different from the motor-accommodating structure, for a support component of the lifting unit that is connectable in a rotationally fixed manner to mounting plate. The support component is disposed on a side of the lifting unit remote from or facing away from the drive motor. Also, a lifting column including the mounting plate. | 2014-02-27 |
20140054523 | KnuckleSaver Binder Release - The KnuckleSaver Binder Release is a safety tool that releases lever-type chain binders with reduced impact danger to the operator. Essentially a J-hook with handles, the operator engages the hook to the handle of the lever-binder and pulls which releases the tension on the binder without dangerous “hands-on” contact with the binder. | 2014-02-27 |
20140054524 | WIRE GRIP | 2014-02-27 |
20140054525 | Pipe Travelling Apparatus and Use Thereof - The pipe travelling apparatus ( | 2014-02-27 |
20140054526 | Apparatus for Positioning Logs - An apparatus to drag logs to a log splitter from locations distant from the log, splitter to locations near the log splitter, and then to assist with lifting logs for placement on the log splitter, comprises generally a mast-and-boom assembly with a first mount point and first pulley, and a second mount point, and second pulley at a height below said first mount point and first pulley, a winch, and a cable attached a one end to said winch, threaded through said first pulley and said second pulley, and connectable at the other end to a log via a connection means, said apparatus being suitable for integration with a log splitter. | 2014-02-27 |
20140054527 | MULTIPURPOSE SEASONAL SPORT SAFETY FENCE - A fence that bounds the outfield of a game played with bat and ball comprises a plurality of mesh panels suspended from a plurality of support posts, with foul posts at either end. The fence can be readily assembled and disassembled. The support posts' anchors can be covered when the fence is disassembled, so that the field is usable for other sports. The function of the fence is twofold: (1) to minimize injury to a player who runs into the fence and (2) to confine such a player within the field of play should the player impact the fence. | 2014-02-27 |
20140054528 | Quasi-wall composite panel fencing system - This invention relates to a modular fencing system composed of panels affixed to modular composite columns mounted onto base footings and encased with preformed laminate façades with custom designs. The panels consist of opposing pairs of composite sandwich core laminate sheets separated and affixed to a polymer filament truss matrix. Each of the panel's two laminate sheets is constructed from fiber reinforced polymer layers laminating segmented sandwich core discs. Modular composite columns consists of two parallel vertically standing fiber reinforced polymer laminate flange plates oriented perpendicular to the panel, linked with two horizontal winged web plates between, forming what resembles an double I-beam. Decorative column façades constructed using the same sandwich core laminate material used in the panels are installed to veil and cover the modular composite column, corner posts, support brackets, and an associated hardware and allow for custom decorative finishes. | 2014-02-27 |
20140054529 | FENCING BASE WITH BALLAST WEIGHT - A ballast weight is provided for a base for supporting tubular fencing poles on spigots. The ballast weight is in the form of a removable slab of molded plastics which in its underside has groove portions to receive frame members of the base. The end of the slab lies over a central transverse member of the frame and has a recess to accommodate the spigots. A pair of identical slabs can be used, one each side of the central transverse member of the frame. | 2014-02-27 |
20140054530 | RAILING ASSEMBLY - A railing assembly comprises an upper rail and an opposed lower rail. Each rail comprises a top surface and an opposed bottom surface. An upper standoff is mounted to the bottom surface of the upper rail, and a lower standoff mounted to the top surface of the lower rail. The railing assembly further comprises a baluster. The baluster comprises a top end portion and an opposed bottom end portion. The top end portion is pivotably mounted to the upper standoff about a generally horizontal upper pivot axis, and the bottom end portion is pivotably mounted to the lower standoff about a generally horizontal lower pivot axis. | 2014-02-27 |
20140054531 | DEFECT ENHANCEMENT OF A SWITCHING LAYER IN A NONVOLATILE RESISTIVE MEMORY ELEMENT - Embodiments of the invention set forth a nonvolatile memory element with a novel variable resistance layer and methods of forming the same. The novel variable resistance layer includes a metal-rich host oxide that operates with a reduced switching voltage and current and requires significantly reduced forming voltage when manufactured. In some embodiments, the metal-rich host oxide is deposited using a modified atomic layer deposition (ALD) process. In other embodiments, the metal-rich host oxide is formed by depositing a metal-containing coupling layer on a host oxide and thermally processing both layers to create a metal-rich composite host oxide with a higher concentration of oxygen vacancies. | 2014-02-27 |
20140054532 | ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer. | 2014-02-27 |
20140054533 | PHASE-CHANGE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A PCRAM device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, and a PN diode formed on the semiconductor substrate and including a layer interposed therein to suppress thermal diffusion of ions. | 2014-02-27 |
20140054534 | SELF-ALIGNED INTERCONNECTION FOR INTEGRATED CIRCUITS - Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device. | 2014-02-27 |
20140054535 | SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE - A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate. | 2014-02-27 |
20140054536 | RESISTIVE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer. | 2014-02-27 |
20140054537 | RESISTIVE MEMORY DEVICE CAPABLE OF PREVENTING DISTURBANCE AND METHOD FOR MANUFACTURING THE SAME - A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof. | 2014-02-27 |
20140054538 | 3-DIMENSIONAL STACK MEMORY DEVICE - A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type. | 2014-02-27 |
20140054539 | METHOD AND STRUCTURE OF MONOLITHICALLY INTEGRATED IC AND RESISTIVE MEMORY USING IC FOUNDRY-COMPATIBLE PROCESSES - The present invention relates to integrating a resistive o y device on top of an IC substrate monolithically using IC-foundry compatible processes. A method for forming an integrated circuit includes receiving a semiconductor substrate having a CMOS IC device formed on a surface region, forming a dielectric layer overlying the CMOS IC device, forming first electrodes over the dielectric layer in a first direction, forming second electrodes over the first electrodes in along a second direction different from the first direction, and forming a two-terminal resistive memory cell at each intersection of the first electrodes and the second electrodes using foundry-compatible processes, including: forming a resistive switching material having a controllable resistance, disposing an interface material including p-doped polycrystalline silicon germanium—containing material between the resistive switching material and the first electrodes, and disposing an active metal material between the resistive switching material and the second electrodes. | 2014-02-27 |
20140054540 | DEVICE INCLUDING SEMICONDUCTOR NANOCRYSTALS & METHOD - A method of making a device comprising semiconductor nanocrystals comprises forming a first layer capable of transporting charge over a first electrode, wherein forming the first layer comprises disposing a metal layer over the first electrode and oxidizing at least the surface of the metal layer opposite the first electrode to form a metal oxide, disposing a layer comprising semiconductor nanocrystals over the oxidized metal surface, and disposing a second electrode over the layer comprising semiconductor nanocrystals. A device comprises a layer comprising semiconductor nanocrystals disposed between a first electrode and a second electrode, and a first layer capable of transporting charge disposed between the layer comprising semiconductor nanocrystals one of the electrodes, wherein the first layer capable of transporting charge comprises a metal layer wherein at least the surface of the metal layer facing the layer comprising semiconductor nanocrystals is oxidized prior to disposing semiconductor nanocrystals thereover. | 2014-02-27 |
20140054541 | METHOD OF MANUFACTURING QUANTUM DOT DEVICE, QUANTUM DOT DEVICE MANUFACTURED BY USING THE METHOD, AND METHOD OF MEASURING ELECTRON MOBILITY OF QUANTUM DOT DEVICE - A method of manufacturing a quantum dot (QD) device includes: forming a first QD solution obtained by dispersing a plurality of QDs in a mixture of a solvent and an anti-solvent; and forming a first QD layer on a substrate structure by applying the first QD solution onto the substrate structure and naturally evaporating the first QD solution. | 2014-02-27 |
20140054542 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - The light emitting device includes a first conductive semiconductor layer; a second conductive semiconductor layer on the first conductive semiconductor layer; and an active layer between the first and second conductive semiconductor layers. The active layer includes a plurality of well layers and a plurality of barrier layers, wherein the well layers include a first well layer and a second well layer adjacent to the first well layer. The barrier layers include a first barrier layer disposed between the first and second well layers, and the first barrier layer includes a plurality of semiconductor layers having an energy bandgap wider than an energy bandgap of the first well layer. At least two layers of the plurality of semiconductor layers are adjacent to the first and second well layers, and have aluminum contents greater than that of the other layer. | 2014-02-27 |
20140054543 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. A first electrode is coupled to the first conductive semiconductor layer, and a second electrode is coupled to the second conductive semiconductor layer. A channel layer is provided around a lower portion of the light emitting structure. A first conductive support member is coupled to the second electrode and disposed adjacent to the second electrode. A second conductive support member is electrically insulated from the first conductive support member and disposed adjacent to the second electrode. A first connection part is coupled to the first electrode and the second conductive support member. | 2014-02-27 |
20140054544 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a light emitting structure including at least a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, an electrode layer on the light emitting structure, and a contact layer between the light emitting structure and the electrode layer and including a nitride semiconductor layer. | 2014-02-27 |
20140054545 | PHOTODETECTOR, EPITAXIAL WAFER AND METHOD FOR PRODUCING THE SAME - Provided are a photodetector in which, in a III-V semiconductor having sensitivity in the near-infrared region to the far-infrared region, the carrier concentration can be controlled with high accuracy; an epitaxial wafer serving as a material of the photodetector; and a method for producing the epitaxial wafer. Included are a substrate formed of a III-V compound semiconductor; an absorption layer configured to absorb light; a window layer having a larger bandgap energy than the absorption layer; and a p-n junction positioned at least in the absorption layer, wherein the window layer has a surface having a root-mean-square surface roughness of 10 nm or more and 40 nm or less. | 2014-02-27 |
20140054546 | Dynamic Random Access Memory Unit And Method For Fabricating The Same - A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer. | 2014-02-27 |
20140054547 | DEVICE WITH STRAINED LAYER FOR QUANTUM WELL CONFINEMENT AND METHOD FOR MANUFACTURING THEREOF - The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer. | 2014-02-27 |
20140054548 | TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES - Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 2014-02-27 |
20140054549 | GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER - A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer. | 2014-02-27 |
20140054550 | METHOD FOR N-DOPING GRAPHENE - The present disclosure provides an n-doping method of graphene, including supplying a reaction gas containing a carbon source and heat to a substrate and reacting to grow graphene on the substrate; and n-doping the graphene by a doping solution containing an n-type dopant or a vapor containing an n-type dopant, an n-doped graphene produced by the method, and a device including the n-doped graphene. | 2014-02-27 |
20140054551 | GATE TUNABLE TUNNEL DIODE - A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric. | 2014-02-27 |
20140054552 | DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS - An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed. | 2014-02-27 |
20140054553 | ACTIVE MATRIX ORGANIC LIGHT-EMITTING DIODE PANEL PACKAGING STRUCTURE - The present invention provides an active matrix organic light-emitting diode (AMOLED) panel packaging structure, which includes a substrate, a pixel zone formed on the substrate, multiple loops of inorganic packaging material formed on the substrate and located outside the pixel zone, multiple loops of organic bonding material formed on the substrate and located outside the pixel zone, and a back lid covering over the inorganic packaging material and the organic bonding material. The multiple loops of inorganic packaging material include at least one loop that circumferentially and hermetically surrounds the pixel zone. The multiple loops of organic bonding material include at least one loop that circumferentially and hermetically surrounds the pixel zone. The inorganic packaging material and the organic bonding material are arranged to separate from each other. The AMOLED panel packaging structure possesses advantages of excellent packaging sealability and bondability and helps realization of size enlargement of AMOLED panel. | 2014-02-27 |
20140054554 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device includes: a substrate; a first antireflection line formed on the substrate and including a first metallic layer and a first inorganic layer stacked sequentially; a gate line formed on the first antireflection line; a gate insulation layer formed on the substrate and the gate line; a second antireflection line formed on the gate insulation layer and including a second metallic layer and a second inorganic layer stacked sequentially; a data line formed on the second antireflection line; and wherein the first inorganic layer connects the first metallic layer and the gate line electrically and the second inorganic layer connects the second metallic layer and the data line. | 2014-02-27 |
20140054555 | Organic Light Emitting Display Device and Method for Fabricating the Same - The organic light emitting display device includes a substrate, a thin film transistor formed on the substrate, a protective film formed to cover the thin film transistor, a color filter layer formed on the substrate exposed by removing a gate insulating layer of the thin film transistor and the protective film, an overcoat layer formed over the entire surface of the substrate to cover the color filter layer and the protective film, a drain contact hole exposing the thin film transistor by selectively removing the protective film and the overcoat layer, and a first electrode connected to the thin film transistor through the drain contact hole on the overcoat layer, a white organic light emitting layer formed on the first electrode, and a second electrode formed to cover the white organic light emitting layer. | 2014-02-27 |
20140054556 | ORGANIC LIGHT-EMITTING DIODE AND METHOD OF FABRICATING THE SAME - An organic light-emitting diode includes an anode on a substrate; a first hole transporting layer on the anode; a second hole transporting layer on the first hole transporting layer and corresponding to the red and green pixel areas; a first emitting material pattern of a first thickness on the second hole transporting layer and corresponding to the red pixel area; a second emitting material pattern of a second thickness on the second hole transporting layer and corresponding to the green pixel area; a third emitting material pattern of a third thickness on the first hole transporting layer and corresponding to the blue pixel area; an electron transporting layer on the first, second and third emitting material patterns; and a cathode on the electron transporting layer, wherein the second thickness is less than the first thickness and greater than the third thickness. | 2014-02-27 |
20140054557 | DISPLAY DEVICE - A display device including a substrate, a display unit on the substrate, a sealing substrate coupled to the display unit, a plurality of power pads on the sealing substrate and electrically coupled to the display unit, and a connector including a housing unit, a power connection unit electrically coupled to the plurality of power pads, and a power contact unit for maintaining contact between the plurality of power pads and the power connection unit. | 2014-02-27 |
20140054558 | CASCADE-TYPE COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME - A cascade-type compound and an organic light-emitting device (OLED) including the same are provided. The cascade-type compound can be generically represented as Formula 1 below: | 2014-02-27 |
20140054559 | ORGANIC LIGHT EMITTING DEVICE - An organic light-emitting device is disclosed, the organic light-emitting device comprising a first electrode, a second electrode disposed opposite to the first electrode, and an emission layer comprising organic materials and disposed between the two electrodes. The emission layer may include a host and a dopant. The host may be a silane derivative of anthracene having at least one silicon substituent that is an aryl group having at least two rings that are fused to each other. The dopant may be a 7H-benzo[c]fluorene having diarylamino substituents at the 5- and 9-positions. This scheme provides organic light-emitting devices having low driving voltages, high light-emitting efficiencies and long lifetimes. | 2014-02-27 |
20140054560 | Bottom and Top Gate Organic Transistors with Fluropolymer Banked Crystallization Well - A method is provided for fabricating a printed organic thin film transistor (OTFT) with a patterned organic semiconductor using a fluropolymer banked crystallization well. In the case of a bottom gate OTFT, a substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode, and source (S) and drain (D) electrodes are formed overlying the gate dielectric. A gate dielectric OTFT channel interface region is formed between the S/D electrodes. A well with fluropolymer containment and crystallization banks is then formed, to define an organic semiconductor print area. The well is filled with an organic semiconductor, covering the S/D electrodes and the gate dielectric OTFT channel interface. Then, the organic semiconductor is crystallized. Predominant crystal grain nucleation originates from regions overlying the S/D electrodes. As a result, an organic semiconductor channel is formed, interposed between the S/D electrodes. | 2014-02-27 |
20140054561 | Electron Transport Material and Organic Electroluminescent Device Using the Same - Provided are a new electron transport material and an organic electroluminescent device including the same. The electron transport material according to the present invention may have the excellent luminescence property and reduce the driving voltage to increase the power efficiency, such that the organic electroluminescent device using less consumption power may be manufactured. | 2014-02-27 |
20140054562 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole. | 2014-02-27 |
20140054563 | PHOSPHORESCENT EMITTERS WITH PHENYLIMIDAZOLE LIGANDS - Phosphorescent materials are provided, where the materials comprise a coordination compound having at least one ligand L | 2014-02-27 |
20140054564 | ELECTROLUMINESCENT DEVICE USING ELECTROLUMINESCENT COMPOUND AS LUMINESCENT MATERIAL - Provided is an organic electroluminescent device that exhibits an efficient host-dopant energy transfer mechanism, and thus, expresses a certain high-efficiency electroluminescent performance, based on improved electron density distribution. The organic electroluminescent device also overcomes low initial efficiency and short operation life property, and secures high-performance electroluminescent performance with high efficiency and long life property for each color. | 2014-02-27 |
20140054565 | OTFT ARRAY SUBSTRATE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to embodiments of the present invention, there are disclosed an organic thin film transistor (OTFT) array substrate, a display device and a method for manufacturing the same, which are capable of improving quality of a channel. The OTFT array substrate comprises: a transparent substrate, a gate line and a data line which are formed on the transparent substrate, and a pixel unit which are defined by crossing of the gate line and the data line; the pixel unit including an organic thin film transistor (OTFT) and a pixel electrode; on a channel region of an active layer of the OTFT, there is provided a first passivation layer unit. | 2014-02-27 |
20140054566 | Novel Structures for Light-Emitting Transistors - Disclosed are light-emitting transistors having novel structures that can lead to enhanced device brightness, specifically, via new arrangements of electrodes that can favor carrier recombination and exciton formation. | 2014-02-27 |
20140054567 | Organic Electroluminescent Device - Provided is an organic electroluminescent device including, in an order mentioned: a reflective electrode; an organic electroluminescent layer; a light extraction layer; and a transparent substrate, wherein a ratio (w/d) is 9 or more where “d” denotes a total average thickness from the organic electroluminescent layer to the transparent substrate and “w” denotes a minimum width of a non-light-emitting region present outside of an outer periphery of an effective light-emitting region in the organic electroluminescent layer. | 2014-02-27 |
20140054568 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A semiconductor device includes: a gate electrode; an organic semiconductor film forming a channel; and a pair of source-drain electrodes formed on the organic semiconductor film, the pair of source-drain electrodes each including a connection layer, a buffer layer, and a wiring layer that are laminated in order. | 2014-02-27 |
20140054569 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode display includes a display substrate including a display region having an organic light emitting diode; an encapsulation substrate facing the display substrate and covering the display region; a first sealing material between the display substrate and the encapsulation substrate, the first sealing material sealing the display region; a second sealing material in contact with an external exposed surface of the first sealing material and sealing the first sealing material; and a molding portion surrounding a lateral surface and an external corner of each of the display substrate and the encapsulation substrate and surrounding an external exposed surface of the second sealing material. | 2014-02-27 |
20140054570 | ORGANIC LIGHT EMITTING DEVICE AND METHOD OF PREPARING SAME AND DISPLAY DEVICE THEREOF - Disclosed is an organic light-emitting device comprising a substrate ( | 2014-02-27 |
20140054571 | Electroluminescent Element, Display Device And Method For Preparing Electroluminescent Element - Disclosed are an electroluminescent element, a display device and a method for preparing the electroluminescent element. The electroluminescent element comprises a substrate ( | 2014-02-27 |
20140054572 | ORGANIC ELECTROLUMINESCENT DEVICE - [Problem] To provide an organic electroluminescent device that is excellent in external extraction efficiency of emitted light and able to attain reduced power consumption and prolonged service life. | 2014-02-27 |
20140054573 | Hidden organic optoelectronic devices - An optoelectronic device comprising at least one optoelectronic active region comprising at least a rear electrode and a front electrode between which an organic optoelectronic material is sandwiched, said rear electrode being reflective, and a cover layer arranged in front of said front electrode. The cover layer comprises a material with light-scattering particles of a first material dispersed in a transparent matrix of at an least partly hydrolyzed silica sol. | 2014-02-27 |
20140054574 | HYBRID LAYERS FOR USE IN COATINGS ON ELECTRONIC DEVICES OR OTHER ARTICLES - A method for protecting an electronic device comprising an organic device body. The method involves the use of a hybrid layer deposited by chemical vapor deposition. The hybrid layer comprises a mixture of a polymeric material and a non-polymeric material, wherein the weight ratio of polymeric to non-polymeric material is in the range of 95:5 to 5:95, and wherein the polymeric material and the non-polymeric material are created from the same source of precursor material. Also disclosed are techniques for impeding the lateral diffusion of environmental contaminants. | 2014-02-27 |
20140054575 | DISPLAY UNIT - A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity. | 2014-02-27 |
20140054576 | ORGANIC ELECTROLUMINESCENT DISPLAY - An organic electroluminescent (EL) display includes a plurality of organic EL devices for red, green, and blue subpixels, each including a first electrode on a light output side, a second electrode opposite the first electrode, and an organic compound layer including a light-emitting layer therebetween. The organic EL devices have a resonator structure between a first reflective surface closer to the first electrode than the organic compound layer and a second reflective surface closer to the second electrode than the organic compound layer. A predetermined white color is displayed by mixing the three colors such that an optical distance of the organic EL devices of each color between an emission position in the light-emitting layer and the second reflective surface is set within ±10% from an optical distance corresponding to an nth-order minimum of a curve of required current density against at least the optical distance. | 2014-02-27 |
20140054577 | PHOTOELECTRIC CONVERSION ELEMENT AND SOLID-STATE IMAGING DEVICE - A photoelectric conversion element comprises a first photoelectric conversion part, the first photoelectric conversion part comprising: a pair of electrodes; and a photoelectric conversion film between the pair of electrodes, wherein the photoelectric conversion film comprises an organic photoelectric conversion material having an absorption peak in an infrared region of an absorption spectrum within a combined range of a visible region and the infrared region and generating an electric charge according to light absorbed, and the first photoelectric conversion part as a whole transmits 50% or more of light in the visible region. | 2014-02-27 |
20140054578 | LAYERED ELECTRONIC DEVICE - A device includes an organic polymer layer and an electrode positioned against the polymer layer, the electrode being constituted by a transparent stack of thin layers including an alternation of n thin metallic layers and of (n+1) antireflection coatings, with n≧1, where each thin metallic layer is placed between two antireflection coatings. At least one of the two antireflection coatings located at the ends of the constituent stack of the electrode includes a stack that is a barrier to moisture and gases, the layers of the or each barrier stack having alternately lower and higher densities. | 2014-02-27 |
20140054579 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer. | 2014-02-27 |
20140054580 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - Embodiment of the present invention disclose an array substrate and a manufacturing method thereof, and the manufacturing method of an array substrate comprises the following steps: Step S1: a gate electrode metal layer, an insulating layer and an active layer are deposited successively on a substrate, and gate electrodes, gate lines and an active layer pattern are formed through a first mask process; Step S | 2014-02-27 |
20140054581 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the invention relate to an array substrate, a manufacturing method thereof and a display device comprising the array substrate. The array substrate comprises a gate line and a data line which define a pixel region, the pixel region comprises a thin film transistor region and an electrode pattern region, a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode and a passivation layer are formed in the thin film transistor region, the gate insulation layer, a pixel electrode, the passivation layer and a common electrode are formed in the electrode pattern region, and the common electrode and the pixel electrode form a multi-dimensional electric field. A color resin layer is formed between the gate insulation layer and the pixel electrode. | 2014-02-27 |
20140054582 | DISPLAY DEVICE - An inorganic insulating film containing nitrogen, which has high adhesion to a sealant and an excellent effect of blocking hydrogen, water, and the like, is used as a layer in contact with the sealant. Further, the sealant is provided on the outer side than a side surface of an end portion of the organic insulating film provided over the transistor or the inorganic insulating film containing nitrogen is provided to cover an area from a region which is on the outer side than the edge of the organic insulating film to the side surface and the top surface of the end portion of the organic insulating film. Accordingly, the entry of hydrogen, water, and the like existing outside the display device into the oxide semiconductor included in the transistor can be suppressed, so that the display device can have high reliability. | 2014-02-27 |
20140054583 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode. | 2014-02-27 |
20140054584 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer. | 2014-02-27 |
20140054585 | LATERAL SEMICONDUCTOR DEVICE WITH VERTICAL BREAKDOWN REGION - A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event. | 2014-02-27 |
20140054586 | MANUFACTURING METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY - Embodiments of the present invention disclose a manufacturing method of an array substrate, an array substrate and a display. The manufacturing method comprises: forming a gate electrode of a TFT on a substrate; forming a metal oxide semiconductor thin film and a top metal thin film, and performing a mask process to the metal oxide semiconductor thin film and the top metal thin film, in order to form an active layer opposing the gate electrode and a source electrode and a drain electrode of the TFT respectively; and forming a passivation layer overlying the source electrode and the drain electrode, wherein during the mask process to the top metal thin film, a hydrogen peroxide-based etchant with a pH value between 6 and 8 is used to etch the top metal thin film. | 2014-02-27 |
20140054587 | Semiconductor Device, Display Device, And Electronic Device - A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided. | 2014-02-27 |
20140054588 | THIN-FILM TRANSISTOR STRUCTURE, AS WELL AS THIN-FILM TRANSISTOR AND DISPLAY DEVICE EACH HAVING SAID STRUCTURE - There is provided an oxide semiconductor layer capable of making stable the electric characteristics of a thin-film transistor without requiring an oxidatively-treated layer when depositing a passivation layer or the like in display devices such as organic EL displays depositing and liquid crystal displays. The thin-film transistor structure of the present invention at least having, on a substrate, an oxide semiconductor layer, a source-drain electrode, and a passivation layer in order from the substrate side, wherein the oxide semiconductor layer is a stacked product of a first oxide semiconductor layer and a second oxide semiconductor layer; the first oxide semiconductor layer has a Zn content of 50 atomic % or more as a percentage of all metal elements contained therein, and the first oxide semiconductor layer is formed on the source-drain electrode and passivation layer side; the second oxide semiconductor layer contains at least one element selected from the group consisting of In, Ga, and Zn, and the second oxide semiconductor layer is formed on the substrate side; and the first oxide semiconductor layer is in direct contact both with the source-drain electrode and with the passivation layer. | 2014-02-27 |
20140054589 | BISMUTH-DOPED SEMI-INSULATING GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD - The present invention discloses a semi-insulating wafer of Ga | 2014-02-27 |
20140054590 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THIN-FILM SEMICONDUCTOR DEVICE - A thin-film semiconductor device includes: a gate electrode; a channel layer; a first amorphous semiconductor layer; a channel protective layer; a pair of second amorphous semiconductor layers formed on side surfaces of the channel layer; and a pair of contact layers which contacts the side surfaces of the channel layer via the second amorphous semiconductor layers. The gate electrode, the channel layer, the first amorphous semiconductor layer, and the channel protective layer are stacked so as to have outlines that coincide with one another in a top view. The first amorphous semiconductor layer has a density of localized states higher than those of the second amorphous semiconductor layers. The second amorphous semiconductor layers have band gaps larger than that of the first amorphous semiconductor layer. | 2014-02-27 |
20140054591 | LIQUID CRYSTAL DISPLAY INCLUDING A VARIABLE WIDTH SPACER ELEMENT AND METHOD FOR FABRICATING THE SAME - A liquid crystal display with two insulating substrates. A first insulating substrate has crossing signal lines, a pixel electrode, and a drain electrode electrically connected to the pixel electrode through a contact hole. A spacer is formed on the first signal line of the first insulating substrate, and is wider at a first portion close to the first insulating substrate than at a second portion close to the second insulating substrate, and the drain electrode comprises a first portion and a second portion extending in a different direction with respect to the first portion. | 2014-02-27 |
20140054592 | TFT-LCD ARRAY SUBSTRATE - A pixel unit at a TFT-LCD array substrate includes a thin film transistor, a first storage capacitor, and a second storage capacitor. The first storage capacitor includes a transparent common electrode, a pixel electrode, and a first insulating layer disposed between the transparent common electrode and the pixel electrode. The second storage capacitor includes a first conductive layer, a second conductive layer, and a second insulating layer disposed between the first and second conductive layers. The first conductive layer is connected to the transparent common electrode within the pixel unit. The second conductive layer is connected to the pixel electrode within the pixel unit. | 2014-02-27 |
20140054593 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 02014-02-27 | |
20140054594 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a dielectric layer, a first electrode, a second electrode and a support substrate. The first layer has a first and second surface. The second layer is provided on a side of the second surface of the first layer. The emitting layer is provided between the first and the second layer. The dielectric layer contacts the second surface and has a refractive index lower than that of the first layer. The first electrode includes a first and second portion. The first portion contacts the second surface and provided adjacent to the dielectric layer. The second portion contacts with an opposite side of the dielectric layer from the first semiconductor layer. The second electrode contacts with an opposite side of the second layer from the emitting layer. | 2014-02-27 |
20140054595 | COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE - The present invention discloses a novel composite substrate which solves the problem associated with the quality of substrate surface. The composite substrate has at least two layers comprising the first layer composed of Ga | 2014-02-27 |
20140054596 | SEMICONDUCTOR DEVICE WITH ELECTRICAL OVERSTRESS (EOS) PROTECTION - A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer. | 2014-02-27 |
20140054597 | POWER DEVICE AND PACKAGING THEREOF - The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside. | 2014-02-27 |
20140054598 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Certain embodiments provide semiconductor device including a semiconductor layer including a channel layer, a barrier layer, and a cap layer, the semiconductor layer provided on a semiconductor substrate, a drain electrode and a source electrode, an opening of the cap layer, and a gate electrode. The drain electrode and the source electrode are provided on the barrier layer. The opening is provided in the cap layer provided between the drain electrode and the source electrode, the opening being separated from the drain electrode and the source electrode. The gate electrode is provided so as to be in contact with the barrier layer exposed in the opening of the cap layer and also insulated from a side surface of the opening of the cap layer. Inside the opening, a distance between the gate electrode and the side surface of the opening increases with a decreasing distance from the barrier layer. | 2014-02-27 |
20140054599 | FLEXIBLE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A flexible semiconductor device and a method of manufacturing the flexible semiconductor device are provided. The flexible semiconductor device may include at least one vertical semiconductor element that is at least partly embedded in a flexible material layer. The flexible semiconductor device may further include a first electrode formed on a first surface of the flexible material layer and a second electrode formed on a second surface of the flexible material layer. A method of manufacturing a flexible semiconductor device may include separating a flexible material layer, in which the at least one vertical semiconductor element is embedded, from a substrate by weakening or degrading an adhesive force between an underlayer and a buffer layer by using a difference in coefficients of thermal expansion of the underlayer and the buffer layer. | 2014-02-27 |
20140054600 | NITRIDE SEMICONDUCTOR AND FABRICATING METHOD THEREOF - This specification is directed to a semiconductor device capable of reducing a leakage current by forming a first GaN layer including a plurality of GaN layers and Fe | 2014-02-27 |
20140054601 | GALLIUM NITRIDE (GAN) DEVICE WITH LEAKAGE CURRENT-BASED OVER-VOLTAGE PROTECTION - A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region. | 2014-02-27 |
20140054602 | FIELD EFFECT TRANSISTOR (FET) HAVING FINGERS WITH RIPPLED EDGES - A field effect transistor (FET) having fingers with rippled edges is disclosed. The FET includes a semiconductor substrate having a front side with a finger axis. A drain finger is disposed on the front side of the semiconductor substrate such that a greatest dimension of the drain finger lies parallel to the finger axis. A gate finger is disposed on the front side of the semiconductor substrate. The gate finger is spaced from the drain finger such that a greatest dimension of the gate finger lies parallel to the finger axis. A source finger is disposed on the front side of the semiconductor substrate. The source finger is spaced from the gate finger such that a greatest dimension of the source finger lies parallel to the finger axis. The drain finger, the gate finger, and the source finger each have rippled edges with an axis parallel with the finger axis. | 2014-02-27 |
20140054603 | Semiconductor Heterostructure Diodes - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 2014-02-27 |
20140054604 | SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT DISSIPATION - A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias. | 2014-02-27 |
20140054605 | Composite Substrates, Light Emitting Devices and a Method of Producing Composite Substrates - A plurality of protrusions | 2014-02-27 |
20140054606 | SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE PROVIDED OVER ACTIVE REGION IN P-TYPE NITRIDE SEMICONDUCTOR LAYER AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer. | 2014-02-27 |
20140054607 | Group III-V Device with Strain-Relieving Layers - According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer. | 2014-02-27 |
20140054608 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT - A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components. | 2014-02-27 |