| 09th week of 2009 patent applcation highlights part 61 |
| Patent application number | Title | Published |
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| 20090055587 | Adaptive Caching of Input / Output Data - To improve caching techniques, so as to realize greater hit rates within available memory, of the present invention utilizes a entropy signature from the compressed data blocks to supply a bias to pre-fetching operations. The method of the present invention for caching data involves detecting a data I/O request, relative to a data object, and then selecting appropriate I/O to cache, wherein said selecting can occur with or without user input, or with or without application or operating system preknowledge. Such selecting may occur dynamically or manually. The method further involves estimating an entropy of a first data block to be cached in response to the data I/O request; selecting a compressor using a value of the entropy of the data block from the estimating step, wherein each compressor corresponds to one of a plurality of ranges of entropy values relative to an entropy watermark; and storing the data block in a cache in compressed form from the selected compressor, or in uncompressed form if the value of the entropy of the data block from the estimating step falls in a first range of entropy values relative to the entropy watermark. The method can also include the step of prefetching a data block using gap prediction with an applied entropy bias, wherein the data block is the same as the first data block to be cached or is a separate second data block. The method can also involve the following additional steps: adaptively adjusting the plurality of ranges of entropy values; scheduling a flush of the data block from the cache; and suppressing operating system flushes in conjunction with the foregoing scheduling step. | 2009-02-26 |
| 20090055588 | Performing Useful Computations While Waiting for a Line in a System with a Software Implemented Cache - Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed. | 2009-02-26 |
| 20090055589 | Cache memory system for a data processing apparatus - A data processing apparatus is provided having a cache memory | 2009-02-26 |
| 20090055590 | Storage system having function to backup data in cache memory - A storage system comprises a plurality of control modules having a plurality of cache memories respectively. One or more dirty data elements out of a plurality of dirty data elements stored in a first cache memory in a first control module are copied to a second cache memory in a second control module. The one or more dirty data elements stored in the second cache memory are backed up to a non-volatile storage resource. The dirty data elements backed up from the first cache memory to the non-volatile storage resource are dirty data elements other than the one or more dirty data elements of which copying has completed, out of the plurality of dirty data elements. | 2009-02-26 |
| 20090055591 | Hierarchical cache memory system - A hierarchical cache memory system having first and second cache memories includes: a controller which outputs dirty data stored in the first cache memory to write back to a main memory; and a controller which processes the write-back to the main memory of the dirty data outputted from the first cache memory in parallel with the write-back to the main memory of dirty data stored in the second cache memory. | 2009-02-26 |
| 20090055592 | DIGITAL SIGNAL PROCESSOR CONTROL ARCHITECTURE - A system includes a control store memory populated with data path instructions indexable by control store addresses and jump addresses. The system further includes a control state machine to provide at least one control store address and at least one jump address to the control store memory, wherein the control store memory is configured to identify one or more data path instructions for both the control store address and the jump address. | 2009-02-26 |
| 20090055593 | STORAGE SYSTEM COMPRISING FUNCTION FOR CHANGING DATA STORAGE MODE USING LOGICAL VOLUME PAIR - A storage system writes a data element stored in a primary volume to a secondary volume constituting a volume pair with the primary volume in accordance with a selected storage mode, which is a data storage mode selected from a plurality of types of data storage modes. This storage system is provided with a function for switching the above-mentioned selected storage mode from a currently selected data storage mode to a different type of data storage mode. | 2009-02-26 |
| 20090055594 | System for and method of capturing application characteristics data from a computer system and modeling target system - A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. | 2009-02-26 |
| 20090055595 | ADJUSTING PARAMETERS USED TO PREFETCH DATA FROM STORAGE INTO CACHE - Provided are a method, system, and article of manufacture for adjusting parameters used to prefetch data from storage into cache. Data units are added from a storage to a cache, wherein requested data from the storage is returned from the cache. A degree of prefetch is processed indicating a number of data units to prefetch into the cache. A trigger distance is processed indicating a prefetched trigger data unit in the cache. The number of data units indicated by the degree of prefetch is prefetched in response to processing the trigger data unit. The degree of prefetch and the trigger distance are adjusted based on a rate at which data units are accessed from the cache. | 2009-02-26 |
| 20090055596 | MULTI-PROCESSOR SYSTEM HAVING AT LEAST ONE PROCESSOR THAT COMPRISES A DYNAMICALLY RECONFIGURABLE INSTRUCTION SET - A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co-processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor. | 2009-02-26 |
| 20090055597 | Method and Device for Sharing Information Between Memory Parcels In Limited Resource Environments - The invention relates to the management of information such as data and/or procedures residing in the memory in systems with reduced processing and storing capacity, for example, those available in a smart card. A method and a device disclosed in the invention make it possible for various applications lodged in different memory parcels to safely share data and/or procedures by making optimum use of the processing capacity of the system to which the memory belongs. A strict sharing mechanism ensures that if an application has obtained a data item or a procedure from another application or the system itself in which it is lodged, it has done so because it is authorized to use it and therefore no verification has to be made. The sharing mechanism is based on the principle that data and procedures of one application can only be referenced by another application during its execution and through the sharing mechanisms defined in this invention. | 2009-02-26 |
| 20090055598 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 2009-02-26 |
| 20090055599 | CONSISTENT DATA STORAGE SUBSYSTEM CONFIGURATION REPLICATION - Consistency for replicating data storage subsystem configurations in accordance with a “golden” configuration file. A data storage subsystem comprises a blade system with a plurality of slots, the blade system configured to support a plurality of blades and a storage system, each arranged in a predetermined slot of the blade system. The storage system arranges a logical configuration of the server blades in accordance with a “golden” configuration file. The server blade slot versus WWN information is collected and provided to the storage system. The storage system converts the “golden” configuration file slot information to WWNs. The server blades are enabled for access to said storage system as they log on with WWNs in accordance with the “golden” configuration file. | 2009-02-26 |
| 20090055600 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 2009-02-26 |
| 20090055601 | Efficient Sharing Of Memory Between Applications Running Under Different Operating Systems On A Shared Hardware System - A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution of the first and second operating systems, and further includes a region of shared memory managed on behalf of the first and second applications. Techniques are used to avoid preemption when the first application is accessing the shared memory region. In this way, the second application will not be unduly delayed when attempting to access the shared memory region due to delays stemming from the first application's access of the shared memory region. This is especially advantageous when the second application and operating system are adapted for real-time processing. Additional benefits can be obtained by taking steps to minimize memory access faults. | 2009-02-26 |
| 20090055602 | METHOD AND APPARATUS FOR EMBEDDED MEMORY SECURITY - A method and apparatus for embedded memory security is disclosed. One embodiment protects data in a memory block from unauthorized reading. When writing or reading data to or from the memory block an error correction code is used to calculate an ECC value, wherein the calculation of the ECC value is based on a combination of the data and a access identifier provided to the memory block prior to reading. The access identifier identifies the requesting program. A read error is signalled in case the calculated ECC value does not match a stored value thus indicating an access violation. | 2009-02-26 |
| 20090055603 | MODIFIED COMPUTER ARCHITECTURE FOR A COMPUTER TO OPERATE IN A MULTIPLE COMPUTER SYSTEM - A modified computer architecture ( | 2009-02-26 |
| 20090055604 | Systems and methods for portals into snapshot data - In one embodiment, a user or client device communicates with a distributed file system comprised of one or more physical nodes. The data on each of the physical nodes store metadata about files and directories within the file system. Some of the embodiments permit a user to take a snapshot of data stored on the file system. The snapshot may include a single file, a single directory, a plurality of files within a directory, a plurality of directories, a path on the file system that includes nested files and subdirectories, or more than one path on the file system that each includes nested files and directories. In some embodiments, systems and methods intelligently choose whether to use copy-on-write or point-in-time copy when saving data in a snapshot version of a file whose current version is being overwritten. In some embodiments, systems and methods allow snapshot users to return from a snapshot directory to the immediate parent directory from which the user entered into the snapshot. | 2009-02-26 |
| 20090055605 | METHOD AND SYSTEM FOR OBJECT-ORIENTED DATA STORAGE - In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read/write speed requirements. A data block to be written may be considered an object, and is examined, and from its attributes one or more memory device operating modes may be determined, such as different numbers of bits per cell, different numbers of error-correction code (ECC) parities per user data block, and encryption vs. lack of encryption. The storage controller then performs the writing process according to the mode(s) of operation determined by the attributes. Multi-level flash memory, in particular, is capable of operating in these various modes, at a trade-off between reliability, speed, endurance on the one hand, and capacity on the other hand. | 2009-02-26 |
| 20090055606 | CONVERTING BACKUP COPIES OF OBJECTS CREATED USING A FIRST BACKUP PROGRAM TO BACKUP COPIES CREATED USING A SECOND BACKUP PROGRAM - Provided are a method, system, and article of manufacture for converting backup copies of objects created using a first backup program to backup copies created using a second backup program. A plurality of backup copies of versions of an object are created using a first backup program, wherein the object has an object name. The first backup program is used to restore at least one of the backup copies to a restored version of the object having a name different from the object name. A second backup program is used to create a backup copy of each restored version of the object. A name of a designated object is assigned to each backup copy created using the second backup program. Metadata of each backup copy created using the second backup program is updated with metadata for the designated object. | 2009-02-26 |
| 20090055607 | Systems and methods for adaptive copy on write - In one embodiment, a user or client device communicates with a distributed file system comprised of one or more physical nodes. The data on each of the physical nodes store metadata about files and directories within the file system. Some of the embodiments permit a user to take a snapshot of data stored on the file system. The snapshot may include a single file, a single directory, a plurality of files within a directory, a plurality of directories, a path on the file system that includes nested files and subdirectories, or more than one path on the file system that each includes nested files and directories. In some embodiments, systems and methods intelligently choose whether to use copy-on-write or point-in-time copy when saving data in a snapshot version of a file whose current version is being overwritten. In some embodiments, systems and methods allow snapshot users to return from a snapshot directory to the immediate parent directory from which the user entered into the snapshot. | 2009-02-26 |
| 20090055608 | PREVENTIVE MEASURE AGAINST DATA OVERFLOW FROM DIFFERENTIAL VOLUME IN DIFFERENTIAL REMOTE COPY - In a computer system that executes remote copy of differential data between snapshots, data overflow in a differential volume of a secondary site is prevented when update data of a primary volume increases in amount. A controller of a primary site predicts whether or not data overflow happens in the differential volume of the secondary site and, predicting that data overflow happens, delays data write processing in which a host computer writes data in the primary volume by a given period of time. | 2009-02-26 |
| 20090055609 | SYSTEMS FOR DYNAMICALLY RESIZING MEMORY POOLS - There are disclosed systems and computer program products for dynamically resizing memory pools used by database management systems. In one aspect, if a decrease in allocation to the memory pool is required, at least one page grouping that may be freed from the memory pool is identified as a candidate based on its position in a list of page groupings. If the page grouping contains any used memory blocks, the used memory blocks may be copied from a candidate page grouping to another page grouping in the list in order to free the candidate page grouping. Once the candidate page grouping is free of used memory blocks, the candidate page grouping may be freed from the memory pool. As an example, this system or computer program product may be used for dynamically resizing locklists or lock memory. | 2009-02-26 |
| 20090055610 | MAINTAINING CONSISTENCY FOR REMOTE COPY USING VIRTUALIZATION - Provided are a system and article of manufacture for copying storage, wherein a first unit receives data updates from a second unit. The data updates are stored in a plurality of physical storage locations associated with the first unit. Links are generated to at least one of the plurality of physical storage locations to achieve consistent data between the first unit and the second unit. | 2009-02-26 |
| 20090055611 | REORGANIZING A WAGERING GAME MACHINE'S NVRAM - This document discusses, among other things, systems and methods for managing the contents of NVRAM in a wagering game machine. A method copies a first data of an NVRAM module to a storage device, wherein the NVRAM module is associated with a wagering game machine and then copies a second data to the NVRAM module. | 2009-02-26 |
| 20090055612 | SECURE PROCESSING UNIT SYSTEMS AND METHODS - A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of hardware resources. Because the additional hardware required to support security functions is a relatively small fraction of the overall device hardware, this type of SPU can be competitive with ordinary non-secure CPUs or microcontrollers that perform the same functions. A set of minimal initialization and management hardware and software is added to, e.g., a standard CPU/microcontroller. The additional hardware and/or software creates an SPU environment and performs the functions needed to virtualize the SPU's hardware resources so that they can be shared between security functions and other functions performed by the same CPU. | 2009-02-26 |
| 20090055613 | STORAGE SYSTEM PERFORMING VIRTUAL VOLUME BACKUP AND METHOD THEREOF - The respective data fragments stored in each page assigned to the respective virtual areas of the virtual volume are copied to the logical volume, and information representing the respective copy source pages corresponding with information representing the respective virtual areas in the mapping information that indicates which storage area corresponds with which virtual area is updated to information representing the respective copy destination storage areas of the data fragments stored in the respective copy source pages and copies the updated mapping information to the logical volume which constitutes the data fragment copy destination. | 2009-02-26 |
| 20090055614 | Information processing program and information processing apparatus - A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attitude out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attitude different from the attitude in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined. | 2009-02-26 |
| 20090055615 | MEMORY TUNING FOR GARBAGE COLLECTION AND CENTRAL PROCESSING UNIT (CPU) UTILIZATION OPTIMIZATION - A method, system and computer program product for garbage collection sensitive load balancing is disclosed. The method for memory tuning for garbage collection and CPU utilization optimization can include benchmarking an application across multiple different heap sizes to accumulate garbage collection metrics and utilizing the garbage collection metrics accumulated during benchmarking to compute both CPU utilization and garbage collection time for each of a selection of candidate heap sizes. One of the candidate heap sizes can be matched to a desired CPU utilization and garbage collection time, and the matched one of the candidate heap sizes can be applied to a host environment. | 2009-02-26 |
| 20090055616 | MAINTAINING RESERVED FREE SPACE FOR SEGMENTED LOGICAL VOLUMES - A storage manager application implemented in a first computational device maintains a virtual logical volume having a plurality of segments created by the storage manager application, wherein space is reserved at the end of a physical volume corresponding to the virtual logical volume, and wherein the physical volume comprises a linear storage medium. A request is received to write data, at the first computational device, from a second computational device. The data is written to the reserved space, wherein the writing of the data causes new segments to be created in the reserved space. | 2009-02-26 |
| 20090055617 | Apparatus, System, and Method for Dynamically Allocating Main Memory Among A Plurality of Applications - A method is disclosed for dynamically allocating main memory among applications. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size. | 2009-02-26 |
| 20090055618 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD - For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges ( | 2009-02-26 |
| 20090055619 | DISK FORMATTER AND METHODS FOR USE THEREWITH - A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data. | 2009-02-26 |
| 20090055620 | DEFECT MANAGEMENT USING MUTABLE LOGICAL TO PHYSICAL ASSOCIATION - The application relates to defect management using mutable logical to physical association. Embodiments disclosed utilize mutable mapping between logical blocks and physical blocks. Dynamically updated mapping data, which mutably associates the logical blocks and the physical blocks, also includes physical block defect allocations. | 2009-02-26 |
| 20090055621 | Column redundancy system for a memory array - A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to which memory of the main memory are mapped. Each replacement unit includes columns of redundant memory arranged in input-output (IO) groups and further includes columns of redundant memory from a plurality of IO groups. The IO groups have columns of memory associated with a plurality of different IOs and the plurality of IO groups of the replacement unit adjacent one another. | 2009-02-26 |
| 20090055622 | Processor, virtual memory system, and virtual storing method - A processor includes an address specifying unit that specifies an address range on a virtual storage area; an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range; a calculating unit that calculates the data corresponding to the address range, according to the instruction code set for the address range; a load instruction obtaining unit that obtains a load instruction for the specified address range; and a data output unit that supplies the data calculated by the calculating unit corresponding to the address range indicated by the load instruction, as data for the load instruction. | 2009-02-26 |
| 20090055623 | Method and Apparatus for Supporting Shared Library Text Replication Across a Fork System Call - A fork system call by a first process is detected. A second process is created as a replication of the first process with a second affinity. If a replication of the replicated shared library is present in the second affinity domain, effective addresses of the replication of the replicated shared library are mapped using a mapping mechanism of the present invention to physical addresses in the second affinity domain. | 2009-02-26 |
| 20090055624 | CONTROL OF PROCESSING ELEMENTS IN PARALLEL PROCESSORS - The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a row select line connecting to all of the processing elements in the row. A processing element in the array may be selected by activation of its row and column select lines. | 2009-02-26 |
| 20090055625 | Parallel Processing Systems And Method - Methods and systems for parallel computation of an algorithm using a plurality of nodes configured as a Howard Cascade. A home node of a Howard Cascade receives a request from a host system to compute an algorithm identified in the request. The request is distributed to processing nodes of the Howard Cascade in a time sequence order in a manner to minimize the time to so expand the Howard Cascade. The participating nodes then perform the designated portion of the algorithm in parallel. Partial results from each node are agglomerated upstream to higher nodes of the structure and then returned to the host system. The nodes each include a library of stored algorithms accompanied by data template information defining partitioning of the data used in the algorithm among the number of participating nodes. | 2009-02-26 |
| 20090055626 | METHOD OF SHARING COARSE GRAINED ARRAY AND PROCESSOR USING THE METHOD - A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core. | 2009-02-26 |
| 20090055627 | Efficient Pipeline Parallelism Using Frame Shared Memory - A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory. | 2009-02-26 |
| 20090055628 | METHODS AND COMPUTER PROGRAM PRODUCTS FOR REDUCING LOAD-HIT-STORE DELAYS BY ASSIGNING MEMORY FETCH UNITS TO CANDIDATE VARIABLES - Assigning each of a plurality of memory fetch units to any of a plurality of candidate variables to reduce load-hit-store delays, wherein a total number of required memory fetch units is minimized. A plurality of store/load pairs are identified. A dependency graph is generated by creating a node Nx for each store to variable X and a node Ny for each load of variable Y and, unless X=Y, for each store/load pair, creating an edge between a respective node Nx and a corresponding node Ny; for each created edge, labeling the edge with a heuristic weight; labeling each node Nx with a node weight Wx that combines a plurality of respective edge weights of a plurality of corresponding nodes Nx such that Wx=Σω | 2009-02-26 |
| 20090055629 | Instruction length determination device and method using concatenate bits to determine an instruction length in a multi-mode processor - An instruction length determination device includes an instruction input unit having a memory space to store a plurality of N-bit data; an instruction fetch unit which fetches the plurality of N-bit data from the instruction input unit; an instruction length determination logic which compares concatenate bits of a first N-bit data with a predetermined value for determination of an instruction length; and an instruction concatenate unit which selectively concatenates a number of successive N-bit data based on the determination. The instruction length determination logic determines that the first N-bit data is a complete instruction when the concatenate bit of the first N-bit data is not equal to the predetermined value. Otherwise, the instruction length determination logic determines that a complete instruction is formed of last N-bit data finally fetched and all N-bit previously reserved. | 2009-02-26 |
| 20090055630 | Program Processing Device, Parallel Processing Program, Program Processing Method, Parallel Processing Compiler, Recording Medium Containing The Parallel Processing Compiler, And Multi-Processor System - In a multi-processor system for performing a parallel processing, each of a plurality of processors includes a communication processing unit for performing control between the processors in a data flow machine-type data-driven control method; and a program processing unit for performing control in each processor in a Neumann-type program-driven control method. The communication processing unit performs a communication between the processors in synchronization with the program processing unit, and has a function of detecting a communication data hazard between the processors. The program processing unit performs a processing based on an execution code stored in a local memory, and has a function of executing or suspending the execution code, according to a result of detecting the data hazard. | 2009-02-26 |
| 20090055631 | Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search - A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time. | 2009-02-26 |
| 20090055632 | Emulation Scheme for Programmable Pipeline Fabric - The present invention allows emulation of a programmable pipeline processor fabric or architecture. According to certain aspects, the invention permits real-time capture of state information for any given stage of a processing flow performed by the fabric or architecture. According to other aspects, the invention allows a particular stage and data set of a SIMD flow to be analyzed. According to other aspects, the invention utilizes an independent clocking domain for the capture of state information. | 2009-02-26 |
| 20090055633 | COMPUTER PROCESSING SYSTEM EMPLOYING AN INSTRUCTION REORDER BUFFER - A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implementing a Super Re-Order Buffer (SuperROB) in which received instructions are re-ordered after out-of-order execution when at least one of the plurality of processors is in an Instruction Level Parallelism (ILP) mode and at least one of the plurality of processors has a Thread Level Parallelism (TLP) core; detecting an imbalance in a dispatch of instructions of a first dependence chain compared to a dispatch of instructions of a second dependence chain with respect to dependence chain priority; determining a source of the imbalance; and activating the ILP mode when the source of the imbalance has been determined. | 2009-02-26 |
| 20090055634 | COMPILING METHOD, APPARATUS, AND PROGRAM - Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal. | 2009-02-26 |
| 20090055635 | PROGRAM EXECUTION CONTROL DEVICE - A program execution control device which controls execution of a program by a processor having a predicate function for conditional execution of an instruction, wherein the program includes a branch instruction to control iterations in loop processing, the branch instruction is further an instruction to generate an execute-or-not condition indicating whether or not the branch instruction is to be executed at an iteration in the loop processing after a current iteration, and to reflect the execute-or-not condition on a predicate flag used for conditional execution of the branch instruction, the program execution control device comprises a processor status changing unit configured to change, before an execution cycle of the branch instruction, a status of the processor in advance for execution of an instruction following the branch instruction, the status being changed based on the execute-or-not condition reflected on the predicate flag. | 2009-02-26 |
| 20090055636 | METHOD FOR GENERATING AND APPLYING A MODEL TO PREDICT HARDWARE PERFORMANCE HAZARDS IN A MACHINE INSTRUCTION SEQUENCE - A computer implemented method, data processing system, and computer program product for generating and applying a model to predict hardware performance hazards in a machine instruction sequence. The illustrative embodiments generate rules which specify relationships between a first instruction code sequence and hardware performance hazards. This rule generation is performed as a machine task rather than a human task (e.g., traditional hand coding tools). When a second instruction code sequence is received, the rules are applied to the second instruction code sequence. Responsive to a prediction that execution of the second instruction code sequence will cause the hardware performance hazards, instructions in the second instruction code sequence that cause the hardware performance hazards are identified. | 2009-02-26 |
| 20090055637 | SECURE POWER-ON RESET ENGINE - A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party. | 2009-02-26 |
| 20090055638 | Algorithm update system - A design data storage unit stores a plurality of pieces of design data. A judgment unit | 2009-02-26 |
| 20090055639 | Methods and system for modular device booting - The present invention a method for modular device booting comprising retrieving a first boot code from a non-volatile memory element, receiving a memory access request from at least one subsystem, said memory access including at least a boot status indication indicating a memory region and a memory address, if said received address and region match a predefined address and region, associating said at least one subsystem with a corresponding subsystem boot code address included in said retrieved first boot code, retrieving a corresponding subsystem boot code from said associated boot code address, and transferring said boot code to said corresponding subsystem. | 2009-02-26 |
| 20090055640 | Masking a Hardware Boot Sequence - One of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. Such masking may involve running the same boot code as the boot processor but without obtaining access to security information, such as the security key for accessing the system. The electromagnetic and/or thermal signatures generated by the execution of the masking code preferably approximate the electromagnetic and/or thermal signatures of the actual boot code executing on the boot processor. In this way, it is difficult to distinguish which processor is the actual boot processor. | 2009-02-26 |
| 20090055641 | Method and apparatus for virtualization of a multi-context hardware trusted platform module (TPM) - In one embodiment, the present invention includes a method for receiving a request for a trusted platform module (TPM) operation from a virtual machine, determining whether the request is for a modification of a TPM version, and associating part of a multi-context hardware TPM with a virtual TPM (vTPM) to enable the modification. Other embodiments are described and claimed. | 2009-02-26 |
| 20090055642 | Method, system and computer program for protecting user credentials against security attacks - A method, system and computer program is provided for protecting against one or more security attacks from third parties directed at obtaining user credentials on an unauthorized basis, as between a client computer associated with a user and a server computer is provided. The server computer defines a trusted Public Key Cryptography utility for use on the client computer. The Public Key Cryptography utility is operable to perform one or more cryptographic operations consisting of encrypting/decrypting data, authenticating data, and/or authenticating a sender, decrypting and/or verifying data. The user authenticates to the Public Key Cryptography utility, thereby invoking the accessing of user credentials associated with the user, as defined by the server computer. The Public Key Cryptography Utility facilitates the communication of the user credentials to the server computer, whether directly or indirectly via an authentication agent, the server computer thereby authenticating the user. In response, the server computer providing access to one or more system resources linked to the server computer to the user. The present invention also provides a series of methods enabling the server computer to authenticate the user by operation of the Public Key Cryptography utility and/or based on enrolment of the user and providing the Public Key Cryptography utility to the user. | 2009-02-26 |
| 20090055643 | SYSTEM AND METHOD FOR DISPLAYING A SECURITY ENCODING INDICATOR ASSOCIATED WITH A MESSAGE ATTACHMENT - An apparatus and method of displaying a message on a display of a computing device. The message comprises at least a first attachment. At least a portion of the message is displayed to a user. The displayed portion comprises an identifier for the first attachment. In one embodiment, a security encoding indicator is associated with the identifier for the first attachment and displayed to the user. If a security encoding has been applied to the first attachment, the security encoding indicator indicates the security encoding applied to the first attachment. | 2009-02-26 |
| 20090055644 | ADDRESS LIST MANAGEMENT APPARATUS, ADDRESS LIST MANAGEMENT METHOD, AND STORAGE MEDIUM - An address list management apparatus stores, for each user of an MFP (Multi Function Peripheral), a different address list that lists address information pieces for transmission of image data by the MFP. Upon being instructed by a logged-in user to transmit image data, the MFP transmits, to the address list management apparatus, a request for the address list that specifies the user. Upon receiving the request, the address list management apparatus transmits, to the MFP, a sending list pertaining to the user. The sending list is created by deleting secret information from address information pieces in the address list, and modifying such address information pieces so that image data is transmitted to the address list management apparatus. The address list management apparatus refers to the address list, and transfers the image data to the specified address. | 2009-02-26 |
| 20090055645 | METHOD AND APPARATUS FOR CHECKING ROUND TRIP TIME BASED ON CHALLENGE RESPONSE, AND COMPUTER READABLE MEDIUM HAVING RECORDED THEREON PROGRAM FOR THE METHOD - An apparatus and method of checking adjacency between devices are provided. A challenge response based round trip time (RTT) checking method includes: generating a random number; encrypting the random number using a symmetrical key; transmitting a challenge request message including the encrypted random number to a device; receiving a challenge response message including the random number from the device which received the challenge request message and decrypted the encrypted random number using the symmetrical key, from the device; and determining an RTT based on a time when the challenge response message is received and a time when the challenge request message is transmitted. | 2009-02-26 |
| 20090055646 | DISTRIBUTED MANAGEMENT OF CRYPTO MODULE WHITE LISTS - An apparatus and method for managing the distribution and expansion of public keys held by a group or array of systems in white lists. The addition of a new system to the array entails a manual input to authorize the introduction of the new system to one trusted system in the array. After the introduction the new system is trusted by the one member and the white list of the one member is loaded into the white list of the new system. The new system then requests joining each of the other systems in the array. For each system in the array asked by the new system, the systems in the array ask if any other systems in the array already trust the new member. In response, a system of the array that trusts the new system responds by sending its white list (containing the public key of the new system) to the requesting system. Eventually the public key of the new system is in the white lists of all the systems in the array. In practice this trusts expansion occurs in the background with respect to running applications. | 2009-02-26 |
| 20090055647 | Auxiliary display system, device and method - The present invention provides an auxiliary display system, device and method. The auxiliary display system includes a client and a server. The client includes an auxiliary display unit which further includes a security module. The server generates information to be shown in the auxiliary display unit, and uses a shared encryption key of the auxiliary display unit to encrypt the information. The security module uses the shared encryption key to verify validity of encrypted information from the server, and decrypts the encrypted information so that the decrypted information will be shown in the auxiliary display unit. The present invention can prevent from forging the auxiliary display information by malicious programs and provide users with reliable information display, and improve experience of the users. | 2009-02-26 |
| 20090055648 | METHOD OF AND APPARATUS FOR SHARING SECRET INFORMATION BETWEEN DEVICE IN HOME NETWORK - A method and apparatus for sharing secret information between devices in a home network are provided. In the method and apparatus, home network devices receive a password (credential) input by a user and encrypt secret information based on the credential by using keys generated according to a predetermined identity-based encryption (IBE) scheme. Accordingly, it is possible to securely share the secret information between home network devices without any certificate authority or certificate. | 2009-02-26 |
| 20090055649 | KEY ALLOCATING METHOD AND KEY ALLOCATION SYSTEM FOR ENCRYPTED COMMUNICATION - Both a management server and a validation server are installed. Both a terminal and a terminal register setting information which is usable in an encrypted communication in the management server. When carrying out the encrypted communication, the management server searches the registered setting information for coincident setting information. The management server generates keys for the encrypted communications which can be used by the terminals, and delivers these generated keys in combination with the coincident setting information. The management server authenticates both the terminals in conjunction with the validation server. Since the terminals trust such results that the management server has authenticated the terminals respectively, these terminals need not authenticate the respective communication counter terminals. | 2009-02-26 |
| 20090055650 | CONTENT PLAYBACK DEVICE, CONTENT PLAYBACK METHOD, CONTENT PLAYBACK PROGRAM, AND INTEGRATED CIRCUIT - When a plurality of types of copyright information are detected on a disk or the like, a content playback device and method can appropriately control playback of content in accordance with the copyright information. As the content playback device, a digital watermark detection device attempts to detect watermark information in blocks that make up the content, and a result storage subunit ( | 2009-02-26 |
| 20090055651 | AUTHENTICATED MEDIA COMMUNICATION SYSTEM AND APPROACH - Media authentication is facilitated. In connection with an example embodiment, media is authenticated using an encoded projection of the media that is decoded using the media as an input. A condition of authenticity of the media is determined based upon an indication of distortion of the media characterized by a decoding of the encoded projection. | 2009-02-26 |
| 20090055652 | SYSTEM AND METHOD FOR SECURING ONLINE CHAT CONVERSATIONS - A system, method and program product for securing online chat conversations. The disclosed method includes the steps of capturing a chat conversation into an image file; adding a watermark to the image file; extracting the watermark from the watermarked image file; and validating the watermark. | 2009-02-26 |
| 20090055653 | Computerized data management method and computerized data management system using the same - A computerized data management method and a computerized data management system using the same are provided. The computerized data management method is used for encrypting/decrypting a digital data of an electronic device. The computerized data management method comprises the following steps. Firstly, a user's facial characteristic is captured. Next, whether the user's facial characteristic matches with an encrypting-permission user's facial characteristic stored in a database is determined in an encrypting process. If the user's facial characteristic matches with the encrypting-permission user's facial characteristic stored in the database, then the user is allowed to encrypt a digital data. Then, whether the user's facial characteristic matches with a facial characteristic of a decrypting-permission user corresponding a digital data is determined in a decrypting process. If the user's facial characteristic matches with the facial characteristic of the decrypting-permission user corresponding the digital data, then the user is allowed to decrypt the digital data. | 2009-02-26 |
| 20090055654 | SECURE ENTRY OF A USER-IDENTIFIER IN A PUBLICLY POSITIONED DEVICE - A method for secure entry of a user-identifier in a publicly positioned device can include establishing a private communications link between a user and the publicly positioned device; dividing the user-identifier into at least two portions; separately prompting the user for each portion of the user-identifier; prompting the user for a combination of random data and the user-identifier; and, discarding the random data from the combination. In the preferred embodiments, the publicly positioned device can have a visual interface through which the user can be visually prompted for the random data and the user-identifier. Alternatively, the publicly positioned device can have a telephone interface through which the user can be audibly prompted for the random data and the user-identifier. In the case of a visual display, the private communications link can be established by linking the publicly positioned device to active glasses having a shuttered display. The opening and closing of the shuttered display can be synchronized with the display of the prompts in the visual interface such that only the wearer of the active glasses can view the prompts. In the case of a telephone interface, an telephone operator system, for example an Interactive Voice Response system or a human operator, can provide the prompts audibly through the telephone interface. | 2009-02-26 |
| 20090055655 | Apparatus and Method For Securing Data on a Portable Storage Device - A portable storage device including a microprocessor and a secure user data area, the microprocessor operable to perform on-the-fly encryption/decryption of secure data stored on the storage device under a user password, the microprocessor also operable to exclude access to the secure user data area unless the user password is provided. | 2009-02-26 |
| 20090055656 | Method of Maintaining Software Integrity - A method of maintaining the integrity of software stored in memory, the method comprising: storing an indicator associated with the memory; calculating a reference value from the stored indicator; storing the reference value; modifying the indicator when the software in the memory is modified; storing the modified indicator; recalculating the reference value from the modified indicator; storing the recalculated reference value; and verifying the integrity of the software by: retrieving the modified indicator; calculating an expected value from the modified indicator; and comparing the expected value with the recalculated reference value. Preferably the integrity of the software is verified without calculating an expected value from the software. The reference and expected values are typically calculated in accordance with a secret key. | 2009-02-26 |
| 20090055657 | Program Converting Device, Secure Processing Device, Computer Program, and Recording Medium - To provide a program conversion device capable of executing a program that includes a secret operation for decrypting encrypted data using secret information without exposure of the secret information in a memory thereby to improve confidentiality in execution of the program. In an execution program generation device | 2009-02-26 |
| 20090055658 | Authenticating and Verifying an Authenticable and Verifiable Module - A module-specific public key and cryptographically protected data related to the module-specific public key are extracted from an authenticable and verifiable module. The cryptographically protected data is compared with the module-specific public key to authenticate the authenticable and verifiable module. A value calculated from an image, including a size and location block, included within the authenticable and verifiable module is compared with a value extracted from a digital signature contained in a verification block within the authenticable and verifiable module to verify the authenticable and verifiable module. | 2009-02-26 |
| 20090055659 | Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies - A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing. | 2009-02-26 |
| 20090055660 | Security flash memory, data encryption device and method for accessing security flash memory - The present invention discloses a security flash memory which includes a flash memory chip with a plurality of data transmission terminals, and a data encryption device. The data encryption device includes a verifier module with default pass code, a secret key module and a switching module. The verifier module compares a pass code with the default pass code for outputting a control signal. The secret key module is used for data encryption and data decryption. The switching module is connected to the verifier module, the data transmission terminals of the flash memory chip and the secret key module, and may connect or disconnect the data transmission terminals of the flash chip and the secret key module in response to the control signal. | 2009-02-26 |
| 20090055661 | ALWAYS-ON SYSTEM - The invention relates to an always-on system mainly provided with a control unit to govern a power supply switch unit. When one of main power supply units or a bypass power supply unit of an external power supply device is to be installed or uninstalled, a user can operate the control unit to enable the power supply switch unit to switch to the main power supply unit or the bypass power supply unit that is not to be installed or uninstalled to provide power for loads connected with the always-on system to operate continuously, without interrupting the operation of the load. | 2009-02-26 |
| 20090055662 | MIDSPAN POWERING IN A POWER OVER ETHERNET SYSTEM - A midspan power sourcing equipment (PSE) for operation with power over Ethernet (PoE). The midspan PSE provides powering over wire pairs that are also used for data communication. To ensure compatibility with legacy Ethernet devices, the ports used for transmission of data are designed to present an increased level of inductance. | 2009-02-26 |
| 20090055663 | POWER SUPPLY CONTROL SIGNAL GENERATING CIRCUIT - A power supply control signal generating circuit includes a connector, a switch, a transistor, and an input-output (I/O) controller. The connector includes a first pin and a grounded second pin. The switch has two terminals respectively coupled to the first pin and the second pin of the connector. The transistor has its base coupled to the first pin of the connector and a power supply via a first resistor, its collector coupled to the power supply via a second resistor, and its emitter grounded. The I/O controller has an input terminal coupled to the collector of the transistor, and outputs a power supply control signal at the output terminal. | 2009-02-26 |
| 20090055664 | Communication Device - A communication device includes a bus including a signal line supplied with a pull-up voltage Vp, a first power supply operating during both a standby state and a power-ON state, and supplies a source of a first predetermined voltage of 3.3V, a second power supply operating during only the power-ON state, and supplies a source of a second predetermined voltage of 5V, a first device driven by the first power supply, and capable of communicating via the bus when the pull-up voltage Vp is equal to either of 3.3V and 5V, a second device driven by the second power supply, and capable of communicating via the bus when the pull-up voltage Vp is equal to 5V, and a pull-up voltage supply circuit supplying the pull-up voltage Vp by the first power supply during the standby state, and supplying the pull-up voltage Vp by the second power supply during the power-ON state. | 2009-02-26 |
| 20090055665 | Power Control of Servers Using Advanced Configuration and Power Interface (ACPI) States - A method of managing power consumption by a plurality of blade servers within a processing system. The speed of at least one of the plurality of blade servers is reduced in response to the processing system reaching a power or thermal threshold. At least one of the plurality of blade servers is identified as not being critical to maintain in a working state and the critical blade server is put in a sleep state. A satellite management controller may control blade server power consumption and heat generation in various ways that combine processor speed-stepping and control of processor sleep states. Known sleep states save more power than speed-stepping by turning off the processor and/or volatile memory. The processor speed and sleep-states of at least one non-critical blade server, and optionally the processor speed of a critical processor, may be changed in order to control the power consumption below a power threshold or control the temperature below a thermal threshold. | 2009-02-26 |
| 20090055666 | POWER SAVINGS FOR A NETWORK DEVICE - An example embodiment is illustrated to reduce power consumed by inactive connections. This embodiment may include detecting a connection condition signifying a requirement for an active connection between one network device and another network device. Thereafter, an enable instruction may be retrieved based upon the detecting of the connection condition, and a port may be enabled based upon the retrieved enable instruction resulting in increased electrical power consumption by a port component. The electrical power consumption may be increased relative to a prior level of electrical power consumption in which the port is disabled. | 2009-02-26 |
| 20090055667 | MEMORY CARD WITH POWER SAVING - A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate. | 2009-02-26 |
| 20090055668 | Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design - A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies. | 2009-02-26 |
| 20090055669 | METHOD, COMPUTER SYSTEM AND CONTROL DEVICE FOR REDUCING POWER CONSUMPTION - A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result. | 2009-02-26 |
| 20090055670 | MODE-SWITCHING SYSTEM AND CAMERA - A mode-switching system, comprising plural switches, a timer, and a controller, is provided. The mode-switching system switches an operation mode of a first unit to one of normal and power-saving modes. The plural switches separately correspond to plural specific functions. Each of the specific functions is carried out when the corresponding switch is switched on. The timer clocks the elapsed time since the switching operation is carried out for any of the switches. The controller switches the operation mode to the power-saving mode from the normal mode when the elapsed time exceeds a threshold value determined for the switch for which the latest switching operation has been carried out. The threshold value is determined individually for each of the switches. | 2009-02-26 |
| 20090055671 | Apparatus and method for entering idle mode in a broadband wireless access (BWA) system - A power saving mode is provided. A method for entering a power saving mode of a terminal includes a first operation for starting a first timer after transmitting an idle mode request message; a second operation for, when an idle mode approval message is not received until the first timer expires, checking whether a number of retransmissions of the idle mode request message exceeds a number of allowed retransmissions of the idle mode request message; a third operation for, when the number of the retransmissions of the idle mode request message exceeds the number of the allowed retransmissions of the idle mode request message, increasing a number of idle mode entry failures; and a fourth operation for, when the increased number of the idle mode entry failures is greater than N times, entering a power saving mode which powers off a modem. | 2009-02-26 |
| 20090055672 | Power Budget Management In Power Over Ethernet Systems - A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node into a monitor current. The second resistor has a resistance value proportional to a maximum power budget of the PSE and receives the monitor current. A monitor voltage develops across the second resistor indicative of the total power demanded by the power ports. The comparator compares the monitor voltage to the reference voltage and provides a comparator output signal indicating whether the maximum power budget of the PSE has been exceeded. | 2009-02-26 |
| 20090055673 | MULTI-FUNCTION PERPIHERAL DEVICE - A multi-function peripheral device includes: a plurality of interfaces that communicate data with an external devices; a power source for supplying the interfaces with power required for the respective interfaces to operate; a monitoring unit that monitors operational statuses of the respective interfaces; a display unit that displays a parameter indicating the operational status of each of the interfaces monitored by the monitoring unit; an input unit that is capable of inputting a command indicating whether or not power is to be supplied from the power source to each of the interfaces; and a power control unit that controls to supply power to an interface for which a command indicating that power is to be supplied is inputted by the input unit, and controls to shut off power to an interface for which a command indicating that power is not to be supplied is inputted by the input unit. | 2009-02-26 |
| 20090055674 | Method and device for a switchover and for a data comparison in a computer system having at least two processing units - A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data. | 2009-02-26 |
| 20090055675 | Adjustable Byte Lane Offset For Memory Module To Reduce Skew - Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors. | 2009-02-26 |
| 20090055676 | Apparatus and method for redundant and spread spectrum clocking - An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a predetermined range of frequencies. A slave clock synthesizer circuit is provided to track the output clock signal generated by the master clock synthesizer circuit. If the master clock synthesizer circuit fails or generates an invalid output clock signal, the slave clock synthesizer circuit takes over and functions as the master clock synthesizer circuit. In one embodiment a method of fault-tolerant spread spectrum clocking includes generating a first digital data stream; receiving the first digital data stream, a first input reference signal and a first clock signal in a master clock synthesizer circuit; generating an first output clock signal of varying frequency by the master clock synthesizer circuit in response to the first digital data stream and the first clock signal. | 2009-02-26 |
| 20090055677 | Asynchronous first in first out interface and operation method thereof - The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer. | 2009-02-26 |
| 20090055678 | Clock processors in high-speed signal converter systems - Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs. | 2009-02-26 |
| 20090055679 | Recovery Of A Redundant Node Controller In A Computer System - Recovery of a redundant node controller in a computer system including determining a loss of a heartbeat for a predefined period of time between a system controller and the redundant node controller; in response to determining the loss of the heartbeat for the predefined period of time, checking network connectivity between the system controller and the redundant node controller; if there is network connectivity between the system controller and the redundant node controller, determining whether an application on the redundant node controller is running; and if an application on the redundant node controller is running, resetting the redundant node controller through a primary node controller. | 2009-02-26 |
| 20090055680 | NONVOLATILE STORAGE DEVICE, MEMORY CONTROLLER, AND DEFECTIVE REGION DETECTION METHOD - It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erasing in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data written by physical erasing after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors. | 2009-02-26 |
| 20090055681 | INTRA-DISK CODING SCHEME FOR DATA-STORAGE SYSTEMS - Exemplary embodiments of the present invention comprise a method for the use of an intra-disk redundancy storage protection operation for the scrubbing of a disk. The method comprises initiating a disk scrubbing operation upon each disk of a plurality of disks that are comprised within a storage disk array, issuing a disk scrubbing command for a predetermined segment of the disks that are comprised within the storage disk array at a predetermined time interval, and identifying an unrecoverable segment on a disk. The method further comprises determining if unrecoverable sectors comprised within the unrecoverable segment can be reconstructed, and reconstructing the unrecoverable sectors of the unrecoverable segment and relocating the segment to a spare storage location on the disk in the event that the segment cannot be reconstructed within its original storage location. | 2009-02-26 |
| 20090055682 | Data storage systems and methods having block group error correction for repairing unrecoverable read errors - Data storage systems and methods perform error correction on a single physical storage disk. The technique includes arranging a plurality of addressable blocks on the single physical storage disk into error correction groups, wherein each error correction group includes N data blocks and M coding blocks. M is determined in accordance with a desired failure tolerance of the error correction groups and an error-correcting code. For each error correction group, error-correcting code data is computed across the N data blocks in the error correction group. The computed error-correcting coding data is stored in the M coding blocks in the error correcting group. The arranging, computing and storing steps are performed by a hardware or software component external to the single physical storage disk. | 2009-02-26 |
| 20090055683 | Method of restoring previous computer configuration - A method of handling and storing data in a computer by establishing a plurality of zones or sessions with different levels of write protection, writing attempted changes to data stored in a protected zone to a temporary zone, creating representative maps of some or all of the zones or sessions to track such attempted changes, reading the changes from the temporary zone such that it seems as though the changes were successful, and erasing the temporary zone when the computer is restarted, thereby allowing for “restoring” the data, or, more generally, the computer's configuration, to a state prior to the attempted change. One of the zones may contain working files which are relatively frequently changed, and such changes are treated, e.g., saved, in a substantially conventional manner and not affected by restarting the computer. Access to specific non-temporary zones may be restricted. | 2009-02-26 |
| 20090055684 | METHOD AND APPARATUS FOR EFFICIENT PROBLEM RESOLUTION VIA INCREMENTALLY CONSTRUCTED CAUSALITY MODEL BASED ON HISTORY DATA - A system for problem resolution in network and systems management includes a database of trouble ticket data including information fields for checked components and affected components, an automated model builder system that processes the trouble ticket data to construct a causality model to represent causality information between system components identified in the checked component and affected component fields of the trouble ticket data, and an automated problem analysis system that receives information indicative of a problem event and determines a cause of the problem event using the causality model. | 2009-02-26 |
| 20090055685 | Electronic apparatus in which functioning of of a microcomputer is monitored by another microcomputer to detect abnormal operation - In an electronic apparatus, a first microcomputer is monitored by a second microcomputer, which periodically transmits data relating to a main function to the first microcomputer to be processed. The first microcomputer periodically updates a variable value, performs a predetermined calculation operation whose final result should be a specific fixed value, adds that final result to the updated variable value to obtain a sum value, and transmits the sum value and updated variable value concurrently to the second microcomputer. The second microcomputer determines that the first microcomputer is operating abnormally if the difference between the received sum value and variable value is not equal to the specific fixed value. | 2009-02-26 |
| 20090055686 | SERVER SIDE LOGIC UNIT TESTING - A method for server side logic unit testing in an application server environment is provided. The method includes reading a plurality of input parameters from an XML input repository, where the input parameters define an initial state of a test environment, and configuring the test environment to the initial state using the input parameters. The method further includes executing a unit test case using a command test manager to interface between the unit test case and the test environment, where the command test manager translates a command from the unit test case into a test command. The method also includes passing the test command to controller command logic, and accessing test data stored in a database through an access bean using a bean simulator. The method additionally includes receiving test results, including catching an exception on an error condition, and outputting the test results to an XML output repository. | 2009-02-26 |
