09th week of 2009 patent applcation highlights part 27 |
Patent application number | Title | Published |
20090052178 | Configuration of multiple LED modules - A configuration of multiple LED modules comprising a plurality of LED modules that each contain a carrier that has a first main area, a second main area and at least one semiconductor layer, wherein the first main area has a planar configuration. The LED modules also include a plurality of LED semiconductor bodies that applied on the first main area of the carrier. In addition, the multiple LED modules include a common heat sink, where the carrier of the LED modules in each case are connected to the common heat sink on the second main area. | 2009-02-26 |
20090052179 | Race Track Lighting Fixture and Race Track lighting System - A race track lighting system comprising a plurality of fixtures mounted in spaced relationship to one another on the infield side of the track and projecting light outwardly and downwardly onto the track surface from relatively low poles. Each fixture is asymmetric so as to provide a strong cut-off preventing light from being projected, into the eyes of oncoming driver, but a divergent pattern in the direction of traffic flow so as to blend the light from one fixture with the light from an adjacent fixture for the purpose of promoting uniformity in the lighting intensity. The lamp is offset in the fixture and a blocker strip is placed in from of the lamp to prevent direct, uncontrolled light, from reaching the track. | 2009-02-26 |
20090052180 | ELECTRONIC APPARATUS AND BADGE PANEL FOR USE THEREIN - An electronic apparatus such as a notebook PC or mobile telephone is provided with a badge comprising a multi-layer panel and a light source mounted within the body to illuminate the badge panel from behind. A control circuit senses the orientation of the part of the casing body controls the light source so as to activate it when body part is in a predetermined range of orientations. The multi-layer panel is designed to present a logo in a first orientation (relative to said body part) when illuminated by ambient light and in a second orientation when illuminated from behind by light source. By this means, the orientation of the graphic elements as viewed by an observer can be correct more of the time than by a conventional badge. | 2009-02-26 |
20090052181 | WORKING LAMP - A working lamp is provided, comprising a lamp head, a lamp body, and a luminous body array disposed on one side of the lamp body. Additionally, the working lamp further comprises a detachable bracket and a connecting part located on the other side of the lamp body. Moreover, the working lamp further comprises a charging base matching with the lamp body so as to charge the chargeable battery in the lamp body without electrical contact. While in use, the detachable bracket can be applied if necessary, eliminating the need for hand holding. Besides, the connection will be more stable as a screw hole is provided on the magnet, and being dustproof and waterproof as well as charging without electrical contact are achieved due to sealed measures. | 2009-02-26 |
20090052182 | ILLUMINATION SYSTEM - There is provided a lighting system simple in configuration and capable of irradiating an irradiation image with less distortion onto an irradiation surface. For this reason, light shielding masks | 2009-02-26 |
20090052183 | LIGHT-EMITTING MODULE - A light-emitting module with a focus adjusting function is described. A light-emitting module includes a light-emitting diode, a first hollow cylinder and a second hollow cylinder. A first hollow cylinder encloses the light-emitting diode and has a first thread around an outer surface thereof. A second hollow cylinder has a second thread on an inner surface thereof, wherein the first thread is meshed with the first thread such that the second hollow cylinder is telescoped from the first hollow cylinder when the second hollow cylinder rotates relative to the first hollow cylinder. An optical lens is disposed within the second hollow cylinder, wherein the optical lens moves relative to the light-emitting diode so as to adjust a projected beam's focus. | 2009-02-26 |
20090052184 | Multi-Purpose Light Source - The present invention is a multi-purpose light source of a unique design and specialized attachments which are also independently unique that can be used for, but not limited to, Dental, Medical, Cosmetic, and Industrial applications and procedures. Specifically the spectral irradiance of the light source can be controlled in such a way as to allow it to be used for procedures currently performed by lasers, electrosurgical devices, and hand instruments while retaining the benefits of the light source for other uses such as the photo-initiation of resins, tooth whitening, fluorescence, and illumination. The present invention may be used instead of a laser either independently or in conjunction with electrosurgical devices and hand instruments. | 2009-02-26 |
20090052185 | LIGHT SOURCE DEVICE - A light source device includes a light-condensing device that condenses an illumination light that is emitted from a light source lamp. The light-condensing device includes at least one lens, a lens holder in which a lens is fixedly provided, and a lens holding member. The lens holding member is a member for fixing a lens to the lens holder. The lens holding member causes at least one circumferential portion of the lens to protrude to the lens holder side, and causes the optical axis of the lens to match the optical axis of the illumination light. | 2009-02-26 |
20090052186 | High Power LED Lamp - A high power LED lamp comprises a cover; a base panel; an LED mounted on the base panel which further includes an insulator; a substrate; a power supply received in the insulator; and a heat sink device disposed between the cover and substrate; wherein the insulator is engaged with the heat sink device, and both the LED and base panel are defined above the heat sink device. In accordance with the present invention, the heat created during work of the LED can be radiated rapidly via the heat sink device and thus ensuring good heat dispersion, high brightness, long life and low temperature. | 2009-02-26 |
20090052187 | Heat-Dissipating Lighting System - The heat dissipating lighting system includes a closed-loop coolant path with a warmed fluid channel and a cooled fluid channel. The outlet of the warmed fluid channel is in fluid communication with the inlet of the cooled fluid channel and vice versa. Substantial portions of the warmed and cooled fluid channels are thermally isolated from one another. A light source is thermally connected to the coolant path along the warmed fluid channel, near the warmed fluid inlet. | 2009-02-26 |
20090052188 | Deflection Component for a Luminaire and Associated Luminaire - A deflection component for a luminaire is hollow and consists of two sections, of which a first section is parallel to the axis and a second section in contrast runs obliquely outwards. | 2009-02-26 |
20090052189 | LED SPOTLIGHT - An LED spotlight includes: a light source unit including an RGB-LED light source composed of R, G and B LEDs, and a condenser lens for condensing light beams of mixed color projected from the RGB-LED light source on an entrance end face of a rod lens; a pyramid rod lens whose cross-sectional area converges from an entrance end face to an exit end face; and a reflector for condensing rays of exiting light exiting as a point light source from the exit face of the pyramid rod lens on an axial line of the pyramid rod lens. A light beam incident on the pyramid rod lens progresses while repeatedly internally reflected several times, thereby brightness irregularity at the exit end of the rod lens is lowered, and color mixture is accelerated, so that a light beam is emitted as a point light source of white light whose color is observed as the same color, seen from any direction, and the light beams are condensed as a spotlight on the axial line of the pyramid rod lens by the reflector. | 2009-02-26 |
20090052190 | Indicator lamp having a converging lens - It is sought to provide an indicator lamp, which is excellent not only in short distance visual recognition property but also in long distance one, as well as being further excellent in sight field angle property. | 2009-02-26 |
20090052191 | LED ILLUMINATOR - A light emitting diode illuminator includes a reflecting shell ( | 2009-02-26 |
20090052192 | Light emitting device and lighting device having the same - A light-emitting device ( | 2009-02-26 |
20090052193 | OPTICAL DEVICE FOR LED LIGHT SOURCES - Optical device and optical component part for the targeted reproduction of light emitted by LED light sources ( | 2009-02-26 |
20090052194 | Light Fixture Assembly and Method - A lamp cover assembly for a recessed light fixture assembly is provided. The light fixture has a socket for receiving an electrical light bulb and a canister housing for housing the bulb of the light fixture assembly. The canister housing has an opening for allowing the passage of light through the opening. The lamp cover assembly includes a lens body that is substantially translucent to allow the passage of light through the body and is configured to cover the opening so that the light bulb of the light fixture assembly is generally concealed from view through the opening. A light fixture engagement portion for engagement with the light fixture assembly is provided with the lamp cover assembly so that the lamp cover may be selectively engaged and disengaged from the light fixture assembly. The body of the lamp cover assembly has an outer perimeter that is sized so that the perimeter is spaced radially inward a distance from the edges of the opening of the light fixture assembly when the cover assembly is engaged with the light fixture assembly. | 2009-02-26 |
20090052195 | SCATTERING MEMBER AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE USING THE SAME - A scattering member includes: a binder; and a light scattering particle, wherein the scattering member is used for an organic electroluminescent display device; and an organic electroluminescent display device uses the scattering member. | 2009-02-26 |
20090052196 | ROTATING STRUCTURE FOR FOLDING SUPPORTS OF A LAMP - A rotating structure for folding supports of a lamp comprises a rotating axle having at least a support, and a fixed axle disposed in relation to the rotating axle, the fixed axle also includes at least a support thereon; a trough and an elastic positioning component disposed at a joined surface between the rotating axle and the fixed axle, so that the rotating axle causes that at least a support move positionally. As a result, the supports of the lamp of the invention is rotatabel and is folded for storage, or unfolded for use. | 2009-02-26 |
20090052197 | REAR LIGHT FOR A MOTOR VEHICLE - A rear light for a motor vehicle has a light chamber for holding at least one lighting device for a flashing light and further has at least one light chamber which adjoins the light chamber for the flashing light and has the purpose of holding at least one lighting device for a reversing light, for holding at least one lighting device for a tail light, for holding at least one lighting device for a brake light and/or for holding at least one lighting device for a fog light. Wherein a plurality of LEDs are positioned in the light chamber for the flashing light and transmit light toward the rear for the flashing light. Accordingly, the rear light contains at least one LED which transmits light for the flashing light into a light chamber which is positioned adjacent to the light chamber for the flashing light. | 2009-02-26 |
20090052198 | Quick release illuminating and display apparatus and system - A quick release illuminating and display apparatus and system for vehicles and structures to provide lighting and illumination effects and to display data or other information on a display screen. The apparatus and system includes a removable housing assembly with illumination sources, a power source and an optional display screen to provide lighting to accent a vehicle or structure and to display data, pictures or other information. The apparatus and system includes a quick release mechanism with a biasing cam operably connected to a number of biased lock shafts. The controlled movement of the biasing cam operates so as to quickly lock or unlock the housing assembly onto or off of the support structure. The apparatus and system has enhanced lighting and display effects by the use of optional ball bearings, a cap to exhibit team or manufacturer logos, the use of LED lights secured to directional nipples, a display screen, a USB port, computer memory, a control switch, remote control operation and solar power. | 2009-02-26 |
20090052199 | CAMOUFLAGED COMPOSITE MILITARY VEHICLE LAMP - A composite lamp assembly for use on a camouflaged military vehicle comprises a lamp housing colored to match the camouflaged scheme of the vehicle. The lamp housing defines an interior space, a first opening and a plurality of second openings in communication with the interior space. The lamp assembly includes a clear lens attached to the housing to occupy the first opening and a plurality of diffusers attached to the housing to occupy the plurality of second openings, the diffusers being colored to match the camouflaged scheme of the vehicle. The lamp assembly further includes a circuit board arranged within the interior space of the lamp housing having first and second pluralities of LEDs mounted thereto. The first plurality of LEDs is positioned to provide light through the clear lens and the second is positioned to provide light through the diffusers. | 2009-02-26 |
20090052200 | Single source visible and IR vehicle headlamp - A vehicle light ( | 2009-02-26 |
20090052201 | LAMP FOR MOTOR VEHICLES - A lamp assembly for a motor vehicle includes a housing receiving at least one light source. The housing includes a covering pane and including first and second fixing arrangement for releasably securing the lamp to the vehicle. | 2009-02-26 |
20090052202 | Vehicle lamp fixing device - A vehicle lamp fixing device includes at least an engage groove in a rear wall of a lamp socket, the engage groove provided with an opening formed in an outer side, and an elastic stop lug formed in a sidewall of the engage groove. The elastic stop lug can be pressed to retreat in the sidewall so as to let the shank of a bolt to pass over, and then recover to its original position to stop the shank of the bolt not to fall out of the opening, so the bolt can be held in the engage groove without using a finger so that a worker can conveniently fix the lamp socket on a vehicle body. | 2009-02-26 |
20090052203 | Illumination light source and image display apparatus - A coherent light source includes a plurality of light emitting points arranged in one-dimensional array. A beam shaping unit shapes a light beam so that a diameter of a light emitted from the coherent light source in a direction perpendicular to a direction of the light emitting point array is larger than a diameter in the direction of the light emitting point array, and an intensity distribution of the light emitted from each of the light emitting points is uniform. A magnification of a focusing optical system is set such that a light emitted from the beam shaping unit is coupled to an optical fiber based on a maximum diameter of the light emitted from the beam shaping unit. | 2009-02-26 |
20090052204 | Surface Light Emitting Apparatus - The present invention provides a thin, low-power consumption, lightweight, and inexpensive surface light emitting apparatus using LEDs in conjunction with a light conducting member having a plurality of light conducting rods. More specifically, the surface light emitting apparatus of the invention comprises: a light conducting member constructed from a plurality of light conducting rods and having an end face and a light-emitting face; a light source for emitting light into the light conducting member through the end face; and light deflecting means for causing the light introduced through the end face of the light conducting member to emerge from the light-emitting face of the light conducting member. | 2009-02-26 |
20090052205 | LIGHT SOURCE MODULE OF SCANNING DEVICE - A light source module of scanning device includes a light guide rod and a light emitting diode. The light guide rod has a top surface, a bottom surface and two end portions. The top surface and the bottom surface are disposed opposite to each other. The light emitting diode is disposed adjacent to one of the end portions. | 2009-02-26 |
20090052206 | Display Device - A wall-mounted display device, which uses a light guiding panel for an LED light source includes display body | 2009-02-26 |
20090052207 | LIGHT SOURCE MODULE OF SCANNING DEVICE - A light source module of scanning device includes a first light guide rod, a second light guide rod, and a light emitting diode. The first light guide rod has a first incident surface and is disposed at a first end portion. The second light guide rod has a second incident surface and is disposed at a second end portion. The light emitting diode is disposed between the first end portion and the second end portion. | 2009-02-26 |
20090052208 | Apparatus to Extend HDMI Connections over a Single Ethernet CAT Cable - This invention is to use a single standard unshielded or shielded Ethernet CAT cable, such as CAT5, CAT5e, CAT6 and similar cable, to extend original digital video signals over long distances. The Ethernet CAT cable can be installed with the required length easily and terminated in the field with simple tools. The Ethernet cable is the standard communication wiring in modern buildings. On the contrary, HDMI cable must be pre-terminated in the factory and is extremely difficult to install in buildings. HDMI video signals contain three pairs of CML video signals, one pair of high-speed clock signals, and three control signals. Each video signal has a data rate over 1.6 Gbps, and one of the control signals is bi-directional. Sending these signals over a single Ethernet CAT cable is very difficult. This invention presents an apparatus to extend HDMI signals over a single Ethernet CAT cable. The present invention is able to extend 1080p video over more than 150 feet, and to reliably extend 1080i over more than 200 feet with HDCP capability over a single unshielded or shielded Ethernet CAT cable. | 2009-02-26 |
20090052209 | Inverter Device - An inverter device includes a converter circuit that rectifies a first alternating current output from a power supply to generate a rectified current, a capacitor that stores therein the rectified current and outputs a direct current based on the rectified current, and an inverter circuit that converts the direct current into a second alternating current for driving a load. Moreover, a voltage control unit generates and outputs, during a period when any one of an instantaneous power cut and an instantaneous voltage drop occurs in the power supply, a first current command based on a voltage of the capacitor and a second current command; and a current control unit generates and outputs, based on the first current command, the second current command for controlling the inverter circuit to output the second alternating current. | 2009-02-26 |
20090052210 | TEMPERATURE SENSING ARRANGEMENTS FOR POWER ELECTRONIC DEVICES - A cooling system is provided for controlling temperature in a power electronic device. The power electronic device includes a semiconductor having a major surface. The cooling system includes a temperature sensor coupled to the major surface of the semiconductor; and a control circuit coupled the temperature sensor. The control circuit is configured to reduce current to the inverter circuit when the temperature exceeds a predetermined temperature. | 2009-02-26 |
20090052211 | POWER CONVERTER - In a bridge type power converter including series connectors of power semiconductor switches having first and second main terminals and a control terminal; plural steps of the series connectors connected in parallel, a gate drive circuit for limiting voltage between the first and second main terminals of the power semiconductor switch to a predetermined value only in turning off the power semiconductor switch is provided between the first main terminal and the control terminal of the power semiconductor switch. | 2009-02-26 |
20090052212 | POWER SUPPLY APPARATUS - A power supply apparatus includes: a transformer which converts input power supplied to a primary winding to be induced to a secondary winding; a current detector which detects an output current of the secondary winding of the transformer; a voltage detector which detects an output voltage of the secondary winding of the transformer; a switch which adjusts the output voltage outputted by the transformer; and a controller which controls the switch to maintain output power obtained by multiplying the output current by output voltage, within a predetermined level. | 2009-02-26 |
20090052213 | POWER CONVERTER SYSTEM FOR AN AUTOMOTIVE VEHICLE AND METHOD FOR CONFIGURING SAME - A DC/DC power converter includes an electrically configurable transformer/inductor. The electrically configurable transformer/inductor receives a power plug. The power plug, depending on its configuration, configures the operation of the transformer/inductor and therefore the DC/DC power converter. The power plug may permit access to power received from the power converter. The power plug may also pass power to the power converter from a remote electrical source. | 2009-02-26 |
20090052214 | Insulating transformer and power conversion device - An insulating transformer includes a semiconductor substrate, an insulating substrate, a primary winding provided on one of the semiconductor substrate and the insulating substrate, a secondary winding provided on other of the semiconductor substrate and the insulating substrate, and an insulating spacer layer provided in between the semiconductor substrate and the insulating substrate for insulating and separating the primary winding and the secondary winding. The primary winding and the secondary winding are disposed to face each other. The insulating spacer layer maintains a constant interval between the semiconductor substrate and the insulating substrate. | 2009-02-26 |
20090052215 | CURRENT CONTROLLER AND CURRENT OFFSET CORRECTION METHOD OF THE SAME - To provide a current controller capable of constantly detecting an offset value of a current detection system, the offset value overlapping with a current detection value, in a state of regular operation of a motor to correct the current detection value and capable of current detection with high accuracy and a current offset correction method of the same. | 2009-02-26 |
20090052216 | LEVEL SHIFT CIRCUIT AND POWER SUPPLY DEVICE - In a level shift circuit including: an inverter circuit having a series circuit of a Pch-type transistor and an Nch-type transistor, which re connected between electrodes of a floating power supply; and a transistor Q | 2009-02-26 |
20090052217 | METHOD AND APPARATUS FOR STABILIZING VOLTAGE OF INTERMEDIATE CIRCUT OF FREQUENCY CONVERTER - A method and an apparatus for damping voltage oscillation of a voltage intermediate circuit of a frequency converter, the frequency converter comprising a half controlled rectifier bridge coupled to a supply network. The method comprises determining magnitude (U | 2009-02-26 |
20090052218 | SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE - A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes. | 2009-02-26 |
20090052219 | MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF - A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line. | 2009-02-26 |
20090052220 | ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY - An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor. | 2009-02-26 |
20090052221 | SEMICONDUCTOR DEVICE INCLUDING ANTIFUSE ELEMENT - An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region. | 2009-02-26 |
20090052222 | MEMORY ELEMENT WITH THERMOELECTRIC PULSE - A memory element comprises an addressable memory cell. A thermoelectric device couples to the memory cell. Electrical conductors provide a current pulse to the thermoelectric device. The current pulse generates a thermoelectric heat flow pulse between the thermoelectric device and the memory cell. | 2009-02-26 |
20090052223 | Switching Element, Method of Manufacturing the Switching Element, and Memory Element Array - Disclosed is a switching element including: an insulative substrate; a first electrode and a second electrode provided to the insulative substrate; an interelectrode gap between the first electrode and the second electrode, comprising a gap of a nanometer order which causes switching phenomenon of resistance by applying a predetermined voltage between the first electrode and the second electrode; and a sealing member to seal the interelectrode gap such that the gap is retained. | 2009-02-26 |
20090052224 | Ferroelectric random access memory apparatus and method of driving the same - In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed. | 2009-02-26 |
20090052225 | Nonvolatile Semiconductor Memory Device - A nonvolatile semiconductor memory device capable of suppressing parasitic currents in unselected memory cells, in cross-point array including memory cells comprising a two-terminal circuit having a variable resistor storing information according to electric resistance change due to electric stress. The memory cell comprises a series circuit of the variable resistive element holding a variable resistor between an upper and lower electrodes, and the two-terminal element having non-linear current-voltage characteristics making currents flow bi-directionally. The two-terminal element has a switching characteristic that currents bi-directionally flow according to polarity of a voltage applied to both ends when an absolute voltage value exceeds a certain value, and currents larger than predetermined minute currents do not flow when the absolute value is the certain value or less, and can make currents whose current density is 30 kA/cm | 2009-02-26 |
20090052226 | Resistive random access memory device - Provided is a resistive random access memory device that includes a storage node connected to a switching device. The resistive random access memory device includes a first electrode, a resistance variable layer, and a second electrode which are sequentially stacked, wherein a diffusion blocking layer is formed between the first electrode and the resistance variable layer or between the resistance variable layer or/and the second electrode. | 2009-02-26 |
20090052227 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged. | 2009-02-26 |
20090052228 | OPERATING PROCESS OF ORGANIC DEVICE - An operating process of an organic device includes performing a programming process and an erasing process. The programming process includes steps of applying a first positive bias from the first electrode to the second electrode on the organic device so that a conductive state of the organic device is switched to be a first turn-on state when the organic device is in a turn-off state and applying a negative bias from the first electrode to the second electrode on the organic device so that the conductive state of the organic device is switched to be a second turn-on state when the organic device is in the first turn-on state. The erasing process includes a step of applying a second positive bias from the first electrode to the second electrode on the organic device so that the conductive state of the organic device is switched to be the turn-off state. | 2009-02-26 |
20090052229 | MIS-TRANSISTOR-BASED NONVOLATILE MEMORY DEVICE WITH VERIFY FUNCTION - A nonvolatile semiconductor memory device includes a first latch to store data, a nonvolatile memory cell including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch, a second latch to store data obtained by sensing a difference in the transistor characteristics between the two MIS transistors, a logic circuit to produce a signal indicative of comparison between the data of the first latch and the data of the second latch, and a control circuit configured to repeat a store operation storing data in the nonvolatile memory cell, a recall operation storing data in the second latch, and a verify operation producing the signal indicative of comparison until the signal indicates that the data of the first latch and the data of the second latch are the same. | 2009-02-26 |
20090052230 | INTEGRATED CIRCUIT INCLUDING SILICIDE REGION TO INHIBIT PARASITIC CURRENTS - An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode. | 2009-02-26 |
20090052231 | SEMICONDUCTOR DEVICE - A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other. | 2009-02-26 |
20090052232 | METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL - A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone | 2009-02-26 |
20090052233 | SEMICONDUCTOR MEMORY DEVICE AND WRITING CONTROL METHOD THEREOF - A semiconductor memory device includes: a plurality of write control circuits; a plurality of memory cells grouped in the write control circuits; a plurality of write drivers that write data to a corresponding memory cell when the write control circuit is activated; and a main control circuit that causes the write control circuits to become active in response to presence of a data writing request to the memory cells belonging to a predetermined group and subsequent absence of the data writing request to the memory cells belonging to the same group within a predetermined period. | 2009-02-26 |
20090052234 | Phase-change random access memory device and semiconductor memory device - A semiconductor memory device includes: first and second wiring layers extending in substantially parallel to each other in a first direction; a first semiconductor region formed in a part of a portion between the first and second wiring layers; a second semiconductor region formed on an opposite side to the first semiconductor region with respect to the second wiring layer and making a pair with the first semiconductor region; a third semiconductor region formed in another part of the portion between the first and second wiring layers; a fourth semiconductor region formed on an opposite side to the third semiconductor region with respect to the first wiring layer and making a pair with the third semiconductor region; a third wiring layer extending in a second direction that crosses the first direction and having an electrical contact with the first semiconductor region; a fourth wiring layer extending in the second direction and having an electrical contact with the fourth semiconductor region; a fifth wiring layer extending in the first direction to cross over the first and third semiconductor regions; a sixth wiring layer extending in the first direction in substantially parallel to the fifth wiring layer to cross over the second semiconductor region; seventh wiring layers extending in the second direction in substantially parallel to one another, each of the seventh wiring layers intersecting each of the fifth and sixth wiring layers; first memory elements each disposed at an intersection of an associated one of the seventh wiring layers and the fifth wiring layer; and second memory elements each disposed at an intersection of an associated one of the seventh wiring layers and the sixth wiring layer. | 2009-02-26 |
20090052235 | Resistance variable memory device and programming method thereof - Provided is a method of programming a resistance variable memory device. The resistance variable memory device includes a memory cell having multi states and a write driver outputting a program pulse for programming the memory cell into one of the multi states. The method of programming the resistance variable memory device includes applying a first program pulse to the resistance variable memory device and applying a second program pulse to a memory cell when the memory cell is programmed into an intermediate state. When the first program pulse is a reset pulse, the reset pulse is an over program pulse, that is, an over reset pulse. Therefore, the resistance variable memory device can secure a sufficient read margin as well as improve a resistance drift margin. | 2009-02-26 |
20090052236 | Resistance variable memory device and operating method thereof - Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current. | 2009-02-26 |
20090052237 | MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY APPARATUS - A magnetic memory element includes a laminated construction of a first electrode, a first pinned layer, a first intermediate layer, a memory layer, a second intermediate layer, a second pinned layer and a second electrode, and a third electrode coupled to the first intermediate layer and not directly coupled to the memory layer. The magnetization directions of the first pinned layer, the second pinned layer, and the memory layer are parallel or antiparallel to each other. The magnetization direction of the memory layer takes a first direction when the current is passed with a first polarity so that the current flowing through the first pinned layer exceeds a first threshold. The magnetization direction of the memory layer takes a second direction when the current is passed with a second polarity so that the current flowing through the first pinned layer exceeds a second threshold. | 2009-02-26 |
20090052238 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more. | 2009-02-26 |
20090052239 | Nonvolatile memory devices and data reading methods - Methods of reading memory cell data and nonvolatile memory devices, which apply a low voltage to memory cells adjacent to a memory cell from which data may be read are provided. Methods of reading memory cell data of nonvolatile memory device include applying a first voltage to a control gate of a read memory cell from among the plurality of memory cells, applying a third voltage to control gates of memory cell adjacent to the read memory cell, and applying a second voltage to control gates of memory cells other than the read memory cell and the adjacent memory cells. | 2009-02-26 |
20090052240 | Flash Memory Device and Method of Programming the Same - A flash memory device may include a memory cell array, a page buffer unit, and a switching element. The page buffer unit may include first and second latches and is configured to program data into the memory cell array and read data from the memory cell array. The switching element enables the first latch during a verify operation of a first program based on a first verify voltage, and enables or disables the first latch in order to execute a verify operation of a second program based on a second verify voltage lower than the first verify voltage depending on whether data to be programmed has been stored in the second latch. | 2009-02-26 |
20090052241 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node. | 2009-02-26 |
20090052242 | NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a control gate electrode of a second memory cell adjacent to the first memory cell, and applies a third voltage lower than the second voltage to control gate electrodes of third memory cells other than the first and second memory cells at the time of programming. The first, second and third voltages have values not less than a value for turning on the n-numbered memory cells regardless of their threshold voltages. | 2009-02-26 |
20090052243 | Method of controlling a memory cell of non-volatile memory device - A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells. | 2009-02-26 |
20090052244 | MULTILEVEL STORAGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE ENABLING HIGH-SPEED DATA READING AND HIGH-SPEED DATA WRITING - A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2 | 2009-02-26 |
20090052245 | CMOS Logic Compatible Non-Volatile Memory Cell Structure, Operation, And Array Configuration - The present invention is to provide a logic based single-poly non-volatile memory cell which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation. A non-volatile memory cell in accordance with the present invention comprises a program transistor with a program transistor source as a first program terminal; a select transistor with a select transistor gate as a select terminal and a select transistor drain as a second program terminal; and an erase transistor with an erase transistor source and an erase transistor drain connected as an erase terminal, wherein the erase transistor shares a floating gate with the program transistor and the drain program transistor is connected to the select transistor source. By employing the present invention, significant cost advantages in feature-rich semiconductor products, such as System-on-Chip (SoC) design, compared to conventional dual-poly floating gate embedded Flash memory are provided. | 2009-02-26 |
20090052246 | NON-VOLATILE SHADOW LATCH USING A NANOTUBE SWITCH - A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device. | 2009-02-26 |
20090052247 | FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME - A fuse circuit in a flash memory device is disclosed. The fuse circuit includes a plurality of memory cells turned on/off by a first voltage in accordance with program state, a switching circuit configured to switch in response to a control signal, thereby transmitting a verifying signal for verifying program of the memory cell to the memory cell, and a cell controller configured to output the verifying signal for controlling program, verification and erase of the memory cells and the control signal. | 2009-02-26 |
20090052248 | FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL - A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included. | 2009-02-26 |
20090052249 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad. | 2009-02-26 |
20090052250 | SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - A semiconductor memory device has a plurality of word line provided on a semiconductor region, extending in a row direction, a plurality of bit lines provided in the semiconductor region, extending in a column direction, and a plurality of memory elements provided at intersections between the plurality of word lines and the plurality of bit lines. Each word line provides a first gate electrode in the corresponding memory element. A lower portion of a side surface of each word line in a direction parallel to an extending direction of the word line is perpendicular to a main surface of the semiconductor region. An upper portion of the side surface is inclined so that a width thereof becomes smaller toward a top thereof. | 2009-02-26 |
20090052251 | INTEGRATED CIRCUIT MEMORY DEVICES INCLUDING MEMORY CELLS ON ADJACENT PEDESTALS HAVING DIFFERENT HEIGHTS, AND METHODS OF FABRICATING SAME - Coupling among adjacent rows of memory cells on an integrated circuit substrate may reduced by forming the adjacent rows of memory cells on adjacent semiconductor pedestals that extend different distances away from the integrated circuit substrate. NAND flash memory devices that include different pedestal heights and fabrication methods for integrated circuit memory devices are also disclosed. | 2009-02-26 |
20090052252 | METHODS OF APPLYING READ VOLTAGES IN NAND FLASH MEMORY ARRAYS - Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage. | 2009-02-26 |
20090052253 | Memory device and method reducing fluctuation of read voltage generated during read while write operation - Provided is a device and method for reducing a fluctuation of a read voltage generated during a read while write (RWW) operation. A semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality of banks where the write voltage generator generates the write voltage to have a voltage level of a read voltage before the write operation changes to a read operation. The semiconductor device may also include a read voltage generator configured to generate a read voltage to perform the read operation to at least one of the other plurality of banks and/or a plurality of switches configured to switch a voltage applied to at least one of the banks to one of the write voltage and the read voltage in response to a plurality of control signals. | 2009-02-26 |
20090052254 | Non-Volatile Semiconductor Memory - A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells. | 2009-02-26 |
20090052255 | PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY - Methods of programming or erasing a nonvolatile memory device having a charge storage layer including performing at least one unit programming or erasing loop, each unit programming or erasing loop including applying at least one programming pulse, at least one erasing pulse, at least one time delay, at least one soft erase pulse, at least one soft programming pulse and/or at least one verifying pulse as a positive or negative voltage to a portion (for example, a word line or a substrate) of the nonvolatile memory device. | 2009-02-26 |
20090052256 | THRESHOLD VOLTAGE DIGITIZER FOR ARRAY OF PROGRAMMABLE THRESHOLD TRANSISTORS - A system includes a voltage generator, current sensing amplifiers, and a control module. The voltage generator outputs a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1. The current sensing amplifiers sense currents through the N transistors via N bit lines, respectively, and generate control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current. The control module generates measured values of the threshold voltages of the N transistors by compensating the ones of the codewords based on at least one of a position of the corresponding ones of the N transistors and a temperature. | 2009-02-26 |
20090052257 | NONVOLATILE SEMICONDUCTOR MEMORIES FOR PREVENTING READ DISTURBANCE AND READING METHODS THEREOF - A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line. | 2009-02-26 |
20090052258 | Systems, methods and devices for a memory having a buried select line - Embodiments are described for programming and erasing a memory cell by utilizing a buried select line. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge. | 2009-02-26 |
20090052259 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing is carried out by connecting two gate electrodes, and the voltage of the gate electrode is reduced by capacitive coupling with another gate electrode adjacent thereto, to largely reduce the potential of the gate electrode. Thereby, the voltage level generated by the charge pump circuit can be reduced. As a result, the size of the charge pump circuit can be reduced, or the circuit itself can be eliminated, resulting in reduction of the chip area. | 2009-02-26 |
20090052260 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal. | 2009-02-26 |
20090052261 | DATA STROBE BUFFER AND MEMORY SYSTEM INCLUDING THE SAME - A data strobe buffer and a memory system including the data strobe buffer are provided. The data strobe buffer includes: a first input/output node; a first driver coupled to the first input/output node, the first driver configured to output a first data strobe signal to the first input/output node during a write operation; and a first receiver coupled to receive a second data strobe signal from the first input/output node and output a third data strobe signal during a read operation when the data strobe buffer is in a first or second mode, the first receiver configured to compare the second data strobe signal with a first reference voltage and output a result of the comparison as the third data strobe signal when the data strobe buffer is in the first mode, the receiver further configured to not compare the second data strobe signal with the first reference voltage when the data strobe buffer is in the second mode. | 2009-02-26 |
20090052262 | SEMICONDUCTOR MEMORY DEVICE - A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word line and second word line. Then, for example, when the same memory cell row is accessed, a voltage level of the power supply line is raised by a coupling capacitance of the word lines. Thus, even in identical-row-access, static noise margin in identical-row-access can be maintained to be as great as that in different-row-access. Therefore, for example, even when a size or the like of a driver transistor is not made larger, deterioration of static noise margin can be suppressed and a circuit area can be made smaller. | 2009-02-26 |
20090052263 | Write driving circuit - A write driving circuit is provided to drive a global input/output line to write same data to memory cells according to a combination of a first test data signal and a second test data signal in a test mode, regardless of input data signals. | 2009-02-26 |
20090052264 | Refresh characteristic testing circuit and method for testing refresh using the same - A refresh characteristic test circuit is provided, in a recessed semiconductor device, that is capable of verifying whether a refresh failure is caused by the neighbor/passing gate effect or not and a method for testing the refresh characteristic. The refresh characteristic test circuit includes a select signal generating unit for receiving first address signals and a test mode signal and generate select signals to select cell blocks, a main word line signal generating unit for receiving second address signals and the test mode signal and generate main word lines signals to select main word lines of the selected cell block, and a sub word line signal generating unit for receiving third address signals and the test mode signal and enable sub word lines of the selected main word line. | 2009-02-26 |
20090052265 | Semiconductor Memory Device Changing Refresh Interval Depending on Temperature - A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit. | 2009-02-26 |
20090052266 | TEMPERATURE THROTTLING MECHANISM FOR DDR3 MEMORY - A method for throttling a bus, e.g. a memory bus, may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices, accessed through the bus. For example, in case of a memory bus, a memory controller may be configured to throttle the memory bus in a way that maximizes system performance while ensuring that the memory devices keep operating within their thermal limits. Readings obtained from the memory, or from close proximity to the memory, may indicate whether the temperature of the memory has crossed over one or more designated trip points, and one or more algorithms may be executed to perform throttling according to the readings and based on fixed and dynamic throttling modes. The memory controller may infer temperature changes taking place in the memory devices when successive readings are indicating that the temperature of the memory device has remained over a given trip point. Based on these inferences, the memory controller may then change the manner in which the bus is throttled. | 2009-02-26 |
20090052267 | METHOD OF SIMPLE CHIP SELECT FOR MEMORY SUBSYSTEMS - Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID. | 2009-02-26 |
20090052268 | SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path. | 2009-02-26 |
20090052269 | Charge loss compensation methods and apparatus - Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis. | 2009-02-26 |
20090052270 | METHOD OF FLEXIBLE MEMORY SEGMENT ASSIGNMENT USING A SINGLE CHIP SELECT - Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID. | 2009-02-26 |
20090052271 | SEMICONDUCTOR MEMORY DEVICE - An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address. | 2009-02-26 |
20090052272 | ULTRASONIC STIRRING OF LIQUIDS IN SMALL VOLUMES - Ultrasound-assisted contactless stirring of liquids in a resonator cell by microparticles is achieved by repeated creating and destruction of nodal patterns associated with standing waves of various resonance frequencies causing continuous movements of microparticles inside the cell. Swept-frequency sonication methods include using constant or variable rate of frequency change as well as a stepwise change of frequency of the transducer within a predefined range. Other useful steps include initial detection of the set of resonance frequencies and periodic refreshing of that set. Control systems are described including means to automatically detect the resonance frequencies and maintain the operation of the transducer thereon. Advantageous designs of the apparatus are described for use in microstirring, mixing of liquids using magnetic microbeads, microbubbles, microtiter plates, microarray plates, etc. | 2009-02-26 |
20090052273 | APPARATUS FOR ULTRASONIC STIRRING OF LIQUIDS IN SMALL VOLUMES - Ultrasound-assisted contactless stirring of liquids in a resonator cell by microparticles is achieved by repeated creating and destruction of nodal patterns associated with standing waves of various resonance frequencies causing continuous movements of microparticles inside the cell. Swept-frequency sonication technique includes using constant or variable rate of frequency change as well as a stepwise change of frequency of the transducer within a predefined range. Other useful provisions include initial detection of the set of resonance frequencies and periodic refreshing of that set. Control systems are described including means to automatically detect the resonance frequencies and maintain the operation of the transducer thereon. Advantageous designs of the apparatus are described for use in microstirring, mixing of liquids using magnetic microbeads, microbubbles, microtiter plates, microarray plates, etc. | 2009-02-26 |
20090052274 | Apparatus for Heat Exchange with Radial Mixing - An apparatus for heat exchange with radial mixing comprises a trough with two rotatably arranged shafts extending alongside each other, which shafts are each provided with paddles spaced apart in an axial direction with an intermediate distance. The paddles extend substantially in a radial plane with respect to the shafts, and extend in a circumferential direction over at least a part of the circumference. In the circumferential direction, the paddles are at least partly wedge-shaped. Upon opposite rotation of the shafts, successive paddles mesh alternately, thereby forming a gap narrowing again and again. Per shaft, successive paddles in an axial direction are staggered relative to each other in circumferential direction through an angle. | 2009-02-26 |
20090052275 | ARRANGEMENT FOR MIXING STEAM INTO A FLOW OF CELLULOSE PULP - The invention concerns an arrangement to counteract problems associated with mixing in steam into a pipe that is transferring a flow of pulp of medium consistency. The arrangement comprises a chamber ( | 2009-02-26 |
20090052276 | Agitator - An agitator head tailored for mixing a viscous liquid such as driveway sealer or paint has an elongated shape consisting of two arcs which meet at their end points, and a common chord between the two arcs passes through a center of the head. Each arc is radiused to match the radius of a container holding the liquid to be mixed. A plurality of tapered openings in the head permit easy vertical movement through the liquid in the container. Vertical ribs in the head provide the structural strength necessary to withstand the force of agitation and keep the head from breaking. | 2009-02-26 |
20090052277 | Full wave seismic recording system - The present disclosure generally relates to systems and methods for acquiring seismic data. In one exemplary embodiment, a method for acquiring seismic data is described in which recorder instruments are deployed to the seafloor and utilized for recording pressure wave and shear wave data. An acoustic array, displaced from the seafloor, is also provided for sending acoustic signals to the instruments on the seafloor. The orientation of the instruments on the seafloor is determined via acoustic communication between the acoustic array and the instruments. Related systems and methods for acquiring seismic data are also described. | 2009-02-26 |