| 09th week of 2009 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20090051378 | Air Bridge Structures And Methods Of Making And Using Air Bridge Structures - A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons. | 2009-02-26 |
| 20090051379 | METHOD OF TREATING AND PROBING A VIA - A method of treating a via connected with a substrate and a method of probing the via are disclosed. A pattern of a lead-free solder paste is applied around a hole of the via without completely covering a pad of the via. The paste is reflowed to form a pattern of a lead-free solder on a pad that covers only a portion of a surface area of the pad and is positioned around the hole. The solder may be substantially symmetrically positioned around the hole. A flux generated during reflow is insufficient to plug the hole. The lead-free solder can be probed by a blade probe including collinear first and second edges and having a preferred orientation relative to the pattern of the lead-free solder. | 2009-02-26 |
| 20090051380 | LRL VECTOR CALIBRATION TO THE END OF THE PROBE NEEDLES FOR NON-STANDARD PROBE CARDS FOR ATE RF TESTERS - A method and apparatus for radio frequency vector calibration of s-parameter measurements to the tips of the wafer probe needles of an automatic test equipment production tester. The method involves a modified Line-Reflect-Line (LRL) calibration routine that uses a Thru-Reflect-Line to LRL shift to eliminate the need for a precisely characterized reflect standard used during a conventional LRL calibration. The method further involves de-embedding the non-ideal effects of the non-zero length thru standard used during the calibration routine to improve measurement accuracy of the tester. The apparatus may involve the use of RF relays to allow multiple wafer probe needles to share RF test ports. | 2009-02-26 |
| 20090051381 | Electronic Device Testing Apparatus and Temperature Control Method in an Electronic Device Testing Apparatus - An electronic device testing apparatus | 2009-02-26 |
| 20090051382 | PROBE FOR ELECTRICAL TEST AND ELECTRICAL CONNECTING APPARATUS USING IT - A probe includes an arm region extending in the back and forth direction, and a tip region extending downward from the front end portion of the arm region. The tip region has a pedestal portion integrally continuous to a lower edge portion at the front end side of the arm region and having an underside inclined to an imaginary axis extending in the vertical direction; and a contact portion projected from the underside of the pedestal portion and having a tip orthogonal to an imaginary axis. Thus, the position of the tip can be accurately determined. | 2009-02-26 |
| 20090051383 | Test Method and Production Method for a Semiconductor Circuit Composed of Subcircuits - Test method and production method for testing a semiconductor circuit comprising a plurality of subcircuits. The semiconductor circuit is produced according to specification stipulations comprising a design based on a hardware description language for a functional implementation, a logic synthesis for a structural implementation, a layout design for a topological implementation and processing a semiconductor substrates in accordance with the layout design. A test pattern having test signal sequences is coupled into the semiconductor circuit and functional results are coupled out. Test signal lengths and/or test signal levels are selected from a previously generated test parameter list, wherein the test parameter list is generated during the logic synthesis. | 2009-02-26 |
| 20090051384 | COMPLEMENTARY LOGIC CIRCUIT - A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current between the first conductive members and the second conductive members. Another insulating member hardly passing a tunnel current between the first conductive members and the third conductive members. An electric field generated by a potential applied to the third conductive members has an effect on the sub-band of the first conductive members. | 2009-02-26 |
| 20090051385 | Cell with Fixed Output Voltage for Integrated Circuit - The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell ( | 2009-02-26 |
| 20090051386 | Integrate Circuit Chip with Magnetic Devices - A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for routing magnetic gates in the first and second logic gate layers, wherein the first logic gate layer, the second logic gate layer, and the routing layer are electrically connected by vias. | 2009-02-26 |
| 20090051387 | Field programmable gate array with integrated application specific integrated circuit fabric - A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner. | 2009-02-26 |
| 20090051388 | Reducing leakage power in low power mode - Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal input, and to output a data signal from said sequential circuitry at said data output in response to said clock signal. The sequential circuitry is responsive to a predetermined value at said clamp signal input to switch to a low power mode and to set said data output to a forced value, while retaining said sequential state within said circuitry, said forced value being selected to reduce leakage power from combinatorial circuitry arranged to receive said output data signal. | 2009-02-26 |
| 20090051389 | Configurable on-die termination - Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted. | 2009-02-26 |
| 20090051390 | GLITCH REDUCED COMPENSATED CIRCUITS AND METHODS FOR USING SUCH - Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal. | 2009-02-26 |
| 20090051391 | ADJUSTABLE INPUT RECEIVER FOR LOW POWER HIGH SPEED INTERFACE - A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5˜0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance. | 2009-02-26 |
| 20090051392 | Circuit device and electronic equipment provided with the same - In one embodiment, a circuit device that performs a certain processing operation with respect to an input signal by referring to a reference voltage and outputs the result is caused to have a function of switching the reference voltage, whereby a circuit device from which a stable output can be obtained is disclosed. The circuit device includes a comparator and a reference voltage setting circuit. The comparator compares an input voltage fed from outside with a reference voltage selected from a reference voltage set including a plurality of voltage values that are different from one another. The reference voltage setting circuit selects a voltage value lower than the reference voltage from the reference voltage set when it is detected that the input voltage in a rising transition reaches the reference voltage, selects a voltage value higher than the reference voltage from the reference voltage set when it is detected that the input voltage in a falling transition reaches the reference voltage, and sets the selected voltage value as the reference voltage of the comparator. | 2009-02-26 |
| 20090051393 | Low side driver - An output driver circuit has an input, an output node, and first and second transistors coupled in series between the output node and a first source of operating potential. Parasitic diodes of the first and second transistors are anti-serially coupled. The output driver circuit has first and second control circuits coupled to control the first and second transistors respectively. The first transistor is controlled as a controlled current source depending on a signal at the input during normal conditions when the current that flows through the output is in a first direction, and the second control circuit controls the second transistor to prevent unwanted DC current at the output from flowing through the output in a second direction. The first and second transistors are also controlled to limit unwanted transient currents during an EMC disturbance substantially symmetrically. | 2009-02-26 |
| 20090051394 | Frequency Multipliers Using Multi-Phase Oscillation - A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0≦i≦(n−1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n. | 2009-02-26 |
| 20090051395 | DC/DC converter with spread spectrum switching signals - A DC/DC converter includes a converting circuit for converting a first voltage into a second voltage; a controller for generating spread spectrum switching signals; and a switch according to the spread spectrum switching signals controlling the on/off state of the switch. | 2009-02-26 |
| 20090051396 | Ring Oscillation Circuit, Delay Time Measuring Circuit, Testing Circuit, Clock Generating Circuit, Image Sensor, Pulse Generating Circuit, Semiconductor Integrated Circuit, and Testing Method Thereof - A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator. | 2009-02-26 |
| 20090051397 | Clock pulse generating circuit - A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator. | 2009-02-26 |
| 20090051398 | METHOD AND DELAY CIRCUIT WITH ACCURATELY CONTROLLED DUTY CYCLE - A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle. | 2009-02-26 |
| 20090051399 | ELECTRONIC CIRCUIT WITH LOW NOISE DELAY CIRCUIT - An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages ( | 2009-02-26 |
| 20090051400 | SYSTEM AND METHOD FOR FULLY DIGITAL CLOCK DIVIDER WITH NON-INTEGER DIVISOR SUPPORT - A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency. | 2009-02-26 |
| 20090051401 | CALIBRATION CIRCUIT FOR AN ADJUSTABLE CAPACITANCE - A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps. The calibration circuit includes a controllable capacitance for receiving a control signal and including an array of switched capacitors selectively activated by the control signal to connect to a first common node that conducts a voltage value depending on the total capacitance value of the activated capacitors; an assessment unit for comparing this voltage value with a reference voltage to output a logic signal that can transition between first and second logic levels; a control and timing unit to receive the logic signal and change the control signal to carry out a subsequent calibration step that is provided at the end of the integration interval during a comparison interval of a preset duration, which allows a transition of the logic signal to occur prior to the beginning of the consecutive calibration step. | 2009-02-26 |
| 20090051402 | MULTI-FUNCTION CIRCUIT MODULE HAVING VOLTAGE LEVEL SHIFTING FUNCTION AND DATA LATCHING FUNCTION - The present invention discloses a multi-function circuit module having voltage level shifting function and data latching function via switching a plurality of switch elements. The multi-function circuit module includes a first circuit module, a fourth switch element, and a fifth switch module, wherein the first circuit module further includes a first switch module, a second switch module, and a third switch module. The multi-function circuit module can substantially reduce the circuit layout area. For example, when the multi-function circuit module of the present invention is applied in a source driving chip circuit, the multi-function circuit module can replace the original low-to-high voltage level shifting circuit and data latching circuit, so as to attain the purpose of reducing the chip area. | 2009-02-26 |
| 20090051403 | Signal process circuit, level-shifter, display panel driver circuit, display device, and signal processing method - In one embodiment of the present invention, a signal process circuit in accordance with the present invention includes: a first input terminal via which an input signal is supplied; a second input terminal via which a predetermined signal is supplied; a cross-coupled inverter circuit, including first and second CMOS inverter circuits, in which an input of the first CMOS inverter circuit and an output of the second CMOS inverter circuit are interconnected to each other and an output of the first CMOS inverter circuit and an input of the second CMOS inverter circuit are interconnected to each other; a current control circuit that applies currents to the first and second CMOS inverter circuits in accordance with a timing signal, the input signal, and the predetermined signal; output terminals which are connected to the outputs of the first and second CMOS inverter circuits, respectively, and from which an output signal is supplied; and a reset circuit that resets the output signal based on the timing signal. With the arrangement, it is possible to cause a signal of a small amplitude to be level-shifted and latched at low power consumption. | 2009-02-26 |
| 20090051404 | INTERFACE CIRCUIT AND INTEGRATED CIRCUIT APPARATUS INCLUDING THE CIRCUIT - An interface circuit provided with a first input/output unit and a second input/output unit which respectively access external apparatuses to which electric power is supplied from power sources via different electric power supply lines includes an acquisition unit configured to acquire information whether electric power is supplied to the respective external apparatuses based on a command from the outside; a selection circuit configured to select an input/output unit corresponding to an external apparatus to which electric power is supplied, from the first input/output unit and the second input/output unit based on the information acquired by the acquisition unit; and a control circuit configured to output an instruction corresponding to the command, to the external apparatus to which electric power is supplied, via the input/output unit selected by the selection circuit. | 2009-02-26 |
| 20090051405 | ADAPTIVE CAPACITANCE FOR TRANSISTOR - A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state. | 2009-02-26 |
| 20090051406 | SEMICONDUCTOR DEVICE - A semiconductor device whose operational state is switched between a test state and a normal operational state according to a logical value of a signal input from the outside is provided. The semiconductor device includes a first power line, a second power line, a switch that is controlled by a signal line to couple/isolate the first power line to/from the second power line, a control circuit that outputs a control signal, and a state switching circuit that drives the signal line to couple/isolate the first power line to/from the second power line according to a logical value of the control signal when the input signal is one of logical values, whereas the state switching circuit drives the signal line to couple the first power line to the second power line when the first signal is the other logical value. | 2009-02-26 |
| 20090051407 | SWITCH CIRCUIT - A switch circuit is disclosed. The switch circuit comprises: a hysteresis buffer, an electric switch, a first discharge resistor, a second discharge resistor, a capacitor, a feedback resistor, a first reciprocal switch, and a second reciprocal switch. When the second reciprocal switch is turned on, a power supply voltage charges the capacitor, and thus the voltage on the signal input terminal of the hysteresis buffer is decreased. Accordingly, the voltage on the signal output terminal of the hysteresis buffer is decreased, so as to turn on the electric switch. When the first reciprocal switch is turned on, the capacitor is discharged, and thus the voltage on the signal input terminal of the hysteresis buffer is increased. Accordingly, the voltage applied to the signal output terminal of the hysteresis buffer is increased, so as to turn off the electric switch. | 2009-02-26 |
| 20090051408 | SWITCH FOR VEHICLES - Provided is a switch for vehicles, which includes an intermittent driving device connected to a control device which opens and closes a switching device based on the magnitude of the magnetism of a magnet mounted on an operating body. Therefore, the supply of power from a battery to a detection device and the control device is intermittently performed at a predetermined period by the intermittent driving device. | 2009-02-26 |
| 20090051409 | SWITCH FOR VEHICLES - Provided is a switch for vehicles, including a first switching device which performs the electrical connection/disconnection between a battery and a stop lamp and a second switching device connected to a control device which opens and closes the first switching device based on the magnitude of the magnetism of a magnet mounted on an operating body. Various controls such as auto-cruise control and so on as well as the turn on/off of the stop lamp can be simultaneously performed by the one magnet mounted on the operating body of the switch for vehicles. | 2009-02-26 |
| 20090051410 | Integrated powered device (PD) and physical layer (PHY) chip - An integrated physical layer (PHY) and powered device (PD) chip for use in a Power over Ethernet (PoE) system is provided. Embodiments reduce circuit size and cost and enable improved and novel PoE applications. Embodiments include one or more of a PHY circuit, a PD controller circuit, a DC-DC converter circuit, and an enterprise Internet Protocol (IP) circuit, integrated within a single integrated circuit (IC) chip. Embodiments are implemented using a floating ground design. Embodiments can be implemented using a mixed-voltage or a “voltage island” design or using a multi-die scheme. | 2009-02-26 |
| 20090051411 | Trimmer circuit and method - A trimmer circuit is so configured that an electronic device will break down to produce a high current to trim a fuse. The electronic device is selectively configured to have a breakdown voltage lower than an applied voltage, for the trigger of its breakdown to be controllable. In an embodiment, the electronic device is switched between two states having two breakdown voltages respectively, and the applied voltage is higher than one of the breakdown voltages and lower than the other one. | 2009-02-26 |
| 20090051412 | INTEGRATED CIRCUT, AND APPARATUS AND METHOD FOR PRODUCTION THEREOF - An integrated circuit includes a trimming signal creating section, disposed downstream of a trimming circuit in which a number of fuses are arranged in alignment, creating a trimming signal corresponding to the trimming value on the basis of a signal output from said trimming circuit and arranges blown object fuses such that every two of the blown object fuses are interposed at least one un-blown fuses in the trimming circuit. An efficient arrangement of blowing points in addition to the above arrangement of blown object fuses can reduce the area occupied by the trimming circuit. | 2009-02-26 |
| 20090051413 | APPARATUS AND METHOD FOR INCREASING CHARGE PUMP EFFICIENCY - A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage. | 2009-02-26 |
| 20090051414 | Dual conversion rate voltage booster apparatus and method - An apparatus and method of boosting voltages. A boosting circuit includes a first and a second boosting circuit that each provide a boosted voltage in response to a set of control signals. The first and second boosting circuits receive different sets of control signals so that the boosted voltages may be alternately transferred to and combined at a load terminal. | 2009-02-26 |
| 20090051415 | Ripple current reduction circuit - A ripple current reduction circuit includes a supply node coupled to the output of a high ripple voltage source such as a charge pump. A first current mirror is referred to the supply node and mirrors a current I | 2009-02-26 |
| 20090051416 | Apparatus, electronic component and method for generating reference voltage - An apparatus, includes a plurality of circuits each of which operates with a reference voltage, a constant current generator which generates a substantially constant current, and distributes the substantially constant current to each of the circuits, and a plurality of converters, each of the converters respectively corresponding to each of the circuits, each of which converts the substantially constant current to the reference voltage and respectively provides the reference voltage to each of the circuits. | 2009-02-26 |
| 20090051417 | Voltage Supply Insensitive Bias Circuits - A voltage-insensitive circuit includes a second circuit, and a biasing means for providing a constant bias current to the second circuit, the bias current being insensitive to power fluctuations of the voltage-insensitive circuit. | 2009-02-26 |
| 20090051418 | DISTRIBUTED VOLTAGE REGULATOR - An integrated circuit device and a method for providing distributed voltage regulation. The device includes a plurality of memory cell arrays and access circuitry dependent on one or more regulated voltages generated on the device and a plurality of pulsed digital distributed output units configured to generate the one or more regulated voltages. The device also includes a voltage regulator control logic configured to generate one or more control signals to control the distributed output units based, at least in part, on a comparison between one or more reference voltages and the one or more regulated voltages. | 2009-02-26 |
| 20090051419 | Internal voltage compensation circuit - An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals. | 2009-02-26 |
| 20090051420 | INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES - Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit. | 2009-02-26 |
| 20090051421 | SWITCHED CAPACITOR INTEGRATION AND SUMMING CIRCUITS - A switched capacitor circuit employs a single operational amplifier to implement both an integrator and a summer. One input signal is routed to the input of the operational amplifier through (1) one or more integration branches, and (2) one or more first summing branches. A second input signal is routed to the input of the operational amplifier through one or more second summing branches. Each of the branches includes a capacitor and a number of switches controlled by different clock phases. The switched capacitor circuit may be single-ended or differential. The circuit may be used in an access terminal of a cellular communication system. The access terminal may operate under a code division multiple access (CDMA) communication standard. | 2009-02-26 |
| 20090051422 | Filter Device - Provided is a switched capacitor type filter device having a steep characteristic with a small number of taps. The filter device includes positive polarity selecting switches ( | 2009-02-26 |
| 20090051423 | DIGITAL AUDIO AMPLIFIERS, ELECTRONIC SYSTEMS, AND METHODS - An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage. | 2009-02-26 |
| 20090051424 | ACTIVE CIRCUITS WITH LOAD LINEARIZATION - Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation. | 2009-02-26 |
| 20090051425 | PREDISTORTION SYSTEM AND METHOD BASED ON LOOK UP TABLE INTERPOLATION - A system comprising a pre-power amplifier and a hardware device which is configured to predistort an amplitude input signal by comparing interpolated data places, determined by comparing the input signal with data from a LUT, coming from a LUT with the amplitude input signal and choosing the closest input data place to the amplitude input signal to produce an amplitude predistortion output signal. The LUT contains predistortion data associated with the pre-power amplifier. The amplitude input signal is multiplied and scaled prior to being compared with the data in the LUT. A second LUT is used to predistort a phase input signal and the phase predistortion output signal is combined in the pre-power amplifier with the amplitude predistortion output signal. The system may be implemented in a mobile communications device. | 2009-02-26 |
| 20090051426 | Large-Dynamic-Range Lookup Table for a Transmitter Predistorter and System and Method Employing the Same - A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one embodiment, the predistorter includes: (1) a lookup table having non-uniformly spaced entries therein, (2) a compander configured to compand an input signal based on a nonlinearity of the nonlinear element to address the entries and (3) an interpolation offset calculation circuit associated with the lookup table and configured to produce an output based on a value of the input signal and a linear interpolation involving at least two entries from the lookup table. | 2009-02-26 |
| 20090051427 | OUTPUT LIMITING CIRCUIT, CLASS D POWER AMPLIFIER AND AUDIO EQUIPMENT - An output limiting circuit includes a reference current generating portion for converting a predetermined constant voltage into a reference current by using a first resistor, an upper side clip voltage generating portion for converting the reference current into an upper side clip voltage with respect to a bias voltage of the operational amplifier by using a second resistor, a lower side clip voltage generating portion for converting the reference current into a lower side clip voltage with respect to the bias voltage of the operational amplifier by using a third resistor, and a gain adjusting portion for adjusting a gain of the operational amplifier so that a voltage level of the output signal does not exceed an upper side limit level corresponding to the upper side clip voltage and that the voltage level of the output signal does not exceed a lower side limit level corresponding to the lower side clip voltage. | 2009-02-26 |
| 20090051428 | AGC CIRCUIT - This invention offers an AGC circuit that prevents disturbance in an output waveform when an input signal varies abruptly. A first terminal of a capacitor is connected with an output terminal of a variable gain amplifier and a second terminal of the capacitor is connected with a non-inverting input terminal (+) of a differential amplifier. A reference voltage Vref | 2009-02-26 |
| 20090051429 | HIGH RESOLUTION VARIABLE GAIN CONTROL - A gain circuit includes an analog section with variable gain and a digital section with variable gain. The gain steps for the digital section have a higher resolution than the gain steps for the analog section. In some implementations, gain steps can be achieved much finer than 0.1 db or less without sensitivity to device tolerances. | 2009-02-26 |
| 20090051430 | Variable gain circuit - Disclosed is a variable gain circuit, which operates in a region where the gain varies substantially exponentially with respect to a control voltage, having an operation region in which the gain varies substantially with an exponential function | 2009-02-26 |
| 20090051431 | HIGH-SWING OPERATIONAL AMPLIFIER OUTPUT STAGE USING ADAPTIVE BIASING - An output stage includes two transistors (switching transistor and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit adjusts the gate voltage on a biasing transistor based on the output node voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings. | 2009-02-26 |
| 20090051432 | High-bandwidth high-gain amplifier - A pipelined analog to digital converter includes a first stage that receives an input voltage, that generates a first sampled digital value and a first residue voltage, and that includes a first amplifier that amplifies the first residue voltage and generates a first amplified residue voltage. A second stage receives the first amplified residue voltage, generates a second sampled digital value and a second residue voltage, and includes a second amplifier that amplifies the second residue voltage. At least one of the first amplifier and the second amplifier comprises a first transistor having a control terminal, a first terminal, and a second terminal, a second transistor having a control terminal, a first terminal, and a second terminal that communicates with the second terminal of the first transistor, a differential transimpedance amplifier and a differential output amplifier. | 2009-02-26 |
| 20090051433 | DIFFERENTIAL SENSING WITH HIGH COMMON MODE REJECTION - A differential operation circuit that uses the differential input signals to generate a reference voltage that fluctuates with the common mode voltage of the differential input signals. The reference voltage includes a common mode component that generally follows the common mode voltage of the differential input signals. The common mode component of the reference voltage is used to fully or almost fully offset the common mode voltage of the differential input signals, thereby increasing the differential operation circuit's common mode rejection characteristics. | 2009-02-26 |
| 20090051434 | SIGNAL TRANSFER CIRCUIT AND CIRCUIT DEVICE USING SAME - A signal transfer circuit appropriate for use in realizing both high circuit stability and high current driving ability is disclosed. Signal transfer circuit A has current transfer circuit | 2009-02-26 |
| 20090051435 | RF AMPLIFIER WITH STACKED TRANSISTORS, TRANSMITTING DEVICE, AND METHOD THEREFOR - An RF transmitting device ( | 2009-02-26 |
| 20090051436 | METHOD AND SYSTEM FOR FET-BASED AMPLIFIER CIRCUITS - Amplifier circuits and methods are implemented using a variety of different embodiments. According to one such embodiment, a method is implemented using a field-effect transistor (FET) having a gate node, a source node and a drain node. A first circuit state is implemented in which the gate node, the source node and the drain node are connected to inputs that generate a stored a charge at the gate node, the amount of stored charge at the gate node being responsive to a first voltage level. A second circuit state is implemented in which the drain node is connected to a voltage source, the source node is connected to a load, and while charge at the gate node is preserved, current between the drain node to the source node drives a voltage level of the load to a proportionally amplified version of the first voltage level. | 2009-02-26 |
| 20090051437 | POWER AMPLIFIER - An emitter follower circuit applies to an input terminal of a second amplifying device a voltage according to a reference voltage applied to a reference terminals. First and second resistors are connected in series between the reference terminal and an input terminal of a first amplifying device. The collector of a first transistor is connected to the reference terminal, and a control voltage is applied to the base of the first transistor. A third resistor is connected between the emitter of the first transistor and a grounding point. A current mirror circuit draws a current proportional to a current input from the collector of the first transistor from a connection point of the first and second resistors. | 2009-02-26 |
| 20090051438 | Amplifying system - The performance of an amplifying system is improved by achieving adequate matching. The amplifying system for amplifying signals includes distributing means | 2009-02-26 |
| 20090051439 | TRANSCONDUCTANCE SIGNAL CAPACITY FORMAT - Operational transconductance amplifiers have a natural signal capacity format in which signal performance can be expressed in terms of fixed percentages. Input signal can be applied to Operational transconductance amplifiers in this natural signal capacity format in order to optimize performance. A signal which drives a given Operational transconductance amplifier architecture to produce an output current which is at 50% of it's maximum available output current can be thought of as applying an input voltage which is at 50% of an Operational transconductance amplifier's maximum input voltage capacity. In this input/output channel capacity format, dc offset, distortion, and noise all are temperature independent. By translating input signal between a voltage format to a channel capacity format using the methods of this invention, output signal performance attributes such as gain, frequency response, dc offset, temperature drift, distortion, and noise, can all be optimize over the full temperature range for all types of Operational transconductance amplifier architectures and applications. | 2009-02-26 |
| 20090051440 | ACTIVE BALUN CIRCUIT - There is provided an active balun circuit including: a load circuit unit including a first and a second load; a differential amplifying unit including a first amplifying unit connected to the first load, and a second amplifying unit connected to the second load and forming a differential amplifying unit together with the first amplifying unit, the differential amplifying unit differentially amplifying an input signal, and outputting first and second output signals out-of-phase with each other through first and second output terminals, respectively; a current source connected between a ground and a common connection node of the first and second amplifying units, and maintaining a constant amount of current flowing through the differential amplifying unit; and a compensation amplifying unit amplifying the input signal supplied through the input terminal, transmitting the amplified input signal to the second amplifying unit, and rejecting common mode noise of the differential amplifying unit. | 2009-02-26 |
| 20090051441 | LOW-NOISE AMPLIFIER - Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values. | 2009-02-26 |
| 20090051442 | TRANSIMPEDANCE AMPLIFIER CIRCUIT FOR OPTICAL RECEIVER IN OPTICAL COMMUNICATION SYSTEM - A transimpedance amplifier circuit for an optical receiver in an optical communication system in which a range of an increase/decrease in bandwidth according to gain change is reduced by a bandwidth adjustor. The circuit includes: a photodiode (PD) for generating a current signal by photoelectric conversion of an input optical signal; a Transimpedance Amplifier (TIA) for converting the current signal input from the photodiode into a voltage signal; an auto gain adjustor for adjusting feedback resistances of the transimpedance amplifier; a photodiode parallel capacitor reducer for reducing a parallel capacitor current of the photodiode; and a bandwidth adjustor for reducing a range of an increase/decrease in bandwidth according to an increase/decrease in gain of the transimpedance amplifier. | 2009-02-26 |
| 20090051443 | Oscillator Stabilized for Temperature and Power Supply Variations - A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage. | 2009-02-26 |
| 20090051444 | FREQUENCY-CORRECTED CLOCK SIGNAL GENERATION INTEGRATED CIRCUIT DEVICE - An integrated circuit device including: an oscillation circuit that generates a first clock signal; a frequency comparison section that compares a frequency of the first clock signal with a frequency of a second clock signal; and a clock signal generation section that generates a third clock signal based on the first clock signal. The clock signal generation section corrects a frequency of the third clock signal to be a value within a predetermined range based on the comparison result. For example, the frequency comparison section counts a predetermined period based on the first clock signal, the predetermined period being defined based on the second clock signal, and the clock signal generation section generates the third clock signal by dividing the frequency of the first clock signal based on the count result. | 2009-02-26 |
| 20090051445 | LOOSELY-COUPLED OSCILLATOR - Aspects and embodiments of the present invention provide a loosely-coupled oscillator including a sensor circuit and an electronic device that are not physically connected. In some embodiments, the electronic device includes an amplifier stage and a feedback network and the sensor circuit includes one or more LC circuits. When electromagnetically connected, the sensor circuit and electronic device form an oscillator that is adapted to output an oscillation signal. The resonant frequency of the sensor circuit can be obtained based on the oscillation signal. The sensor circuit may be implanted into an object and the resonant frequency of the sensor circuit can be used to determine characteristics of the object. | 2009-02-26 |
| 20090051446 | Ovenized oscillator - An ovenized oscillator package including at least a heater and a crystal package mounted on opposite sides of a circuit board. Vias extend through the body of the circuit board to transfer heat from the heater to the crystal package. Layers of thermally conductive material extend through the body of the circuit board and are in thermally coupled relationship with the vias for spreading heat throughout the circuit board and other elements mounted thereon. | 2009-02-26 |
| 20090051447 | Ovenized oscillator - An ovenized oscillator package including a ball grid array substrate seated on a circuit board, a heater and a temperature sensor mounted on the ball grid array substrate, and a crystal package mounted to the ball grid array substrate and overlying at least the heater. A layer of thermally conductive epoxy or adhesive material couples the heater to the crystal package. Stabilizer posts, which are made of an insulative adhesive or epoxy material, are formed between the ball grid array substrate and the circuit board for stabilizing and relieving the stress on the ball grid array substrate. A lid is seated on the circuit board and covers and defines an oven for the ball grid array substrate. | 2009-02-26 |
| 20090051448 | SECOND HARMONIC OSCILLATOR - A second harmonic oscillator has a series positive feedback configuration, suppresses output of a fundamental signal, and outputs a second harmonic signal having a frequency in a range from 1 GHz to 200 GHz generated inside of a circuit. The second harmonic oscillator includes: a transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal; a resonator circuit connected to the base terminal; a first transmission line short-circuiting stub connected to one of the two emitter terminals; and a second transmission line short-circuiting stub connected to the other of the two emitter terminals and having a line length obtained by adding one-fourth of one wavelength of the fundamental signal to an integer multiple of one-half wavelength of the fundamental signal. | 2009-02-26 |
| 20090051449 | DIELECTRIC RESONATOR OSCILLATOR AND RADAR SYSTEM USING THE SAME - In the mass production of dielectric resonator oscillators (DROs), it is necessary to regulate the position where a dielectric resonator is placed with a high degree of accuracy and thus time required for the assembly work increases undesirably. Further, a terminating resistor and earthing means are formed at an end of a transmission line that is electromagnetically coupled to the dielectric resonator and constitutes the resonator on a dielectric substrate, and as a result the production cost increases. The present invention is characterized in that, in the components of a DOR, only a transmission line is formed on a dielectric substrate, and an oscillating active element and a terminating resistor and the earthing means on an MMIC chip are connected to the transmission line with metallic wires, metallic ribbons, or the like. Further, an open stub is formed in the middle of the transmission line on the side close to the oscillating active element when it is viewed from the dielectric resonator. | 2009-02-26 |
| 20090051450 | CLOCK GENERATION CIRCUIT AND CLOCK GENERATION CONTROL CIRCUIT - According to a preferred embodiment, a clock signal generation circuit includes an oscillating circuit configured to output a clock signal having a clock frequency corresponding to a control signal, a counter configured to generate a count value by counting a pulse number of the clock signal outputted from the oscillating circuit during a predetermined time period, a subtracting circuit configured to produce differential data by subtracting the count value from a preset value previously set based on a predetermined clock frequency, a control signal correcting circuit configured to generate a correcting control signal by correcting a value of the control signal based on the differential data, and a digital-analog converter circuit configured to convert the correcting control signal into an analog correcting control signal and output the converted analog correcting control signal to the oscillating circuit. This clock signal generation circuit can prevent increasing of the circuit size or the system size due to a resistor, a capacitor element, etc., used in a PLL (Phase Locked Loop) without using a central processing unit. | 2009-02-26 |
| 20090051451 | GYROMAGNETIC PRECESSION OSCILLATOR - The present invention is, in one aspect, a radio frequency source, comprising a gyromagnetic precession oscillator. In a second aspect, the gyromagnetic precession oscillator comprises a closed, non-magnetic, cylindrical outer conductor defining a cavity therein; an axial field solenoid wound about the outer conductor; a non-magnetic, cylindrical inner conductor disposed within the cavity and coaxially aligned with the outer conductor; a plurality of cylindrical ferrite precessors, each defining a respective bore through which the inner conductor runs; a plurality of dividers disposed within and defining a resonant chamber in the cavity; and a dielectric material filling the cavity. In a third aspect, the radio frequency source is actively tunable. In a fourth aspect, the radio frequency source that is tunable pulse-to-pulse. | 2009-02-26 |
| 20090051452 | Oscillation device and inspection apparatus - An oscillation device has a resonant tunneling diode formed by interposing a gain medium including a first barrier layer, a quantum well layer and a second barrier layer between a first thickness adjusting layer and a second thickness adjusting layer. The oscillation device also has a switch for switching the polarity of a bias voltage being applied to the resonant tunneling diode. The first thickness adjusting layer and the second thickness adjusting layer have different thicknesses. Thus, a single oscillation device is driven to oscillate with different oscillation frequencies. | 2009-02-26 |
| 20090051453 | VOLTAGE-CONTROLLED OSCILLATOR USING LC RESONATOR - Provided is a voltage-controlled oscillator (VCO) using an LC resonator circuit which includes a first resonance circuit in which two serially connected varactor diodes and an inductor are connected in parallel, a second resonance circuit in which one or more inductor L | 2009-02-26 |
| 20090051454 | Voltage controlled oscillator - According to one aspect of the present invention, there is provided a voltage controlled oscillator controlling frequency of an output signal according to input voltage, the voltage controlled oscillator including a current controlled oscillator setting the frequency of the output signal based on control current, and a voltage-current converter including a transistor controlling a current amount of the control current according to the input voltage, in which the voltage-current converter is supplied with control voltage, and threshold value voltage of the transistor is controlled according to the control voltage. | 2009-02-26 |
| 20090051455 | MODULATION/DEMODULATION APPARATUS AND MODULATION/DEMODULATION METHOD - A modulation/demodulation apparatus according to an embodiment of the present invention includes a sine wave generating circuit configured to output two sine waves which are orthogonal to each other and have equal amplitude, an orthogonal modulator connected to the sine wave generating circuit and configured to modulate the sine waves to generate a modulated signal, a detecting section configured to detect amplitude fluctuation in the modulated signal, a multiplying section configured to multiply the modulated signal and the amplitude fluctuation detected by the detecting section together, and an orthogonal demodulator configured to demodulate the modulated signal multiplied with the amplitude fluctuation by the multiplying section to generate a demodulated signal. | 2009-02-26 |
| 20090051456 | Circulator/isolator housing with inserts - A circulator/isolator housing is provided that includes body and a plurality of slots within the body configured to receive therethrough inserts having magnetic permeability. The housing further includes a plurality of receiving portions within the body corresponding to the plurality of slots and configured to maintain a position of the inserts. | 2009-02-26 |
| 20090051457 | DMS-Filter with Connected Resonators - A surface acoustic wave filter arrangement is described herein. The surface acoustic wave filter arrangement includes a first gate configured to operate symmetrically or asymmetrically, and a second gate configured to operate symmetrically. The filter arrangement also includes a double-mode surface acoustic wave (DMS) filter structure including an input connected to the first gate, and an output. The output includes a terminal pair that includes two symmetrical terminals configured to operate symmetrically. Each of the two symmetrical terminals of the terminal pair is electrically connected at the output of the DMS filter structure to a cascaded resonator. | 2009-02-26 |
| 20090051458 | Receiver With Adaptive Equalizer - Receivers and methods for receiving a signal may result in improved performance by resolving specific impairments at particular levels. For example, bit error ratio (BER) in the downstream signal of an HFC network may be improved by resolving up to 6% AM hum. Thus, the receivers and methods described herein may function with dramatically improved error rates and continuous FEC lock, in relation to conventional receivers, in the presence of SCTE 40 impairments and full channel loading over the receivers entire input dynamic range. | 2009-02-26 |
| 20090051459 | FILTER - A filter is provided with one unbalanced input terminal, a first balanced output terminal and a second balanced output terminal. A primary coil is connected between a connecting point, which is of a second capacitor and a third capacitor, and GND. Furthermore, a secondary coil is connected between the first balanced output terminal and the second balanced output terminal, and the primary coil and the secondary coil are magnetically coupled. | 2009-02-26 |
| 20090051460 | MODULE AND PASSIVE PART - A passive part includes a filter unit having first resonance electrode to a third resonance electrode and an impedance matching circuit unit electrically connected to the third resonance electrode of the filter unit arranged on a dielectric substrate. The entire passive part has a configuration including a circuit unit equivalent to characteristic containing the second impedance matching circuit by an impedance component of the third resonance electrode. For example, by modifying the width of the third resonance electrode, it is possible to adjust the impedance in the same way as when a capacitance as the impedance matching circuit unit is connected, without connecting any capacitance. | 2009-02-26 |
| 20090051461 | OUTPUT POWER DETECTING SYSTEM WITH A DIRECTIONAL COUPLER - A output power detecting system with a directional coupler has a directional coupler at the output terminal of the output power detecting system. The directional coupler includes a main line, a first sub line, and a second sub line. The output of the power amplifying unit is fully coupled to a power detecting unit via the coupling between the main line and the first sub line, and the external noise is coupled to the ground via the coupling between the first sub line and the second sub line. Therefore, the power detecting unit accurately detects the output power of the output power detecting system. | 2009-02-26 |
| 20090051462 | HF Coupler or HF Power Splitter, Especially a Narrow-Band and/or 3DB Coupler or Power Splitter - An improved HF coupler or HF power splitter comprises four connection lines arranged on the same side of the substrate. Two coupling zones are formed on the substrate on two opposite sides; the second coupling zone is connected to the associated connection lines arranged on the side of the substrate opposing the coupling zone, by means of two via holes in an electroplated manner. The capacitors provided at the beginning and at each end of each coupling zone are respectively embodied as interdigital capacitors; and the capacitors are respectively coupled to earth. | 2009-02-26 |
| 20090051463 | SPLITTER/COMBINER CIRCUIT - A circuit for combining/splitting at least two RF signals comprising: (a) at least two or more transmission portions coupled at an intersection, the intersection having a common port for inputting or outputting a combination of the at least two RF signals; (b) each transmission portion extending from the intersection to a port for inputting or outputting a selection of signals from the combination, and comprising at least one set of intersecting transmission lines; (c) each set of intersecting transmission lines rejecting a particular signal of the combination; and (d) each intersecting transmission line of a given set having a length of about an odd multiple of a quarter wavelength of the particular signal which is rejected by the given set. | 2009-02-26 |
| 20090051464 | Switch cicuit and phase shifter - A switch circuit in which the cut-off characteristic is improved over a wide range of frequencies in the microwave band includes a first field-effect transistor functioning as a switch element, a second field-effect transistor and an inductor. A serially connected circuit composed of the inductor and second field-effect transistor is connected in parallel with the first field-effect transistor across the source and drain thereof. The second field-effect transistor is turned on when the first field-effect transistor operates normally and is turned off when the first field-effect transistor is inspected. | 2009-02-26 |
| 20090051465 | DELAY LINE - In a band-pass filter of a delay line, an input terminal and a first resonator adjacent to the input terminal are coupled through a capacitor. The first resonator and a second resonator adjacent to the first resonator are coupled through a capacitor. The second resonator and a third resonator adjacent to the second resonator are coupled through an inductance. The third resonator and a fourth resonator adjacent to the third resonator are coupled through a capacitor. The fourth resonator and an output terminal adjacent to the fourth resonator are coupled through a capacitor. | 2009-02-26 |
| 20090051466 | Micro-power source module - A power source IC and noise absorption capacitors (decoupling capacitors) are formed on an inductor in such a manner that the noise absorption capacitors are provided on the input side and the output side, respectively. A micro-power source module can'thus be provided which is small in occupied area and height and can reduce conduction noise due to ground lines. | 2009-02-26 |
| 20090051467 | APPARATUS AND METHOD FOR MODE SUPPRESSION IN MICROWAVE AND MILLIMETERWAVE PACKAGES - A parallel plate waveguide structure configured to suppress parallel-plate waveguide modes is described. The electromagnetic material properties of individual layers disposed between the conductive plates of waveguide may be selected to allow an apparent stopband to form. Several physical examples of electromagnetic bandgap (EBG) structures are presented that are analyzed by full wave simulations and transverse resonance models. | 2009-02-26 |
| 20090051468 | COAXIAL CONCENTRIC NONLINEAR TRANSMISSION LINE - A radio frequency source includes a coaxial non-linear transmission line. The coaxial non-linear transmission line may include a closed, non-magnetic, cylindrical outer conductor defining a cavity therein; and a plurality of stages enclosed by the outer conductor. Each stage may then includes an axial field solenoid wound about the outer conductor; a non-magnetic, cylindrical inner conductor disposed within the cavity and coaxially aligned with the outer conductor; a plurality of cylindrical ferrite switch elements, each defining a respective bore through which the inner conductor runs; and a plurality of inner and outer cups coaxially aligned with the inner and outer conductors, each defining a respective bore through which the inner conductor runs. | 2009-02-26 |
| 20090051469 | MULTI-FUNCTIONAL COMPOSITE SUBSTRATE STRUCTURE - A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal. | 2009-02-26 |
| 20090051470 | APPARATUS FOR AUXILIARY CONTACT OF CIRCUIT BREAKER - An apparatus for auxiliary contact of circuit breaker is disclosed that is capable of preventing an erroneous operation of and damage to an ON/OFF switch caused by over-stroke of a linkage mounted at an auxiliary contact apparatus, and enhancing reliability despite repeated opening/closing thereof. | 2009-02-26 |
| 20090051471 | Long-proportional-stroke force motor - There is provided a long-proportional-stroke force motor whose force vs. stroke characteristic provides a long stroke in which a constant force is output proportional to the exciting current in magnitude without involvement of problems in actual use, and which does not impose any limitations on the stroke so as to effectively use the stroke. | 2009-02-26 |
| 20090051472 | SOLENOID DEVICE WITH STABLE ACTIVATION - A solenoid may include a core having a junction surface; a plunger having a junction surface and located adjacent to the core; a shading ring located proximate to an interface between the core junction surface and the plunger junction surface, the shading ring having an outside diameter slightly smaller than the diameter of the core, and operable to produce a concentration of magnetic attraction within an annular range of the interface between a center of the interface and a location of the shading ring; wherein a contact region between the core junction surface and the plunger junction surface is substantially smaller than the respective junction surfaces and located proximate to the annular range of the concentration of magnetic attraction. | 2009-02-26 |
| 20090051473 | METHODS AND APPARATUS FOR ELECTROMAGNETIC COMPONENTS - Methods and apparatus for electromagnetic components comprise a core and a winding. The core and winding are configured to provide smaller and more effective electromagnetic components. | 2009-02-26 |
| 20090051474 | LAMINATED INDUCTOR - There is provided a laminated inductor including: a body where a plurality of magnetic layers are laminated; a coil part formed on the magnetic layers, the coil part including a plurality of conductor patterns and a plurality of conductive vias; first and second external electrodes formed on an outer surface of the body to connect to both ends of the coil part, respectively; and a non-magnetic conductor formed on at least one of the magnetic layers so as to relax magnetic saturation caused by direct current flowing through the coil part. The laminated inductor employs the non-magnetic conductor as a non-magnetic gap to be simplified in a manufacturing process and effectively improved in DC superposition characteristics. | 2009-02-26 |
| 20090051475 | EMBEDDED INDUCTOR AND MANUFACTURING METHOD THEREOF - An embedded inductor includes a coil and a magnetic body covering the coil. The magnetic body includes an insulated magnetic powder, a coupling agent and a resin. In addition, a manufacturing method of the embedded inductor includes steps of performing an insulation process for a magnetic powder to obtain an insulated magnetic powder; performing a surface process on the insulated magnetic powder; mixing the surface-processed insulated magnetic powder with a liquid resin to form a mixture; providing a coil; covering the coil with the mixture; and performing pressing and curing processes to obtain the embedded inductor. | 2009-02-26 |
| 20090051476 | LAMINATE DEVICE AND MODULE COMPRISING SAME - The laminate device of the present invention comprises magnetic layers and coil patterns alternately laminated, the coil patterns being connected in a lamination direction to form a coil, and pluralities of magnetic gap layers being disposed in regions in contact with the coil patterns. | 2009-02-26 |
| 20090051477 | PLANAR TRANSFORMER, TRANSMISSION LINE BALUN AND METHOD OF FABRICATION - A planar transformer or balun device, having small trace spacing and high mutual coupling coefficient, and a method of fabricating the same is disclosed. The method may comprise providing a first and a second inductor on a primary and a second substrate respectively, interleaving at least partially the first inductor with the second inductor, coupling the primary and the secondary substrates to form a unitary structure, and providing electrical contacts to couple the first and second inductors with another device or circuit. | 2009-02-26 |
