| 09th week of 2009 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20090050877 | Semiconductor memory device - A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode. | 2009-02-26 |
| 20090050878 | MULTIFUNCTION ORGANIC DIODE AND MATRIX PANEL THEREOF - Disclosed is organic diode which is capable of light emitting display by an organic EL display, image sensing by a organic photodiode and power generation by an organic solar cell. Also disclosed is a matrix panel of such a multifunction organic diode. Specifically disclosed is a multifunction organic diode comprising a first electrode ( | 2009-02-26 |
| 20090050879 | ORGANIC THIN FILM TRANSISTOR AND ACTIVE MATRIX DISPLAY - An organic thin film transistor is disclosed. The organic thin film transistor includes a substrate, a gate electrode , a gate insulating film , a source electrode on the gate insulating film, a drain electrode on the gate insulating film at an interval with the source electrode, and an organic semiconductor layer. The gate insulating film includes an electrode formation region having surface energy modified by energy deposition, one or more corners of the electrode formation region has an obtuse-angled shape, and the source electrode and/or the drain electrode is formed in the electrode formation region so as to have substantially the same corner shape as the electrode formation region having the obtuse-angled shaped corners. | 2009-02-26 |
| 20090050880 | Method of Fabricating Thin-Film Transistor - The core metal of a protein such as ferritin is used as a nucleus for crystallizing a silicone thin film and then the thus crystallized film is employed in the channel part of a thin-film transistor. By aligning the protein on the surface of amorphous silicone and heating, the crystallinity is controlled. In the case of ferritin, the core diameter of the protein is 7 mm. That is, this protein is highly even in size (i.e., the metal content). Thus, the amount of the protein to be deposited on the amorphous silicone surface can be accurately controlled by controlling the protein core density. Furthermore, the type of the core metal can be altered by chemical reactions and the above method is applicable not only to amorphous silicone but also to amorphous films of various types such as germanium. Thus, the amount of nickel required in crystallization is controlled by using a protein. Moreover, the distribution density of the nickel core is controlled to thereby conduct crystallization at a desired crystal size. | 2009-02-26 |
| 20090050881 | PHOTOELECTRIC CONVERSION ELEMENT, METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION ELEMENT, AND SOLID-STATE IMAGING DEVICE - A photoelectric conversion element is provided and includes a photoelectric conversion portion. The photoelectric conversion portion includes: a pair of electrodes; and a photoelectric conversion layer between the pair of electrodes, and at least part of the photoelectric conversion layer includes a mixed layer of a p-type organic semiconductor and a fullerene, and a mixing ratio of the fullerene to the p-type organic semiconductor in terms of thickness ratio is less than 1:1. | 2009-02-26 |
| 20090050882 | Organic thin film transistor - An organic thin film transistor including: a substrate; a gate electrode placed on the substrate; a gate insulating film placed on the gate electrode; a source electrode and a drain electrode which are placed on the gate insulating film; an organic semiconductor layer placed on the gate insulating film between the source electrode and the drain electrode; a hole transport layer placed on the organic semiconductor layer; an electron transport layer placed on the hole transport layer; and a conductor layer placed on the electron transport layer; the organic thin film transistor which characteristics are stable by being protected from oxygen or moisture and being protected electromagnetically and which is suitable for integration. | 2009-02-26 |
| 20090050883 | Method of manufacturing organic electroluminescent device and organic electroluminescent device - An organic electroluminescent device, which, on a substrate, has a plurality of first electrodes, and a second electrode opposing the plurality of first electrodes. The organic electroluminescent device also including a light-emitting functional layer between the second electrode and one of the first electrodes and a buffering layer that covers the second electrode. The buffering layer having a side end portion with an angle equal to or less than 30°. The organic electroluminescent device further including a gas barrier layer that covers the buffering layer. | 2009-02-26 |
| 20090050884 | THIN FILM TRANSISTORS USING THIN FILM SEMICONDUCTOR MATERIALS - The present invention generally comprises TFTs having semiconductor material comprising oxygen, nitrogen, and one or more element selected from the group consisting of zinc, tin, gallium, cadmium, and indium as the active channel. The semiconductor material may be used in bottom gate TFTs, top gate TFTs, and other types of TFTs. The TFTs may be patterned by etching to create both the channel and the metal electrodes. Then, the source-drain electrodes may be defined by dry etching using the semiconductor material as an etch stop layer. The active layer carrier concentration, mobility, and interface with other layers of the TFT can be tuned to predetermined values. The tuning may be accomplished by changing the nitrogen containing gas to oxygen containing gas flow ratio, annealing and/or plasma treating the deposited semiconductor film, or changing the concentration of aluminum doping. | 2009-02-26 |
| 20090050885 | Semiconductor wafers and methods of fabricating semiconductor devices - A semiconductor wafer includes a plurality of unitary semiconductor chips formed on a semiconductor substrate. Scribe lane region separate the unitary semiconductor chips from each other. Test element group (TEG) pads are configured to apply testing signals for testing respective test elements. A TEG pad is arranged such that an acute angle formed at an intersection of a line extending from portion of a perimeter of the TEG pad and at least a portion of the outer edge of a corresponding scribe lane region is greater than 0° and less than or equal to 60°. | 2009-02-26 |
| 20090050886 | Test device, SRAM test device, semiconductor integrated circuit device and methods of fabricating the same - A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction on a semiconductor substrate, a plurality of test gate lines crossing the test active regions, a plurality of test contacts on at least one of the test active regions and test gate lines, a plurality of conducting regions electrically connecting the test contacts, and a plurality of conductive wiring lines interconnecting the plurality of test contacts, wherein an open contact chain, which electrically connects the plurality of test contacts, is formed. | 2009-02-26 |
| 20090050887 | CHIP ON FILM (COF) PACKAGE HAVING TEST PAD FOR TESTING ELECTRICAL FUNCTION OF CHIP AND METHOD FOR MANUFACTURING SAME - A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip. | 2009-02-26 |
| 20090050888 | Semiconductor device and manufacturing method thereof - The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film | 2009-02-26 |
| 20090050889 | Repairable capacitor for liquid crystal display - A thin film transistor array substrate, which can repair a current-leakage defect of a storage capacitor, is disclosed. The thin film transistor array substrate of the present invention comprises: a substrate, a plurality of data lines, and a plurality of scan lines, wherein the data lines and the scan lines divide the substrate into a plurality of display units, i.e. pixels. Each of these display units comprises: a thin film transistor, a lower electrode of a storage capacitor, a first dielectric layer covering the lower electrode of a storage capacitor, an upper electrode of the storage capacitor formed on the first dielectric layer, a second dielectric layer covering the upper electrode of a storage capacitor and the thin film transistor, a plurality of openings formed in the second dielectric layer, and a pixel electrode formed on the second dielectric layer. Besides, the lower electrode of the storage capacitor is further divided into a first portion and a second portion, wherein the first portion and the second portion are separate, but are electrically connected with each other. | 2009-02-26 |
| 20090050890 | CONTACT STRUCTURE - There is disclosed a contact structure for electrically connecting conducting lines formed on a first substrate of an electrooptical device such as a liquid crystal display with conducting lines formed on a second substrate via conducting spacers while assuring a uniform cell gap among different cells if the interlayer dielectric film thickness is nonuniform across the cell or among different cells. A first conducting film and a dielectric film are deposited on the first substrate. Openings are formed in the dielectric film. A second conducting film covers the dielectric film left and the openings. The conducting spacers electrically connect the second conducting film over the first substrate with a third conducting film on the second substrate. The cell gap depends only on the size of the spacers, which maintain the cell gap. | 2009-02-26 |
| 20090050891 | PHOTODIODE AND DISPLAY DEVICE - Disclosed is a photodiode having a silicon film ( | 2009-02-26 |
| 20090050892 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region formed on the photodiode area at a first side of the gate electrode; a high-density second conductive the diffusion region formed on the transistor area at a second side of the gate electrode; an insulating layer formed on the semiconductor substrate at both sides of the gate electrode with a thickness less than a thickness of the gate electrode, but greater than a thickness of a gate insulating layer; and insulating layer sidewalls formed on the insulating layer at both sides of the gate electrode. | 2009-02-26 |
| 20090050893 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and crystallized using a metal catalyst, a gate insulating layer disposed on the semiconductor layer, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to source and drain regions of the semiconductor layer through contact holes exposing predetermined regions of the source and drain regions of the semiconductor layer formed within the gate insulating layer and the interlayer insulating layer. A metal silicide including a metal that is different from the metal catalyst is present within a region of the semiconductor layer under the contact hole from the surface of the semiconductor layer to a predetermined depth. | 2009-02-26 |
| 20090050894 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAING THE TFT, AND METHOD OF FABRICATING THE OLED DISPLAY DEVICE - A thin film transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate and including a channel region and source and drain regions, a gate electrode disposed in a position corresponding to the channel region of the semiconductor layer, a gate insulating layer interposed between the gate electrode and the semiconductor layer to electrically insulate the semiconductor layer from the gate electrode, a metal structure made up of metal layer, a metal silicide layer, or a double layer thereof disposed apart from the gate electrode over or under the semiconductor layer in a position corresponding to a region of the semiconductor layer other than a channel region, the structure being formed of the same material as the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer. | 2009-02-26 |
| 20090050895 | SEMICONDUCTOR MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS, AND DISPLAY UNIT - In a semiconductor manufacturing method that manufactures a coplanar type thin film transistor, a microcrystalline film | 2009-02-26 |
| 20090050896 | Display device - The present invention provides a display device which forms a drive circuit using a bottom-gate-type TFT made of poly-Si which generates a small leak current in a periphery of a display region. A gate electrode is made of Mo having a high melting point, and a gate insulation film is formed on the gate electrode. A channel layer constituted of a poly-Si layer is formed on the gate insulation film, and the poly-Si layer is covered with an a-Si layer. An n+ Si layer is formed on the a-Si layer, and an SD electrode is formed on the n+ Si layer. Although holes are induced in the poly-Si layer when a negative voltage (inverse bias) is applied to the gate electrode, the holes cannot pass through the a-Si layer and hence, no drain current flows. Accordingly, it is possible to realize a bottom-gate-type TFT using poly-silicon which generates a small leak current. | 2009-02-26 |
| 20090050897 | Substrate, method of polishing the same, and polishing apparatus - A polishing method and a polishing apparatus capable of polishing a surface of a substrate made of SiC or diamond extremely smoothly and efficiently without causing subsurface damage are provided. A polishing platen | 2009-02-26 |
| 20090050898 | Silicon carbide semiconductor device and method for producing the same - A silicon carbide semiconductor device ( | 2009-02-26 |
| 20090050899 | High-output diamond semiconductor element - The present invention relates to a high-output diamond semiconductor element, including a Schottky electrode as a cathode, a diamond P | 2009-02-26 |
| 20090050900 | FIELD-EFFECT TRANSISTOR - At least two drain ohmic contacts are arranged to intersect with an active area. A source ohmic contact is arranged between the drain ohmic contacts. A drain coupling portion on an element separating area couples ends of the drain ohmic contacts on the same side thereof. A gate power supply wiring on the element separating area couples gate fingers at the end thereof on the opposite side of the arrangement side of the drain coupling portion. A gate edge coupling portion couples two gate fingers adjacent to each other, sandwiching the source ohmic contact at the end thereof on the arrangement side of the drain coupling portion. The gate edge coupling portion does not intersect with the drain ohmic contact and the drain coupling portion. | 2009-02-26 |
| 20090050901 | GLASS-CERAMIC-BASED SEMICONDUCTOR-ON-INSULATOR STRUCTURES AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer. | 2009-02-26 |
| 20090050902 | SEMICONDUCTOR DEVICE HAVING SILICON CARBIDE AND CONDUCTIVE PATHWAY INTERFACE - The present invention provides semiconductor device formed by an in situ plasma reducing process to reduce oxides or other contaminants, using a compound of nitrogen and hydrogen, typically ammonia, at relatively low temperatures prior to depositing a subsequent layer thereon. The adhesion characteristics of the layers are improved and oxygen presence is reduced compared to the typical physical sputter cleaning process of an oxide layer. This process may be particularly useful for the complex requirements of a dual damascene structure, especially with copper applications. | 2009-02-26 |
| 20090050903 | Selective wet etching of gold-tin based solder - The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes. | 2009-02-26 |
| 20090050904 | LIGHT EMITTING DIODE CIRCUIT - A light emitting diode circuit includes a chip and a light emitting diode. The chip includes a current control unit that is used for controlling a driving current flowing through a path. The light emitting diode is positioned outside of the chip and is coupled to the path. The light emitting diode generates a light source according to the driving current. The light emitting diode circuit can directly control the current value of a driving current flowing through the light emitting diode. In this way, the circuit design is simplified and the production cost of the electronic product is reduced. | 2009-02-26 |
| 20090050905 | Highly Efficient Light-Emitting Diode - A high extraction efficiency light-emitting diode (LED) capable of producing a light beam of selected cross-section and selected spatial distribution of light in terms of intensity and angle is disclosed. The LED utilizes micro and/or nano optical elements in order to extract more light at one or more specified cone angles. | 2009-02-26 |
| 20090050906 | Photo Detector and a Display Panel having the Same - A photo detector has a sensing TFT (thin film transistor) and a photodiode. The sensing TFT has a gate and a base. The photodiode has an intrinsic semiconductor region electrically connected to the gate and the base of the sensing TFT. The sensing TFT and the photodiode both have a structure comprising low temperature poly-silicon. A display panel contains the photo detector is also disclosed. | 2009-02-26 |
| 20090050907 | Solid state lighting component - An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips. | 2009-02-26 |
| 20090050908 | Solid state lighting component - An LED component according to the present invention comprising an array of LED chips mounted on a submount with the LED chips capable of emitting light in response to an electrical signal. The array can comprise LED chips emitting at two colors of light wherein the LED component emits light comprising the combination of the two colors of light. A single lens is included over the array of LED chips. The LED chip array can emit light of greater than 800 lumens with a drive current of less than 150 milli-Amps. The LED chip component can also operate at temperatures less than 3000 degrees K. In one embodiment, the LED array is in a substantially circular pattern on the submount. | 2009-02-26 |
| 20090050909 | LIGHT-EMITTING DIODE APPARATUS AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) apparatus includes an epitaxial layer and an etching mask layer. The epitaxial layer has a first semiconductor layer, an active layer and a second semiconductor layer in sequence. The etching mask layer is disposed on the epitaxial layer and has a plurality of hollows. The second semiconductor layer includes a roughing structure. | 2009-02-26 |
| 20090050910 | FLAT PANEL BASED LIGHT EMITTING DIODE PACKAGE STRUCTURE - The present invention discloses a flat panel based light emitting diode (LED) package structure. The package structure comprises a substrate, a plurality of first LED chips, a plurality of second LED chips and a protective layer. The first LED chips and the second LED chips are located on the substrate, and the second LED chips surround the first LED chips. The protective layer is for covering the first LED chips and the second LED chips. The protective layer has a first sub-structure and a plurality of second sub-structures, wherein the first sub-structure corresponds to the first LED chips, and the second sub-structures correspond to the plurality of second LED chips. | 2009-02-26 |
| 20090050911 | Light emitting device packages using light scattering particles of different size - A radiation emitting device comprising light scattering particles of different sizes that at least partially surround an emitter, improving the spatial color mixing and color uniformity of the device. Multiple sizes of light scattering particles are dispersed in a medium to at least partially surround a single- or multiple-chip polychromatic emitter package. The different sizes of light scattering particles interact with corresponding wavelength ranges of emitted radiation. Thus, radiation emitted over multiple wavelength ranges or sub-ranges can be efficiently scattered to eliminate (or intentionally create) spatially non-uniform color patterns in the output beam. | 2009-02-26 |
| 20090050912 | LIGHT EMITTING DIODE AND OUTDOOR ILLUMINATION DEVICE HAVING THE SAME - A light emitting diode includes a first electrode, a second electrode, at least a first LED chip, at least a second LED chip, and an encapsulant. The second electrode has an opposite polarity with the first electrode and parallel with the first electrode. The first LED chip is electrically connected to the first electrode and the second electrode, for emitting first light of a first wavelength. The second LED chip is electrically connected to the first electrode and the second electrode, for emitting second light of a second wavelength being in a range from 570 nm to 670 nm. The encapsulant encapsulates the first and second LED chip therein, and has a phosphor material doped therein. The phosphor material is configured for emitting white light by excitation of the first light, and the second light is configured for adjusting a color temperature of the combined white light. | 2009-02-26 |
| 20090050913 | METHOD FOR ACHIEVING LOW DEFECT DENSITY ALGAN SINGLE CRYSTAL BOULES - A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth to achieve n-, i-, or p-type conductivity. In order to have growth cycles of sufficient duration, preferably an extended Ga source is used in which a portion of the Ga source is maintained at a relatively high temperature while most of the Ga source is maintained at a temperature close to, and just above, the melting temperature of Ga. To grow large boules of AlGaN, preferably multiple Al sources are used, the Al sources being sequentially activated to avoid Al source depletion and excessive degradation. In order to achieve high growth rates, preferably a dual growth zone reactor is used in which a first, high temperature zone is used for crystal nucleation and a second, low temperature zone is used for rapid crystal growth. Although the process can be used to grow crystals in which the as-grown material and the seed crystal are of different composition, preferably the two crystalline structures have the same composition, thus yielding improved crystal quality. | 2009-02-26 |
| 20090050914 | SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH SELECTIVELY FORMED BUFFER LAYER ON SUBSTRATE - The invention discloses a semiconductor light-emitting device and a method of fabricating the same. The semiconductor light-emitting device according to the invention includes a substrate, a buffer layer, a multi-layer structure, and an ohmic electrode structure. The buffer layer is selectively formed on an upper surface of the substrate such that the upper surface of the substrate is partially exposed. The multi-layer structure is formed to overlay the buffer layer and the exposed upper surface of the substrate. The multi-layer structure includes a light-emitting region. The buffer layer assists a bottom-most layer of the multi-layer structure in lateral and vertical epitaxial growth. The ohmic electrode structure is formed on the multi-layer structure. | 2009-02-26 |
| 20090050915 | Group III-V nitride semiconductor substrate and method for producing same - A group III-V nitride semiconductor substrate includes a first region of group III-V nitride semiconductor crystal grown on a facet on a heterosubstrate, and a second region of the group III-V nitride semiconductor crystal grown on a plane with a predetermined plane orientation on the heterosubstrate. The first region has an area ratio of not more than 10% to the second region in a plane of the substrate. A method for producing a group III-V nitride semiconductor substrate includes a first crystal growth step of supplying a source gas of a group III-V nitride semiconductor onto a heterosubstrate at a first partial pressure to grow the group III-V nitride semiconductor on a plane with a predetermined plane orientation and a facet on the heterosubstrate, and a second crystal growth step of supplying onto the heterosubstrate the source gas at a second partial pressure higher than the first partial pressure to grow the semiconductor on the plane with the predetermined plane orientation and the facet after the first crystal growth step is conduced for a predetermined time period so as to suppress a crystal growth of the semiconductor on the facet. | 2009-02-26 |
| 20090050916 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING APPARATUS - A semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode provided on the first semiconductor layer, a second electrode including a first metal film provided on the second semiconductor layer and containing at least one of silver and a silver alloy, and a second metal film provided on the first metal film and made of a metal substantially not containing silver, and a dielectric film spaced from the first metal film on the second semiconductor layer. The second metal film covers the first metal film, at least part of the dielectric film, and a surface of the second semiconductor layer exposed between the first metal film and the dielectric film. | 2009-02-26 |
| 20090050917 | Semiconductor light emitting device - A semiconductor light emitting device includes a substrate, and a light emitting portion that is disposed on the substrate, and includes an active layer formed of a group III nitride semiconductor using a nonpolar plane or a semipolar plane as a growth principal surface, in which side end surfaces of the active layer are specular surfaces. | 2009-02-26 |
| 20090050918 | Phosphor, its preparation method and light emitting devices using the same - A phosphor can be excited by UV, purple or blue light LED, its preparation method, and light emitting devices incorporating the same. The phosphor contains rare earth, silicon, alkaline-earth metal, halogen, and oxygen, as well as aluminum or gallium. Its General formula of is aLn | 2009-02-26 |
| 20090050919 | LIGHT EMITTING DIODE MODULE - The present invention relates to a light emitting diode (LED) module ( | 2009-02-26 |
| 20090050920 | CERAMIC WIRING BOARD AND PROCESS FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME - A ceramic wiring board | 2009-02-26 |
| 20090050921 | Light Emitting Diode Array - A one-dimensional array of light emitting diodes (LEDs) is configured to place the LEDs in close proximity to each other, e.g., 150 μm or less and to place at least one side of the LEDs in close proximity to the edge of the substrate, e.g., 150 μm or less. With the LEDs close to the edge of the substrate, multiple one-dimensional arrays may be joined together, side by side, to form a two-dimensional array with the LEDs from adjacent one-dimensional arrays positioned close together. By minimizing the gaps between the LEDs on the same one-dimensional arrays and adjacent one-dimensional arrays, the luminance of the device is improved making the device suitable for high radiance applications. Moreover, using a number of one-dimensional arrays to form a larger two-dimensional array increases yield relative to conventional monolithic two-dimensional arrays. | 2009-02-26 |
| 20090050922 | Front and rear covering type LED package structure and method for packaging the same - A front and rear covering type LED package structure includes an insulating body, a substrate unit, at least one light-emitting element, and a package colloid. The insulating body has a receiving space. The substrate unit has two electrode pins separated from each other. Each electrode pin has one side covered by the insulating body. Each electrode pin has another side bent into a U-shape and exposed outside the insulating body in order to cover two opposite lateral sides and front and rear sides of the insulating body by a front and rear covering method. The at least one light-emitting element is received in the receiving space and electrically connected with the two electrode pins of the substrate unit. The package colloid is filled into the receiving space of the insulating body. | 2009-02-26 |
| 20090050923 | LIGHT EMITTING DIODE PACKAGE - Provided is an LED package including a printed circuit board (PCB); a conductive structure that is formed on the PCB and is composed of any one selected from a silicon structure and an aluminum structure; and an LED chip that is mounted on the PCB and is electrically connected to the PCB through the conductive structure. | 2009-02-26 |
| 20090050924 | DROOP-FREE HIGH OUTPUT LIGHT EMITTING DEVICES AND METHODS OF FABRICATING AND OPERATING SAME - Light emitting devices include a semiconductor light emitting diode that is configured to operate at a substantially droop-free quantum efficiency while producing warm white light output of at least about 100 lumens/cool white light output of at least about 130 lumens. The semiconductor light emitting diode may include a single semiconductor die of at least about 4 mm | 2009-02-26 |
| 20090050925 | RESIN MOLDING, SURFACE MOUNTED LIGHT EMITTING APPARATUS AND METHODS FOR MANUFACTURING THE SAME - The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus. | 2009-02-26 |
| 20090050926 | Light emitting device - A light emitting device includes a light emitting element, an element mounting board including a wiring layer on an element mounting surface thereof, and a sealing portion that seals the light emitting element. The light emitting element includes a contact electrode including a transparent conductive film, a transparent dielectric layer formed on a surface of the contact electrode and including a refractive index lower than the contact electrode, and a pad electrode electrically connected to the contact electrode. The light emitting element is flip-chip mounted on the wiring layer. A part of the transparent dielectric layer is formed between the contact electrode and the pad electrode. | 2009-02-26 |
| 20090050927 | METHOD OF FABRICATION InGaAlN FILM AND LIGHT-EMITTING DEVICE ON A SILICON SUBSTRATE - There is provided a method of fabricating InGaAlN film on a silicon substrate, which comprises the following steps of forming a pattern structured having grooves and mesas on the silicon substrate, and depositing InGaAlN film on the surface of substrate, wherein the depth of the grooves is more than 6 nm, and the InGaAlN film formed on the mesas of both sides of the grooves are disconnected in the horizontal direction. The method may grow high quality, no crack and large area of InGaAlN film by simply treating the substrate. At the same time, there is also provided a method of fabricating InGaAlN light-emitting device by using the silicon substrate. | 2009-02-26 |
| 20090050928 | Zinc-blende nitride semiconductor free-standing substrate, method for fabricating same, and light-emitting device employing same - A zinc-blende nitride semiconductor free-standing substrate has a front surface and a back surface opposite the front surface. The distance between the front and back surfaces is not less than 200 μm. The area ratio of the zinc-blende nitride semiconductor to the front surface is not less than 95%. | 2009-02-26 |
| 20090050929 | SEMICONDUCTOR SUBSTRATE WITH NITRIDE-BASED BUFFER LAYER FOR EPITAXY OF SEMICONDUCTOR OPTO-ELECTRONIC DEVICE AND FABRICATION THEREOF - The invention discloses a semiconductor substrate for epitaxy of a semiconductor optoelectronic device and the fabrication thereof. The semiconductor substrate according to the invention includes a substrate, and a nitride-based buffer layer. The buffer layer is formed by an atomic layer deposition process and/or a plasma-enhanced (or a plasma-assisted) atomic layer deposition process on an upper surface of the substrate. The nitride-based buffer layer assists the epitaxial growth of a semiconductor material layer of the semiconductor optoelectronic device. | 2009-02-26 |
| 20090050930 | Light-emitting device and the manufacturing method thereof - This invention provides an optoelectronic semiconductor device having a rough surface and the manufacturing method thereof. The optoelectronic semiconductor device comprises a semiconductor stack having a rough surface and an electrode layer overlaying the semiconductor stack. The rough surface comprises a first region having a first topography and a second region having a second topography. The method comprises the steps of forming a semiconductor stack on a substrate, forming an electrode layer on the semiconductor stack, thermal treating the semiconductor stack, and wet etching the surface of the semiconductor stack to form a rough surface. | 2009-02-26 |
| 20090050931 | SWITCHING ASSEMBLY FOR AN AIRCRAFT IGNITION SYSTEM - A switching assembly is disclosed for a high voltage aircraft ignition system. The switching assembly includes a ceramic substrate and switch die that includes an anode bonded to an electrical pad on the ceramic substrate. The switch die includes a semiconductor device having a plurality of interleaved gates and cathodes, and includes a ceramic cap having at least one gate pad connected to the gates and at least one cathode pad connected to the cathodes. The switching assembly includes leads connected to the gate pad, the cathode pad, and the electrical pad on the substrate. The switch die and a portion of the leads are potted to form the completed assembly. | 2009-02-26 |
| 20090050932 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region | 2009-02-26 |
| 20090050933 | SEMICONDUCTOR LIGHT-RECEIVING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor light-receiving device having high reproducibility and reliability. Also disclosed is a method for manufacturing a semiconductor light-receiving device. Specifically disclosed is a semiconductor light-receiving device | 2009-02-26 |
| 20090050934 | MICROCHANNEL AVALANCHE PHOTODIODE (VARIANTS) - The invention—microchannel avalanche diode, belongs to semiconductor photosensitive devices, and specifically to semiconductor avalanche diodes with internal amplification of the signal. The proposed microchannel avalanche diode can be used for registration of super feeble light pulses, including up to individual photons, and also gamma quants and charged particles in devices for medical gamma tomography, radiation monitoring, and nuclear physics experiments. | 2009-02-26 |
| 20090050935 | Silicon-Germanium Hydrides and Methods for Making and Using Same - The present invention provides silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the compounds. The compounds are defined by formula: SiHnI (GeHn2)y, wherein y is 2, 3, or 4 wherein n | 2009-02-26 |
| 20090050936 | NITRIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER INCLUDING THE SAME - A nitride semiconductor device includes a RESURF layer containing p-type In | 2009-02-26 |
| 20090050937 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region. | 2009-02-26 |
| 20090050938 | MIS GATE STRUCTURE TYPE HEMT DEVICE AND METHOD OF FABRICATING MIS GATE STRUCTURE TYPE HEMT DEVICE - A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate and between a gate and a source is sufficiently lowered, and at the same time, a P-type region is formed immediately under the gate. This realizes a normally-off type HEMT device having a low on-resistance. Further, when a film thickness of an insulating layer is defined as t (nm) and a relative permittivity of a substance forming the insulating layer is defined as k, a threshold voltage as high as +3 V or more can be attained by satisfying k/t≦0.85 (nm | 2009-02-26 |
| 20090050939 | III-NITRIDE DEVICE - A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body. | 2009-02-26 |
| 20090050940 | SEMICONDUCTOR DEVICE - The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer. | 2009-02-26 |
| 20090050941 | Semiconductor device - A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer. | 2009-02-26 |
| 20090050942 | SELF-ALIGNED SUPER STRESSED PFET - The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth. | 2009-02-26 |
| 20090050943 | IMAGERS, APPARATUSES AND SYSTEMS UTILIZING PIXELS WITH IMPROVED OPTICAL RESOLUTION AND METHODS OF OPERATING THE SAME - A pixel array resolution is doubled by adding a plurality of second photodiodes, but only a single, common transfer control line. By controlling a combination of the single, common transfer control line and a transfer control line unique to controlling first transfer transistors in pixels in a row, first and second photodiodes in a pixel can be separately readout. | 2009-02-26 |
| 20090050944 | CMOS image sensor and method of fabrication - A CMOS imaging device including a two pixel detection system for red, green, and blue light. One pixel detects red and blue light and another pixel detects green light. The detection of red and blue is based on wavelength and the device is structured such that in the red/blue pixel, detection of blue light is at a shallow substrate depth, while detection of red is at a deeper substrate depth. The pixel array is structured such that the red/blue pixel is adjacent to the green pixel and alternates between red/blue and green pixels. The invention is also related to methods of forming such an imager array and pixels. | 2009-02-26 |
| 20090050945 | SOLID-STATE IMAGE SENSING DEVICE - A solid-state image sensing device has a pixel that includes a photodiode that generates an electrical charge according to an amount of incoming light, a floating diffusion portion, a charge transfer transistor that transfers the electrical charge to the floating diffusion portion from the photoelectric conversion portion, a reading circuit that outputs an signal on the basis of said electrical charge held in said floating diffusion portion, and a light-shielding member disposed so as to cover a side wall of a gate electrode of the charge transfer transistor on the photoelectric conversion portion side. | 2009-02-26 |
| 20090050946 | CAMERA MODULE, ARRAY BASED THEREON, AND METHOD FOR THE PRODUCTION THEREOF - The invention relates to the development of economical camera modules having objectives contained therein with a minimal constructional length and excellent optical properties. It is made possible as a result that camera modules of this type can be used in mobile telephones or minicomputers, such as PDAs (personal digital assistant). | 2009-02-26 |
| 20090050947 | Apparatus, system, and method providing backside illuminated imaging device - Method, apparatus, and/or system providing a backside illuminated imaging device. A non-planar metallic or otherwise reflective layer is provided in an image pixel cell at the frontside of the device substrate to capture radiation passing through the device substrate. The non-planar surface is formed to be capable of reflecting substantially all such radiation back to a photosensor located in the same pixel cell. | 2009-02-26 |
| 20090050948 | SPIN MOS FIELD EFFECT TRANSISTOR AND TUNNELING MAGNETORESISTIVE EFFECT ELEMENT USING STACK HAVING HEUSLER ALLOY - A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer. | 2009-02-26 |
| 20090050949 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - The present invention is to provide a semiconductor memory device capable of providing excellent storage properties, scaling and high integration and a method of fabricating the same. A semiconductor memory device has a multiferroic film exhibiting ferroelectricity and ferromagnetism, a channel region on an interface of a semiconductor substrate below the multiferroic film, source and drain regions formed on both sides of the channel region, a gate electrode (data write electrode) applying gate voltage to the multiferroic film to write data in such a way that the orientation of magnetization is changed as corresponding to the orientation of dielectric polarization, and source and drain electrodes (data read electrodes) that read data based on a deviation in a flow of the carrier, the deviation caused by applying the Lorentz force to the carrier flowing in the channel region from a magnetic field occurring in the channel region because of magnetization. | 2009-02-26 |
| 20090050950 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first MOS type capacitor having a first insulating film and a first electrode that are formed on a semiconductor substrate, and a second MOS type capacitor having a second insulating film and a second electrode that are formed on the semiconductor substrate. The first electrode has a first concentration difference as a difference when an impurity concentration in an interface region with the first insulating film is subtracted from an impurity concentration in a top portion of the first electrode. The second electrode has a second concentration difference as a difference when an impurity concentration in an interface region with the second insulating film is subtracted from an impurity concentration in a top portion of the second electrode. The second concentration difference is larger than the first concentration difference. | 2009-02-26 |
| 20090050951 | Semiconductor Device and Method of Manufacturing the Same - A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching. | 2009-02-26 |
| 20090050952 | FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer. | 2009-02-26 |
| 20090050953 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile memory device including a substrate, an insulating layer, a charge storage layer, a multi-layer tunneling dielectric structure and a gate is provided. The substrate has a channel region. The insulating layer is disposed on the channel region. The charge storage layer is disposed on the insulating layer. The multi-layer tunneling dielectric structure is disposed on the charge storage layer. The gate is disposed on the multi-layer tunneling dielectric structure and the charge carriers are injected from the gate. | 2009-02-26 |
| 20090050954 | Non-volatile memory device including charge trap layer and method of manufacturing the same - Provided are a non-volatile memory device and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes a charge trap layer having a crystalline material. In the method, a tunneling insulating layer is formed on a substrate, and a crystalline charge trap layer is formed on the tunneling insulating layer. | 2009-02-26 |
| 20090050955 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced. | 2009-02-26 |
| 20090050956 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer. | 2009-02-26 |
| 20090050957 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device 1 has a metallic base substrate | 2009-02-26 |
| 20090050958 | SEMICONDUCTOR DEVICE HAVING A SPACER LAYER DOPED WITH SLOWER DIFFUSING ATOMS THAN SUBSTRATE - A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the spacer layer. | 2009-02-26 |
| 20090050959 | Method and Structure for Shielded Gate Trench FET - A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric. | 2009-02-26 |
| 20090050960 | Stacked Trench Metal-Oxide-Semiconductor Field Effect Transistor Device - Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET | 2009-02-26 |
| 20090050961 | Semiconductor Device - A semiconductor device is disclosed which has a shorter turn-on time. The semiconductor device includes an epitaxial layer, two base regions embedded in a surface portion of the epitaxial layer, source regions respectively embedded in the base regions, a drain region including at least a portion of the epitaxial layer excluding the base regions, and a gate electrode provided on the epitaxial layer with the intervention of an insulation film with ends thereof respectively opposed to surfaces of the two base regions. The drain region is arranged so that depletion layers respectively extending from boundaries between the drain region and the two base regions are connected to each other in an OFF state in a portion of the drain region located between the two base regions. | 2009-02-26 |
| 20090050962 | MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF - A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors. | 2009-02-26 |
| 20090050963 | STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION - Stressed MOS devices and methods for their fabrication are provided. The stressed MOS device comprises a T-shaped gate electrode formed of a material having a first Young's modulus. The T-shaped gate electrode includes a first vertical portion and a second horizontal portion. The vertical portion overlies a channel region in an underlying substrate and has a first width; the horizontal portion has a second greater width. A tensile stressed film is formed overlying the second horizontal portion, and a material having a second Young's modulus less than the first Young's modulus fills the space below the second horizontal portion. The tensile stressed film imparts a stress on the horizontal portion of the gate electrode and this stress is transmitted through the vertical portion to the channel of the device. The stress imparted to the channel is amplified by the ratio of the second width to the first width. | 2009-02-26 |
| 20090050964 | METHOD FOR MANUFACTURING THIN FILM INTEGRATED CIRCUIT, AND ELEMENT SUBSTRATE - Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time. | 2009-02-26 |
| 20090050965 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an epitaxial crystal layer containing a conductive impurity, which is formed sandwiching the channel region and has a function as a source region and a drain region, and formed on a recess in the semiconductor substrate; and a growth suppressing portion formed on the recess in the semiconductor substrate, and configured to suppress an epitaxial growth of a crystal in the epitaxial layer from the semiconductor substrate. | 2009-02-26 |
| 20090050966 | SEMICONDUCTOR DEVICE - In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection. | 2009-02-26 |
| 20090050967 | SEMICONDUCTOR DEVICE - In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection. | 2009-02-26 |
| 20090050968 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger. | 2009-02-26 |
| 20090050969 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element. | 2009-02-26 |
| 20090050970 | Diode-Based ESD Concept for DEMOS Protection - The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails. | 2009-02-26 |
| 20090050971 | High voltage durability transistor and method for fabricating same - According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness. | 2009-02-26 |
| 20090050972 | Strained Semiconductor Device and Method of Making Same - A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner. | 2009-02-26 |
| 20090050973 | INTEGRATED CIRCUIT INCLUDING A FIRST CHANNEL AND A SECOND CHANNEL - An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width. | 2009-02-26 |
| 20090050974 | Method, System and Apparatus for Gating Configurations and Improved Contacts in Nanowire-Based Electronic Devices - Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core. | 2009-02-26 |
| 20090050975 | Active Silicon Interconnect in Merged Finfet Process - Dummy fins are positioned between source and drain regions of adjacent complementary multi-gate fin-type field effect transistors (MUGFETS) prior to selective silicon growth and silicidation. The dummy fins are parallel to, have the same thickness as, and have a smaller length than the fins within the MUGFETs. Further, the source regions of a first MUGFET, the drain regions of a second MUGFET, and the dummy fins are positioned along a single straight linear path, such that the single straight linear path crosses all of the source regions of the first MUGFET, the drain regions of the second MUGFET, and the dummy fins. Because the dummy fins comprise silicon, the dummy fins enhance the ability to selectively grow silicon within the source/drain connection silicide region. Then, after the source/drain connection silicide region is silicided, a consistently formed and reliable electrical connection is made between the source regions of one transistor and the drain regions of the other transistor to properly connect a CMOS structure. | 2009-02-26 |
| 20090050976 | PROCESS METHOD TO FULLY SALICIDE (FUSI) BOTH N-POLY AND P-POLY ON A CMOS FLOW - An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over the NMOS devices. The method further comprises concurrently forming a second silicide in at least a top portion of a gate electrode of both the NMOS and PMOS devices, and forming a FUSI gate silicide of the gate electrodes. In one embodiment, the thickness of the second silicide is greater than the first silicide by an amount which compensates for a difference in the rates of silicide formation between the NMOS and PMOS devices. | 2009-02-26 |
