08th week of 2016 patent applcation highlights part 54 |
Patent application number | Title | Published |
20160056150 | POWER SEMICONDUCTOR ELEMENT - A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor. | 2016-02-25 |
20160056151 | POWER SEMICONDUCTOR DEVICE WITH OVER-CURRENT PROTECTION - A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current. | 2016-02-25 |
20160056152 | MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE - One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening. | 2016-02-25 |
20160056153 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width. | 2016-02-25 |
20160056154 | SEMICONDUCTOR DEVICE - The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation. | 2016-02-25 |
20160056155 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact. | 2016-02-25 |
20160056156 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME - Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins. | 2016-02-25 |
20160056157 | Tuning Tensile Strain on FinFET - A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. | 2016-02-25 |
20160056158 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer. | 2016-02-25 |
20160056159 | SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS OVERLAPPING ASSOCIATED BITLINE STRUCTURES AND CONTACT HOLES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another. | 2016-02-25 |
20160056160 | SEMICONDUCTOR DEVICE HAVING PASSING GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region. | 2016-02-25 |
20160056161 | MEMORY DEVICE - A memory device including a substrate including a plurality of unit cell regions; a plurality of active regions on the substrate; and a plurality of gate electrodes on the substrate and extending in a first direction and intersecting at least one of the plurality of active regions, the plurality of active regions being adjacent to a boundary between the plurality of unit cell regions, and being separated from each other within the plurality of unit cell regions along a second direction orthogonal to the first direction. | 2016-02-25 |
20160056162 | CMOS-COMPATIBLE POLYCIDE FUSE STRUCTURE AND METHOD OF FABRICATING SAME - CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode. | 2016-02-25 |
20160056163 | NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE - There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices. | 2016-02-25 |
20160056164 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor substrate; a first gate insulating film; a floating gate electrode; a second gate insulating film; and a control gate electrode. The first gate insulating film is formed on the semiconductor substrate. The floating gate electrode is formed arranged in a first direction on the first gate insulating film. The second gate insulating film is formed on an upper surface and a side surface of the floating gate electrode. The control gate electrode is formed extending in the first direction and facing the upper surface and the side surface of the floating gate electrode via the second gate insulating film. In addition, the floating gate electrode includes boron. Moreover, a concentration of boron in the floating gate electrode is higher with being further from the semiconductor substrate. | 2016-02-25 |
20160056165 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes alternately forming plural first insulators and plural first films on a substrate, and etching the first insulators and the first films to form a contact region having first to N-th upper faces whose heights are mutually different where N is an integer of two or more. The method further includes forming a second insulator containing boron or hafnium on the first to N-th upper faces, forming a third insulator on the second insulator, and forming plural electrode layers between the plural first insulators. The method further includes etching the second and third insulators to form first to N-th contact holes respectively reaching the electrode layers under the first to N-th upper faces, and forming first to N-th contact plugs in the first to N-th contact holes respectively. | 2016-02-25 |
20160056166 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to n | 2016-02-25 |
20160056167 | TUNGSTEN SEPARATION - Methods of selectively etching tungsten from the surface of a patterned substrate are described. The etch electrically separates vertically arranged tungsten slabs from one another as needed, for example, in the manufacture of vertical flash memory devices. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a capacitively-excited chamber plasma region. The methods then include exposing the tungsten slabs to remotely-excited fluorine formed in an inductively-excited remote plasma system. A low electron temperature is maintained in the substrate processing region during each operation to achieve high etch selectivity. | 2016-02-25 |
20160056168 | 3D NAND NONVOLATILE MEMORY WITH STAGGERED VERTICAL GATES - A memory device includes a plurality of stacks of conductive strips, a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, a plurality of vertical gate columns, and control circuitry. The plurality of word lines is electrically coupled to the plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips. The plurality of word lines including a first word line and a second word line adjacent to each other. The plurality of vertical gate columns is between the plurality of stacks of conductive strips. The plurality of vertical gate columns includes a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line. The first set of vertical gate columns is staggered relative to the second set of vertical gate columns. The control circuitry controls the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips, and controls nonvolatile memory operations. | 2016-02-25 |
20160056169 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING EPITAXIAL LAYER - According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate. | 2016-02-25 |
20160056170 | METHOD OF FABRICATING FLASH MEMORY DEVICE - A method of fabricating a flash memory device includes sequentially forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes an upper sacrificial pad portion and an upper sacrificial line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as an etch mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. Finally, a lower mask pattern including at least one line mask, at least one bridge mask, and at least one pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure. | 2016-02-25 |
20160056171 | INTEGRATED CIRCUIT DEVICE INCLUDING POLYCRYSTALLINE SEMICONDUCTOR FILM AND METHOD OF MANUFACTURING THE SAME - An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device. | 2016-02-25 |
20160056172 | VERTICALLY-INTEGRATED NONVOLATILE MEMORY DEVICES HAVING LATERALLY-INTEGRATED GROUND SELECT TRANSISTORS - Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines. | 2016-02-25 |
20160056173 | SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NAND CIRCUIT - A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit. | 2016-02-25 |
20160056174 | SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NOR CIRCUIT - A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit. | 2016-02-25 |
20160056175 | Circuit Structures, Memory Circuitry, and Methods - A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed. | 2016-02-25 |
20160056176 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display including the array substrate, the array substrate includes a substrate ( | 2016-02-25 |
20160056177 | Array Substrate, Manufacturing Method Thereof and Display Device - The present invention provides array substrate, manufacturing method thereof, and display device, relating to manufacturing technology field of liquid crystal display. The array substrate of the present invention includes: a base substrate, on which a plurality of gate lines and a plurality of data lines are provided; shielding electrodes, which are provided above and electrically insulated from the data lines, and the shielding electrodes at least partially cover the data lines; first electrodes, which are provided in the same layer as the shielding electrodes and are electrically insulated from the shielding electrodes; second electrodes, which are provided above and electrically insulated from the first electrodes, wherein, the shielding electrodes are applied with a shielding voltage signal, the second electrodes are applied with a stable voltage signal, and no electric field or weak electric filed is formed between the shielding electrodes and the second electrodes. | 2016-02-25 |
20160056178 | Array Substrate and Method for Fabricating the Same, and Display Panel - The embodiments of the present invention provide an array substrate, a method for fabricating the array substrate and a display panel. The array substrate comprises a first region and a second region adjoining the first region, a plurality of signal lines are provided in the first region, and a plurality of lead wires connected with the plurality of signal lines are provided in the second region, the array substrate comprises at least one conductive member, each conductive member is connected in parallel with one lead wire, and an overall resistance of the conductive member and the lead wire connected in parallel with the conductive member is smaller than a resistance of the lead wire connected in parallel with the conductive member. | 2016-02-25 |
20160056179 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A semiconductor device includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor. The third layer includes a second transistor. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The second layer includes a first insulating film, a second insulating film, and a conductive film. The conductive film has a function of electrically connecting the first transistor and the second transistor. The first insulating film is over and in contact with the conductive film. The second insulating film is provided over the first insulating film. The second insulating film includes a region with a carbon concentration of greater than or equal to 1.77×10 | 2016-02-25 |
20160056180 | HETEROGENEOUS SEMICONDUCTOR MATERIAL INTEGRATION TECHNIQUES - Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands. | 2016-02-25 |
20160056181 | METHODS OF FORMING FIELD EFFECT TRANSISTORS USING A GATE CUT PROCESS FOLLOWING FINAL GATE FORMATION - Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs. | 2016-02-25 |
20160056182 | ARRAY SUBSTRATE OF DISPLAY PANEL - An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region. | 2016-02-25 |
20160056183 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device and a manufacturing method thereof are provided, and the display device includes an array substrate, an opposite substrate and sealant frames between the array substrate and the opposite substrate, with a pre-cutting position disposed between two adjacent the sealant frames. The display device further includes a barrier layer between the array substrate and the opposite substrate and at a position corresponding to the above-mentioned pre-cutting position, and a material forming the barrier layer has an elongation at fracture smaller than that of a material forming the sealant frames. The display device can solve the problem of a large quantity of burrs caused by the sealant frames during the cutting process of a display screen under the precondition of reducing production costs. | 2016-02-25 |
20160056184 | THIN FILM TRANSISTOR, DISPLAY, AND METHOD FOR FABRICATING THE SAME - A thin film transistor (TFT) device is provided. The TFT device includes a first conductive layer including a gate electrode and a connection pad. The TFT device further includes a first dielectric layer covering the gate electrode, and a semiconductor layer disposed on the dielectric layer and overlapping the gate electrode. The TFT device further includes a second dielectric layer disposed on the semiconductor layer and the first dielectric layer so as to expose first and second portions of the semiconductor layer and the connection pad. The TFT device further includes a second conductive layer which includes a source electrode portion covering the first portion of the semiconductor layer; a pixel electrode portion extending to the source electrode portion; a drain electrode portion covering the second portion of the semiconductor layer; and an interconnection portion disposed on the connection pad and extending to the drain electrode portion. | 2016-02-25 |
20160056185 | SINGLE-PHOTON AVALANCHE DIODE AND AN ARRAY THEREOF - A Single-Photon Avalanche Diode (SPAD) is disclosed. The SPAD may include an active region for detection of incident radiation, and a cover configured to shield part of the active region from the incident radiation. An array is also disclosed and includes SPADs arranged in rows and columns. A method for making the SPAD is also disclosed. | 2016-02-25 |
20160056186 | PHOTO SENSOR MODULE - The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer. | 2016-02-25 |
20160056187 | IMAGING DEVICES WITH DUMMY PATTERNS - An imaging device is provided. The imaging device includes a plurality of photoelectric conversion elements fromed on a substrate in an active area. A microlens structure is disposed above the photoelectric conversion elements. A dummy pattern having a plurality of protruding elements is disposed above the substrate in a peripheral area surrounding the active area. Furthermore, a passivation film is conformally formed on the microlens structure and the dummy pattern. The passivation film on the tops of the protruding elements of the dummy pattern has a surface area smaller than a surface area of the peripheral area outside of the microlens structure. | 2016-02-25 |
20160056188 | IMAGE SENSOR HAVING SHIELDING STRUCTURE - An image sensor is provided. The image sensor includes a substrate, a first interlayer insulating layer, a first metal line, and a shielding structure. The substrate includes a pixel array, a peripheral circuit area, and an interface area disposed between the pixel array and the peripheral circuit area. The first interlayer insulating layer is formed on a first surface of the substrate. The first metal line is disposed on the first interlayer insulating layer of the pixel array. The second interlayer insulating layer is disposed on the first interlayer insulating layer wherein the second interlayer insulating layer covers the first metal line. The shielding structure passes through the substrate in the interface area wherein the shielding structure electrically insulates the pixel array of the substrate and the peripheral circuit area. | 2016-02-25 |
20160056189 | SOLID-STATE IMAGING APPARATUS AND MANUFACTURING METHOD OF SOLID-STATE IMAGING APPARATUS - The first face of the pad is situated between the front-side face of the second semiconductor substrate and a hypothetical plane including and being parallel to the front-side face, and a second face of the pad that is a face on the opposite side of the first face is situated between the first face and the front-side face of the second semiconductor substrate, and wherein the second face is connected to the wiring structure so that the pad is electrically connected to the circuit arranged in the front-side face of the second semiconductor substrate via the wiring structure. | 2016-02-25 |
20160056190 | SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, AND METHOD OF DRIVING THE SOLID-STATE IMAGING DEVICE - A solid-state imaging device including a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to form a light receiving unit; a peripheral circuit formed in a portion on an outside of the light receiving unit on the semiconductor substrate; a wiring section formed on the light receiving unit and formed for connecting the plural photoelectric conversion units and the peripheral circuit; and a dummy wiring section formed on an opposite side of the wiring section for at least one photoelectric conversion unit among the plural photoelectric conversion units on the light receiving unit and formed for functioning as a non-connected wiring section not connected to the photoelectric conversion units and the peripheral circuit, wherein the dummy wiring section has a predetermined potential. | 2016-02-25 |
20160056191 | IMAGE SENSOR AND METHOD FOR FORMING THE SAME - An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer. | 2016-02-25 |
20160056192 | VERTICAL GATE TRANSISTOR AND PIXEL STRUCTURE COMPRISING SUCH A TRANSISTOR - The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region. | 2016-02-25 |
20160056193 | IMAGE SENSING DEVICE AND METHOD FOR FABRICATING THE SAME - An image sensing device includes: an active layer with a plurality of photo-sensing elements; a color pattern disposed over one of the photo-sensing elements, wherein the color pattern has a color selected from the group consisting of red (R), green (G), and blue (B); a microlens disposed on the color pattern; and a transmissive pattern being adjacent to the color pattern and over another one of the photo-sensing elements, wherein the transmissive pattern includes a color filter portion and a microlens portion, and an absolute value of a difference of refractive indexes between the microlens and the color pattern is less than 0.3, and there is no difference of refractive indexes between the microlens portion and the color filter portion of the transmissive pattern. | 2016-02-25 |
20160056194 | OPTOELECTRONIC MODULES HAVING A SILICON SUBSTRATE, AND FABRICATION METHODS FOR SUCH MODULES - Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described. | 2016-02-25 |
20160056195 | IMAGE SENSOR AND ELECTRONIC DEVICE HAVING THE SAME - An image sensor may include: a substrate including a substrate comprising a photoelectric conversion element; a pixel lens formed over the substrate and comprising a plurality of light condensing layers in which a lower layer has a larger area than an upper layer; a color filter layer covering the pixel lens; and an anti-reflection structure formed over the color filter layer. | 2016-02-25 |
20160056196 | CONDUCTION LAYER FOR STACKED CIS CHARGING PREVENTION - A semiconductor device includes a first semiconductor chip comprising a first metallic structure and a second semiconductor chip comprising a second metallic structure. The second semiconductor chip is bonded with the first semiconductor chip by a first conductive plug. A second conductive plug extends from the first metallic structure and into a substrate of the first semiconductor chip. The first conductive plug connects the first metallic structure and the second metallic structure, wherein a conductive liner is along a sidewall of the first conductive plug or the second conductive plug. | 2016-02-25 |
20160056197 | Image Sensor Devices and Design and Manufacturing Methods Thereof - Image sensor devices, design methods thereof, and manufacturing methods thereof are disclosed. In some embodiments, a design method for an image sensor device includes providing an initial design for an image sensor device. The initial design includes a pixel array region and a through-via region disposed proximate the pixel array region. The initial design has a first length between the pixel array region and the through-via region. The initial design has a second length that is a width of the through-via region. The design method includes analyzing a ratio of the second length and the first length, and modifying the initial design to achieve an optimal ratio of the second length and the first length. | 2016-02-25 |
20160056198 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSORS - A complementary metal-oxide-semiconductor (CMOS) image sensor is provided. The CMOS image sensor may include an epitaxial layer having a first conductivity type and having first and second surfaces, a first device isolation layer extending from the first surface to the second surface to define first and second pixel regions, a well impurity layer of a second conductivity type formed adjacent to the first surface and formed in the epitaxial layer of each of the first and second pixel regions, and a second device isolation layer formed in the well impurity layer in each of the first and second pixel regions to define first and second active portions spaced apart from each other in each of the first and second pixel regions. | 2016-02-25 |
20160056199 | UNIT PIXELS, IMAGE SENSORS INCLUDING THE SAME, AND IMAGE PROCESSING SYSTEMS INCLUDING THE SAME - A unit pixel of an image sensor which operates in global shutter mode is provided. The unit pixel includes a photo diode area including a photo diode configured to accumulate photocharges generated from incident light during a first period and a storage diode area including a storage diode configured to receive and store the photocharges from the photo diode. The photo diode corresponds to a micro lens that focuses the incident light. | 2016-02-25 |
20160056200 | Unit Pixels for Image Sensors and Pixel Arrays Comprising the Same - Provided are unit pixels for image sensors and pixel arrays including the same. The unit pixels include a first pixel including first and second photo diodes which are adjacent to each other, and a first deep trench isolation (DTI) fully surrounding sides of the first and second photo diodes and electrically separating the first pixel from other pixels adjacent to the first pixel. The first pixel includes a second DTI positioned between the first photo diode and the second photo diode and having one side formed to be spaced apart from the first DTI. The first pixel also includes a color filter positioned on the first and second photo diodes and fully overlapping the first and second photo diodes. The first pixel further includes a floating diffusion node electrically connected with the first and second photo diodes. The first and second photo diodes share one floating diffusion node. | 2016-02-25 |
20160056201 | PIXEL WITH MULTIGATE STRUCTURE FOR CHARGE STORAGE OR CHARGE TRANSFER - This disclosure provides an integrated circuit (IC) including one or more pixels. A photodiode is arranged in a semiconductor substrate and includes an n-type region near an upper surface of the substrate and a p-type region under the n-type region. A semiconductor fin is arranged over the photodiode and is electrically coupled to the n-type region of the photodiode. The semiconductor fin includes a transfer transistor and a separate charge storage or charge transfer region, wherein the charge storage or charge transfer region is adapted to store or transfer charge generated by the photodiode in response to impingent light. | 2016-02-25 |
20160056202 | Isolation for Semiconductor Devices - A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material. | 2016-02-25 |
20160056203 | PIXEL ARRAY AND DISPLAY DEVICE - A pixel array and a display device are provided. The pixel array includes a two-dimensional array that is formed by arranging a plurality of color sub-pixels and a plurality of white sub-pixels in the row direction and in the column direction, the color sub-pixels include color sub-pixels in three different colors. For color sub-pixels in each color in each row, color sub-pixels with the same color in the same row are arranged so that, the odd-numbered column sub-pixel and the even-numbered column sub-pixel alternate one by one, or they are disposed by way of groups each including two odd-numbered column sub-pixels alternating with even-numbered column sub-pixels or by way of groups each including two even-numbered column sub-pixels alternating with odd-numbered column sub-pixels. | 2016-02-25 |
20160056204 | ACTIVE MATRIX DISPLAY PANEL WITH GROUND TIE LINES - A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. A ground line is located in the non-pixel area and an array of ground tie lines run between the bank openings in the pixel area and are electrically connected to the ground line in the non-pixel area. | 2016-02-25 |
20160056205 | MAGNETIC MEMORY, MAGNETIC MEMORY DEVICE, AND METHOD FOR MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a magnetic memory including a first magnetic unit, a first nonmagnetic unit, a first fixed magnetic unit, a second fixed magnetic unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit extends in a first direction. The first magnetic unit includes a plurality of magnetic domains arranged in the first direction. The first nonmagnetic unit contacts one end of the first magnetic unit. The first fixed magnetic unit is separated from the first magnetic unit. The first fixed magnetic unit contacts the first nonmagnetic unit. The second fixed magnetic unit is separated from the first magnetic unit and the first fixed magnetic unit. The second fixed magnetic unit is in contact with the first nonmagnetic unit. The second fixed magnetic unit is magnetized in a direction different from a magnetization direction of the first fixed magnetic unit. | 2016-02-25 |
20160056206 | 3-D PLANES MEMORY DEVICE - The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors). | 2016-02-25 |
20160056207 | SEMICONDUCTOR DEVICE AND FORMING METHOD - Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL | 2016-02-25 |
20160056208 | CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME - The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements. | 2016-02-25 |
20160056209 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND A SYSTEM HAVING THE SAME - A 3D semiconductor device and a system having the same are provided. The 3D semiconductor device includes a semiconductor substrate, a common source region formed on the semiconductor substrate and extending in a line shape, an active region formed on the common source region and including a lateral channel region, which is substantially in parallel to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, and a gate formed in a space between the source region and the drain region. | 2016-02-25 |
20160056210 | WORD LINE CONNECTION FOR MEMORY DEVICE AND METHOD OF MAKING THEREOF - A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level. | 2016-02-25 |
20160056211 | ELECTRONIC DEVICE INCLUDING MEMORY CELLS HAVING VARIABLE RESISTANCE CHARACTERISTICS - An electronic device includes a semiconductor memory. The semiconductor memory includes a stack structure including a first electrode, a second electrode, a third electrode, an insulating layer interposed between the first electrode and the second electrode, and a variable resistance layer interposed between the second electrode and the third electrode; and a selection element layer disposed over at least a part of a sidewall of the stack structure. | 2016-02-25 |
20160056212 | PROTECTIVE LAYER(S) IN ORGANIC IMAGE SENSORS - The present disclosure relates to an organic image sensor and an associated method. By inserting an inorganic protective layer between an electrode and an organic photo active region of the image sensor, the organic photo active region is protected from moisture, oxygen or following process damage. The inorganic protective layers also help to suppress the leakage in the dark. In some embodiments, the organic image sensor comprises a first electrode, an organic photoelectrical conversion structure disposed over the first electrode and a second electrode disposed over the organic photoelectrical conversion structure. The organic image sensor further comprises a first protective structure covering a top surface and a sidewall of the organic photoelectrical conversion structure. | 2016-02-25 |
20160056213 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes: a display area including a plurality of pixels including organic light emitting diodes, pixel circuits connected to the organic light emitting diodes, and one or more repair circuit units disposed between the pixel circuits of the pixels disposed on adjacent lines, in which the one or more repair circuit units include a plurality of repair circuits arranged to form at least one line within the display area. | 2016-02-25 |
20160056214 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a substrate having a red pixel region, a blue pixel region, and a green pixel region. An anode is on the substrate, a light-emitting layer is on the anode, and a cathode is on the light-emitting layer, wherein the light-emitting layer includes a red light-emitting layer emitting red light on the red pixel region, a blue light-emitting layer emitting blue light on the blue pixel region, and a green light-emitting layer emitting green light on the red pixel region, the blue pixel region, and the green pixel region. Each of the red light, the blue light, and the green light is resonated between the anode and the cathode. | 2016-02-25 |
20160056215 | ORGANIC LIGHT EMITTING DIODE DISPLAY, OPTICAL UNIT, AND METHOD FOR MANUFACTURING OPTICAL UNIT - An organic light emitting diode display includes: a display module including a first organic light emitting diode to emit light with a first wavelength, a second organic light emitting diode to emit light with a second wavelength, and a third organic light emitting diode to emit light with a third wavelength; a phase difference layer including a first liquid crystal pattern on the first organic light emitting diode, and a second liquid crystal pattern on the second organic light emitting diode and the third organic light emitting diode; and a linear polarization layer on the phase difference layer. | 2016-02-25 |
20160056216 | DUAL-MODE PIXELS INCLUDING EMISSIVE AND REFLECTIVE DEVICES, AND DUAL-MODE DISPLAY USING THE PIXELS - A dual-mode display including a substrate and a multiple sub-pixels on the substrate, in which each sub-pixel includes, a color selection reflector, and an optical shutter disposed on the color selection reflector, and an emissive devised disposed on the shutter, wherein the emissive device includes a cathode and an anode, and the cathode and the anode include a carbon-based material including graphene sheets, graphene flakes, and graphene platelets, and a binary or ternary transparent conductive oxide including indium oxide, tin oxide, and zinc oxide. | 2016-02-25 |
20160056217 | SUBSTRATE-LESS FLEXIBLE DISPLAY AND METHOD OF MANUFACTURING THE SAME - A substrate-less display device is disclosed. The substrate-less display device includes a barrier stack. The barrier stack includes a plurality of inorganic barrier films and a plurality of polymer films. The inorganic barrier films and the polymer films are alternatively disposed. The substrate-less display device further includes a thin-film-transistor (TFT) device layer disposed on the barrier stack, a display medium layer disposed on the TFT device layer, and an encapsulation layer disposed on the display medium layer. | 2016-02-25 |
20160056218 | DISPLAY PANEL WITH PIXEL DEFINING LAYER AND MANUFACTURING METHOD OF PIXEL DEFINING LAYER - Embodiments of the present invention provide a display panel with a pixel defining layer and a manufacturing method of the pixel defining layer, and the display panel with the pixel defining layer comprises: a substrate; a plurality of pixel regions, arranged on the substrate in a matrix form; the pixel defining layer, disposed on the substrate and comprising: a plurality of openings; a pixel divider, surrounding each of the plurality of openings and defining the plurality of pixel regions, wherein a sidewall of the pixel divider for defining each of the pixel regions is formed so that a slope angle of an upper portion is larger than that of a lower portion thereof. | 2016-02-25 |
20160056219 | LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting display device includes a substrate having a plurality of pixels. A first electrode is provided on the substrate for each pixel, and a pixel defining layer defines each of the pixels. The pixel defining layer has an opening to expose the first electrode. A charge injection layer is on the first electrode, and a surface processing layer is on the charge injection layer. The surface processing layer extends from inside the opening of the pixel defining layer to a top surface of the pixel defining layer. The surface processing layer including a plurality of grooves in a portion extending on the top surface of the pixel defining layer. A charge transport layer is on the surface processing layer, a light-emitting layer is on the charge transport layer, and a second electrode is on the light-emitting layer. | 2016-02-25 |
20160056220 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) on the substrate; a pixel-defining layer (PDL) disposed on the TFT and comprising a first area having a first thickness and a second area having a second thickness greater than the first thickness, and a via hole in the first area; a pixel electrode disposed on at least a portion of the first area, and electrically connected to the TFT via the via hole; an intermediate layer on the pixel electrode, the intermediate layer comprising an emission layer (EML); and an opposite electrode on the intermediate layer. According to a method of manufacturing the organic light emitting display apparatus, the PDL is formed on the substrate and then the pixel electrode is formed on the first area | 2016-02-25 |
20160056221 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus, including a substrate, a reflection control layer disposed on the substrate and including a metal layer and dielectric layer, a thin-film transistor disposed on the reflection control layer and including an active layer, a gate electrode, a source electrode, and a drain electrode, a storage capacitor disposed on the reflection control layer and including a first electrode and a second electrode, a pixel electrode connected to one of the source electrode and the drain electrode, an intermediate layer disposed on the pixel electrode and including an organic emission layer, an opposite electrode disposed on the intermediate layer, in which a portion of the metal layer of the reflection control layer comprises the first electrode of the storage capacitor. | 2016-02-25 |
20160056222 | ORGANIC EL DISPLAY DEVICE - A terminal is formed on a substrate. An anisotropic conductive film is disposed on the terminal. A flexible printed board is connected to the terminal via the anisotropic conductive film. At least one opening is formed in the terminal. An adhesion reinforcing portion as a projection is formed inside the opening. The adhesion reinforcing portion is formed of a material having higher adhesion to the anisotropic conductive film than a material constituting the surface of the terminal, and is adhered to the anisotropic conductive film. | 2016-02-25 |
20160056223 | High-Yield Fabrication of Large-Format Substrates with Distributed, Independent Control Elements - A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s). | 2016-02-25 |
20160056224 | LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - To provide a method for fabricating a light-emitting device using flexible glass which is capable of withstanding a process temperature higher than or equal to 500° C., and the light-emitting device. A second substrate is attached to a support substrate using an adsorption layer. The second substrate is bonded to a backplane substrate provided with a transistor and a light-emitting element. The backplane substrate includes a separation layer and a buffer layer. A first substrate is separated from the backplane substrate by separation between the separation layer and the buffer layer. A flexible third substrate is bonded, using a second adhesive layer, to a surface of the buffer layer exposed by the separation. The support substrate is separated from the second substrate by separation between the second substrate and the adsorption layer. | 2016-02-25 |
20160056225 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes a plurality of pixels, each of the pixels including at least one wiring configured to receive an electrical signal and a storage capacitor formed on the same layer as the wiring. The wiring includes a first conductive pattern layer, an intermediate insulation pattern layer, and a second conductive pattern layer that are sequentially stacked. The first and second conductive pattern layers are electrically connected to each other through a first via hole. | 2016-02-25 |
20160056226 | WAFER LEVEL PACKAGE (WLP) INTEGRATED DEVICE COMPRISING ELECTROMAGNETIC (EM) PASSIVE DEVICE IN REDISTRIBUTION PORTION, AND RADIO FREQUENCY (RF) SHIELD - Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal. | 2016-02-25 |
20160056227 | WELL RESISTORS AND POLYSILICON RESISTORS - An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor. | 2016-02-25 |
20160056228 | CAPACITOR HAVING A GRAPHENE STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR AND METHOD OF FORMING THE SAME - A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers. | 2016-02-25 |
20160056229 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The method includes forming a metal interconnection layer and a first interlayer insulating layer on a semiconductor substrate, forming a reservoir capacitor region by etching the first interlayer insulating layer to expose the metal interconnection layer, forming a barrier metal layer on the reservoir capacitor region, forming a sacrificial insulating layer on the barrier metal layer in a lower portion of the reservoir capacitor region, performing a pre-cleaning process to remove the barrier metal layer on a sidewall of the reservoir capacitor region, and removing the sacrificial insulating layer. | 2016-02-25 |
20160056230 | GUARD RING STRUCTURE AND METHOD OF FORMING THE SAME - A circuit device includes core circuitry. The circuit device further includes a first set of guard rings having a first dopant type, the first set of guard rings being around a periphery of the core circuitry, the first set of guard rings comprising a first guard ring and a second guard ring. The circuit device further includes a second set of guard rings having a second dopant type, the second dopant type being opposite to the first dopant type, wherein at least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings, and the second set of guard rings comprises a third guard ring and a fourth guard ring. | 2016-02-25 |
20160056231 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - Semiconductor devices and fabrication methods thereof are provided. The semiconductor devices include: a substrate, the substrate including a p-type well adjoining an n-type well; a first p-type region and a first n-type region disposed within the n-type well of the substrate, where the first p-type region at least partially encircles the first n-type region; and a second p-type region and a second n-type region disposed in the p-type well of the substrate, where the second n-type region at least partially encircles the second p-type region. In one embodiment, the first p-type region fully encircles the first n-type region and the second n-type region fully encircles the second p-type region. In another embodiment, the semiconductor device may be a bipolar junction transistor or a rectifier. | 2016-02-25 |
20160056232 | MULTI-GATE DEVICE STRUCTURE INCLUDING A FIN-EMBEDDED ISOLATION REGION AND METHODS THEREOF - A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and a fin-embedded isolation region. In some examples, the fin-embedded isolation region includes an STI region. In some embodiments, the fin-embedded isolation separates a first portion of the fin from a second portion of the fin. Also, in some examples, the first portion of the fin includes a channel region. In various embodiments, a source region is formed in the first portion of the fin, a drain region is formed in the second portion of the fin, and an active gate is formed over the channel region. In some examples, the active gate is disposed adjacent to the source region. In addition, a plurality of dummy gates may be formed over the fin, to provide a uniform growth environment and growth profile for source and drain region formation. | 2016-02-25 |
20160056233 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Electric-field concentration in the vicinity of a recess is suppressed. A gate insulating film is provided on a substrate that has a drain region and a first recess therein. The first recess is located between the gate insulating film and the drain region, and is filled with an insulating film. The insulating film has a second recess on its side close to the gate insulating film. An angle defined by an inner side face of the first recess and the surface of the substrate is rounded on a side of the drain region close to the gate insulating film. | 2016-02-25 |
20160056234 | DEEP TRENCH ISOLATION STRUCTURES AND SYSTEMS AND METHODS INCLUDING THE SAME - Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures. | 2016-02-25 |
20160056235 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer. | 2016-02-25 |
20160056236 | SILICON AND SILICON GERMANIUM NANOWIRE FORMATION - Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. | 2016-02-25 |
20160056237 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - There is provided a semiconductor device including: a semiconductor substrate; a first semiconductor region that includes an extension portion extending in a specific direction at a specific width as viewed along a direction orthogonal to the main surface; a second semiconductor region that is shaped to include a portion running along the extension portion of the first semiconductor region as viewed along the direction orthogonal to the main surface; a field relaxation layer that relaxes a field generated between the first semiconductor region and the second semiconductor region, that is formed on the second semiconductor region side of the main surface, and that is formed by a semiconductor layer; and a conductor that is connected to the second semiconductor region, and that has an end portion on the first conductor region side positioned within the range of the field relaxation layer. | 2016-02-25 |
20160056238 | RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH - A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions. | 2016-02-25 |
20160056239 | METHOD AND SYSTEM FOR DIAMOND-BASED OXYGEN SENSOR - A diamond based oxygen sensor is able to function in harsh environment conditions. The oxygen sensor includes a gateless field effect transistor including a synthetic, quasi-intrinsic, hydrogen-passivated, monocrystalline diamond layer exhibiting a | 2016-02-25 |
20160056240 | GRAPHENE FILM, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A GNR is a ribbon-shaped graphene film which includes: five or more (for example, five, seven, or nine) six-membered rings of carbon atoms which are bonded and arranged in line in a short side direction; and a complete armchair type edge structure along a long side direction. By such a constitution, without using a transfer method, there are materialized a highly reliable graphene film which has an armchair type edge structure with a uniform width at a desired value and which enables an electric current on-off ratio of 10 | 2016-02-25 |
20160056241 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A recess is formed by partially etching a silicon carbide substrate. A mask layer is formed on the silicon carbide substrate by means of photolithography using the recess as an alignment mark. An impurity is implanted into the silicon carbide substrate using the mask layer. The silicon carbide substrate is annealed. After the annealing, a first electrode layer is deposited on the silicon carbide substrate. The first electrode layer is patterned by means of photolithography using the recess in the silicon carbide substrate as an alignment mark. | 2016-02-25 |
20160056242 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate is formed of a first region and a second region. The first region includes a first impurity region, a second impurity region, and a first portion forming part of a third impurity region. The second region includes a second portion, the second portion forming part of the third impurity region and being connected to the first portion. Further, a gate insulating film is in contact with the first impurity region, the second impurity region, and the first portion of the third impurity region. An upper electrode is disposed on the second portion of the second region. A channel region extends linearly along a first direction when viewed along a direction perpendicular to a first main surface. The second portion is provided to connect a plurality of impurity region portions together. Consequently, a silicon carbide semiconductor device capable of achieving reduced on-resistance is provided. | 2016-02-25 |
20160056243 | REUSABLE SUBSTRATE BASES, SEMICONDUCTOR DEVICES USING SUCH REUSABLE SUBSTSRATE BASES, AND METHODS FOR MAKING THE REUSABLE SUBSTRATE BASES - Reusable substrate bases for producing multilayer semiconductor devices are provided, as well as free-standing semiconductor devices and reusable substrate bases produced for the multilayer semiconductor devices. The reusable substrate bases comprise a Si-based substrate, a transition lattice overlayed thereon, and a sacrificial ZnO-based layer overlayed on the transition lattice. The transition lattice comprises alternating transition layers of aluminum nitride (AlN) and GaN or Al-doped GaN. The multilayer semiconductor devices comprise the aforesaid reusable substrate bases and a semiconductor stack which comprises a pair of p-n junction forming layers. Methods for producing the multilayer semiconductor devices, the reusable substrate base, as well as free standing semiconductor devices detached from the reusable substrate bases, are also provided. | 2016-02-25 |
20160056244 | NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY - A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation. | 2016-02-25 |
20160056245 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a channel layer which is made of In | 2016-02-25 |
20160056246 | ELECTRONIC DEVICE - An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body. | 2016-02-25 |
20160056247 | PROCESS FOR TREATING A SUBSTRATE USING A LUMINOUS FLUX OF DETERMINED WAVELENGTH, AND CORRESPONDING SUBSTRATE - A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer. | 2016-02-25 |
20160056248 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate. | 2016-02-25 |
20160056249 | BACKSIDE SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME - An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type. | 2016-02-25 |