08th week of 2010 patent applcation highlights part 18 |
Patent application number | Title | Published |
20100044814 | Camera Module and Manufacturing Method Thereof - A camera module includes an image sensor chip module and a lens module. The image sensor chip module includes a base, an image sensor chip disposed on the base and electrically connected with the base, and a frame disposed on the base and surrounding the image sensor chip therein. The lens module includes a barrel mounted on the frame of the image sensor chip module and at least two lens units disposed in the barrel respectively. One of the lens units is disposed on the frame and over the image sensor chip and has a transparent cover capable of filtering infrared rays out and a lens attached to a side of the transparent cover such that the transparent cover separates the lens away from the image sensor chip. | 2010-02-25 |
20100044815 | CMOS IMAGE SENSOR PACKAGE AND CAMERA MODULE USING SAME - An image sensor package includes a cover glass, a color filter layer, an image sensor chip, and a reflecting layer. The cover glass includes a first surface and a second surface at opposite sides thereof. The color filter layer is formed on the first surface of the cover glass. The image sensor chip includes a silicon layer formed on the second surface of the cover glass, a number of pixel regions formed on a third surface of the silicon layer facing away from the cover glass, and a number of bumps formed on the third surface of the silicon layer, the bumps is capable of for electrically connecting the image sensor chip to a circuit board. The reflecting layer covers the pixel regions of the image sensor chip. | 2010-02-25 |
20100044816 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS USING THE SAME - A semiconductor device includes: a semiconductor substrate having an imaging region in which a plurality of photoreceptors are arranged, and a peripheral circuit region arranged around the imaging region; a plurality of microlenses formed on the imaging region; a low-refractive-index film formed on the semiconductor substrate to cover the plurality of microlenses and part of the peripheral circuit region; and a transparent substrate formed on part of the low-refractive-index film above the imaging region. A through hole is formed in part of the low-refractive-index film above an amplifier circuit arranged in the peripheral circuit region. | 2010-02-25 |
20100044817 | PHOTOSENSITIVE RESIN COMPOSITION, COLOR FILTER AND METHOD OF PRODUCING THE SAME, AND SOLID-STATE IMAGING DEVICE - A photosensitive resin composition is provided which provides a high resolution even when a pattern is formed using a low exposure intensity (in particular, less than 200 mJ/cm | 2010-02-25 |
20100044818 | SEMICONDUCTOR LIGHT-RECEIVING DEVICE - Disclosed is light-receiving device ( | 2010-02-25 |
20100044819 | Method for Manufacturing CMOS Image Sensor Having Microlens Therein with High Photosensitivity - The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence; forming a color filter array having a plurality of color filters on the passivation layer; forming an over-coating layer (OCL) on the color filter array by using a positive photoresist or a negative photoresist; forming openings in the OCL by patterning the OCL by using a predetermined mask; and forming dome-typed microlenses on a patterned OCL. | 2010-02-25 |
20100044820 | CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A CMOS image sensor is disclosed. The image sensor includes a plurality of polysilicon patterns provided on a silicon epitaxial layer which correspond to the location of a plurality of photodiodes provided in a dummy pixel area, a silicide layer of metal with a high melting point provided on the plurality of the polysilicon patterns, a device protecting layer and a planarization layer provided on the silicon epitaxial layer and silicide layer, and a plurality of microlenses on the planarization layer which correspond to the location of the silicide layer. | 2010-02-25 |
20100044821 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention offers a semiconductor device to measure a luminance for the visible wavelength range of light components and its manufacturing method which reduce its manufacturing cost. A first light-receiving element and a second light-receiving element are formed in a semiconductor substrate. Then, there is formed an arithmetic circuit that calculates a difference between a value of an electric current corresponding to an amount of light detected by the first light-receiving element (that is, a value of an electric current representing a relative sensitivity against the light) and a value of an electric current corresponding to an amount of light detected by the second light-receiving element (that is, a value of an electric current representing a relative sensitivity against the light). Next, a first green pass filter permeable only to light in a green wavelength range and an infrared wavelength range is formed to cover the first light-receiving element, while a second green pass filter similar to the first green filter is formed to cover the second light-receiving element. In addition, a red pass filter permeable only to light in a red wavelength range and the infrared wavelength range is formed to cover the second light-receiving element. | 2010-02-25 |
20100044822 | LUMINOUS RADIATION COLOUR PHOTOSENSITIVE STRUCTURE - There is described a structure which is photosensitive to the colour of a light radiation; said structure being formed by a semiconductor substrate having a first type of conductivity and the substrate is adapted to generate a different distribution of carriers upon incidence of a light radiation as the depth varies as a function of the at least one wave length of the light radiation. The structure comprises at least one first and one second element, both arranged in the substrate and adapted to collect the generated carriers; both the first and second element being adapted to generate first and second electrical signals as a response to the amount of collected carriers. The structure comprises means adapted to generate an electrical field orthogonal to the upper surface of the substrate and further means adapted to generate an electrical field transversal to the structure and parallel to its upper surface: said means in combination with said further means are adapted to generate a resulting electrical field such as to determine different trajectories for the carriers within the substrate as a function of the at least one wave length of the incident light radiation. The trajectories are directed towards the first element or towards the second element. | 2010-02-25 |
20100044823 | SEMICONDUCTOR PHOTONIC DEVICES WITH ENHANCED RESPONSIVITY AND REDUCED STRAY LIGHT - In accordance with the invention, a photonic device comprises a semiconductor substrate including at least one circuit component comprising a metal silicide layer and an overlying layer including at least one photoresponsive component. The metal silicide layer is disposed between the circuit component and the photoresponsive component to prevent entry into the circuit component of light that penetrates the photoresponsive component. The silicide layer advantageously reflects the light back into the photoresponsive element. In addition, the overlying layer can include one or more reflective layers to reduce entry of oblique light into the photoresponsive component. In an advantageous embodiment, the substrate comprises single-crystal silicon including one or more insulated gate field effect transistors (IGFETs), and/or capacitors, and the photoresponsive element comprises germanium and/or germanium alloy epitaxially grown from seeds on the silicon. The metal silicide layer can comprise the gate of the IGFET and/or an electrode of the capacitor. | 2010-02-25 |
20100044824 | STRATIFIED PHOTODIODE FOR HIGH RESOLUTION CMOS IMAGE SENSOR IMPLEMENTED WITH STI TECHNOLOGY - A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages. | 2010-02-25 |
20100044825 | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body. | 2010-02-25 |
20100044826 | 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL - A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure. | 2010-02-25 |
20100044827 | Method for making a substrate structure comprising a film and substrate structure made by same method - A method for manufacturing a substrate structure comprising a film and a substrate structure made by this method are disclosed. The method for manufacturing a substrate structure comprising a film includes the steps of: providing a target substrate; providing an initial substrate; forming an embrittlement-layer on the initial substrate; forming a device layer on the embrittlement-layer; doping with hydrogen ions; bonding the device layer with the target substrate; and separating the device layer from the initial substrate. The hydrogen ions are added into the embrittlement-layer through doping, before an energy treatment is applied to embrittle and break the embrittlement-layer, thereby separating the device layer from the initial substrate. Since the hydrogen ions are added into the embrittlement-layer through doping, a crystal lattice structure of the device layer will not be damaged during the step of doping with hydrogen ions. | 2010-02-25 |
20100044828 | MONOLITHIC INTEGRATED COMPOSITE DEVICE HAVING SILICON INTEGRATED CIRCUIT AND SILICON OPTICAL DEVICE INTEGRATED THEREON, AND FABRICATION METHOD THEREOF - Provided is a monolithic integrated composite device including: a silicon substrate which is partitioned into a silicon integrated circuit forming region and a silicon optical device forming region; a buried oxide layer which is formed locally in the silicon substrate of the silicon optical device forming region and isolates unit devices of the silicon optical device forming region; an overlay layer formed locally on the buried oxide layer; a silicon optical device formed in the silicon optical device forming region using the silicon overlay layer; a silicon integrated circuit formed in the silicon integrated circuit forming region of the silicon substrate; and wiring connecting the silicon integrated circuit and the silicon optical device or connecting the silicon optical devices or connecting the silicon integrated circuits. | 2010-02-25 |
20100044829 | METHOD FOR PRODUCING SOI SUBSTRATE AND SOI SUBSTRATE - The present invention is a method for producing an SOI substrate including the steps of: preparing a bond wafer and a base wafer which are composed of single crystal silicon wafers; forming an oxide film on a surface of at least one of the bond wafer and the base wafer so that a thickness of a buried oxide film after bonding becomes 3 μm or more; bonding the bond wafer and the base wafer via the oxide film; performing a law-temperature heat treatment at a temperature of 400° C. or more and 1000° C. or less to the bonded substrate; thinning the bond wafer to be an SOI layer; and increasing bonding strength by performing a high-temperature heat treatment at a temperature exceeding 1000° C. Thus, a method for producing an SOI substrate by which generation of slip dislocations is suppressed and an SOI substrate having a high-quality SOI layer can be obtained, for producing a SOI layer in which the thickness of a buried oxide film is thick as 3 μm or more by a bonding method, etc. are provided. | 2010-02-25 |
20100044830 | METHOD OF PRODUCING AN SOI STRUCTURE WITH AN INSULATING LAYER OF CONTROLLED THICKNESS - The invention relates to semiconductor-on-insulator structure and its method of manufacture. This structure includes a substrate, a thin, useful surface layer and an insulating layer positioned between the substrate and surface layer. The insulating layer is at least one dielectric layer of a high k material having a permittivity that is higher than that of silicon dioxide and a capacitance that is substantially equivalent to that of a layer of silicon dioxide having a thickness of less than or equal to 30 nm. | 2010-02-25 |
20100044831 | MULTI-LAYER FILM CAPACITOR WITH TAPERED FILM SIDEWALLS - A multi-layer capacitor of staggered construction is formed of one or more layers having tapered sidewall(s). The edge(s) of the capacitor film(s) can be etched to have a gentle slope, which can improve adhesion of the overlying layers and provide more uniform film thickness. The multi-layer capacitor can be used in various applications such as filtering and decoupling. | 2010-02-25 |
20100044832 | STRUCTURE OF TRENCH CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer can be operated by detecting the protective layer. If the protective layer is detected, the collar oxide layer is therefore at a suitable thickness. Furthermore, a mask layer rather than the collar oxide layer is used as a mask during the trench formation. | 2010-02-25 |
20100044833 | INTEGRATED CAPACITOR - According to the preferred embodiment, an integrated capacitor having a comb-meander structure is provided. The integrated capacitor comprises a first comb-shaped metal pattern; a second comb-shaped metal pattern interdigitating with the first comb-shaped metal pattern; and a meandering metal pattern traversing a spacing between the first and second comb-shaped metal patterns. | 2010-02-25 |
20100044834 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other. | 2010-02-25 |
20100044835 | SETTING THE DC OPERATING CURRENT OF A RAIL-TO-RAIL OUTPUT STAGE OF AN OP-AMP - In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor. | 2010-02-25 |
20100044836 | PROCESS FOR PRODUCING LOCALISED Ge0I STRUCTURES, OBTAINED BY GERMANIUM CONDENSATION - The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer. | 2010-02-25 |
20100044837 | REPLICATION AND TRANSFER OF MICROSTRUCTURES AND NANOSTRUCTURES - A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved. Additional processing steps can also be carried out using the replica before transfer, including the formation of nanostructures, microdevices, or portions thereof. These structures are then also transferred onto the substrate when the replica is transferred, and remain on the substrate when the replica is dissolved. This is a technique that can be applied as a complementary process or a replacement for various lithographic processing steps in the fabrication of integrated circuits and other microdevices. | 2010-02-25 |
20100044838 | SEMICONDUCTOR COMPONENT WITH MARGINAL REGION - A semiconductor component having a semiconductor body includes an active region and a marginal region surrounding the active region. The marginal region extends from the active region as far as an edge of the semiconductor body. A zone composed of porous material is formed in the marginal region. | 2010-02-25 |
20100044839 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface ( | 2010-02-25 |
20100044840 | SHIELDED MULTI-LAYER PACKAGE STRUCTURES - Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate ( | 2010-02-25 |
20100044841 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material deposited over the sealed chip and the sealed carrier. | 2010-02-25 |
20100044842 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a chip coupled to the carrier, a dielectric layer coupled to the carrier and the chip, and conducting elements connected to both the carrier and contacts of the chip. The chip includes a first face with a first contact spaced apart from a second contact. The dielectric layer includes a photoinitiator that configures the dielectric layer to be selectively opened to expose the first and second contacts and the carrier. A first conducting element is connected to the first contact, a second conducting element is connected to the second contact, and a third conducting element is connected to the carrier. | 2010-02-25 |
20100044843 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection. | 2010-02-25 |
20100044844 | LEAD FRAME, RESIN PACKAGE, SEMICONDUCTOR DEVICE AND RESIN PACKAGE MANUFACTURING METHOD - A pressure loss section H | 2010-02-25 |
20100044845 | CIRCUIT SUBSTRATE, AN ELECTRONIC DEVICE ARRANGEMENT AND A MANUFACTURING PROCESS FOR THE CIRCUIT SUBSTRATE - [Problem to be Solved] There are provided a circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate which enable to directly implement the surface mounting and so on of electronic components on the conductive wiring without forming solder resist, and also which enable to enhance high speed transmission characteristics and to enlarge wiring rule for the electrode terminal of the function element to be contained therein, and to implement with excellent workability and reliability when connecting the electronic device. | 2010-02-25 |
20100044846 | THREE-DIMENSIONAL STRUCTURAL SEMICONDUCTOR DEVICE - A semiconductor device of three-dimensional structure in which the operating frequency of a chip can be raised while preventing the chip area from increasing. The three-dimensional structure semiconductor device have a first integrated circuit including a plurality of areas formed on a first conductor layer and a first wiring layer formed on the first conductor layer, a first insulating layer laminated on the first wiring layer, and a second integrated circuit including a plurality of areas formed on a second conductor layer which is laminated on the first insulating layer, and a second wiring layer formed on the second conductor layer. The first integrated circuit and the second integrated circuit are connected electrically by interconnection penetrating in the laminating direction and at least one of bidirectional communication of data, control signal supply, and clock signal supply between the first integrated circuit and the second integrated circuit is carried out through the penetrating interconnection. | 2010-02-25 |
20100044847 | SEMICONDUCTOR CHIP INCLUDING A CHIP VIA PLUG PENETRATING A SUBSTRATE, A SEMICONDUCTOR STACK, A SEMICONDUCTOR DEVICE PACKAGE AND AN ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure. | 2010-02-25 |
20100044848 | SOLDER JOINT RELIABILITY IN MICROELECTRONIC PACKAGING - A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni. | 2010-02-25 |
20100044849 | STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a stacked integrated circuit package-in-package system includes forming a substrate with a top contact, mounting a first device having a first terminal over the substrate, stacking a second device having a second terminal over the first device in an offset configuration, connecting the first terminal to the top contact below the first terminal, and connecting the second terminal to the top contact below the second terminal. | 2010-02-25 |
20100044850 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier. | 2010-02-25 |
20100044851 | Flip chip packages - Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity. | 2010-02-25 |
20100044852 | VERTICAL STACK TYPE MULTI-CHIP PACKAGE HAVING IMPROVED GROUNDING PERFORMANCE AND LOWER SEMICONDUCTOR CHIP RELIABILITY - A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate. | 2010-02-25 |
20100044853 | SYSTEM-IN-PACKAGE WITH THROUGH SUBSTRATE VIA HOLES - The present invention relates to a system-in-package that comprises an integration substrate with a thickness of less than 100 micrometer and a plurality of through-substrate vias, which have an aspect ratio larger than 5. A first chip is attached to the integration substrate and arranged between the integration substrate and a support, which is suitable for mechanically supporting the integration substrate during processing and handling. The system-in-package can be fabricated according to the invention without a through-substrate-hole etching step. The large aspect ratio implies reduced lateral extensions, which allow increasing the integration density and decreasing lead inductances. | 2010-02-25 |
20100044854 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME AND A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed which includes a tab ( | 2010-02-25 |
20100044855 | INTEGRATED THERMAL STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer. | 2010-02-25 |
20100044856 | ELECTRONIC PACKAGE WITH A THERMAL INTERPOSER AND METHOD OF MANUFACTURING THE SAME - An electronic package includes a die including a thermal interface material through which a primary heat flux path is enabled for conducting heat from the die, an organic substrate, and a thermal interposer provided between the organic substrate and the die, the thermal interposer having an area extending beyond a footprint of the die, the area including the thermal interface material, the thermal interposer conducting heat generated by the die through the thermal interface material such that an auxiliary heat flux path for conducting heat generated in the die is enabled. | 2010-02-25 |
20100044857 | WLCSP TARGET AND METHOD FOR FORMING THE SAME - The invention provides a Wafer Level Chip Size Packaging (WLCSP) target and a method for forming it. A WLCSP target is formed by recombining single chips, wafer parts each including two or more chips or half finished packaging targets which have been subjected to at least one previous step of packaging onto a first substrate, or bonding a wafer part which is formed by dicing a whole wafer and includes at least two chips to a second substrate for bonding. Thus, a wafer with a larger size can be packaged through the WLCSP on a WLCSP apparatus with a smaller size while benefiting from the advantages of the WLCSP, the WLCSP apparatus remains applicable within a longer period of time, the cost is lowered, and enterprises may keep up with the development of the market and the increase of the wafer size without having to update the WLCSP apparatus substantially. | 2010-02-25 |
20100044858 | Product Chips and Die With a Feature Pattern That Contains Information Relating to the Product Chip, Methods for Fabricating Such Product Chips and Die, and Methods for Reading a Feature Pattern From a Packaged Die - Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging. | 2010-02-25 |
20100044859 | Semiconductor device and method of fabricating semiconductor device - There is provided a semiconductor device including a semiconductor substrate on which at least one electrode pad is formed, a rewiring layer connected to the electrode pad, and an encapsulation part which encapsulates the semiconductor substrate, the electrode pad being formed of a first region including a connection part connected to the rewiring layer and a second region other than the first region, the device including: an insulating film provided on the semiconductor substrate, having an opening at which the first region in the electrode pad is exposed, and covering the second region of the electrode pad, wherein the rewiring layer is connected to the first region of the electrode pad exposed at the opening, and extends across the insulating film so as to cover the second region of the electrode pad from above. | 2010-02-25 |
20100044860 | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer - An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer. | 2010-02-25 |
20100044861 | SEMICONDUCTOR DIE SUPPORT IN AN OFFSET DIE STACK - A semiconductor device is disclosed including a support structure for supporting an edge of a semiconductor die that is not supported on the substrate or semiconductor die below. In embodiments, the semiconductor device may in general include a substrate having a plurality of contact pads, a first semiconductor die mounted on the substrate, and a second semiconductor die mounted on the first semiconductor die in an offset configuration so that an edge of the second semiconductor die overhangs the first semiconductor die. A support structure may be affixed to one or more of the contact pads beneath the overhanging edge to support the overhanging edge during a wire bonding process which exerts a downward force on the overhanging edge. | 2010-02-25 |
20100044862 | METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR SUBSTRATE - A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate. | 2010-02-25 |
20100044863 | Semiconductor device - An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad. | 2010-02-25 |
20100044864 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The present invention aims at providing a method of manufacturing a semiconductor device capable of suppressing metal diffusion from the upper face of wiring. | 2010-02-25 |
20100044865 | FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS - A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved. | 2010-02-25 |
20100044866 | SEMICONDUCTOR DEVICE HAVING VIA CONNECTING BETWEEN INTERCONNECTS - A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via. | 2010-02-25 |
20100044867 | METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION - Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention. | 2010-02-25 |
20100044868 | SEMICONDUCTOR DEVICE - A semiconductor device includes an external terminal, a plurality of first interconnections, an electrode, a conductor, and a second interconnection. The first interconnections are positioned below the external terminal. The electrode is positioned at the same level as the first interconnections and is electrically connected to the external terminal through the conductor. The second interconnection is positioned below the first interconnections and the electrode. The semiconductor device has a region where the shortest distance between an edge surface of the electrode and an edge surface of one of the first interconnections positioned most adjacent to the electrode is less than 0.11 times the total thickness of the conductor and the electrode. The second interconnection is positioned at a position different from that of the region in a thickness direction of the semiconductor device. | 2010-02-25 |
20100044869 | RELIABLE INTERCONNECTS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography. | 2010-02-25 |
20100044870 | Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same - An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode. | 2010-02-25 |
20100044871 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - In order to attain, in a semiconductor device in which a semiconductor element is mounted, formation of a mark of a relatively large size which is easily recognizable by the naked eye or a machine, and which can apply a code system containing enough amount of information for tracing a manufacturing history, a semiconductor device according to the present invention includes an interposer electrically connected to a semiconductor element, which semiconductor device has a mark for displaying at least predetermined information relevant to the semiconductor element. | 2010-02-25 |
20100044872 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 2010-02-25 |
20100044873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When a thin semiconductor device is formed by grinding a wafer, it has been necessary to dice the wafer into dies and process the back surfaces of the dies separately. In the invention, a wafer | 2010-02-25 |
20100044874 | INTEGRATED CIRCUIT OF DECREASED SIZE - An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface. | 2010-02-25 |
20100044875 | METHODS AND APPARATUS FOR DEFINING MANHATTAN POWER GRID STRUCTURES HAVING A REDUCED NUMBER OF VIAS - A method for defining and producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45° or 135° diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1. | 2010-02-25 |
20100044876 | CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES - Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate. | 2010-02-25 |
20100044877 | ELECTRONIC DEVICE HAVING A CHIP STACK - An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads. | 2010-02-25 |
20100044878 | INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING CAVITY - An integrated circuit package system includes providing a carrier having a first side and a second side; mounting an integrated circuit over the carrier with the first side facing the integrated circuit; attaching an external interconnect to the second side; and forming an encapsulation over the integrated circuit and around the external interconnect with the external interconnect exposed from the encapsulation and with the encapsulation and the second side forming a cavity. | 2010-02-25 |
20100044879 | Layered chip package and method of manufacturing same - A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes. | 2010-02-25 |
20100044880 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes a multilayer wiring substrate having a plurality of inner wiring layers and a semiconductor chip mounted on the multilayer wiring substrate. The multilayer wiring substrate has a groove formed in the bottom surface. The groove does not reach the lowermost of the inner wiring layers. | 2010-02-25 |
20100044881 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes: a first semiconductor element; a second semiconductor element mounted on an upper surface of the first semiconductor element via an adhesive layer; a mold resin body for overmolding the first semiconductor element and the second semiconductor element; and a first spherical filler having a diameter smaller than an average thickness of the adhesive layer and a second spherical filler having a diameter larger than the average thickness of the adhesive layer, the first or second spherical filler being dispersed in the mold resin body. The mold resin body does not contain a spherical filler which has a diameter substantially equal to the average thickness of the adhesive layer. | 2010-02-25 |
20100044882 | INTEGRATED CIRCUIT PACKAGE SYSTEM FLIP CHIP - An integrated circuit package system includes: providing a substrate having a top side with a trace conductor connected to a bottom side with a system interconnect; forming a bump ring on the substrate, the bump ring having an inner cavity area over the trace conductor and an outer bump area; applying a substrate mask layer adjacent a perimeter of the outer bump area; connecting a device to the trace conductor below the bump ring; and applying a compound between the device and the substrate. | 2010-02-25 |
20100044883 | Plastic Semiconductor Package Having Improved Control of Dimensions - A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area. The encapsulation compound has a plurality of side areas reaching from the substrate to the top area; these side areas form edge lines with the top area, where the top area plane intersects with the respective plane of each side area. The encapsulation compound is recessed along the edge lines so that the material is caved-in along the lines; this feature causes the recess to prevent any compound from the side area planes to reach the top area plane, whereby the planarity of the top area is preserved. | 2010-02-25 |
20100044884 | INTEGRATED CIRCUIT PACKAGE EMPLOYING PREDETERMINED THREE-DIMENSIONAL SOLDER PAD SURFACE AND METHOD FOR MAKING SAME - An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described. | 2010-02-25 |
20100044885 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method. One embodiment provides at least two semiconductor chips. A dielectric material is applied to the at least two semiconductor chips to attach the at least two semiconductor chips to each other. A portion of the dielectric material is selectively removed between the at least two semiconductor chips to form at least one recess in the dielectric material. Metal particles including paste is applied to the at least one recess in the dielectric material. | 2010-02-25 |
20100044886 | SEMICONDUCTOR DEVICE HAVING PAIRS OF PADS - An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These zones extend perpendicularly to the pitch direction. The electrical connection pads are grouped in adjacent pairs. An insulation space is located between the pads of each pair of electrical connection pads. In a direction perpendicular to the pitch direction, the pads in the pair are spaced apart. The pads of each pair of electrical connection pads extend over a pair of adjacent zones and are associated with two adjacent vias. | 2010-02-25 |
20100044887 | METHOD FOR PRODUCING CIRCUIT SUBSTRATE, AND CIRCUIT SUBSTRATE - The method for producing a circuit substrate of the present invention is characterized in that the circuit substrate is produced using as sheet a circuit substrate sheet including an uncured layer a part of which, the part being other than a part at which a circuit chip is disposed, is selectively curable before or after disposal of said circuit chip, wherein the uncured layer has a softness that enables embedding of the circuit chip in the circuit substrate sheet upon pressing the circuit chip that has been disposed on a surface of the uncured layer. According to the method for producing the circuit substrate of the present invention, the circuit chip can be embedded inwards with high accuracy, and the circuit substrate can be produced easily with high accuracy. | 2010-02-25 |
20100044888 | BIS(AMINOPHENOL) DERIVATIVE, PROCESS FOR PRODUCING SAME, POLYAMIDE RESIN, POSITIVE PHOTOSENSITIVE RESIN COMPOSITION, PROTECTIVE FILM, INTERLAYER DIELECTRIC FILM, SEMICONDUCTOR DEVICE, AND DISPLAY ELEMENT - A bis(aminophenol) derivative having substituents at positions adjacent to two amino groups is provided. The bis(aminophenol) derivative is used as a raw material of a polyamide resin for a positive-tone photosensitive resin composition. A polyamide resin comprising bis(aminophenol) and a structure derived from a carboxylic acid is also provided, the bis(aminophenol) having substituents at positions adjacent to the two amino groups. A positive-tone photosensitive resin composition comprising a polybenzooxazole precursor resin, exhibiting high sensitivity and a high cyclization rate even when cured at a low temperature is provided. Also provided is a positive-tone photosensitive resin composition comprising a polyamide resin having an imide structure, an imide precursor structure, or an amide acid ester structure. The composition exhibits high sensitivity and produces a cured product having low water absorption even when cured at a low temperature. | 2010-02-25 |
20100044889 | Electrical Component and Film Composite Laminated On the Component and Method for Production - At least one film composite is laminated on a surface of at least one electrical component. The film composite includes at least one electrically-conducting plastic film with at least one electrically conducting conductor. The electrically-conducting plastic film has a high-ohmic resistance. This method may be used in planar large-surface electrical contacting technology for the production of modules with power semiconductors, where an electrical contacting of the components is achieved by the plastic films. A low lateral electrical conductivity is achieved, such that an electrical charging of the plastic films required for the contacting technology is prevented on operation of the component or the module. | 2010-02-25 |
20100044890 | SEMICONDUCTOR SUBSTRATE MANUFACTURE APPARATUS, SEMICONDUCTOR SUBSTRATE MANUFACTURE METHOD, AND SEMICONDUCTOR SUBSTRATE - [Problems] To perform predetermined processing such as annealing and coating application of a semiconductor material with high accuracy on a number of semiconductor formation areas formed over a wide region on a surface of a substrate having elasticity such as a plastic substrate even when the substrate expands and contracts. | 2010-02-25 |
20100044891 | GAS-LIQUID MIXING DEVICE - This invention relates to a gas-liquid mixing device, forming a safety valve, designed capable of being incorporated into a gas-cleaning installation including a liquid tank ( | 2010-02-25 |
20100044892 | Separating Device For Sintering Shoes - Device comprising means of separating at least two sintering shoes for transporting nuclear fuel pellets capable of moving according to a first axis (X) and of which two end faces are in contact with one another, wherein said separating means are capable of moving at least one of the two sintering shoes close to said end faces in contact, according to a second vertical axis (Y) substantially orthogonal to the first axis (X). | 2010-02-25 |
20100044893 | Apparatus for Removing an Ophthalmic Lens from a Mold Half - An apparatus ( | 2010-02-25 |
20100044894 | PREPARATION OF CAPSULES - Prior art processes for producing protein-based capsules (for example, capsules for use in electrophoretic media) tend to be wasteful because they produce many capsules outside the desired size range, which is typically about 20 to 50 μm. Capsule size distribution and yields can be improved by either (a) emulsifying a water-immiscible phase in a preformed coacervate of the protein; or (b) using a limited coalescence process with colloidal alumina as the surface-active particulate material. | 2010-02-25 |
20100044895 | Method of forming a dental product - The invention provides a method of shaping a dental product, comprising:
| 2010-02-25 |
20100044896 | Injection Molding Apparatus Having a Nozzle Tip Component for Taking a Nozzle Out of Service - A nozzle tip component for taking a nozzle of an injection molding apparatus out-of service, wherein the nozzle tip component has a tapered interior surface that circumferentially surrounds and grips an associated valve pin to lock the valve pin in a closed position and prevent flow of molding material. The injection molding apparatus includes a plurality of nozzles defining nozzle channels, each nozzle associated with a mold gate, and a plurality of valve pins releasably coupled to an actuated valve pin plate. Each valve pin extends through the one of the nozzles for controlling flow of molding material in the nozzle channel, and the actuated valve pin plate is operable to move the plurality of valve pins between open and closed positions of the mold gates. | 2010-02-25 |
20100044897 | POLYMERIC MATERIALS - A part may be manufactured in a desired colour from virgin or recycled polymeric material by selection of a colour formulation to be used in a first location | 2010-02-25 |
20100044898 | MOLDING DEVICE AND METHOD FOR CONTROLLING THE SAME - A molding device for easily releasing a molding material produced by transferring a minute shape to resin using a die having the minute shape formed thereon from the die with no damage. A method for controlling such molding device is also provided. The molding device and the control method are characterized in that the force for releasing the molding material from the die is detected and an alarm signal is delivered if the number of times when the releasing force becomes higher than a level preset depending on the molding material reaches a preset number of times. | 2010-02-25 |
20100044899 | METHOD AND APPARATUS FOR CONTROLLING THE GEOMETRY OF A COMPOSITE COMPONENT - A method of controlling the geometry of a composite component ( | 2010-02-25 |
20100044900 | INJECTION MOLDING SYSTEM, COMPUTER PROGRAM, METHOD OF INJECTION MOLDING, AND INJECTION MOLDING MACHINE - There are provided an injection molding system, a computer program, a method of injection molding, and an injection molding machine capable of performing precise temperature control of a mold even when there is a delay in temperature increase of the mold in heat supply with a heating medium. The temperature control is performed so that temperatures of a fixed mold and a movable mold are maintained between an upper limit TU and a lower limit TL of a predetermined temperature range after start of injection of resin during an injection molding cycle. The temperature control of the fixed mold and the movable mold is performed only by switching ON/OFF supply of the heating medium, and cooling with a cooling medium is not performed. In a process of cooling the resin, the temperature control is performed so that the temperatures of the fixed mold and the movable mold are maintained between an upper limit TUa and a lower limit TLa of a temperature range effective for resin annealing by stop of supply of the cooling medium and the supply and stop of the heating medium. | 2010-02-25 |
20100044901 | Porous vinylidene fluoride resin membrane for water treatment and process for producing the same - A water treatment membrane comprising a porous membrane of vinylidene fluoride resin, wherein 0.01-5 wt. parts of photocatalytic titanium oxide is uniformly dispersed in 100 wt. parts of the vinylidene fluoride resin. The water treatment membrane can solve problems accompanying the hydrophobicity of a porous membrane of vinylidene fluoride resin while taking advantage of excellent mechanical properties, weatherablility, chemical resistance, etc., thereof. | 2010-02-25 |
20100044902 | COMPOSITE SEMIPERMEABLE MEMBRANE AND PROCESS FOR PRODUCING THE SAME - The present invention aims at providing a composite semipermeable membrane in which water permeability and salt-blocking rate cannot deteriorate by long-term storage, and at providing a process for producing the same. The present invention relates to a composite semipermeable membrane having a skin layer formed on the surface of a porous support, the skin layer including a polyamide resin obtained by interfacial polymerization of a polyfunctional amine component and a polyfunctional acid halide component, wherein the porous support contains at least one kind of additives selected from the group consisting of antioxidants, antibacterial agents, antifungal agents, and moisturizers, in an amount of 95% by weight or more with respect to the whole composite semipermeable membrane. | 2010-02-25 |
20100044903 | AUTOMATED INFILTRANT TRANSFER APPARATUS AND METHOD - An apparatus provides a method for transferring infiltrant to a 3D printed article comprising the steps of (i) calculating the amount of infiltrant based in part upon the particulars of the 3D printed articles; (ii) dispensing the calculated amount of infiltrant to a scale from an infiltrant dispenser through a controller; (iii) weighing the dispensed infiltrant during the dispensing; providing the controller with a signal of the weighed dispensed infiltrant; and (iv) automatically stopping the infiltrant dispenser through the controller as the weighed infiltrant reaches the calculated amount of infiltrant. | 2010-02-25 |
20100044904 | Method of creating decorative wood - The method of creating decorative wood consists of deep firing of the wood surface with the following removal/cleaning of slag. The procedure of firing in this particular case would consist of the use of propane torch or any other source of fire that can be used for working with a top layer of wood. The removal/cleaning procedure would include the manual use of metal brush, or any other source of mechanical way of slag removal. The decorative wood doesn't need any necessary addition of coloring and may be finished with varnish, oil or other finishing material. Such method provides an opportunity to feel the texture with bare hands, and not only what is visually perceived with a human eye. | 2010-02-25 |
20100044905 | METHOD OF FORMING PATTERN AND METHOD OF PRODUCING ELECTRONIC ELEMENT - A method of forming a pattern and a method of producing an electronic element with which a fine and precise pattern is stably formed are provided. Each of the method of forming a pattern and the method of producing an electronic element includes a step of forming an electrically conductive film D by applying a liquid composition onto a first plate | 2010-02-25 |
20100044906 | METHOD OF TRIMMING UNFIRED POTTERY USING A TURNTABLE APPARATUS - A rotatable turntable tool is used in trimming wheel-thrown pottery. The turntable tool includes a base portion, a bearing member, and a cap portion which is rotatably attached to the base portion. A method of trimming an unfired clay workpiece includes steps of inverting the workpiece and placing it at a central portion of a wheel head on a potter's wheel; placing the turntable tool on top of a central portion of the inverted workpiece; pressing downwardly on the cap portion of the turntable tool while rotating said wheel head to stabilize the workpiece, whereby the base portion of the turntable tool rotates with the workpiece, while the cap portion is substantially restrained from rotating; and applying a trimming tool to an edge of the workpiece to remove unwanted clay therefrom. | 2010-02-25 |
20100044907 | Pad Formation Method, Assembly and Pad Produced Thereby - A foam cushion pad formation assembly that includes a conveyance assembly having at least one moving conveyor component presenting a pad shape formation surface, which surface is convoluted and arranged to shape sealed enclosures of a pad chain received by the conveyance assembly. A separation device is provided to separate shaped pads of the pad chain received by said conveyor device. The shaped pads include convoluted surface that are formed by way of gripping projection and recesses combinations in the moving conveyor component. Embodiments include sensing for non separated pads from a downstream end of the bag chain, pad chain separation enhancement devices, and various control system including the requirement of confirmation of separation before feeding a new pad enclosure as in one containing liquid polyurethane precursor chemicals. An embodiment includes a pad chain path disruption sensor and a form feed control which implements the formation of pad enclosures free of filler material in a bridging region between the outlet end of the enclosure formation means and the conveyance assembly. | 2010-02-25 |
20100044908 | PROCESS FOR PRODUCING MIXTURE OF TWO-LIQUID MIXING TYPE CURABLE RESIN AND PROCESS FOR PRODUCING HOLLOW-FIBER MEMBRANE FILTER ELEMENT - An object of the present invention is to provide a process for producing a mixture of a two-liquid mixing type curable resin, which process is hard to generate curing unevenness, can be carried out with low energy consumption, and is suited for mixing even with a disposable static mixer. | 2010-02-25 |
20100044909 | LOFTY, TACKIFIED NONWOVEN SHEET AND METHOD OF MAKING - A method of making a tackified nonwoven sheet that includes forming a densified, tackified web by providing a rebulkable nonwoven fiber web and applying an adhesive to the nonwoven web. The densified, tackified web is rebulked to an open, lofty form by exposing the densified, tackified web to a temperature of at least 225° F. Finally, a sheet is formed from the rebulked, tackified web. In some embodiments, the so-formed sheet is a cleaning wipe configured for picking up diverse debris such as sand, dust, hair, and/or food particles. In other embodiments, the method further includes the rebulked, tackified web having an increased degree of loftiness as compared to a degree of loftiness of the densified, tackified web prior to rebulking. | 2010-02-25 |
20100044910 | METHOD FOR PRODUCING CERAMIC-HONEYCOMB-STRUCTURE-MOLDING DIE AND METHOD FOR PRODUCING CERAMIC HONEYCOMB STRUCTURE - A method for producing a die for molding a ceramic honeycomb structure, which has molding grooves arranged in a lattice pattern and apertures communicating with the molding grooves for supplying a moldable material, wherein the formation of the lattice-patterned grooves by machining is conducted by a first machining operation for forming pluralities of first parallel grooves, and a second machining operation for forming second grooves crossing the first grooves; wherein the first and second machining operations are conducted by at least 2 passes of grinding or cutting using a rotating tool; and wherein the second machining operation is conducted by up-cutting in the second pass or later, and a method for producing a ceramic honeycomb structure using such a die. | 2010-02-25 |
20100044911 | METHOD FOR PRODUCING ALUMINUM-TITANATE-BASED CERAMIC HONEYCOMB STRUCTURE - A method for producing an aluminum-titanate-based ceramic honeycomb structure comprising blending TiO | 2010-02-25 |
20100044912 | Method For Producing a Fiber Composite Component For Aviation and Spaceflight - A method for producing a fiber composite component, in particular for aerospace, includes the following method steps: introducing an elastic core sleeve into a prestressing mechanism; expanding the core sleeve that is introduced, for elastic prestressing of the same, by activating the prestressing mechanism; introducing a core body through an opening of the expanded core sleeve; releasing the core sleeve by deactivating the prestressing mechanism, for the snug enclosing of the core body by the core sleeve and thus for the forming of the molding core ( | 2010-02-25 |
20100044913 | METHOD FOR PRODUCING SURFACE CONVEXES AND CONCAVES - A method for producing surface convexes or concaves enabling easy and highly precise formation of desired convex/concave shapes using a photomask is provided. | 2010-02-25 |