| 08th week of 2010 patent applcation highlights part 17 |
| Patent application number | Title | Published |
|---|
| 20100044714 | DISPLAY DEVICE - The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of the same material as the pixel electrode is disposed to form the auxiliary capacitor by utilizing the pixel electrode. It allows a required value of auxiliary capacitor to be obtained without dropping the aperture ratio. Also, it allows the electrode pattern to function as a electrically shielding film for suppressing the cross-talk between the source and gate lines and the pixel electrode. | 2010-02-25 |
| 20100044715 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - A TFT array substrate including a substrate, a plurality of pixel structures and a plurality of cutting marks is provided. The substrate has a device region and a cutting mark region. The pixel structures are disposed in the device region and each pixel structure includes a TFT, a pixel electrode and a passivation layer covering the TFT. The cutting marks are within the cutting mark region, disposed at two sides of a predetermined cutting position, and are arranged as a row or column perpendicular to a predetermined cutting direction. In particular, the cutting marks are constituted of at least two colors, at least two shapes, at least one color and at least one shape, or a combination thereof. | 2010-02-25 |
| 20100044716 | PIXEL STRUCTURE AND LIQUID CRYSTAL DISPLAY PANEL - A pixel structure is disclosed. The pixel structure is suitable to be disposed on a substrate and includes a first pixel electrode, a second pixel electrode and a top gate TFT. The first pixel electrode and the second pixel electrode are disposed over the substrate, wherein the first pixel electrode and the second pixel electrode are separated from each other. The top gate TFT is disposed between the substrate and the first pixel electrode and includes a patterned semiconductor layer and a gate. | 2010-02-25 |
| 20100044717 | THIN FILM TRANSISTOR PANEL AND METHOD OF MANUFACTURING THE SAME - After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel. | 2010-02-25 |
| 20100044718 | Group III Nitride Articles and Methods for Making Same - Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films. | 2010-02-25 |
| 20100044719 | III-V Compound Semiconductor Epitaxy Using Lateral Overgrowth - A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer. | 2010-02-25 |
| 20100044720 | SEMICONDUCTOR DEVICE WITH A REDUCED BAND GAP AND PROCESS - The application relates to a semiconductor device made of silicon with regionally reduced band gap and a process for the production of same. One embodiment provides a semiconductor device including a body zone, a drain zone and a source zone. A gate extends between the source zone and the drain zone. A reduced band gap region is provided in a region of the body zone, made of at least ternary compound semiconductor material. | 2010-02-25 |
| 20100044721 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer | 2010-02-25 |
| 20100044722 | Sensing Module - A sensing module comprises a carrier, a sensor, a substrate, and a plurality of chips. The carrier has a carrying surface and a back surface opposite to the carrying surface. The sensor and the substrate are disposed on the carrying surface and are electrically connected to the carrier respectively. The chips are disposed on the substrate and are electrically connected to the substrate respectively. The production cost of the sensing module is low. | 2010-02-25 |
| 20100044723 | PACKAGE FOR PHOTOELECTRIC WIRING AND LEAD FRAME - A package for a photoelectric wiring in which a pair of light emitting and receiving devices are mounted as optical devices on a lead frame having an optical waveguide in which an optical waveguide having a plurality of core portions disposed in parallel and surrounded by a cladding is mounted on a support plate of a lead frame having a mirror section including the support plate for supporting the optical waveguide, mirror sections having a mirror surface portion formed by bending both edges of the support plate at an angle of 45 degrees with respect to a planar direction of the support plate in a side direction, and lead portions to be electrically connected to the optical devices, the support plate, the mirror sections and the lead sections being formed by pressing a metallic material, wherein the light emitting device and the light receiving device are mounted in alignment with an optical path of a light reflected by the mirror surface portion and transmitted through the core portions at one of sides and the other side which interpose the optical waveguide of the package for an optical waveguide wiring therebetween. | 2010-02-25 |
| 20100044724 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by reduction of the intensity of light emitted from the at least one active device in the integrated circuit thereby preventing the reduced intensity light emitted from the at least one active device in the integrated circuit from being detected external to the integrated circuit. The intensity of light emitted from the at least one active device in the integrated circuit can be reduced by modification of operational characteristics of the at least one active device during switching transitions. | 2010-02-25 |
| 20100044725 | DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS - An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by fading the light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit. Bright light emission emitted in substantial close proximity to the at least one active device in the integrated circuit, and emitted external to the integrated circuit, fades a pattern of light emission emitted from the at least one active device. | 2010-02-25 |
| 20100044726 | Method for Packaging White-Light LED and LED Device Produced Thereby - This invention relates to light-emitting diodes or devices (LEDs), such as LED lighting assemblies and methods of manufacturing them. More particularly, this invention relates to white-light LED lighting assemblies, devices, and components, methods for packaging white-light LEDs, and LED devices produced thereby. A method for packaging a white-light LED is provided comprising providing a substrate with a resin injection hole and a vent hole, a packaging housing, at least one LED chip, a supporting frame and resin, installing the LED chip on the substrate, coating an inner wall of the packaging housing with fluorescent powder, connecting the packaging housing to the substrate by way of the supporting frame, so that a cavity is formed therebetween, injecting the resin into the cavity between the packaging housing and the substrate by way of the resin injection hole so that gas within the cavity is discharged by way of the vent hole, and curing the resin. LED assemblies made according to this method are also provided. | 2010-02-25 |
| 20100044727 | LED PACKAGE STRUCTURE - A LED package structure includes an insulating ceramic base, whereon a first surface and a second surface are formed. The LED package structure further includes a casing disposed on the first surface of the insulating ceramic base. A hole is formed on the casing. The LED package structure further includes a heat-dissipating structure connected to the second surface of the insulting ceramic base, at least one LED chip, and at least one conductive circuit disposed inside the casing. The conductive circuit includes a first conductive portion, and a second conductive portion connected to the first conductive portion via the hole and electrically connected to the LED chip. | 2010-02-25 |
| 20100044728 | ELECTROLUMINESCENT DEVICE - An electroluminescent device includes, for example, first to third optical output parts respectively corresponding to red, green, and blue colors and each having a light-emitting layer. A visibility spectrum curve has an inclination value corresponding to the first optical output part, an inclination value corresponding to the second optical output part, and an inclination value corresponding to the third optical output part. Each inclination value corresponds to an emission peak wavelength at which an emission spectrum of a light ray emitted from the light-emitting layer of the corresponding optical output part reaches a maximum intensity value. The inclination values have the following relationship: first optical output part>second optical output part>third optical output part. The emission spectra of the optical output parts have widths in the following relationship: first optical output part>second optical output part>third optical output part. | 2010-02-25 |
| 20100044729 | WARM-WHITE LIGHT EMTITTING DIODE AND ITS HALIDE PHOSPHOR POWDER - The invention relates to a halide phosphor powder for warm-white light emitting diode, which is a kind of low-color-temperature phosphor powder of halide nitride based on garnet of rare earth oxides, uses cerium as activating agent and is characterized in that chloride (Cl | 2010-02-25 |
| 20100044730 | Organic light emitting diode display device and method of fabricating the same - An organic light emitting diode display device having a frit which can improve mechanical strength and adhesion between the upper substrate and the lower substrate, and a method of fabricating the same are disclosed. The organic light emitting diode display device includes a lower substrate, an organic light emitting diode disposed on the lower substrate, an upper substrate to be coupled to the lower substrate, and a frit disposed between the lower substrate and the upper substrate to couple both the lower substrate and the upper substrate to each other where the frit has a plurality of pores. | 2010-02-25 |
| 20100044731 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Such a semiconductor light-emitting device ( | 2010-02-25 |
| 20100044732 | Light Emitting Diode Structure and Method of Forming the Same - A light emitting diode structure and a light emitting diode structure forming method are provided. The light emitting diode structure includes a base, a diode chip, and a package lens. The diode chip is mounted on the base. The package lens covers the diode chip. The surface of the package lens includes a plurality of dot structures. The steps of the method include mounting a light-emitting diode chip on a base, assembling a package lens to cover the light emitting diodes chip, and forming a plurality of dot structures on the surface of the package lens. | 2010-02-25 |
| 20100044733 | ELECTROLUMINESCENCE ELEMENT - An electroluminescence element includes: an electroluminescence substrate including a thin film transistor substrate, and a light-emitting layer provided over the thin film transistor substrate and divided by picture-element separating portions so as to correspond to unit picture elements; and a sealing substrate arranged to hermetically seal the light-emitting layer of the electroluminescence substrate. At least one of the electroluminescence substrate and the sealing substrate is a flexible substrate. Spacers are provided between the electroluminescence substrate and the sealing substrate. | 2010-02-25 |
| 20100044734 | MANUFACTURING METHOD OF SEMICONDUCTOR LIGHT-EMITTING APPARATUS AND SEMICONDUCTOR LIGHT-EMITTING APPARATUS - A method includes forming a light-emission operating layer on a growth substrate; forming a reflection insulating layer on the light-emission operating layer; forming opening portions in the insulating layer; forming a contact portion which has a thickness adapted to flatten the opening portions and has been embedded into the opening portions; forming an electrode layer on the insulating layer and the contact portions; forming a first bonding metal layer on the electrode layer; preparing a supporting substrate in which a second bonding metal layer has been formed; and making the first and second bonding metal layers molten and joined. | 2010-02-25 |
| 20100044735 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate ( | 2010-02-25 |
| 20100044736 | Semiconductor apparatus and method of manufacturing same - Disclosed is a semiconductor apparatus having a sealing structure that allows high-precision detection of defects occurring in a protective film, and a method of manufacturing the same. A semiconductor apparatus | 2010-02-25 |
| 20100044737 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device (A) includes a lead frame ( | 2010-02-25 |
| 20100044738 | PREPARATION OF ORGANIC LIGHT EMITTING DIODES BY A VAPOUR DEPOSITION METHOD COMBINED WITH VACUUM LAMINATION - A method of fabricating an organic light emitting diode (OLED) is disclosed, which reduces the formation of physical defects in the GLED, comprising the removal of dust particles from a first and a second substrates ( | 2010-02-25 |
| 20100044739 | Light-Radiating Semiconductor Component with a Luminescence Conversion Element - The light-radiating semiconductor component has a radiation-emitting semiconductor body and a luminescence conversion element. The semiconductor body emits radiation in the ultraviolet, blue and/or green spectral region and the luminescence conversion element converts a portion of the radiation into radiation of a longer wavelength. This makes it possible to produce light-emitting diodes which radiate polychromatic light, in particular white light, with only a single light-emitting semiconductor body. A particularly preferred luminescence conversion dye is YAG:Ce. | 2010-02-25 |
| 20100044740 | SEMICONDUCTOR DEVICE - A semiconductor device with a substrate, a first electrode on the substrate, at least one of an injection layer or a transporting layer on the first electrode, an adhesion layer on the at least one of an injection layer or a transporting layer, and a second electrode on the adhesion layer. | 2010-02-25 |
| 20100044741 | LIGHTING DEVICE - A fighting device of the present invention includes light emitting unit | 2010-02-25 |
| 20100044742 | LIGHT EMITTING DIODE MODULE - The present invention relates to a light emitting diode module capable of facilitating the connection between light emitting diode modules. | 2010-02-25 |
| 20100044743 | Flip chip light emitting diode with epitaxial strengthening layer and manufacturing method thereof - A flip chip light emitting diode with an epitaxial strengthening layer and a manufacturing method thereof are revealed. The flip chip light emitting diode with an epitaxial strengthening layer includes an epitaxial structure connected with an epitaxial strengthening layer while the manufacturing method of the flip chip light emitting diode with an epitaxial strengthening layer is mainly to form an epitaxial strengthening layer on the epitaxial structure. Thus the epitaxial structure of the flip chip light emitting diode is strengthened so as to prevent breakage of the epitaxial structure while removing a substrate by laser assisted lift-off technique or other techniques. Moreover, the thermal expansion coefficient of the epitaxial strengthening layer matches well with thermal expansion coefficient of the epitaxial structure. Thus after being treated with cyclic heating, there is no stress caused by unmatched thermal expansion coefficient. Therefore, reliability of the flip chip light emitting diode with an epitaxial strengthening layer is improved. | 2010-02-25 |
| 20100044744 | LIGHT EMITTING DIODE HAVING EXTENSIONS OF ELECTRODES FOR CURRENT SPREADING - Disclosed is a light emitting diode having extensions of electrodes for improving current spreading. The light emitting diode includes a lower semiconductor layer, an upper semiconductor layer and an active layer, which are formed on a substrate. The upper semiconductor layer is located above the lower semiconductor layer such that edge regions of the lower semiconductor layer are exposed, and has indents indented in parallel with diagonal directions from positions in the edge regions adjacent to corners of the substrate in a clockwise or counterclockwise direction to expose the lower semiconductor layer. The indents have distal ends spaced apart from each other. Meanwhile, a lower electrode is formed on the exposed region of the lower semiconductor layer corresponding to the first corner of the substrate, and an upper electrode is formed on a transparent electrode layer on the semiconductor layer. Lower extensions extending from the lower electrode are formed on the exposed edge regions of the lower semiconductor layer and on the regions of the lower semiconductor layer exposed through the indents. An upper extension extending from the upper electrode are formed on the transparent electrode layer. The lower and upper extensions improve current spreading, particularly, in a light emitting diode with a large area. | 2010-02-25 |
| 20100044745 | OPTICAL SEMICONDUCTOR DEVICE MODULE WITH POWER SUPPLY THROUGH UNEVEN CONTACTS - In an optical semiconductor device module constructed by an optical semiconductor device having a light emitting portion on its top surface, a mounting substrate adapted to mount the optical semiconductor device thereon, at least one wiring pattern layer formed on a front surface of the mounting substrate, and at least one power supplying portion in contact with the wiring pattern layer, at least one of the power supplying portion and the wiring pattern layer is uneven. | 2010-02-25 |
| 20100044746 | CARRIER AND OPTICAL SEMICONDUCTOR DEVICE BASED ON SUCH A CARRIER - A method for providing, on a carrier ( | 2010-02-25 |
| 20100044747 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device (A | 2010-02-25 |
| 20100044748 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device includes a p-well with first protrudent portions, an N-well with second protrudent portions, a P-well/N-well boundary, a PMOS transistor disposed in the N-well, an NMOS transistor disposed in the P-well, first P+ diffusion regions in the first protrudent portions, first N+ diffusion regions in the second protrudent portions, second P+ diffusion regions disposed between the PMOS transistor and the second protrudent portions, second N+ diffusion regions disposed between the NMOS transistor and the first protrudent portions, third P+ diffusion regions disposed between the NMOS transistor, the boundary, and two adjacent second P+ diffusion regions, and third N+ diffusion regions disposed between the PMOS transistor, the boundary, and two adjacent second N+ diffusion regions, wherein the first and second protrudent portions are interlacedly arranged at the boundary. | 2010-02-25 |
| 20100044749 | BIDIRECTIONAL SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCORPORATING THE SAME - A semiconductor device and a method of fabrication thereof includes a bidirectional device having a high breakdown voltage and a decreased ON voltage. An n-type extended drain region is formed in the bottom surface of each trench. A p-type offset region is formed in each split semiconductor region. First and second n-source regions are formed in the surface of the p-type offset region. This reduces the in-plane distance between the first and second n-source regions to thereby increase the density of cells. The breakdown voltage is maintained along the trenches. This increases the resistance to high voltages. Channels are formed in the sidewalls of the trenches by making the voltage across each gate electrode higher than the voltage across each of the first and second n-source electrodes. Thus, a bidirectional LMOSFET through which current flows in both directions is achieved. The LMOSFET has a high breakdown voltage and a decreased ON voltage. | 2010-02-25 |
| 20100044750 | ELECTROSTATIC PROTECTION ELEMENT - An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer. | 2010-02-25 |
| 20100044751 | ENHANCEMENT MODE III-NITRIDE DEVICE WITH FLOATING GATE AND PROCESS FOR ITS MANUFACTURE - An enhancement mode III-Nitride device has a floating gate spaced from a drain electrode which is programmed by charges injected into the floating gate to form a permanent depletion region which interrupts the 2-DEG layer beneath the floating gate. A conventional gate is formed atop the floating gate and is insulated therefrom by a further dielectric layer. The device is a normally off E mode device and is turned on by applying a positive voltage to the floating gate to modify the depletion layer and reinstate the 2-DEG layer. The device is formed by conventional semiconductor fabrication techniques. | 2010-02-25 |
| 20100044752 | Semiconductor device and manufacturing method - A metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) has a substrate in which an electron supply layer is interposed between an electron channel layer and the surface of the substrate. A pair of main electrodes are formed on the surface of the substrate. A recess is formed in the surface of the substrate between the main electrodes. A gate insulation film is formed on the surface of the substrate, at least between the first and second main electrodes, covering the inside walls and floor of the recess. A gate electrode is formed on the gate insulation film, filling in the recess. The gate insulation film has a crystal density of at least 2.9 g/cm | 2010-02-25 |
| 20100044753 | SEMICONDUCTOR DEVICE - A nitride semiconductor device | 2010-02-25 |
| 20100044754 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 2010-02-25 |
| 20100044755 | SEMICONDUCTOR DEVICE - A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch. | 2010-02-25 |
| 20100044756 | METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE - A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided. | 2010-02-25 |
| 20100044757 | SEMICONDUCTOR DEVICE HAVING A CONTACT PLUG AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, arid a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the drain region; a second inter-layer insulation film covering the first contact plug; a groove extending in the second inter-layer insulation film in a same direction as an extending direction of the gate electrode and exposing a top surface of the first contact plug at a bottom thereof; a second contact plug connected to the first contact plug and formed in the groove; and a wiring pattern extending on the second inter-layer insulation film so as to traverse the groove and integrated with the second contact plug. | 2010-02-25 |
| 20100044758 | CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS - An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different from each other. A volume of material is formed that extends through the first layer from the second layer up to the surface of the first layer. The material has a crystalline orientation that substantially matches the orientation of the second layer. Areas of the surface of the first layer that are outside of the region are selectively etched to create a first plurality of fins and areas inside the region to create a second plurality of fins. The etching leaves the first and second pluralities of fins parallel to each other with different surface crystal orientations. | 2010-02-25 |
| 20100044759 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 2010-02-25 |
| 20100044760 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 2010-02-25 |
| 20100044761 | SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME - A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region. | 2010-02-25 |
| 20100044762 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF - A non-planar semiconductor device ( | 2010-02-25 |
| 20100044763 | Method and apparatus providing an imager with a shared power supply and readout line for pixels - A method and apparatus providing an imager with shared power supply and readout lines. A pixel array has a plurality of pixels arranged in rows and columns. Each column of the array comprises a column line coupled to receive pixel signals from the pixels in the column and selectively operated to provide a supply voltage to at least one pixel in a different column. | 2010-02-25 |
| 20100044764 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same are provided. The CMOS image sensor includes: a first conductive type substrate including a trench; a channel stop layer formed by using a first conductive type epitaxial layer over an inner surface of the trench; a device isolation layer formed on the channel stop layer to fill the trench; a second conductive type photodiode formed in a portion of the substrate in one side of the channel stop layer; and a transfer gate structure formed on the substrate adjacent to the photodiode to transfer photo-electrons generated from the photodiode. | 2010-02-25 |
| 20100044765 | SEMICONDUCTOR DEVICE - Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches ( | 2010-02-25 |
| 20100044766 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×10 | 2010-02-25 |
| 20100044767 | STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS - A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer. | 2010-02-25 |
| 20100044768 | REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS - An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. | 2010-02-25 |
| 20100044769 | METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas. | 2010-02-25 |
| 20100044770 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, forming a diffusion barrier for preventing metal diffusion over the insulation layer, forming a gate electrode layer over the diffusion barrier, forming a metal layer over the gate electrode layer, and performing a thermal treatment process on the substrate structure to form a metal silicide layer having a uniform thickness. | 2010-02-25 |
| 20100044771 | Zr-Sn-Ti-O FILMS - A dielectric layer containing a Zr—Sn—Ti—O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO | 2010-02-25 |
| 20100044772 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR DEVICE - A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed. | 2010-02-25 |
| 20100044773 | SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device having an improved write efficiency because deterioration of a gate insulating film is suppressed. | 2010-02-25 |
| 20100044774 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed here in is a flash memory device and a method of fabricating the same. In accordance with one aspect of the invention, a flash memory device includes first contact plugs formed over a semiconductor substrate between gate patterns. Second contact plugs are formed over the semiconductor substrate between gate patterns and disposed alternately with the first contact plugs. The second contact plugs having a height greater than the first contact plugs. First and second conductive pads are connected to the first contact plugs. First and second pad contact plugs are formed on extended edge portions of the first and second conductive pads. First bit lines are connected to the first and second pad contact plugs, and second bit lines are connected to the second contact plugs. | 2010-02-25 |
| 20100044775 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - Provided is a semiconductor memory device that can retain information by trapping electric charges into a trap level in a gate insulating film. The information retention capacity is improved by restricting lateral diffusion of electric charges. The semiconductor memory device is provided with a semiconductor substrate ( | 2010-02-25 |
| 20100044776 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell. | 2010-02-25 |
| 20100044777 | RECONFIGURABLE SEMICONDUCTOR DEVICE - A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer. | 2010-02-25 |
| 20100044778 | Non-volatile memory device and method of manufacturing same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer. | 2010-02-25 |
| 20100044779 | Memory devices capable of reducing lateral movement of charges - Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell. | 2010-02-25 |
| 20100044780 | TRANSISTOR WITH GAIN VARIATION COMPENSATION - A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel. | 2010-02-25 |
| 20100044781 | SEMICONDUCTOR DEVICE - To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed. | 2010-02-25 |
| 20100044782 | INTEGRATED CIRCUIT HAVING LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate. | 2010-02-25 |
| 20100044783 | INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION - A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate. | 2010-02-25 |
| 20100044784 | Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same - A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region. | 2010-02-25 |
| 20100044785 | HIGH ASPECT RATIO TRENCH STRUCTURES WITH VOID-FREE FILL MATERIAL - A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench. | 2010-02-25 |
| 20100044786 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in the semiconductor layer when seen in a plan view; a trench gate formed in a grid fashion in the semiconductor layer so that each of the first column regions is surrounded by the trench gate when seen in a plan view, the trench gate penetrating through the base region to reach the semiconductor layer of the first conductivity type; and a plurality of second column regions of the second conductivity type selectively formed below each intersection of the grid of the trench gate except line section of the trench gate. | 2010-02-25 |
| 20100044787 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes the following processes. A first gate trench is formed if a semiconductor substrate region. Then a first insulating film is formed to cover bottom and side surfaces of the first gate trench. Then, the first insulating film is removed to cover the bottom surface. Then, the semiconductor substrate region exposed to the first gate trench is etched by the first insulating film covering the side surfaces as a mask, to form, in the semiconductor substrate region, a second gate trench directly below the first gate trench. The second gate trench is defined by an unetched film portion of the semiconductor substrate region. The unetched film portion extends toward one of the side surfaces of the first gate trench. | 2010-02-25 |
| 20100044788 | SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE AND PROCESS - A semiconductor device with a charge carrier compensation structure. In one embodiment, the semiconductor device has a central cell field with a gate and source structure. At least one bond contact area is electrically coupled to the gate structure or the source structure. A capacitance-increasing field plate is electrically coupled to at least one of the near-surface bond contact areas. | 2010-02-25 |
| 20100044789 | Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. | 2010-02-25 |
| 20100044790 | Semiconductor device and method of etc. - Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the local oxidation-of-silicon (LOCOS) offset MOS transistor having high withstanding voltage, in order to prevent a gate oxide film ( | 2010-02-25 |
| 20100044791 | Configurations and methods for manufacturing charge balanced devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material. | 2010-02-25 |
| 20100044792 | Charged balanced devices with shielded gate trench - This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown. | 2010-02-25 |
| 20100044793 | SEMICONDUCTOR DEVICE HAVING A PLURALITY OF MISFETS FORMED ON A MAIN SURFACE OF A SEMICONDUCTOR SUBSTRATE - In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs | 2010-02-25 |
| 20100044794 | ASYMMETRIC MULTI-GATED TRANSISTOR AND METHOD FOR FORMING - In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin. | 2010-02-25 |
| 20100044795 | Logic Switch and Circuits Utilizing the Switch - A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described. | 2010-02-25 |
| 20100044796 | Depletion mode trench MOSFET for improved efficiency of DC/DC converter applications - A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate shorted to a source of the low-side enhancement mode MOSFET. A current transmitting in the DC-to-DC converter within a time-period between T | 2010-02-25 |
| 20100044797 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased. | 2010-02-25 |
| 20100044798 | TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation. | 2010-02-25 |
| 20100044799 | METHOD FOR MANUFACTURING A P-TYPE MOS TRANSISTOR, METHOD FOR MANUFACTURING A CMOS-TYPE SEMICONDUCTOR APPARATUS HAVING THE P-TYPE MOS TRANSISTOR, AND CMOS-TYPE SEMICONDUCTOR APPARATUS MANUFACTURED USING THE MANUFACTURING METHOD - A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni). | 2010-02-25 |
| 20100044800 | High-K dielectric metal gate device structure - A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. | 2010-02-25 |
| 20100044801 | DUAL METAL GATE CORNER - In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated. | 2010-02-25 |
| 20100044802 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method. | 2010-02-25 |
| 20100044803 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 2010-02-25 |
| 20100044804 | NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length. | 2010-02-25 |
| 20100044805 | METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS - A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer. | 2010-02-25 |
| 20100044806 | INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION - A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric. | 2010-02-25 |
| 20100044807 | CMOS-Compatible Microstructures and Methods of Fabrication - The present invention addresses the aims and issues of making multi layer microstructures including “metal-shell-oxide-core” structures and “oxide-shell-metal-core” structures, and mechanically constrained structures and the constraining structures using CMOS (complimentary metal-oxide-semiconductor transistors) materials and layers processed during the standard CMOS process and later released into constrained and constraining structures by etching away those CMOS materials used as sacrificial materials. The combinations of possible constrained structures and methods of fabrication are described. | 2010-02-25 |
| 20100044808 | METHOD OF MANUFACTURING A MEMS ELEMENT - The device ( | 2010-02-25 |
| 20100044809 | Sensor Device Packaging And Method - A sensor device and a method of forming comprises a die pad receives a sensor device, such as a MEMS device. The MEMS device has a first coefficient of thermal expansion (CTE). The die pad is made of a material having a second CTE compliant with the first CTE. The die pad includes a base and a support structure with a CTE compliant with the first and second CTE. The die pad has a support structure that protrudes from a base. The support structure has a height and wall thickness which minimize forces felt by the die pad and MEMS device when the base undergoes thermal expansion or contraction forces from a header. | 2010-02-25 |
| 20100044810 | Semiconductor Structural Element - The semiconductor component is intended for a sensor, in particular for a pressure sensor or differential pressure sensor, and includes a semiconductor substrate ( | 2010-02-25 |
| 20100044811 | INTEGRATED CIRCUIT ENCAPSULATION AND METHOD THEREFOR | 2010-02-25 |
| 20100044812 | STRATIFIED PHOTODIODE FOR HIGH RESOLUTION CMOS IMAGE SENSOR IMPLEMENTED WITH STI TECHNOLOGY - A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages. | 2010-02-25 |
| 20100044813 | OPTICALLY CONTROLLED READ ONLY MEMORY - An optically controlled read only memory is disclosed. The optically controlled read only memory includes a substrate, a plurality of memory cells having optical sensors disposed on the substrate, and at least one shielding structure disposed on the optical sensor, in which the shielding structure selectively shields a portion of the optical sensor according to a predetermined layout. Preferably, the optically controlled read only memory of the present invention is capable of providing two types or more program codes and outputting different program codes carrying different function under different lighting condition. | 2010-02-25 |
