08th week of 2012 patent applcation highlights part 24 |
Patent application number | Title | Published |
20120044731 | Method and Apparatus for Boosting DC Bus Voltage - A power converter includes at least two power conversion sections operating in parallel. The power converter receives a variable input power and generates an AC output voltage. When the power source is generating enough power to supply a DC voltage to the power converter greater than or equal to the peak magnitude of the desired AC voltage output, each power conversion section operates in parallel, converting the DC voltage to the desired AC voltage output. When the power generated by the variable power source results in a DC voltage having a magnitude less than the peak magnitude of the desired AC voltage output, the power conversion sections operate in series. One power conversion section operates as a boost converter to boost the DC voltage level to a suitable level for the second power conversion section, which generates the desired AC output voltage. | 2012-02-23 |
20120044732 | ISOLATED EPITAXIAL MODULATION DEVICE - An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage. | 2012-02-23 |
20120044733 | Single Device Driver Circuit to Control Three-Dimensional Memory Element Array - A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal. | 2012-02-23 |
20120044734 | BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME - A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i complementary bit lines are arranged in an i | 2012-02-23 |
20120044735 | STRUCTURES WITH INCREASED PHOTO-ALIGNMENT MARGINS - Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery. | 2012-02-23 |
20120044736 | MEMORY DEVICES USING A PLURALITY OF DIODES AS PROGRAM SELECTORS FOR MEMORY CELLS - At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations. | 2012-02-23 |
20120044737 | CIRCUIT AND SYSTEM OF USING POLYSILICON DIODE AS PROGRAM SELECTOR FOR ONE-TIME PROGRAMMABLE DEVICES - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to an OTP element coupled to the P-terminal of a diode and switching the N-terminal of a diode to a low voltage for suitable duration of time, a current flows through the OTP element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the OTP element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area. | 2012-02-23 |
20120044738 | ONE-TIME PROGRAMMABLE MEMORIES USING POLYSILICON DIODES AS PROGRAM SELECTORS - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s). | 2012-02-23 |
20120044739 | CIRCUIT AND SYSTEM OF USING JUNCTION DIODE AS PROGRAM SELECTOR FOR ONE-TIME PROGRAMMABLE DEVICES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact. | 2012-02-23 |
20120044740 | ONE-TIME PROGRAMMABLE MEMORIES USING JUNCTION DIODES AS PROGRAM SELECTORS - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The OTP device has an OTP element coupled to the diode. The OTP device can be used to construct a two-dimensional OTP memory with the N terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s). | 2012-02-23 |
20120044741 | Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method - A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer. | 2012-02-23 |
20120044742 | VARIABLE RESISTANCE MEMORY ARRAY ARCHITECTURE - Memory devices, memory arrays, and methods of operation of memory arrays are disclosed. In one such memory device, a parallel selection architecture includes a control element, such as a selection transistor, in parallel with a variable resistance memory cell. Biasing of the selection transistor enables access to the memory cell for reading, programming, and/or erasing. Programming and erasing of the memory cell is accomplished through a change of resistance of the memory cell. | 2012-02-23 |
20120044743 | CIRCUIT AND SYSTEM OF USING A POLYSILICON DIODE AS PROGRAM SELECTOR FOR RESISTIVE DEVICES IN CMOS LOGIC PROCESSES - Polysilicon diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to a resistive element coupled to the P terminal of a diode and switching the N terminal of a diode to a low voltage for proper time, a current flows through a resistive element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P+ and N+ implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the resistive element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area. | 2012-02-23 |
20120044744 | PROGRAMMABLY REVERSIBLE RESISTIVE DEVICE CELLS USING POLYSILICON DIODES - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices such as PCRAM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a voltage or a current between a reversible resistive element and the N-terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. | 2012-02-23 |
20120044745 | REVERSIBLE RESISTIVE MEMORY USING POLYSILICON DIODES AS PROGRAM SELECTORS - Embodiments of reversible resistive memory cells using polysilicon diodes are disclosed. The programmable resistive devices can be fabricated using standard CMOS logic processes to reduce cell size and cost. In one embodiment, polysilicon diodes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCRAM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a polysilicon diode. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector. The memory cells can be used to construct a two-dimensional memory array with the N-terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s). | 2012-02-23 |
20120044746 | CIRCUIT AND SYSTEM OF USING A JUNCTION DIODE AS PROGRAM SELECTOR FOR RESISTIVE DEVICES - Junction diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for proper duration of time, a current flows through a resistive element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal can be connected in a single rectangular contact. | 2012-02-23 |
20120044747 | REVERSIBLE RESISTIVE MEMORY USING DIODES FORMED IN CMOS PROCESSES AS PROGRAM SELECTORS - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s). | 2012-02-23 |
20120044748 | Sensing Circuit For Programmable Resistive Device Using Diode as Program Selector - A sensing circuit for programmable resistive device using diode as program selector is disclosed. The sensing circuit can have a reference and a sensing branch. In one embodiment, each branch can have a first type of MOS with the source coupled to a first supply voltage, the drain coupled to the drain of a second type of MOS, which can have the gate coupled to a bias supply voltage. The sources of the second type of MOS in the reference and sensing branches can be coupled to a reference resistor and a programmable resistance element, respectively, and they are further coupled to a second supply voltage through their diodes. The gate of the first type of MOS in the sensing branch can be coupled to the gate of the first type of MOS in the reference branch, which can have the drain coupled to the gate. The resistance difference between the reference resistor and the programmable resistive element can be sensed through the drain of the first type of MOS in the sensing branch into a logic level. | 2012-02-23 |
20120044749 | VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD OF FORMING MEMORY CELL - A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate ( | 2012-02-23 |
20120044750 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell array having a plurality of first wirings and a plurality of second wirings intersecting each other and memory cells disposed at intersections between the plurality of first wirings and the plurality of second wirings. The semiconductor memory device further includes a control circuit for selectively driving the plurality of first wirings and the plurality of second wirings. The control circuit applies a first voltage for a first operation to a first select wiring and applies a second voltage for a second operation different from the first operation to a second select wiring and applies a third voltage for the first and second operation to a third select wiring. The first operation is completed before the second operation is completed. The control circuit applies a fourth voltage for a third operation to a forth select wiring before the second operation is completed. | 2012-02-23 |
20120044751 | BIPOLAR RESISTIVE-SWITCHING MEMORY WITH A SINGLE DIODE PER MEMORY CELL - According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell. | 2012-02-23 |
20120044752 | HIGH DENSITY INTEGRATED CIRCUITRY FOR SEMICONDUCTOR MEMORY - Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells. | 2012-02-23 |
20120044753 | PROGRAMMABLY REVERSIBLE RESISTIVE DEVICE CELLS USING CMOS LOGIC PROCESSES - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. | 2012-02-23 |
20120044754 | Spin-Torque Transfer Magneto-Resistive Memory Architecture - A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLT | 2012-02-23 |
20120044755 | System and Method of Reference Cell Testing - In a particular embodiment, a method of testing a reference cell in a memory array includes coupling a first reference cell of a first reference cell pair of the memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array. | 2012-02-23 |
20120044756 | MEMORY DEVICES USING A PLURALITY OF DIODES AS PROGRAM SELECTORS WITH AT LEAST ONE BEING A POLYSILICON DIODE - Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal of a first diode and to the N-terminal of a second diode. At least one of the diodes can be a polysilicon diode fabricated using standard CMOS processes. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to a resistive element and switching the N-terminal of the first diode to a low voltage while disabling the second diode, a current flowing through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P-terminal of the second diode to a high voltage while disabling the first diode, a current flowing through the memory cell can change the resistance into another state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. A Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. | 2012-02-23 |
20120044757 | MEMORY USING A PLURALITY OF DIODES AS PROGRAM SELECTORS WITH AT LEAST ONE BEING A POLYSILICON DIODE - Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal of a first diode and to the N-terminal of a second diode. At least one of the diodes can be a polysilicon diode fabricated using standard CMOS processes with P+ and N+ implants in two ends. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector. The memory cells can be used to construct a two-dimensional memory array with the N-terminals of the first diodes and the P-terminals of the second diodes in a row connected as wordline(s) and the resistive elements in a column connected as a bitline. | 2012-02-23 |
20120044758 | CIRCUIT AND SYSTEM OF USING AT LEAST ONE JUNCTION DIODE AS PROGRAM SELECTOR FOR MEMORIES - At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for memory cells that can be programmed based on direction of current flow. These cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to a P terminal of a first diode and to an N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the first diodes and the P terminals of the second diodes in a row connected as wordline(s) and the resistive elements in a column connected as a bitline. By applying a high voltage to a selected bitline and a low voltage to a selected wordline to turn on the first diode while disabling the second diode, a selected cell can be programmed into one state. Similarly, by applying a low voltage to a selected bitline and a high voltage to a selected wordline to turn on the second diode while disabling the first diode, a selected cell can be programmed into another state. The data in the resistive memory cell can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s). | 2012-02-23 |
20120044759 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A nonvolatile semiconductor memory device has a first select transistor having a gate connected to a first select word line extending in a column direction, a source connected to a first sub bit line, and a drain connected to a first main bit line extending in a row direction, and a second select transistor having a gate connected to a second select word line extending in the column direction, a source connected to a second sub bit line, and a drain connected to a second main bit line extending in the row direction. The second select transistor has a lower breakdown voltage than the first select transistor. | 2012-02-23 |
20120044760 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A nonvolatile semiconductor memory device has a first select transistor having a gate electrode connected to a first select word line, a source connected to a first sub bit line, and a drain connected to a first main bit line, and a second select transistor having a gate electrode connected to a second select word line, a source connected to a second sub bit line, and a drain connected to a second main bit line. The first sub bit lines are controlled by the first select transistor so as to be electrically isolated from each other between memory cell groups each formed by the memory cells to be erased simultaneously. On the other hand, the second sub bit lines are connected in common to the memory cells of memory cell groups to be erased separately, by the second select transistor. | 2012-02-23 |
20120044761 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method of 4-bit MLC programming a nonvolatile memory device includes inputting an m | 2012-02-23 |
20120044762 | REJUVENATION OF ANALOG MEMORY CELLS - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 2012-02-23 |
20120044763 | Non-Volatile Memory and Semiconductor Device - There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. | 2012-02-23 |
20120044764 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command. | 2012-02-23 |
20120044765 | WORD LINE ACTIVATION IN MEMORY DEVICES - Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address spaces. Each address space has a corresponding configuration control bus. By identifying the address space to which a word line belongs, its appropriate configuration control bus may be selected and the control signals from the selected bus used to select the appropriate potentials for driving the word lines. | 2012-02-23 |
20120044766 | SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage. | 2012-02-23 |
20120044767 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range. | 2012-02-23 |
20120044768 | PROGRAMMING TO MITIGATE MEMORY CELL PERFORMANCE DIFFERENCES - Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage difference between the maximum threshold voltage and a maximum target voltage is used as a gate step voltage for a second programming voltage. Fast and slow programming memory cells are determined from the distribution resulting from the second programming voltage. An effective gate voltage applied to the control gates of the fast programming memory cells is less than an effective gate voltage applied to the control gates of the slow programming memory cells during the third programming voltage. | 2012-02-23 |
20120044769 | MULTI-PASS PROGRAMMING IN A MEMORY DEVICE - A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further. | 2012-02-23 |
20120044770 | NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS flash memory array - A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process. | 2012-02-23 |
20120044771 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES FOR PERFORMING THE METHOD - A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation. | 2012-02-23 |
20120044772 | NON-VOLATILE MEMORY DEVICE, SYSTEM, AND CELL ARRAY - A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line. | 2012-02-23 |
20120044773 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal. | 2012-02-23 |
20120044774 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 2012-02-23 |
20120044775 | Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 2012-02-23 |
20120044776 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in an active state, in which a data signal can be received, while the control signal is in an active state, and otherwise controlled to be in an inactive state. | 2012-02-23 |
20120044777 | SEMICONDUCTOR DEVICE - By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request. | 2012-02-23 |
20120044778 | Semiconductor Device, Method for Inspecting the Same, and Method for Driving the Same - A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited. | 2012-02-23 |
20120044779 | DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY - A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation. | 2012-02-23 |
20120044780 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit of a semiconductor memory apparatus includes: a data control driver configured to drive rising data and falling data to output control rising data and control falling data or drive level data to output the control rising data and the control falling data, in response to an output level test signal; a DLL clock control unit configured to drive a rising clock and a falling clock to output a control rising clock and a control falling clock in response to an enable signal and the output level test signal; and a clock synchronization unit configured to synchronize the control rising data and the control falling data with the control rising clock and the control falling clock to output serial rising data and serial falling data. | 2012-02-23 |
20120044781 | Perfected cylindrical tank for the thermal treatment of a food mixture in general and machine for the production of food mixtures equipped with this cylindrical tank - The invention relates to a cylindrical tank for the thermal treatment of a food product, of the type including heating and/or cooling means of the food product, in addition to a mixer housed so as to be revolving in its interior. The tank has a cylindrical mantle, closed by a rear bottom and a front cover, there also being means (for feeding the product inside the tank. At least one temperature sensor of the food product is also situated in correspondence with this cover, with a sensitive part which, when the cover is closed, is in contact with the product contained in the tank. | 2012-02-23 |
20120044782 | Method for swell noise detection and attenuation in marine seismic surveys - Spatial data sequences are extracted in a frequency-space domain at selected frequencies in selected data windows in seismic data. A signal model and residuals are iteratively constructed for each extracted spatial data sequence. Each data sample in each extracted spatial data sequence is assessed to determine if the data sample is noisy. Each noisy data sample in each data sequence is replaced by a corresponding signal model value. The earth's subsurface is imaged using the noise-attenuated seismic data. | 2012-02-23 |
20120044783 | ACOUSTIC WAVEFORM STACKING USING AZIMUTHAL AND/OR STANDOFF BINNING - A method for making acoustic logging measurements includes grouping received acoustic waveforms into one of a plurality of groups, each group being representative of a measured borehole condition (e.g., a range of measured standoff values and/or a range of measured azimuth angles). The waveforms stored in at least one of the groups are stacked so as to obtain an averaged waveform. The averaged waveform may be further processed, for example, via a semblance algorithm to obtain at least one acoustic wave slowness. | 2012-02-23 |
20120044784 | DETERMINING A POSITION OF A GEOLOGICAL LAYER RELATIVE TO A WAVELET RESPONSE IN SEISMIC DATA - Determining geological layer location in a subterranean formation, including receiving seismic data representing an interaction of the geological layer with propagation of a seismic wave, identifying a source wavelet representing a portion of the seismic wave impinging on a boundary of the geological layer, providing a geological layer template of the geological layer including primary and secondary reflection interfaces associated with reflectivity based on material properties of the geological layer, generating a wavelet response template by applying the source wavelet to the geological layer template using a mathematical convolution operation to model seismic wave interference caused by the primary and secondary reflection interfaces, identifying an extremum of the seismic data, and determining, based on the extremum, the location of the geological layer in the subterranean formation using the wavelet response template. | 2012-02-23 |
20120044785 | MEASURING APPARATUS - Provided is a measuring apparatus, including: a moving mechanism for moving a probe in an elevation direction; a first delay and sum circuit for performing delay and sum of reception signals at individual positions along the elevation direction to output a first add signal; a signal extraction circuit for letting an output of the first delay and sum circuit to pass through delay circuits to output in parallel first add signals obtained at different positions; a second delay and sum circuit for performing delay and sum of the first add signals output from the signal extraction circuit to output a second add signal; and an image processing circuit for generating image data by using the second add signal. Accordingly, image resolution in the elevation direction may be improved with a simple structure without deteriorating an image obtaining speed in the measuring apparatus for obtaining an ultrasonic image. | 2012-02-23 |
20120044786 | ACOUSTIC POSITION-DETERMINATION SYSTEM - The position of a mobile unit ( | 2012-02-23 |
20120044787 | Stepping motor control circuit and analogue electronic watch - The invention is intended to achieve detection of a source voltage without providing a voltage detection circuit and allow a drive stop while holding correct drive pulse information when the source voltage is lowered to a predetermined level or below. A detection segment for detecting the state of rotation of a stepping motor is divided into a plurality of segments and, when a pattern of an induced signal detected in the respective segments is a pattern which indicates that the voltage of a secondary battery is lowered to the predetermined voltage or below, the control circuit memorizes a polarity of the drive pulse used in the last driving in a polarity memory and stops the driving of the stepping motor. When the voltage of the secondary battery is restored to the predetermined voltage or higher, the driving is restarted by a main drive pulse having a polarity opposite from the polarity memorized in the polarity memory. | 2012-02-23 |
20120044788 | Timepiece Dial, Method of Manufacturing a Timepiece Dial, and a Timepiece - A timepiece dial has excellent transparency to electromagnetic waves (radio and light), and an excellent appearance, a timepiece dial manufacturing method enables manufacturing the timepiece dial, and a timepiece has the timepiece dial. The timepiece dial | 2012-02-23 |
20120044789 | BARREL FOR A SELF WINDING TIMEPIECE - Barrel for a self-winding timepiece including a drum of axis AA provided with an internal lateral wall having friction surfaces alternating with locking structures forming salient or inward edges at the boundary of the friction surfaces and a mainspring forming a winding including an outer coil, which is friction coupled to said internal lateral wall and free to slip against said internal lateral wall in the event of overwinding of the mainspring, characterized in that said friction surfaces are demarcated, downstream relative to the direction in which said outer coil slips, by a rounded salient edge or an inward edge. | 2012-02-23 |
20120044790 | HEAD GIMBAL ASSEMBLY WITH TWO WIRING LAYERS COMPRISING THERMALLY-ASSISTED HEAD - Provided is a head gimbal assembly (HGA) in which the electrodes for a thermally-assisted magnetic recording head comprising a light source, a photodetector and a magnetic head element, can be reliably electrically connected to wiring members by solder ball bonding (SBB). The HGA comprises a suspension comprising: a base; a first wiring member for the light source and the photodetector, provided on a side of one surface of the base; and a second wiring member for the magnetic head element, provided on the same surface side. The first and second wiring members protrude from the base toward the head to be fixed. As a result, the end portions (connection pads) of the first and second wiring members can be located close to electrodes for light-source and photodetector and electrodes for magnetic head element, respectively. This arrangement enables the end portions of the first and second wiring members to be reliably electrically connected to the electrodes by SBB. | 2012-02-23 |
20120044791 | RECORDING APPARATUS - A recording apparatus, which records information in an optical recording medium, includes: a mode-lock laser unit including a saturable absorber section that applies a bias voltage, a gain section that feeds a gain current, a semiconductor laser that emits laser light used to record the information on the optical recording medium, and an external resonator; an optical modulation unit performing amplification modulation on the laser light emitted from the mode-lock laser unit; a reference signal generation unit generating a master clock signal and supplying a signal synchronized with the master clock signal to the gain section of the semiconductor laser; a recording signal generation unit generating a recoding signal based on the master clock signal; and a driving circuit generating a driving pulse used to drive the optical modulation unit based on the recording signal. | 2012-02-23 |
20120044792 | METHOD AND APPARATUS FOR DETERMINING AN OPTIMAL FOCUS BIAS AND SPHERICAL ABERRATION COMPENSATING VALUE IN AN OPTICAL DISC DRIVE - A method for determining an optimal combination of focus bias and spherical aberration compensating value (SA value) in an optical disc drive is provided. Firstly, a first focus bias is set, the SA values are adjusted and the corresponding tracking error signal values are measured. Second-order-approximation is performed to obtain a first maximum value of tracking error signal. Secondly, a second focus bias is set, the SA values are adjusted and the corresponding tracking error signal values are measured. Second-order-approximation is performed to obtain a second maximum value of tracking error signal. Thirdly, a third focus bias is set, the SA values are adjusted and the corresponding tracking error signal values are measured. Second-order-approximation is performed to obtain a third maximum value of the tracking error signal. The three maximum values are compared to obtain the optimal combination of focus bias and SA compensating value in the optical disc drive. | 2012-02-23 |
20120044793 | RECORDING DEVICE AND OPTICAL OSCILLATOR DEVICE - A recording device that records information in an optical recording medium includes: a self excited oscillation semiconductor laser including a saturable absorber section to apply a bias voltage and a gain section to inject a gain current, and also emitting a laser light to record the information in the optical recording medium; a reference signal generation unit generating a master clock signal and also supplying an injection signal synchronized with the master clock signal to the gain section of the self excited oscillation semiconductor laser; and a recording signal generation unit generating a recording signal based upon the master clock signal and also applying the recording signal to the saturable absorber section of the self excited oscillation semiconductor laser as the bias voltage. | 2012-02-23 |
20120044794 | DISCRIMINATION METHOD OF OPTICAL DISC - A discrimination method of an optical disc. The method includes: focusing a light spot on a rewritable zone of the optical disc; reading an EFM signal of data marks of the optical disc to check if the optical disc is a data disc or a blank disc; when the optical disc is a data disc, utilizing an SBAD signal for discrimination of the optical disc; when the optical disc is a blank disc, utilizing a DPD signal for discrimination of the optical disc; checking if the header signals exist or not; identifying the optical disc as a DVD-RAM disc if the header signals exist; and identifying the optical disc as a DVD-RW disc if there is no header signal. In this way, the accuracy of the optical disc discrimination is enhanced. | 2012-02-23 |
20120044795 | Optical Disc Drive - Bandwidth is secured for a read signal transmission line by matching the characteristic impedance of the read signal transmission line with the output impedance of a photodetector of an optical pick up, while at the same time securing bandwidth for the photodetector. In an optical disc drive according to an embodiment of the present invention, each line forming a differential transmission line is divided into a plurality of lines of the same quantity, the quantity being two or more, at or near a connection point between a flexible line and the optical pick up. | 2012-02-23 |
20120044796 | METHOD FOR GENERATING SIGNAL PATTERN USING MODULUS OR SEQUENCE, AND DEVICE THEREOF - Disclosed are a method and an apparatus for generating signal patterns used for a transmission/reception process between a terminal and a base station by using a modular sonar sequence. | 2012-02-23 |
20120044797 | Method and Equipment for Sending Radio Link Layer Status Package - The present invention discloses a method and a device for sending a radio link layer status package, and the sending method comprises: when the universal terrestrial radio access network detects that there is data to be sent which has been sent but has not been acknowledged, if a response from a receiving side is not received after a radio link layer status package is sent to the receiving side, a reset operation of the radio link layer is executed. The present invention resets the radio link control layer in time when the path between the universal terrestrial radio access network and the receiving side is failed or invalid, therefore it is advantageous to maintain the stability and self-recovery of system. | 2012-02-23 |
20120044798 | Data Retransmission Method and User Equipment - Embodiments of the present invention provide a data retransmission method and user equipment, where the method includes: if a network indicates switching from a dual stream transmission mode to a single stream transmission mode, stopping data transmission of one data stream and clearing data in an HARQ process of the stopped data stream; or if a network indicates switching from a single stream transmission mode to a dual stream transmission mode, transmitting retransmission data in an HARQ process of the original data stream without changing the HARQ process number, and transmitting new data in the HARQ process of a new data stream; or using the retransmission data of the original data stream as new data to transmit in the HARQ process of either the original data stream or new data stream. | 2012-02-23 |
20120044799 | METHOD AND APPARATUS OF IMPLEMENTING AN INTERNET PROTOCOL SIGNALING CONCENTRATOR - Communication between base station controllers and a mobile switching center may be provided by a consolidating device that operates between the BSCs and the MSCs. One example method of operation may include initiating an active process on an active network device and a standby process on a redundant network device configured as a backup to the active network device. Other operations may include receiving a data message from at least one base station controller on the active network device, and detecting a communication failure by at least one of the active process and the standby process, in response to the received data message. Other operations may include automatically configuring the redundant network device to become the active network device. | 2012-02-23 |
20120044800 | PROTECTION OF USER DATA TRANSMISSION THROUGH A TRANSPORT NETWORK - It is disclosed a method for protecting transmission of user data transmitted from a first to a second user network through a transport network. The user data have a maximum transmission rate. The method comprises: in the transport network, in a failure-free status, providing a first and a second path having an overall capacity equal to the maximum transmission rate; transmitting a first portion of user data along the first path, and a second portion of user data along the second path; at a network management server cooperating with the transport network, detecting a failure affecting transmission of the second portion; at the network management server, switching from the failure-free status to a failure status by operating the transport network so as to increase capacity of the first path to the maximum transmission rate; and at the first user network, transmitting the user data along the first path only. | 2012-02-23 |
20120044801 | TECHNIQUE FOR DETERMINING WHETHER TO REESTABLISH FAST REROUTED PRIMARY TUNNELS BASED ON BACKUP TUNNEL PATH QUALITY FEEDBACK - In one embodiment, a primary tunnel is established from a head-end node to a destination along a path including one or more protected network elements for which a fast reroute path is available to pass traffic around the one or more network elements in the event of their failure. A first path quality measures path quality prior to failure of the one or more protected network elements. A second path quality measures path quality subsequent to failure of the one or more protected network elements, while the fast reroute path is being used to pass traffic of the primary tunnel. A determination is made whether to reestablish the primary tunnel over a new path that does not include the one or more failed protected network elements, or to continue to utilize the path with the fast reroute path, in response to a difference between the first path quality and the second path quality. | 2012-02-23 |
20120044802 | METHOD AND DEVICE FOR REALIZING IP MULTIMEDIA SUBSYSTEM DISASTER TOLERANCE - A method for realizing an Internet protocol (IP) multimedia subsystem (IMS) disaster tolerance includes the steps as follows. An S-CSCF receives a user registration, and backs up necessary data which is required when a user service processing is restored on a storage entity in a network. An I-CSCF of user's home domain receives a service request of the user, and if it is found that the S-CSCF currently providing a service for the user fails, assigns a new S-CSCF to the user, and forwards the service request to the newly assigned S-CSCF. The newly assigned S-CSCF interrogates and acquires subscription data of the user and the necessary data backed up by the original S-CSCF from the storage entity, and then restores the user service processing according to the subscription data and the backup data. A device for realizing an IMS disaster tolerance is also provided. | 2012-02-23 |
20120044803 | RING NETWORK PROTECTION METHOD, NETWORK NODE AND RING NETWORK - A ring network protection method, a network node and a ring network are provided. The ring network protection method includes: receiving, by a network node, a ring network protection switching request message sent by a node that detects a fault when the fault occurs in the ring network, where the ring network protection switching request message carries source and destination node information of the ring network protection switching request message; and determining a fault location according to the source and destination node information, selecting a protection tunnel according to the determined fault location, and switching services to the selected protection tunnel, where the selected protection tunnel is a link protection tunnel of a link between the network node and a source node, or a node protection tunnel of an intermediate node on a short way between the network node and the source node. | 2012-02-23 |
20120044804 | DYNAMIC REROUTING OF DATA PATHS IN A WIRELESS COMMUNICATION NETWORK - A system and methodology that dynamically reroutes active communications sessions between a user equipment (UE) and a wireless network. In particular, the system can determine a current or impending fault condition and reroute a data path for network traffic to another service. Moreover, the system can identify a failed element in a wireless network and deny access and divert traffic until the element is restored. Further, the system can issue an alert to a user interface of the wireless network with information associated with a fault condition, a failed element, or a restored element. | 2012-02-23 |
20120044805 | SYSTEMS AND METHODS FOR TRAFFIC POLICING - Systems and methods for policing traffic in communications systems are described herein. According to systems and methods herein, tokens are generated for a packet data network based on a peak transmission rate associated with the packet data network. Packets are selected for transmission over the packet data network based on availability of tokens. | 2012-02-23 |
20120044806 | METHOD FOR NOTIFYING ABOUT/AVOIDING CONGESTION SITUATION OF DATA TRANSMISSION IN WIRELESS MESH NETWORK, AND MESH NODE FOR THE SAME - Provided is a multi-route routing scheme that supports Quality of Service (QoS) in the wireless mesh network. A method of notifying about and avoiding congestion situation in data transmission in a wireless mesh network and a mesh node may also be provided. Data may be differentially transmitted to multiple routes by obtaining a route congestion level existing in a current multi-hop route and thus, data providing a real-time service, such as a video streaming service, may avoid congested routes and may be promptly transmitted. Multiple queues in a mesh node may be divided into divided queues based on a congestion situation of a transmission route in a network and the divided queues may be transmitted through multiple routes and thus, an efficiency of the overall network may increase. | 2012-02-23 |
20120044807 | METHOD AND SYSTEM FOR ENFORCING TRAFFIC POLICIES AT A POLICY ENFORCEMENT POINT IN A WIRELESS COMMUNICATIONS NETWORK - Embodiments of a method and system for enforcing a traffic policy at a Policy Enforcement Point (PEP) that controls the flow of traffic in a wireless communications network are described. In one embodiment, a method involves learning the topology of the wireless communications network, defining a virtual PEP (VPEP) within the topology of the wireless communications network, the VPEP comprising a location component that is remote from the PEP, associating a traffic policy with the VPEP, associating a traffic flow with the VPEP if the traffic flow has a characteristic that corresponds to the location component of the VPEP, and enforcing, at the PEP, the traffic policy that is associated with the VPEP against the traffic flow. | 2012-02-23 |
20120044808 | METHOD AND APPARATUS OF LOAD BALANCING FEMTOCELL CLUSTER ACCESS - A method of establishing a communication session between an access terminal and an access network is disclosed. The access terminal and access network may be femtocells based on the EVDO communication standard. The example method of communication may include transmitting a connection request from the access terminal to the access network, and receiving a redirect message or a traffic channel assignment message at the access terminal based on a communication between the access network and at least one other access network. More than one access network may be present communicating as a communication pair system aimed at load balancing access terminals. The method may also include establishing packet data communications between the access terminal and a packet data serving node to provide network communication to the access terminal. | 2012-02-23 |
20120044809 | Method for Controlling the Operation of a Processing Unit of a Wireless Communications Device, and Corresponding Communications Device - Method for controlling the operation of a processing unit (IC) of a wireless communications device (WAP) connected to a network (RES) via a communications channel, said processing unit being configured to process at least one application for processing data exchanged with the network (ATEL). The method comprises, in the presence of a detected or predictable processing overload of the processing unit, a transmission from the device to the network (RES) of quality information representing ( | 2012-02-23 |
20120044810 | WIRELESS TERMINAL - A communication permitted slot setting section | 2012-02-23 |
20120044811 | CREATING BALANCED LINK-DISJOINT TOPOLOGIES IN A COMPUTER NETWORK - In one embodiment, each node in a computer network determines a shortest looping ring back to the node through each of its neighbors. Each of these rings may then be marked in a particular direction, ensuring that any ring that shares a link with another ring is marked in such a way that the shared link is in the same direction in each of the rings that share the link. The links that are marked in the particular direction may be stored as part of a first topology. Conversely, the opposite direction on the links (e.g., bidirectional links or parallel unidirectional links) may be stored as a second topology that is link-disjoint from the first topology. | 2012-02-23 |
20120044812 | METHOD AND APPARATUS FOR CHANGE OF PRIMARY CELL DURING CARRIER AGGREGATION - Methods for performing change of primary cell during carrier aggregation operation are described. A mobile station (MS) receives a message to change a primary cell and to perform a random access communication with a new primary cell. Upon receiving a random access response message from the new primary cell, the MS starts transmitting a control channel to the new primary cell. In one embodiment, the MS releases the configuration of an uplink control channel and transmits uplink control information through an uplink shared channel. Upon completion of the primary cell change procedure, the MS starts transmission of an uplink control channel to the new primary cell. | 2012-02-23 |
20120044813 | METHOD AND APPARATUS FOR COPING WITH LINK FAILURES IN CENTRAL CONTROL PLANE ARCHITECTURES - A capability for coping with link failures in central control plane architectures is provided. The capability for coping with link failures enables targeted reporting of link failures within the network in a manner that prevents flooding of link failure messages (LFMs) within the network. A method for reporting a failure of a link associated with a node includes detecting a failure of a link associated with the node, identifying an interface of the node associated with the failed link, identifying, from a flow table of the node, an ingress interface of the node via which a flow intended for the failed link is received, generating an LFM for the identified ingress interface, and sending the LFM via the identified ingress interface. A method for use at a local node having a flow table includes receiving an LFM indicative of a link failure detected at a remote node where the LFM includes a flow definition of a flow received at the remote node from the local node, identifying an interface of the local node via which the LFM is received, identifying from the flow table of the local node an ingress interface of the local node via which a flow intended for the failed link is received, generating a new LFM for the identified ingress interface of the node, and sending the new LFM via the identified ingress interface of the local node. | 2012-02-23 |
20120044814 | UPLINK BUFFER STATUS REPORTING OF RELAY STATIONS IN WIRELESS NETWORKS - The present disclosure is directed to a method for reporting uplink buffer status of a relay station to a base station in a wireless network. The method includes monitoring an uplink buffer of the relay station communicating with the base station, where the uplink buffer comprises data to be transmitted from one or more user terminals to the base station. The method further includes sending an uplink buffer status report from the relay station to the base station, where the uplink buffer status report includes occupancy status information of the monitored uplink buffer and a number of user terminals having data queued up at the relay station to be transmitted to the base station. | 2012-02-23 |
20120044815 | INTERFERENCE COORDINATION FOR PEER-TO-PEER (P2P) COMMUNICATION AND WIDE AREA NETWORK (WAN) COMMUNICATION - Techniques for supporting peer-to-peer (P2P) communication in a wide area network (WAN) are disclosed. In an aspect, interference coordination between P2P devices engaged in P2P communication and WAN devices engaged in WAN communication may be performed based on a network-controlled architecture. For the network-controlled architecture, P2P devices may detect other P2P devices and/or WAN devices and may send measurements (e.g., for pathloss, interference, etc.) for the detected devices to the WAN (e.g., serving base stations). The WAN may perform resource partitioning and/or association for the P2P devices based on the measurements. Association may include selection of P2P communication or WAN communication for a given P2P device. Resource partitioning may include allocation of resources to a group of P2P devices for P2P communication. The WAN may send the results of association and/or resource partitioning to the P2P devices, which may communicate in accordance with the association and/or resource partitioning results. | 2012-02-23 |
20120044816 | METHOD AND APPARATUS FOR DETERMINING WHEN TO USE CONTENTION-BASED ACCESS FOR TRANSMITTING DATA IN A WIRELESS NETWORK - A wireless communication system as described here employs control signaling for contention-based uplink access from user equipment devices to a base station. Contention-based access configuration is performed via physical downlink control channel signaling. Configuration data sent to the user equipment devices identifies multiple contention-based access zones, along with minimum power headroom values for each contention-based access zone. A probability factor may also be used to lower collision possibility by influencing whether the user equipment devices perform contention-based uplink access. An uplink grant message can be used to acknowledge contention-based transmission; contention resolution is achieved implicitly via the uplink grant. | 2012-02-23 |
20120044817 | Managing Network Bandwidth - A system for managing network bandwidth, according to one embodiment of the present invention comprises a configuration storage module and a call manager. The configuration storage module includes a supported codecs storage, codec lists, administrator settings storage and reservation storage list. The call manager includes an extension module, trunk module, location service engine, settings manager, bandwidth manager and media stream manager. The call manager receives an offer message for a call having one or more media types. The call manager uses information included in the offer message, along with information stored in the configuration storage module, to negotiate a call settings list with one or more other sites for connecting the call, and thereby manage bandwidth for the call. | 2012-02-23 |
20120044818 | Adaptation of Receiver Settings in a Heterogeneous Network - Techniques are described for adapting receiver settings used by a mobile terminal operating in a heterogeneous network comprising macro cells and pico cells with overlapping coverage areas. A first set of subframes is allocated to the pico cells for downlink transmissions to a mobile terminal in a link imbalance zone. The mobile terminal acquires information about the subframe allocation and uses the subframe allocation information to select the signals used for adapting receiver settings used when operating in the link imbalance zone. | 2012-02-23 |
20120044819 | ROUTER AND METHOD FOR DISTINGUISHING REAL-TIME PACKETS IN THE ROUTER - A router and method distinguishes real-time packets in the router. The router reads information of reference packets and a packet length of a test packet. A packet arrival rate of the test packet, an inter-arrival time standard deviation of the test packet, and a packet length standard deviation of the test packet are calculated according to the information of the reference packets. The router marks the test packet as the real-time packets in response to a determination that the packet length of the test packet falls in the allowable range, the packet arrival rate of the reference packets falls in the allowable range, the inter-arrival time standard deviation of the test packet falls in the allowable range, and the packet length standard deviation of the test packet falls in the allowable range. | 2012-02-23 |
20120044820 | GATEWAY DEVICE AND METHOD FOR ESTABLISHING A VOICE OVER INTERNET PROTOCOL COMMUNICATION - A gateway device and method for establishing Voice over Internet Protocol (VoIP) communication includes setting coding methods of the VoIP, and setting quality of service (QoS) parameters corresponding to each coding method. In response to dialing a VoIP phone call from a local user terminal, a Session Initiation Protocol (SIP) session is initiated to determine a coding method. QoS parameters corresponding to the determined coding method are parsed to generate a request packet. The request packet is sent to base station to request for establishing a VoIP phone call. The VoIP phone call is established between the local user terminal and a remote user terminal by sending the VoIP packets through the base station to the remote user terminal. | 2012-02-23 |
20120044821 | CONTROL CHANNEL MONITORING APPARATUS IN MULTI-CARRIER SYSTEM AND METHOD THEREOF - The present invention relates to a method for monitoring a control channel and an apparatus thereof. A reference carrier is set, and then the multi-carrier sends blind decoding area information based on the reference carrier to monitor a control channel. A terminal monitors the control channel based on the blind decoding area information. The terminal performs blind decoding only for a component carrier required, and thus reduces power consumption and reception complexity. | 2012-02-23 |
20120044822 | DEVICE AND METHOD FOR CONTROLLING DRIVE TEST IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for matching the radio channel measurement timing of Minimization of Drive Test (MDT) cycle with timings of the Discontinuous Reception (DRX) cycle are provided. The radio channel measurement method of a terminal according to the present invention includes configuring a DRX cycle, receiving a Minimization of Drive Test (MDT) cycle, comparing the DRX cycle and the MDT cycle, measuring, when the MDT cycle is an integer multiple of the DRX cycle, the radio channel at DRX timings matching with MDT timings, and storing a result of the measurement. | 2012-02-23 |
20120044823 | TONE RELAY SYSTEM AND METHOD - A tone relay system comprises a tone detector arranged to receive a sequence of signal samples and to provide a plurality of media descriptors, each media descriptor comprising a cell of one or more of the signal samples and a tone detection meta-information for the cell; and a tone relay module arranged to receive each media descriptor, to perform an evaluation of the meta-information and modify the meta-information depending on one or more preceding media descriptors when a result of the evaluation indicates an undetermined tone state, and to provide the media descriptors with a predetermined delay to a tone aggregator module, when the meta-information indicates a tone, for transmission over a network, and to provide the media descriptors without the predetermined time delay to an encoder module, for transmission over the network, otherwise. | 2012-02-23 |
20120044824 | Controlling Cell Activation in a Radio Communication Network - In a radio communication network there are a number of radio base stations, at least one of which belongs to a first radio access network and manages at least one active cell serving user equipment. It is determined whether a passive other cell of a radio base station belonging to a second overlapping radio access network should be activated based on information representative of radio access preferences of the user equipment (S | 2012-02-23 |
20120044825 | METHOD AND APPARATUS FOR PROCESSING CONTROL MESSAGES IN A WIRELESS COMMUNICATIONS SYSTEM - There is described a method of processing control messages received by a wireless communication network from a wireless communication device. The method comprises: monitoring received control messages sent by the wireless communication device to identify control messages conveying information indicating whether or not the wireless communication device has a handover capability associated with performing a handover between the packet-switched and circuit-switched domains; for any such identified control message which indicates that the corresponding wireless communication device does not have said handover capability, modifying the control message to indicate that said corresponding wireless communication device does have said handover capability and forwarding the modified control message to the core network; and storing data indicative of whether or not the wireless communication device has said handover capability. | 2012-02-23 |
20120044826 | METHOD AND APPARATUS FOR TRANSMITTING MCCH CONTROL SIGNALING IN MBSFN MANNER - A method and device for realizing MBMS control signaling transmission in MBSFN manner are provided in the present invention. Wherein, a base station transmits multimedia broadcast multicast service MBMS control signaling in MBSFN manner, preferably, the base station multiplexes MBMS control signaling and MBMS service data in a same MBSFN subframe, and transmits them according to an adjustment period and/or a repetition period. Then, a mobile station receives the MBMS control signaling at the corresponding MBSFN subframe according to the adjustment period and/or the repetition period. With the solution of the present invention, MBMS control signaling transmission in MBSFN manner is realized. | 2012-02-23 |
20120044827 | COMMUNICATION METHOD AND APPARATUS IN MOBILE AD-HOC NETWORK - A communication method between nodes that have their own timers and have an equal start time of a frame for Time Division Multiple Access (TDMA) communication based on their timers in a mobile ad-hoc network, in which a node receives a timer value derived by a neighbor node on the basis of a transmission time, from the neighbor node, the node calculates a time offset indicative of a difference between a timer value derived on the basis of a time the node received the timer value, and the received timer value, and stores the time offset in a memory, and upon receiving a time value indicating a time related to inter-node TDMA communication from the neighbor node, the node corrects the received time value as a time value based on its timer using the time offset, and performs TDMA communication using the corrected time value. | 2012-02-23 |
20120044828 | METHOD AND APPARATUS FOR RESOURCE MANAGEMENT IN A RELAY COMMUNICATION SYSTEM, AND METHOD AND APPARATUS FOR DATA RELAY USING SAME - Disclosed is a method for transmitting integrated packet data by a relay station (RS) in a multi-hop relay communication system, including: integrating a plurality of packet data received from mobile stations (MSs) and determining a data integration scheme for transmitting the integrated data to base station (BS); receiving packet data from MSs, classifying the received packet data into one or more integration packet classes according to the determined data integration scheme, and storing the same; determining QoS (Quality of Service) requirements and a MCS (Modulation and Coding Scheme) level of the stored integration packet classes; calculating required resource according to the determined MCS level and requesting an allocation of the resource from the BS; receiving an approval for resource allocation from the BS, and modulating and coding the integrated packet class, mapping the same to the resource to configure an integrated packet; and transmitting the configured integrated packet to the BS. | 2012-02-23 |
20120044829 | SYSTEM AND METHOD FOR FACILITATING CO-CHANNEL AND CO-EXISTENCE VIA ENHANCED FRAME PREAMBLES - Enhanced frame preambles facilitate co-channel co-existence in a wireless communication environment by having at least one preamble characteristic that connotes channel-sharing information regarding the wireless communication environment. In an exemplary embodiment, a downlink subframe is received in one or more wireless communication signals in a wireless communication environment. A preamble is detected in the downlink subframe, and at least one characteristic of the preamble is ascertained. Channel-sharing information for the wireless communication environment is determined based upon the at least one characteristic of the preamble. In another exemplary embodiment, a channel is scanned to detect secondary preambles being transmitted on the channel. A current preamble configuration, including a permutation of preamble location and preamble content corresponding to the secondary preambles, is determined, which connote channel-sharing information. A next available preamble location may be adopted based on the current preamble configuration. | 2012-02-23 |
20120044830 | METHOD FOR TRANSMITTING AND RECEIVING SIGNALS USING COLLABORATIVE MIMO SCHEME - A method for reducing inter-cell interference and a method for transmitting a signal by a collaborative MIMO scheme, in a communication system having a multi-cell environment are disclosed. An example of a method for transmitting, by a mobile station, precoding information in a collaborative MIMO communication system includes determining a precoding matrix set including precoding matrices of one more base stations including a serving base station, based on signal strength of the serving base station, and transmitting information about the precoding matrix set to the serving base station. A mobile station in an edge of a cell performs a collaborative MIMO mode or inter-cell interference mitigation mode using the information about the precoding matrix set collaboratively with neighboring base stations. | 2012-02-23 |