08th week of 2012 patent applcation highlights part 12 |
Patent application number | Title | Published |
20120043529 | ORGANIC PHOTOELECTRIC CONVERSION ELEMENT - An organic photoelectric conversion element comprising a pair of electrodes, at least one of the electrodes being transparent or translucent, and an organic layer disposed between the pair of electrodes, wherein the organic layer comprises a conjugated polymer compound, and one or more compounds selected from the group consisting of a low-molecular-weight aromatic compound having a group derived by removing two hydrogen atoms from the structure represented by the following formula (1) and a hydroxyl group, estrogen and a nonconjugated polymer compound having a hydroxyl group: | 2012-02-23 |
20120043530 | Polymer compositions, polymer films, polymer gels, polymer foams, and electronic devices containing such films, gels and foams - A polymer film, polymer gel, and polymer foam each contain an electrically conductive polymer and an ionic liquid and are each useful as a component of an electronic device. | 2012-02-23 |
20120043531 | COMPOUND FOR ORGANIC OPTOELECTRONIC DEVICE, ORGANIC LIGHT EMITTING DIODE INCLUDING THE SAME, AND DISPLAY DEVICE INCLUDING THE LIGHT EMITTING DIODE - A compound for an organic optoelectronic device, an organic light emitting diode, and a display device including the organic light emitting diode, the compound being represented by the following Chemical Formula 1: | 2012-02-23 |
20120043532 | LIGHT EMITTING DEVICE - High light transmission efficiency is achieved in an electroluminescence device without lowering the durability of the device. The electroluminescence device includes: electrodes; a plurality of layers that are deposited one on another between the electrodes; and a light emitting region between the plurality of layers. The light emitting region emits light by application of an electric field between the electrodes. At least one microparticle that induces plasmon resonance on the surface thereof by the light emitted from the light emitting region is arranged in the vicinity of the light emitting region or in the light emitting region. The microparticle is a core-shell-type microparticle including at least one metal microparticle core and an insulation shell that covers the at least one metal microparticle core. | 2012-02-23 |
20120043533 | AROMATIC AMINE DERIVATIVE AND ORGANIC ELECTROLUMINESCENT ELEMENT COMPRISING THE SAME - An aromatic amine derivative represented by the following formula (1):
| 2012-02-23 |
20120043534 | LIGHT-EMITTING ORGANIC COMPOUND AND EL DISPLAY DEVICE UTILIZING THE SAME - By repeating a purification process of a light-emitting organic compound several times, a thin film made of the light-emitting organic compound to be used in an EL display device contains ionic impurities at the concentration of 0.1 ppm or lower and has a volume resistivity in the range of 3×10 | 2012-02-23 |
20120043535 | NOVEL COMPOUND AND ORGANIC LIGHT EMITTING DEVICE USING THE COMPOUND - A novel mono(benzo[k]fluoranthene) compound having a molecular structure containing at least one condensed ring aromatic group which is tricyclic or more at any of 7- to 9-positions of benzo[k]fluoranthene. Also an organic light emitting device including at least a pair of electrodes formed of an anode and a cathode, and a layer formed of an organic compound, the layer being interposed between the pair of electrodes, in which the layer formed of an organic compound contains a compound represented by the following structural formula. An organic light emitting device in which the layer is a light emitting layer. | 2012-02-23 |
20120043536 | ORGANIC EL ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A donor film | 2012-02-23 |
20120043537 | PROCESS FOR PRODUCING SEMICONDUCTIVE LAYERS - The present invention relates to a process for producing a layer comprising at least one semiconductive metal oxide on a substrate, comprising at least the steps of:
| 2012-02-23 |
20120043538 | PROCESS TO MAKE METAL OXIDE THIN FILM TRANSISTOR ARRAY WITH ETCH STOPPING LAYER - The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel. | 2012-02-23 |
20120043539 | SEMICONDUCTOR CHIP WITH THERMAL INTERFACE TAPE - A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip. | 2012-02-23 |
20120043540 | Semiconductor device, method for manufacturing same, and display device - The present invention provides a semiconductor device capable of suppressing a contact failure due to an increase in contact resistance, a production method of the semiconductor device, and a display device. The present invention provides a semiconductor device which includes a thin-film diode including a crystalline semiconductor layer which includes a cathode region and an anode region, a cathode electrode connected to the cathode region, and an anode electrode connected to the anode region, the thin-film diode, the cathode electrode, and the anode electrode being disposed on a substrate, and which is featured in that the crystalline semiconductor layer includes a first low-impurity-concentration region having an impurity concentration lower than the impurity concentration of the cathode region, in that the first low-impurity-concentration region is arranged adjacent to the cathode region, and in that the cathode electrode is in contact with an area of the cathode region, the area being within 3 μm from the boundary at which the cathode region is in contact with the first low-impurity-concentration region. | 2012-02-23 |
20120043541 | SEMICONDUCTOR DEVICE - An object is to provide a transistor in which light deterioration is suppressed as much as possible and electrical characteristics are stable, and a semiconductor device including the transistor. The attention focuses on the fact that light is reflected by a film used for forming a transistor and multiple interaction occurs. When the optical thickness of the film which causes the reflection is roughly an odd multiple of λ | 2012-02-23 |
20120043542 | SEMICONDUCTOR DEVICE - The present invention is a semiconductor device including a first electrode over a substrate; a pair of oxide semiconductor films in contact with the first electrode; a second electrode in contact with the pair of oxide semiconductor films; a gate insulating film covering at least the first electrode and the pair of oxide semiconductor films; and a third electrode that is in contact with the gate insulating film and is formed at least between the pair of oxide semiconductor films. When the donor density of the oxide semiconductor films is 1.0×10 | 2012-02-23 |
20120043543 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - Disclosed is a semiconductor device provided with the following: an active layer | 2012-02-23 |
20120043544 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film | 2012-02-23 |
20120043545 | THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region. | 2012-02-23 |
20120043546 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing an organic light-emitting display device capable of improving efficiency of a laser generator used for crystallization of amorphous silicon. The method crystallizes amorphous silicon selectively to provide an organic light-emitting display device that includes channel area of a pixel contains polycrystalline silicon and storage area of the pixel contains amorphous silicon. | 2012-02-23 |
20120043547 | THIN FILM CHARGED BODY SENSOR - A thin film charged body sensor for sensing a contact and/or non-contact movement of a charged body based on an electric field of the charged body. The thin film charged body sensor may include a substrate, a first thin film transistor unit on the substrate, and including a gate layer, an active layer insulated from the gate layer, and source/drain layers insulated from the gate layer and connected to the active layer; and a thin film antenna unit on the substrate, and including a first film including a conductive material electrically connected to the gate layer, the thin film antenna unit adapted to generate an input current in response to an electric field of a charged body. | 2012-02-23 |
20120043548 | THIN FILM TRANSISTOR AND DISPLAY UNIT - A thin film transistor with which oxygen is easily supplied to an oxide semiconductor layer and favorable transistor characteristics are able to be restored and a display unit including the same. The thin film transistor includes, sequentially over a substrate, a gate electrode, a gate insulting film, an oxide semiconductor layer including a channel region, and a channel protective layer covering the channel region A source electrode and a drain electrode are formed on the oxide semiconductor layer located on both sides of the channel protective layer, and at least one of the source electrode and the drain electrode has an aperture to expose the oxide semiconductor layer. | 2012-02-23 |
20120043549 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element. | 2012-02-23 |
20120043550 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a stacked structural body, first and second electrodes, a high resistance layer and a transparent conductive layer. The stacked structural body includes first and second semiconductor layers and a light emitting layer. The first semiconductor layer is disposed between the first electrode and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the first semiconductor layer. The second electrode has reflectivity with respect to luminescent light. The high resistance layer is in contact with the second semiconductor layer between the second semiconductor layer and the second electrode and includes a portion overlapping with the first electrode. The transparent conductive layer is in contact with the second semiconductor layer between the second semiconductor layer and the second electrode. The transparent conductive layer has a resistance lower than a resistance of the high resistance layer. | 2012-02-23 |
20120043551 | Second contact schottky metal layer to improve GaN schottky diode performance - A Schottky diode includes a first nitride-based semiconductor layer disposed atop a substrate. A second nitride-based semiconductor layer is disposed atop a portion of the first nitride-based semiconductor layer. The second layer has a doping concentration lower than that of the first layer. A first Schottky contact metal layer having a first metal work function is disposed on a top planar surface of the second layer, forming a first Schottky junction. A second Schottky contact metal layer having a second metal work function is disposed atop of and laterally surrounding the first Schottky contact metal layer, the metal work function of the second metal layer is higher than that of the first metal layer. A metal layer disposed on first and second planar surfaces forms an ohmic contact with the first nitride-based semiconductor layer. | 2012-02-23 |
20120043552 | System and Method for Selected Pump LEDs with Multiple Phosphors - An LED pump light with multiple phosphors is described. LEDs emitting radiation at violet and/or ultraviolet wavelengths are used to pump phosphor materials that emit other colors. The LEDs operating in different wavelength ranges are arranged to reduce light re-absorption and improve light output efficiency. | 2012-02-23 |
20120043553 | Hybrid Semiconductor Device Having a GaN Transistor and a Silicon MOSFET - A hybrid device including a silicon based MOSFET operatively connected with a GaN based device. | 2012-02-23 |
20120043554 | LIGHT-EMITTING DEVICES - Light-emitting devices, and related components, systems and methods are disclosed. | 2012-02-23 |
20120043555 | LIQUID FLUORESCENT COMPOSITION AND LIGHT EMITTING DEVICE - The invention provides a liquid fluorescent composition. The liquid fluorescent composition includes at least (a) 0.001-2 parts by weight of a fluorescent material; and (b) 100 parts by weight of a cyclic solvent having a boiling point above 100° C. The invention also provides a light emitting device containing the above liquid fluorescent composition. | 2012-02-23 |
20120043556 | EPITAXIAL GROWTH OF SILICON DOPED WITH CARBON AND PHOSPHORUS USING HYDROGEN CARRIER GAS - A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H | 2012-02-23 |
20120043557 | SEMICONDUCTOR LIGHT-EMITTING DEVICE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY - The present invention provides a semiconductor light-emitting device. The light-emitting device comprises a first conductive clad layer, an active layer, and a second conductive clad layer sequentially formed on a substrate. In the light-emitting device, the substrate has one or more side patterns formed on an upper surface thereof while being joined to one or more edges of the upper surface. The side patterns consist of protrusions or depressions so as to scatter or diffract light to an upper portion or a lower portion of the light-emitting device. | 2012-02-23 |
20120043558 | ACTIVE DEVICE ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME - An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed. | 2012-02-23 |
20120043559 | LIGHT EMITTING DEVICE - There is provided a light emitting device which includes a light emitting element having a main emission peak in the wavelength region of greater than 420 nm and equal to or less than 500 nm, and a phosphor layer formed on the light emitting element. The light emitting element of this light emitting device has a junction temperature of from 100° C. to 200° C. at the time of continuous driving. Furthermore, the phosphor layer contains a phosphor represented by the following general formula (A), which absorbs the light emitted from the light emitting element and thereby emits light having a main emission peak in the wavelength region of equal to or greater than 650 nm and equal to or less than 665 nm: | 2012-02-23 |
20120043560 | LAMP MODULE - A lamp module is provided, including a circuit board, at least an LED, an insulator and a metal barrier. The LED is disposed on the circuit board and has two conductive leads on opposite sides thereof. The insulator is disposed on the circuit board, having an opening and two protruding sheets. The metal barrier is disposed on the insulator, wherein the LED and the protruding sheets are extended through the metal barrier. The conductive leads are insulated from the metal barrier by the protruding sheets of the insulating member. | 2012-02-23 |
20120043561 | Organic Light Emitting Diode Display - An organic light emitting diode display includes: a substrate; a first electrode positioned on the substrate; an organic layer positioned on the first electrode; a transflective layer positioned on the organic layer; an organic emission layer positioned on the transflective layer; and a second electrode positioned on the organic emission layer. | 2012-02-23 |
20120043562 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR - Provided is an organic eletroluminescence display device, which is capable of preventing transfer of an attached matter from the vapor deposition mask to the insulating layer, without increasing steps or manufacturing cost. The organic eletroluminescence display device includes: a first insulating layer formed on a substrate; multiple first electrodes disposed on the first insulating layer; an opening formed in the first insulating layer at a periphery of the first electrode; a second insulating layer disposed in a region overlapping with the opening; an organic compound layer covering the first electrodes; and a second electrode formed on the organic compound layer, in which: a material forming the first electrodes is absent in the opening; and the second insulating layer has a recess formed in a surface thereof, reflecting the opening of the first insulating layer, the recess being formed in a vertical direction of the substrate surface. | 2012-02-23 |
20120043563 | High Voltage Low Current Surface Emitting Light Emitting Diode - A light emitting diode chip includes a submount, a reflective layer on the submount, an insulating layer on the reflective layer opposite the submount, and a plurality of sub-LEDs on the insulating layer. Each of the sub-LEDs includes a first face adjacent to the submount and a transparent contact on the first face between the sub-LED and the insulating layer and electrical interconnects between adjacent ones of the sub-LEDs. | 2012-02-23 |
20120043564 | COMMON OPTICAL ELEMENT FOR AN ARRAY OF PHOSPHOR CONVERTED LIGHT EMITTING DEVICES - A device is provided with at least one light emitting device (LED) die mounted on a submount with an optical element subsequently thermally bonded to the LED die. The LED die is electrically coupled to the submount through contact bumps that have a higher temperature melting point than is used to thermally bond the optical element to the LED die. In one implementation, a single optical element is bonded to a plurality of LED dice that are mounted to the submount and the submount and the optical element have approximately the same coefficients of thermal expansion. Alternatively, a number of optical elements may be used. The optical element or LED die may be covered with a coating of wavelength converting material. In one implementation, the device is tested to determine the wavelengths produced and additional layers of the wavelength converting material are added until the desired wavelengths are produced. | 2012-02-23 |
20120043565 | DISPLAY DEVICE AND METHOD OF PRODUCING THE SAME - A display device includes: a substrate; a plurality of light-emission elements arranged, on the substrate, in a first direction and a second direction intersecting each other, each of the light-emission elements having a first electrode layer, an organic layer including a luminous layer, and a second electrode layer which are laminated in that order; and a separation section disposed, on the substrate, between the light-emission elements adjacent to each other in the first direction, the separation section having two or more pairs of steps. The first electrode layers in the light-emission elements are separated from each other, and the organic layers as well as the second electrode layers in the light-emission elements adjacent to each other in the first direction are separated from each other by the steps included in the separation section. | 2012-02-23 |
20120043566 | AlGaInP Light-Emitting Diode Having Vertical Structure and Method for Manufacturing the Same - A method for manufacturing the AlGaInP LED having a vertical structure is provided, including: growing, epitaxially, a buffer layer, an n-type contact layer, an n-type textured layer, a confined layer, an active layer, a p-type confined layer and a p-type window layer in that order on a temporary substrate, to form a texturable epitaxial layer; forming a transparent conducting film with periodicity on the p-type window layer of the epitaxial layer, forming a regulated through-hole on the transparent conducting film, and filling the through-hole with a conducting material; forming a total-reflection metal layer on the transparent conducting film; bonding a permanent substrate with the texturable epitaxial layer via a bonding layer, and bring the total-reflection metal layer into contact with the bonding layer; removing the temporary substrate and the buffer layer; forming an n-type extension electrode on the exposed n-type contact layer; removing the n-type contact layer, and forming a pad on the n-type textured layer; and forming a p-type electrode on a back of the permanent substrate. The transparent multilayered film with periodicity provides a greater reflectivity difference and hence brings better results than the conventional reflector consisting of single-layered, or, non-periodic, transparent films; and light-emitting efficiency is enhanced. | 2012-02-23 |
20120043567 | LED STRUCTURE WITH BRAGG FILM AND METAL LAYER - The present invention discloses an LED structure with a Bragg film and a metal layer, wherein a Bragg film and a metal layer are coated on a bottom of a sapphire substrate. The Bragg film includes two optical layers having different refractive indexes and alternately stacked. The materials and thickness of the optical layers of the Bragg film are optimized to form a high-reflectivity area via optical operation, which can effectively reflect the incident light generated by the light emitting layer from different incident angles. The Bragg film together with the metal layer can reflect the light, which is projected downward, to be emitted from the top or lateral of an LED structure. Therefore, the present invention can greatly increase the light-extraction efficiency of the LED structure. | 2012-02-23 |
20120043568 | LIGHT-EMITTING DEVICES WITH SUBSTRATE COATED WITH OPTICALLY DENSER MATERIAL - A light-emitting device includes a transparent substrate with a light emitting structure formed on one side of the substrate and a transparent layer formed on the opposing side of the substrate. The refractive index of the transparent layer is greater than the refractive index of the substrate. A light-emitting device includes a package cup having a reflective sidewall and a light emission surface and a light emitting diode (LED) embedded in the package cup. The LED comprises a transparent substrate and a transparent layer formed on the substrate. The reflective sidewall has a first portion in a central area of the package cup and a second portion in a peripheral area of the package cup, the first portion reflects light emitted from the transparent layer to the second portion and, then, the second portion further reflects the light received from the first portion to the light emission surface of the package cup. | 2012-02-23 |
20120043569 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device according to one embodiment includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the following equation (1) and an average particle diameter of 12 μm or more. | 2012-02-23 |
20120043570 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a lead, a frame, an optical semiconductor element, a sealing resin and a lens. The frame includes a main body covering a portion of the lead and being provided with a recess, another portion of the lead being exposed in the recess, and a casing part provided along an opening edge of the recess, the casing part including a cutout portion. The optical semiconductor element is provided in the recess and is in electrical connection with the lead. The sealing resin fills the recess from a bottom to the casing part, thereby covering the optical semiconductor element. The lens is joined to the sealing resin. | 2012-02-23 |
20120043571 | LIGHT-EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode (LED) structure and a method fro manufacturing the same. The LED structure includes a substrate, an illuminant epitaxial structure, first conductivity type and second conductivity type contact layers, a transparent insulating layer, first and second reflective layers, first and second barrier layers, and first conductivity type and second conductivity type electrodes. | 2012-02-23 |
20120043572 | Optoelectronic Semiconductor Body - An optoelectronic semiconductor body with a semiconductor layer sequence ( | 2012-02-23 |
20120043573 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device according to one embodiment includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the following equation (1) and an average particle diameter of 12 μm or more. | 2012-02-23 |
20120043574 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device according to the present embodiment, which includes, a substrate; a first electrode layer disposed on the substrate; a light emitting structure disposed on the first electrode layer, which includes a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer placed between the first and second conductive semiconductor layers; and a conductive layer, which includes a base conductive layer disposed under the substrate, a body connected to the base conductive layer while passing through the substrate and the first electrode layer, and a head disposed on top of the first electrode layer. Accordingly, the light emitting device is capable of improving light extraction efficiency and include a conductive layer to provide a carrier as well as a semiconductor layer, which are securely formed on the device. | 2012-02-23 |
20120043575 | LIGHT EMITTING DIODE - A light emitting diode is disclosed. The disclosed light emitting diode includes a light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first and second semiconductor layers, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a first reflection layer disposed on the second semiconductor layer. The first reflection layer includes at least a first layer having a first index of refraction and a second layer having a second index of refraction different from the first index of refraction. The first reflection layer is further disposed on a side surface of the second electrode and a portion of an upper surface of the second electrode. | 2012-02-23 |
20120043576 | LED PACKAGE STRUCTURE - An LED package structure includes a substrate with a concave groove therein, an LED die received in the concave groove, a heat conductive pillar, two electrically conductive pillars, a heat conductive plate, and two contact pads. The heat conductive pillar extends through the substrate and thermally connects with the LED die and the heat conductive plate. The electrically conductive pillars extend through substrate and electrically connect with the LED die, respectively. The electrically conductive pillars and the heat conductive pillar are spaced from each other. The contact pads respectively and electrically connect with the electrically conductive pillars. The contact pads are spaced from each other. | 2012-02-23 |
20120043577 | CURABLE SILICONE RESIN COMPOSITION AND LIGHT-EMITTING DIODE DEVICE USING THE SAME - This invention discloses a curable silicone resin composition used for sealing a light-emitting diode device, comprising at least a silicone resin having a refractive index of 1.50˜1.55 after curing and a silicon oxide filler having an average particle diameter of 1˜10 μm dispersed uniformly in the said silicone resin at the concentration of 1˜30 mass % and a light-emitting diode device using the same. | 2012-02-23 |
20120043578 | GaN-Based Light-Emitting Diode and Method for Manufacturing the Same - A GaN-based LED and a method for manufacturing the same are provided, and the method includes: providing a substrate, depositing a first transition layer on the substrate; forming a first patterned transition layer by etching with a mask; growing a first epitaxial layer on the first patterned transition layer; depositing a second transition layer on the first epitaxial layer; forming a second patterned transition layer by etching with a mask, such that the second patterned transition layer and the first patterned transition layer are cross-staggered with each other; growing a second epitaxial layer on the second patterned transition layer, wherein the second epitaxial layer includes a P-type layer, a light-emitting layer and an N-type layer; depositing a protection layer on the second epitaxial layer, dicing to obtain chips with a defined size; removing the first patterned transition layer and the second patterned transition layer on the substrate and the protection layer on the second epitaxial layer by wet etching, so as to form a structure with two layers of cross-staggered through holes; forming a conductive layer on the second epitaxial layer; and forming a P-electrode and an N-electrode by etching with a mask. The two layers of cross-staggered through holes of the LED chips can effectively reduce the dislocation density in the epitaxial growth of the GaN-based layer, and improve the lattice quality and luminous efficiency. | 2012-02-23 |
20120043579 | Light-Emitting Device - A light-emitting device having the quality of an image high in homogeneity is provided. A printed wiring board (second substrate) ( | 2012-02-23 |
20120043580 | Semiconductor Device and Manufacturing Method Thereof - There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more. | 2012-02-23 |
20120043581 | SEMICONDUCTOR DEVICE - In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer. | 2012-02-23 |
20120043582 | SEMICONDUCTOR DEVICE HAVING BOTH IGBT AREA AND DIODE AREA - There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted. | 2012-02-23 |
20120043583 | LOW LEAKAGE, LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECITIFER (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction. | 2012-02-23 |
20120043584 | Low-noise large-area photoreceivers with low capacitance photodiodes - A quad photoreceiver includes a low capacitance quad InGaAs p-i-n photodiode structure formed on an InP (100) substrate. The photodiode includes a substrate providing a buffer layer having a metal contact on its bottom portion serving as a common cathode for receiving a bias voltage, and successive layers deposited on its top portion, the first layer being drift layer, the second being an absorption layer, the third being a cap layer divided into four quarter pie shaped sections spaced apart, with metal contacts being deposited on outermost top portions of each section to provide output terminals, the top portions being active regions for detecting light. Four transimpedance amplifiers have input terminals electrically connected to individual output terminals of each p-i-n photodiode. | 2012-02-23 |
20120043585 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 2012-02-23 |
20120043586 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on t he compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate. | 2012-02-23 |
20120043587 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed. | 2012-02-23 |
20120043588 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer; a second semiconductor layer; a two-dimensional carrier gas layer; a source electrode; a drain electrode; a gate electrode; and an auxiliary electrode located above the two-dimensional carrier gas layer between the gate electrode and the drain electrode. Channel resistance of the two-dimensional carrier gas layer between the gate electrode and the auxiliary electrode is set higher than channel resistance of the two-dimensional carrier gas layer between the gate electrode and the source electrode. | 2012-02-23 |
20120043589 | ENTRENCHED TRANSFER GATE - An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node. | 2012-02-23 |
20120043590 | Linear-Cap Varactor Structures for High-Linearity Applications - A device includes a well region over a substrate, and a heavily doped well region over the well region, wherein the well region and the heavily doped well region are of a same conductivity type. A gate dielectric is formed on a top surface of the heavily doped well region. A gate electrode is formed over the gate dielectric. A source region and a drain region are formed on opposite sides of the heavily doped well region. The source region and the drain region have bottom surfaces contacting the well region, and wherein the source region and the drain region are of opposite conductivity types. | 2012-02-23 |
20120043591 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode. | 2012-02-23 |
20120043592 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique. | 2012-02-23 |
20120043593 | Semiconductor Device Structure and Method for Manufacturing the same - The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost. | 2012-02-23 |
20120043594 | Micro-Electro-Mechanical Device And Manufacturing Method For The Same - It is an object of the present invention to provide a micro-electro-mechanical-device having a microstructure and a semiconductor element over one surface. In particular, it is an object of the present invention to provide a method for simplifying the process of forming the microstructure and the semiconductor element over one surface. A space in which the microstructure is moved, that is, a movable space for the microstructure is formed by procecssing an insulating layer which is formed in a process of forming the semiconductor element. The movable space can be formed by forming the insulating layer having a plurality of openings and making the openings face each other to be overlapped each other. | 2012-02-23 |
20120043595 | CAPACITOR DEVICE AND METHOD OF FABRICATING THE SAME - A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode. | 2012-02-23 |
20120043596 | SEMICONDUCTOR DEVICES AND STRUCTURES INCLUDING AT LEAST PARTIALLY FORMED CONTAINER CAPACITORS - Semiconductor device structures include an at least partially formed container capacitor having a generally cylindrical first conductive member with at least one inner sidewall surface, a lattice material at least partially laterally surrounding an upper end portion of the first conductive member, an anchor material, and at least one aperture extending through the lattice material between the at least partially formed container capacitor and an adjacent at least partially formed container capacitor. Other structures include an at least partially formed container capacitor, a lattice material, and an anchor material disposed over a surface of the lattice material and at least a portion of an end surface of the first conductive member and forming a chemical barrier over at least a portion of an interface between the lattice material and the upper end portion of the first conductive member. | 2012-02-23 |
20120043597 | SEA-OF-FINS STRUCTURE ON A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION - A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device. | 2012-02-23 |
20120043598 | POWER FET WITH A RESONANT TRANSISTOR GATE - A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies. | 2012-02-23 |
20120043599 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion. | 2012-02-23 |
20120043600 | Floating-Gate Device and Method Therefor - Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device. | 2012-02-23 |
20120043601 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate. | 2012-02-23 |
20120043602 | Power MOSFET and Its Edge Termination - Improved MOSFET structures and processes, where multiple polysilicon embedded regions are introduced into the n+ source contact area. A top poly Field Plate is used to shield the electric field from penetrating into the channel, so that a very short channel can be used without jeopardizing the device drain-source leakage current. A bottom poly Field Plate is used to modulate the electric field distribution in the drift region such that a more uniform field distribution can be obtained. | 2012-02-23 |
20120043603 | Method of manufacturing semiconductor device, and semiconductor device - A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench. | 2012-02-23 |
20120043604 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof. | 2012-02-23 |
20120043605 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film, a trench formed in the device isolation film and the active region, a gate electrode formed at the bottom of the trench, and a high dielectric material layer formed not only over the top of the gate electrode but also over a surface of the trench. As a result, although the gate electrode does not overlap with the junction region, the semiconductor device prevents channel resistance from being increased, resulting in an increase in semiconductor device characteristics. | 2012-02-23 |
20120043606 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate region, a gate insulating film, and an electric field relaxation region. The first semiconductor region includes a first portion and a second portion. The second semiconductor region includes a third portion and a fourth portion. The third semiconductor region includes a fifth portion and a sixth portion. The fourth semiconductor region is adjacent to the sixth portion. The gate region is provided inside a trench made in a second direction orthogonal to the first direction. The gate insulating film is provided between the gate region and an inner wall of the trench. The electric field relaxation region is provided between the third portion and the fifth portion and has an impurity concentration lower than an impurity concentration of the third semiconductor region. | 2012-02-23 |
20120043607 | Tunneling Field-Effect Transistor with Low Leakage Current - Illustrative embodiments of a vertical tunneling field effect transistor are disclosed which may comprise a semiconductor body including a source region doped with a first dopant type and a pocket region doped with a second dopant type, where the pocket region is formed above the source region. The transistor may also comprise an insulated gate formed above the source and pocket regions, the insulated gate being configured to generate electron tunneling between the source and pocket regions if a voltage is applied to the insulated gate. The transistor may further comprise a lateral tunneling barrier formed to substantially prevent electron tunneling between the source region and a drain region of the semiconductor body, where the drain region is doped with the second dopant type. | 2012-02-23 |
20120043608 | Partially Depleted Dielectric Resurf LDMOS - An partially depleted Dieler LDMOSFET transistor ( | 2012-02-23 |
20120043609 | HIGH-VOLTAGE TRANSISTOR ARCHITECTURES, PROCESSES OF FORMING SAME, AND SYSTEMS CONTAINING SAME - An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device. | 2012-02-23 |
20120043610 | Controlled Fin-Merging for Fin Type FET Devices - A method for fabricating FET devices is disclosed. The method includes forming continuous fins of a semiconductor material and fabricating gate structures overlaying the continuous fins. After the fabrication of the gate structures, the method uses epitaxial deposition to merge the continuous fins to one another. Next, the continuous fins are cut into segments. The fabricated FET devices are characterized as being non-planar devices. A placement of non-planar FET devices is also disclosed, which includes non- planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures. | 2012-02-23 |
20120043611 | METHODS OF FORMING MEMORY CELLS, MEMORY CELLS, AND SEMICONDUCTOR DEVICES - A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure. | 2012-02-23 |
20120043612 | Device Layout in Integrated Circuits to Reduce Stress from Embedded Silicon-Germanium - An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated. | 2012-02-23 |
20120043613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes. | 2012-02-23 |
20120043614 | SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern. | 2012-02-23 |
20120043615 | SEMICONDUCTOR DEVICE - In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer. | 2012-02-23 |
20120043616 | SUB WORD LINE DRIVER AND APPARATUSES HAVING THE SAME - A sub word line driver is provided. The sub word line driver includes a first layer including a plurality of first pads disposed in a first line of a first direction, a plurality of second pads arranged in a second line of the first direction, and two first word lines arranged twisted twice in the first direction between the plurality of first pads and the plurality of second pads, each of the two first word lines being connected to a corresponding pad among the plurality of second pads; and a second layer, which is formed at a lower part of the first layer, and includes the second layer including a plurality of third pads, each the plurality of third pads each being embodied disposed at each corresponding a position corresponding to a pad from among one of the plurality of first pads and the plurality of second pads. | 2012-02-23 |
20120043617 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This invention provides a semiconductor device having a field effect transistor comprising agate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. | 2012-02-23 |
20120043618 | Performance-Aware Logic Operations for Generating Masks - Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules. | 2012-02-23 |
20120043619 | SYSTEM AND CIRCUIT FOR SIMULATING GATE-TO-DRAIN BREAKDOWN - A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET. | 2012-02-23 |
20120043620 | Multiple Threshold Voltages in Field Effect Transistor Devices - A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device. | 2012-02-23 |
20120043621 | STACKABLE NON-VOLATILE RESISTIVE SWITCHING MEMORY DEVICE AND METHOD - A method for forming a vertically stacked memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first plurality of memory cells are formed overlying the first dielectric material. Each of the first plurality of memory cells includes at least a first top metal wiring structure spatially extending in a first direction, a first bottom wiring structure spatially extending in a second direction orthogonal to the first top metal wiring structure, and a first switching element sandwiched in an intersection region between the first top metal wiring structure and the first bottom metal wiring structure. In a specific embodiment, the method forms a thickness of second dielectric material overlying the first plurality of memory. A second plurality of memory cells are formed overlying the second dielectric material. Each of the second plurality of memory cells includes at least a second top metal wiring structure extending in the first direction, a second bottom wiring structure arranged spatially orthogonal to the second top metal wiring structure, and a second switching element sandwiched in an intersection region of the second top metal wiring structure and the second bottom metal wiring structure. | 2012-02-23 |
20120043622 | PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE - Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state. | 2012-02-23 |
20120043623 | METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE - A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. | 2012-02-23 |
20120043624 | ULTRA-THIN BODY TRANSISTOR AND METHOD FOR MANUFCTURING THE SAME - An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer. | 2012-02-23 |
20120043625 | Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor - Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10 | 2012-02-23 |
20120043626 | MICROSTRUCTURE DEVICE WITH AN IMPROVED ANCHOR - The present disclosure provides a system of fabricating a microstructure device with an improved anchor. A method of fabricating a microstructure device with an improved anchor includes providing a substrate and forming an oxide layer on the substrate. Then, a cavity is etched in the oxide layer, such that the cavity includes a sidewall in the oxide layer. A microstructure device layer is then bonded to the oxide layer over the cavity. Forming a microstructure device, a trench is etched in the device layer to define an outer boundary of the microstructure device. In an embodiment, the outer boundary is substantially outside of the sidewall of the cavity. Then, the sidewall of the cavity is etched away through the trench in the device layer, to thereby suspend the microstructure device over the cavity. | 2012-02-23 |
20120043627 | MEMS Sensor Device With Multi-Stimulus Sensing and Method of Fabricating Same | 2012-02-23 |
20120043628 | PACKAGED DEVICE INCLUDING A WELL FOR CONTAINING A DIE - A packaged device includes a package defining a well having a well top, a die positioned in the well of the package, and a retaining substrate attached to the package over the well top. The retaining substrate holds the die in direct contact with a portion of the package exposed at a well bottom opposite the well top. | 2012-02-23 |