08th week of 2015 patent applcation highlights part 14 |
Patent application number | Title | Published |
20150048389 | OPTOELECTRONIC MODULE COMPRISING AN OPTICAL WAVEGUIDE AND METHOD FOR PRODUCING SAME - An optoelectronic module ( | 2015-02-19 |
20150048390 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD FOR SAME - The purpose of the present invention is to provide a double-sided light emitting type semiconductor light emitting device that can be easily fabricated even if a semiconductor light emitting element is flip-chip mounted, and to provide a fabrication process for the same. The semiconductor light emitting device has a plurality of lead frames, a plurality of semiconductor light emitting elements connected to the plurality of lead frames, and a covering member that covers the plurality of semiconductor light emitting elements. The semiconductor light emitting device is characterized in that the edge of one lead frame among the plurality of lead frames is disposed in close proximity to the edge of another lead frame so as to form a gap, and the plurality of semiconductor light emitting elements are flip-chip mounted on the front surface and rear surface of the one lead frame and the other lead frame so as to straddle the gap. | 2015-02-19 |
20150048391 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device has a substrate, one or more semiconductor light-emitting elements provided on the substrate, and that emit light having a peak wavelength in a 380 nm to 480 nm wavelength region, and a molded member covering the semiconductor light-emitting element, and containing a phosphor that emits visible light by being excited by the emitted light from the semiconductor light-emitting element. The molded member is formed so that index A=H/(s/n) satisfies 0.3≦A≦6, where H is the height [mm] of the molded member from the substrate, s is the square root [mm] of the contact area between the substrate and the molded member, and n is the number of the semiconductor light-emitting elements covered with the molded member. | 2015-02-19 |
20150048392 | WAVELENGTH CONVERSION ELEMENT, LIGHT-EMITTING SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS THEREWITH, AND METHOD FOR PRODUCING A WAVELENGTH CONVERSION ELEMENT - A wavelength conversion element including at least two ceramic conversion segments each including a ceramic wavelength conversion substance and connected together in a matrix by a non-transparent connecting material, wherein each conversion segment emits light by absorbing primary radiation and re-emitting secondary radiation different from the primary radiation, and the light comprises the secondary radiation and a proportion of the primary radiation is less than or equal to 5%. | 2015-02-19 |
20150048393 | HIGH DENSITY MULTI-CHIP LED DEVICES - High density multi-chip LED devices are described. Embodiments of the present invention provide high-density, multi-chip LED devices with relatively high efficiency and light output in a compact size. An LED device includes a plurality of interconnected LED chips and an optical element such as a lens. The LED chips may be arranged in two groups, wherein the LED chips within each group are connected in parallel and the groups are connected in series. In some embodiments, the LED device includes a submount, which may be made of ceramic. The submount may include a connection bus and semicircular areas to which chips are bonded. Wire bonds can be connected to the LED chips so that all the wire bonds are disposed on the outside of a group of LED chips to minimize light absorption. | 2015-02-19 |
20150048394 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light emitting device package includes a body including a lead frame part, and a light emitting laminate disposed on the body and electrically connected to the lead frame part to emit light. The light emitting laminate has a multilayer structure in which a plurality of light emitting devices are stacked. In the plurality of light emitting devices, an upper light emitting device is stacked on a lower light emitting device such that vertex portions of the upper light emitting device do not overlap and are offset from vertex portions of the lower light emitting device, and portions of the lower light emitting device are externally exposed. | 2015-02-19 |
20150048395 | OPTICAL CAVITY INCLUDING A LIGHT EMITTING DEVICE AND WAVELENGTH CONVERTING MATERIAL - Embodiments of the invention include a semiconductor light emitting diode attached to a substrate. A first region of wavelength converting material is disposed on the substrate. The wavelength converting material is configured to absorb light emitted by the semiconductor light emitting diode and emit light at a different wavelength. In the first region, the wavelength converting material coats an entire surface of the substrate. The substrate is disposed proximate a bottom surface of an optical cavity. A second region of wavelength converting material is disposed proximate a top surface of the optical cavity. | 2015-02-19 |
20150048396 | LIGHT EMITTING STRUCTURE AND SEMICONDUCTOR LIGHT EMITTING ELEMENT HAVING THE SAME - A light emitting structure includes an N-type semiconductor layer, a P-type semiconductor layer, a light emitting layer, and a stress regulation layer. The light emitting layer is formed between the N-type semiconductor layer and the P-type semiconductor layer. The stress regulation layer is formed between the N-type semiconductor layer and the light emitting layer. The stress regulation layer comprises a plurality of pairs of AlxIn(1-x)GaN and AlyIn(1-y)GaN layers stacked with each other, wherein 02015-02-19 | |
20150048397 | TRANSPARENT ELECTRON BLOCKING HOLE TRANSPORTING LAYER - A light emitting diode includes an active region configured to emit light, a composite electrical contact layer, and a transparent electron blocking hole transport layer (TEBHTL). The composite electrical contact layer includes two materials. At least one of the two materials is a metal configured to reflect a portion of the emitted light. The TEBHTL is arranged between the composite electrical contact layer and the active region. The TEBHTL has a thickness that extends at least a majority of a distance between the active region and the composite electrical contact layer. The TEBHTL has a band-gap greater than a band-gap of light emitting portions of the active region. The band-gap of the TEBHTL decreases as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL. | 2015-02-19 |
20150048398 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - To provide a light-emitting device that is provided with an optical member firmly bonded to a semiconductor light-emitting element and has a high light extraction efficiency, the light-emitting device includes a light-emitting element having a semiconductor layer and an optical member bonded to the light-emitting surface of the light-emitting element with a metal film being interposed therebetween wherein the metal film has a thickness in a film-forming rate conversion not less than 0.05 nm nor more than 2 times of an atomic diameter of the metal atoms forming the metal film. | 2015-02-19 |
20150048399 | COATED NARROW BAND RED-EMITTING FLUOROSILICATES FOR SMECONDUCTRO LEDS - The invention provides a lighting unit comprising a light source, configured to generate light source light and a particulate luminescent material, configured to convert at least part of the light source light into luminescent material light, wherein the light source comprises a light emitting diode (LED), wherein the particulate luminescent material comprises particles comprising cores, said cores comprising a phosphor comprising M′ | 2015-02-19 |
20150048400 | METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - A method of producing an optoelectronic semiconductor chip includes growing an optoelectronic semiconductor layer sequence on a growth substrate, forming an electrically insulating layer on a side of the optoelectronic semiconductor layer sequence facing away from the growth substrate by depositing particles of an electrically insulating material by an aerosol deposition method, and at least partly removing the growth substrate after forming the electrically insulating layer. | 2015-02-19 |
20150048401 | Ceramic Composite for Light Conversion and Light-Emitting Device Using Same - A ceramic composite for light conversion, which can make the fluorescence dominant wavelength longer up to 580 nm, further arbitrarily adjust the wavelength in the range of 570 to 580 nm, and undergoes no decrease in fluorescence intensity even when the fluorescence dominant wavelength is made longer, with luminescence unevenness suppressed. A light-emitting device comprising ceramic composite mentioned above. The ceramic composite for light conversion is a solidified body including a composition expressed by the following formula (1), where the composition has a structure where at least two oxide phases of a first phase and a second phase are continuously and three-dimensionally entangled mutually, and the ceramic composite for light conversion is characterized in that the first phase is a (Tb, Y) | 2015-02-19 |
20150048402 | LIGHT-EMITTING DEVICE - A light-emitting device in accordance with the present invention includes a mounting substrate; an LED chip bonded to a surface of the mounting substrate with a bond; and an encapsulating portion covering the LED chip. The bond transmits light from the LED chip. The mounting substrate includes: a light-transmissive member having a planar size larger than that of the LED chip; and first and second penetrating wirings which penetrate the light-transmissive member in the thickness direction thereof and are electrically connected to first and second electrodes of the LED chip via first and second wires, respectively. The light-transmissive member includes at least two light-transmissive layers with different optical properties which are stacked in the thickness direction. A light-transmissive layer of the light-transmissive layers which is farther from the LED chip is higher in reflectance to the light. | 2015-02-19 |
20150048403 | METHODS FOR MAKING OPTICAL COMPONENTS, OPTICAL COMPONENTS, AND PRODUCTS INCLUDING SAME - Methods for making multiple hermetically sealed optical components are disclosed. Methods for making an individual hermetically sealed optical component are disclosed. An individual hermetically sealed optical component and products including same are also disclosed. | 2015-02-19 |
20150048404 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a bonding pad, a narrow wire electrode and a first insulating layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer and is in contact with the first semiconductor layer. The narrow wire electrode includes a first portion and a second portion. The first portion is provided on a surface of the first semiconductor layer not in contact with the light emitting layer and is in ohmic contact with the first semiconductor layer. The second portion is provided on the surface and located between the first portion and the bonding pad. The narrow wire electrode is electrically connected to the bonding pad. The first insulating layer is provided between the second portion and the first semiconductor layer. | 2015-02-19 |
20150048405 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a substrate, a light emitting structure layer, a second electrode, a first electrode, a contact portion, and a first electrode layer. The first electrode is disposed in the substrate from a lower part of the substrate to a lower part of a first conductive type semiconductor layer in a region under an active layer. The contact portion is wider than the first electrode and makes contact with the lower part of the first conductive type semiconductor layer. The first electrode layer is disposed under the substrate and connected to the first electrode. | 2015-02-19 |
20150048406 | PHOSPHOR AND LIGHT-EMITTING DEVICE - A phosphor has the general formula (M | 2015-02-19 |
20150048407 | OPTOELECTRONIC CHIP-ON-BOARD MODULE - A method is proposed for coating an optoelectronic chip-on-board module including a flat substrate populated with one or more optoelectronic components having at least one primary optical arrangement and optionally at least one secondary optical arrangement. The optoelectronic chip-on-board module is coated with a transparent, UV-resistant, and temperature-resistant coating made of silicone by the following steps: (a) casting a liquid silicone into a mold open towards the top and having outer dimensions corresponding to or exceeding outer dimensions of the substrate; (b) inserting the substrate into the mold, wherein the optoelectronic component(s) are immersed completely into the silicone and a surface of the substrate contacts the silicone completely or the substrate immerses into the silicone at least partially with full surface contact; (c) curing and cross-linking the silicone with the optoelectronic component(s) and the substrate; and (d) removing the substrate from the mold with the coating of cured silicone. | 2015-02-19 |
20150048408 | Method for Manufacturing a Can Package-Type Optical Device, and Optical Device Manufactured Thereby - The present invention relates to a method for manufacturing an optical device, and to an optical device manufactured thereby, which involve using a substrate itself as a heat-dissipating plate, and adopting a substrate with vertical insulation layers formed thereon, such that electrode terminals do not have to be extruded out from a sealed space, and thus enabling the overall structure and manufacturing process for an optical device to be simplified. | 2015-02-19 |
20150048409 | LIGHT EMISSION DEVICE AND ILLUMINATION DEVICE - A light emission device includes: an insulating substrate; a light emitting section including a plurality of LED chips mounted on the insulating substrate; and land electrodes for supplying power to the LED chips. At least a surface of each of the land electrodes is made of a conductive material which is harder than Au and Ag and which has sulfurization resistance to such an extent that secures conduction of each land electrode when a current in a working current range is applied on the land electrode. | 2015-02-19 |
20150048410 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, in a semiconductor light emitting device, a first electrode is provided on a first surface of the semiconductor laminated body including a light emitting layer. A joint metal layer is provided on a second surface of the semiconductor laminated body opposed to the first surface of the semiconductor laminated body. A bonding metal layer covers a first surface of the joint metal layer on a side opposite to the semiconductor laminated body and is provided on a side of the second surface of the semiconductor laminated body. A substrate provided with a second electrode is bonded to the bonding metal layer. A layer having an etching resistance property to an etchant for etching the semiconductor laminated body is formed on a side of the surface of the bonding metal layer facing to the semiconductor laminated body. | 2015-02-19 |
20150048411 | OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device includes a conductive layer; a plurality of electrical connectors extending into the conductive layer; a semiconductor system, formed on the conductive layer, electrically connected to the plurality of electrical connectors and having a side surface; an insulation material directly covering the side surface; and an electrode arranged at a position not corresponding to the plurality of electrical connectors. | 2015-02-19 |
20150048412 | LED MODULE | 2015-02-19 |
20150048413 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drift layer; a base layer arranged in a surface portion of the drift layer; multiple trenches penetrating the base layer and reaching the drift layer; and a gate electrode arranged on the gate insulation film in each trench. Each trench includes: a first trench having an opening on a surface of the base layer; and a second trench connecting the first trench and having a portion, of which a distance between facing sidewalls of the second trench is longer than a distance between facing sidewalls of the first trench. The opening of each first trench is sealed with the gate electrode. An inside of each gate electrode includes a cavity portion. | 2015-02-19 |
20150048414 | IGBT DEVICE WITH BURIED EMITTER REGIONS - An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element. | 2015-02-19 |
20150048415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping. | 2015-02-19 |
20150048416 | SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well. | 2015-02-19 |
20150048417 | Germanium Barrier Embedded in MOS Devices - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage. | 2015-02-19 |
20150048418 | SEMICONDUCTOR POWER DEVICE - A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate, wherein the first semiconductor layer comprises a first group III element; a first grading layer formed on the first semiconductor layer and comprising a first portion; a second semiconductor layer with a second lattice constant formed on the first grading layer, wherein the second semiconductor layer comprises a second group III element; and a first interlayer formed in the first grading layer and adjacent to the first portion of the first grading layer, wherein a composition of the first interlayer is different from that of the first portion, and the first grading layer comprises the first group III element and the second group III element, and concentrations of both the first group III element and the second group III element in the first grading layer are gradually changed. | 2015-02-19 |
20150048419 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate electrode disposed byway of a gate insulation film in the inside of the trench. Then, the end of the bottom of the trench is in a rounded shape and the gate insulation film in contact with the end of the bottom of the trench is in a rounded shape. By providing the end of the bottom of the trench with a roundness as described above, a thickness of the gate insulation film situated between the end of the bottom of the gate electrode and the end of the bottom of the trench can be decreased. Thus, the channel is formed also at the end of the bottom of the trench to reduce the resistance of the channel. | 2015-02-19 |
20150048420 | Integrated Circuit with First and Second Switching Devices, Half Bridge Circuit and Method of Manufacturing - An integrated circuit includes a first switching device including a first semiconductor region in a first section of a semiconductor portion and a second switching device including a second semiconductor region in a second section of the semiconductor portion. The first and second sections as well as electrode structures of the first and second switching devices outside the semiconductor portion are arranged along a vertical axis perpendicular to a first surface of the semiconductor portion. | 2015-02-19 |
20150048421 | HIGH ELECTRON MOBILITY TRANSISTORS, METHODS OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICES INCLUDING THE SAME - Provided are high electron mobility transistors (HEMTs), methods of manufacturing the HEMTs, and electronic devices including the HEMTs. An HEMT may include an impurity containing layer, a partial region of which is selectively activated. The activated region of the impurity containing layer may be used as a depletion forming element. Non-activated regions may be disposed at opposite side of the activated region in the impurity containing layer. A hydrogen content of the activated region may be lower than the hydrogen content of the non-activated region. In another example embodiment, an HEMT may include a depletion forming element that includes a plurality of regions, and properties (e.g., doping concentrations) of the plurality of regions may be changed in a horizontal direction. | 2015-02-19 |
20150048422 | A METHOD FOR FORMING A CRYSTALLINE COMPOUND III-V MATERIAL ON A SINGLE ELEMENT SUBSTRATE - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 2015-02-19 |
20150048423 | SEMICONDUCTOR DEVICE HAVING A III-V CRYSTALLINE COMPOUND MATERIAL SELECTIVELY GROWN ON THE BOTTOM OF A SPACE FORMED IN A SINGLE ELEMENT SUBSTRATE. - A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench. | 2015-02-19 |
20150048424 | STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD - A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern. | 2015-02-19 |
20150048425 | Gate array architecture with multiple programmable regions - An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit. | 2015-02-19 |
20150048426 | IMAGE SENSOR INCLUDING SOURCE FOLLOWER - Provided is an image sensor including a source follower transistor. The source follower transistor may include a channel structure that is provided between a source and a drain, and includes a first semiconductor layer, a second semiconductor layer, and a blocking structure. The first semiconductor layer may be spaced apart from a gate insulating layer of the source follower transistor by a first depth or more. Carriers may move from the source of the source follower transistor to the drain thereof through the first semiconductor layer. | 2015-02-19 |
20150048427 | IMAGE SENSOR PIXEL CELL WITH SWITCHED DEEP TRENCH ISOLATION STRUCTURE - A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion. | 2015-02-19 |
20150048428 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME - A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area. | 2015-02-19 |
20150048429 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned. | 2015-02-19 |
20150048430 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure. | 2015-02-19 |
20150048431 | METHOD FOR FORMING A CONTACT ON A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A method for forming a contact on a semiconductor substrate includes: applying a metal to an exposed partial area of an outer side of the semiconductor substrate and/or of a layer applied to the semiconductor substrate, the partial area being surrounded by at least one edge region of an insulating layer, and the at least one edge region of the insulating layer being at least partially covered by the metal; heating the semiconductor substrate, whereby the metal which is applied to the exposed partial area reacts with at least one semiconductor material of the partial area to form a semiconductor-metal material as the end material or a further processing material of the at least one contact; and etching using an etching material having a higher etching rate for the metal than for the semiconductor-metal material. | 2015-02-19 |
20150048432 | Meander Line Resistor Structure - A system comprises a first transistor comprising a first active region and a second active region, a first resistor comprising a plurality of first vias connected in series, wherein the first resistor is over the first active region, a second resistor comprising a plurality of second vias connected in series, wherein the second resistor is over the second active region, a second transistor comprising a third active region and a fourth active region, a capacitor having a terminal electrically coupled to the fourth active region and a bit line electrically coupled to the third active region. | 2015-02-19 |
20150048433 | Contact Formation for Split Gate Flash Memory - An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array. | 2015-02-19 |
20150048434 | Structure and Method of Manufacturing a Stacked Memory Array for Junction-Free Cell Transistors - A three-dimensional NAND memory device and an associated method for manufacturing this device are provided. The three-dimensional NAND memory device includes a source contact electrically isolated from a conductive gate material. The source contact also electrically connects a conductive source line to a first silicon strip and a second silicon strip through the conductive gate material. | 2015-02-19 |
20150048435 | SEMICONDUCTOR DEVICE - A semiconductor device comprising four semiconductor pillars extending in a direction perpendicular to a substrate, a connection channel formed on the substrate and connected to one ends of the four semiconductor pillars, a source line connected to the other ends of first and second semiconductor pillars adjacent to each other among the four semiconductor pillars, a bit line connected to the other ends of third and fourth semiconductor pillars among the four semiconductor pillars, first to fourth stack structures, which are formed along the first to fourth semiconductor pillars, respectively, between the source and bit lines and the substrate, and each includes a pass word line, at least one word line and a select line which are stacked over the substrate, and a memory layer interposed between the word line and each of the first to fourth semiconductor pillars. | 2015-02-19 |
20150048436 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD FOR THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate; an element isolation insulating film buried in the semiconductor substrate so as to isolate adjacent element; a memory cell having a first insulating film and a charge accumulation film; a second insulating film formed on the charge accumulation films of the memory cells and the element isolation insulating film; and a control electrode film formed on the second insulating film. An upper surface of the element isolation insulating film is lower than an upper surface of the charge accumulation film, the second insulating film is provided with a cell upper portion on the charge accumulation film and an inter-cell portion on the element isolation insulating film, and a dielectric constant of the cell upper portion is lower than a dielectric constant of the inter-cell portion. | 2015-02-19 |
20150048437 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes an insulating film with a recess formed in an upper surface, and a conductive film provided on the insulating film and containing silicon, carbon and an impurity serving as an acceptor or donor for silicon. Carbon concentration of a first portion of the conductive film in contact with the insulating film is lower than carbon concentration of a second portion of the conductive film located in the recess and being equidistant from the insulating film placed on both sides thereof. | 2015-02-19 |
20150048438 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film formed on the semiconductor layer; an organic molecular layer that is formed on the tunnel insulating film, and includes first organic molecules and second organic molecules having a smaller molecular weight than the first organic molecules, the first organic molecules each including a first alkyl chain or a first alkyl halide chain having one end bound to the tunnel insulating film, the first organic molecules each including a charge storage portion bound to the other end of the first alkyl chain or the first alkyl halide chain, the second organic molecules each including a second alkyl chain or a second alkyl halide chain having one end bound to the tunnel insulating film; a block insulating film formed on the organic molecular layer; and a control gate electrode formed on the block insulating film. | 2015-02-19 |
20150048439 | SPLIT GATE EMBEDDED MEMORY TECHNOLOGY AND METHOD OF MANUFACTURING THEREOF - Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure. | 2015-02-19 |
20150048440 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 2015-02-19 |
20150048441 | SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS - A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm. | 2015-02-19 |
20150048442 | SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR COLUMNS - A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance. | 2015-02-19 |
20150048443 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. | 2015-02-19 |
20150048444 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 2015-02-19 |
20150048445 | Semiconductor Chip with Integrated Series Resistances - A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region. | 2015-02-19 |
20150048446 | REDUCTION OF OXIDE RECESSES FOR GATE HEIGHT CONTROL - An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height. | 2015-02-19 |
20150048447 | LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICE WITH TAPERED DRIFT ELECTRODE - A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region, and partially overlaps the drift region. Floating gate pieces are over the STI structure. A conformal dielectric layer is on the top surface and on the gate conductor and floating gate pieces and forms a mesa above the gate conductor and floating gate pieces. A conformal etch-stop layer is embedded within the conformal dielectric layer. A drift electrode is formed on the conformal etch-stop layer over, relative to the top surface, the drift region. The drift electrode has a variable thickness relative to the top surface. | 2015-02-19 |
20150048448 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. | 2015-02-19 |
20150048449 | High Voltage Semiconductor Device and Method of Forming the Same - A high voltage semiconductor device includes a semiconductor substrate having a first conductivity type and including a low voltage part and a high voltage part, a semiconductor layer having a second conductivity type on the semiconductor substrate, a body region having the first conductivity type on the semiconductor layer, a first buried layer having the second conductivity type between the high voltage part of the semiconductor substrate and the semiconductor layer, and a second buried layer having the first conductivity type and having sidewalls inside sidewalls of the first buried layer and extending deeper into the substrate than the first buried layer. A surface of the body region adjacent the substrate is spaced apart from a surface of the second buried layer remote from the substrate such that a portion of the semiconductor layer is disposed therebetween. | 2015-02-19 |
20150048450 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A protective diode has a basic structure including an n | 2015-02-19 |
20150048451 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region. The gate structure is on the semiconductor substrate, and has a first gate sidewall and a second gate sidewall opposite to the first gate sidewall. The first doped contact region has a first type conductivity and is formed in the semiconductor substrate on the first gate sidewall of the gate structure. The second doped contact region has the first type conductivity and is formed in the semiconductor substrate on the second gate sidewall of the gate structure. The well doped region has the first type conductivity and is under the first doped contact region. | 2015-02-19 |
20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 2015-02-19 |
20150048453 | FinFETs and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region. | 2015-02-19 |
20150048454 | METHOD FOR FABRICATING A GATE ALL AROUND DEVICE - The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base. | 2015-02-19 |
20150048455 | SELF-ALIGNED GATE CONTACT STRUCTURE - Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided. | 2015-02-19 |
20150048456 | METAL GATE FEATURES OF SEMICONDUCTOR DIE - A semiconductor die comprises two or more active regions over a substrate. A first set of dummy blocks are over the substrate, in contact with one another, and completely surrounding at least one of the two or more active regions. A second set of dummy blocks are over the substrate and farther from the at least one active region surrounded by the first set of dummy blocks than the dummy blocks of the first set of dummy blocks. Each of the dummy blocks of the first set of dummy blocks has individual surface areas, each of the dummy blocks of the second set of dummy blocks has individual surface areas, and the individual surface areas of each of the dummy blocks of the second set of dummy blocks is larger than the individual surface areas of each of the dummy blocks of the first set of dummy blocks. | 2015-02-19 |
20150048457 | Mask Optimization for Multi-Layer Contacts - A method for mask optimization, the method including moving any features of a gate contact mask that are in violation of a spacing rule to a second layer contact mask, splitting an elongated feature of the second layer mask that is too close to a feature moved to the second layer mask from the gate contact mask, and connecting two split features of a first layer contact mask, the split features corresponding to the elongated feature of the second layer mask. | 2015-02-19 |
20150048458 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method for manufacturing the same. The method may include: forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopant to the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack comprising the first metal gate layer, the high K gate dielectric layer, and the interfacial oxide layer. | 2015-02-19 |
20150048459 | DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP - A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate. | 2015-02-19 |
20150048460 | GATE STRUCTURE FOR SEMICONDUCTOR DEVICE - A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin. | 2015-02-19 |
20150048461 | DEVICE WITH A MICRO- OR NANOSCALE STRUCTURE - A device with a micro- or nanoscale structure representing one or more of a mechanical structure, a sensing element, an active and/or passive electrical circuitry, comprises a component ( | 2015-02-19 |
20150048462 | SENSOR PACKAGE AND METHOD OF FORMING SAME | 2015-02-19 |
20150048463 | PACKAGE DEVICE FOR MICROELECTROMECHANICAL INERTIAL SENSOR - A package device for a microelectromechanical inertial sensor comprises a ceramic substrate having an upper accommodation space and a lower accommodation and having a plurality of interconnect metal lines thereinside; a microelectromechanical system (MEMS) chip mounted inside the upper accommodation of the ceramic substrate and electrically connected with the interconnect metal lines; a top cover arranged on the ceramic substrate and sealing the upper accommodation space; and an integrated circuit (IC) chip mounted inside the lower accommodation space and electrically connected with the interconnect metal lines. The present invention can improve the reliability of components, increase the yield and decrease the fabrication cost. | 2015-02-19 |
20150048464 | SEMICONDUCTOR DEVICE HAVING PINNED LAYER WITH ENHANCED THERMAL ENDURANCE - A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer. | 2015-02-19 |
20150048465 | SMALL FORM FACTOR MAGNETIC SHIELD FOR MAGNETORESTRICTIVE RANDOM ACCESS MEMORY (MRAM) - Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation. | 2015-02-19 |
20150048466 | IMAGE SENSOR AND FABRICATING METHOD OF IMAGE SENSOR - The present invention provides an image sensor and a fabricating method of the image sensor. The image sensor comprises: a first type epitaxial layer, a photodiode region, a first type well region, a gate region of a source follower transistor, and a first type implant isolation region. The first type well region is formed within the first type epitaxial layer with a first horizontal distance to the photodiode region and a vertical distance to a surface of the first type epitaxial layer. The gate region of a source follower transistor is formed on the surface of the first type epitaxial layer and above the first type well region, and has a second horizontal distance to the photodiode region. There is a distance between the first type implant isolation region and the first type well region as an anti-blooming path. | 2015-02-19 |
20150048467 | Structure of Dielectric Grid with a Metal Pillar for Semiconductor Device - An image sensor device and a method for manufacturing the image sensor device are provided. An image sensor device includes a substrate, sensor elements disposed at a front surface of the substrate, and a dielectric grid disposed over a back surface of the substrate. The dielectric grid includes a first dielectric layer as a bottom portion, a metal pillar, as a core portion of a upper portion, disposed over the first dielectric layer and a second dielectric layer wrapping around the metal pillar. The image sensor device also includes a stack of layers disposed over the back surface of the substrate. Refractive index of each layers increases from top layer to bottom layer. The image sensor device also includes a color filter and a microlens disposed over the back surface of the substrate. | 2015-02-19 |
20150048468 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes a first light-receiving portion and a first light guide layer. The first light-receiving portion is formed in the surface of a semiconductor substrate. The first light guide layer is formed to correspond to a portion above the first light-receiving portion, and has an inverse tapered shape in which the width becomes larger from an upper surface a lower surface. The inverse tapered shape ranges from the upper surface the lower surface. | 2015-02-19 |
20150048469 | IMAGE SENSOR - An image sensor is provided. The image sensor comprises a substrate including a first surface and a second surface which are opposite to the first surface and a photoelectric converting element formed therein, a graphene layer formed on the first surface of the substrate to be flat, and a plurality of micro lenses which is formed on the graphene layer. | 2015-02-19 |
20150048470 | ELECTROMAGNETIC RADIATION MICRO DEVICE, WAFER ELEMENT AND METHOD FOR MANUFACTURING SUCH A MICRO DEVICE - The invention refers to an electromagnetic radiation sensor micro device for detecting electromagnetic radiation, which device comprises a substrate and a cover at least in part consisting of an electromagnetic radiation transparent material, and comprising a reflection reducing coating and providing a hermetic sealed cavity and an electromagnetic radiation detecting unit arranged within the cavity. The reflection reducing coating is arranged in form of a multi-layer thin film stack, which comprises a first layer and a second layer arranged one upon the other. The first layer has a first refractive index and the second layer has a second refractive index different from the one of said first layer. First and second layer are of such layer thickness that for a certain wavelength there is destructive interference. The invention also refers to a wafer element as well as method for manufacturing such a device. | 2015-02-19 |
20150048471 | SEMICONDUCTOR MODULE HAVING AN INTEGRATED WAVEGUIDE FOR RADAR SIGNALS - A semiconductor module, having an integrated circuit, a rewiring layer for externally connecting the integrated circuit, and at least one waveguide integrated into the semiconductor module for radar signals having a conductive pattern, which laterally surrounds the interior of the waveguides, the integrated circuit and the at least one waveguide being embedded, at least in regions, in a housing material of the semiconductor module; as well as a radar sensor, a motor vehicle radar system having such a semiconductor module, and a method for producing a semiconductor module. | 2015-02-19 |
20150048472 | MULTI-PIXEL AVALANCHE PHOTODIODE - Semiconductor avalanche photo transistors and methods of manufacturing the same, operable for internal amplification of a photo signal and for use in detection of weak light signals, gamma rays and nuclear particles. The multi-pixel avalanche photo transistor devices can comprise a semiconductor layer, a plurality of semiconductor areas (pixels) forming a p-n-junction with the semiconductor layer, a common conductive grid separated from the semiconductor layer by a dielectric layer and individual micro-resistors connected said semiconductor areas with the common conductive grid. Systems and methods described can be operable to decrease optical crosstalk at high signal amplification and the special capacity of the multi-pixel avalanche photo transistor, as well as improve speed its photo response. | 2015-02-19 |
20150048473 | IMAGE PICKUP ELEMENT AND IMAGE PICKUP DEVICE - An image pickup element includes: a photoelectric conversion film provided on a semiconductor substrate and including a chalcopyrite-based compound; an insulating film provided on a light incident surface side of the photoelectric conversion film; and a conductive film provided on the insulating film. | 2015-02-19 |
20150048474 | IMAGE PICKUP UNIT AND ELECTRONIC APPARATUS - A solid-state image pickup unit includes substrate; a red pixel including a red charge storage section; a blue pixel including a blue charge storage section; and a green pixel including a plurality of green charge storage sections, the red charge storage section and the blue charge storage section being provided in the substrate. Then, the plurality of green charge storage sections are arranged in the substrate along a thickness direction of the substrate. | 2015-02-19 |
20150048475 | Semiconductor Structures With Shallow Trench Isolations - A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed. | 2015-02-19 |
20150048476 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE - Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches. | 2015-02-19 |
20150048477 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a surface having a plurality of portions and a dielectric material over the surface. The dielectric material includes an aspect ratio substantially equal to or greater than a predetermined value. | 2015-02-19 |
20150048478 | TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures. | 2015-02-19 |
20150048479 | SELF-ALIGNED VIA FUSE - A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second via opening is self-aligned to a second trench in the substrate, a portion of the second via opening overlaps a portion of the first via opening to form an overlap region, and the overlap region having a width (w) equal to or greater than a space (s) between the first trench and the second trench, and removing a portion of the substrate in the overlap region to form a bridge opening, the bridge opening is adjacent to the first and second via openings and extends between the first and second trenches. | 2015-02-19 |
20150048480 | INTEGRATED PASSIVE DEVICE (IPD) ON SUBTRATE - Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer. | 2015-02-19 |
20150048481 | SEMICONDUCTOR DEVICE - To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. | 2015-02-19 |
20150048482 | SEMICONDUCTOR CAPACITOR - A semiconductor capacitor is includes a substrate, a plurality of odd layers formed on the substrate, and a plurality of even layers formed on the substrate. Each odd layer includes a plurality of first odd fingers and a first odd terminal electrically connected thereto, and a plurality of second odd fingers and a second odd terminal electrically connected thereto. Each even layer includes a plurality of first even fingers and a first even terminal electrically connected thereto, and a plurality of second even fingers and a second even terminal electrically connected thereto. The semiconductor capacitor further includes at least a first odd connecting structure electrically connecting the first odd terminals, at least a second odd connecting structure electrically connecting the second odd terminals, at least a first even connecting structure electrically connecting the first even terminals, and at least a second even connecting structure electrically connecting the second even terminals. | 2015-02-19 |
20150048483 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer. | 2015-02-19 |
20150048484 | Passivation for Group III-V Semiconductor Devices Having a Plated Metal Layer over an Interlayer Dielectric Layer - A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress. | 2015-02-19 |
20150048485 | METHODS OF FORMING FILMS INCLUDING GERMANIUM TIN AND STRUCTURES AND DEVICES INCLUDING THE FILMS - Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein. | 2015-02-19 |
20150048486 | SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening. | 2015-02-19 |
20150048487 | PLASMA POLYMERIZED THIN FILM HAVING HIGH HARDNESS AND LOW DIELECTRIC CONSTANT AND MANUFACTURING METHOD THEREOF - The present invention relates to a plasma polymerized thin film having high hardness and a low dielectric constant and a manufacturing method thereof, and in particular, relates to a plasma polymerized thin film having high hardness and a low dielectric constant for use in semiconductor devices, which has improved mechanical strength properties such as hardness and elastic modulus while having a low dielectric constant, and a manufacturing method thereof. | 2015-02-19 |
20150048488 | Semiconductor Devices, Methods of Manufacture Thereof, and Inter-metal Dielectric (IMD) Structures - Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure. | 2015-02-19 |