07th week of 2010 patent applcation highlights part 39 |
Patent application number | Title | Published |
20100041164 | Mechanical device for mixing a fluid sample with a treatment solution - A method of preparing a fluid sample for use in a fluid analyte monitor, the method including drawing a fluid sample into a capillary channel in a body having a septum piercing projection; piercing a first septum covering a treatment solution chamber with the septum piercing projection, thereby exposing the fluid sample in the capillary channel to the contents of the treatment solution chamber; mixing the fluid sample with the contents of the treatment solution chamber; and piercing a second septum covering the treatment solution channel such that the mixed fluid and treatment solution chamber contents are received into a fluid analyte meter. The method may also include shaking the treatment solution chamber with the capillary channel therein, thereby mixing the fluid sample with the contents of the treatment solution chamber. | 2010-02-18 |
20100041165 | PROBE-IMMOBILIZED CARRIER STORING MANUFACTURING CONDITION DATA AND MANUFACTURING METHOD AND APPARATUS THEREOF, DETECTING METHOD OF TARGET SUBSTANCE BY USE OF THE PROBE-IMMOBILIZED CARRIER, AND MEASURING APPARATUS, RECORDING MEDIUM, KIT AND SYSTEM FOR USE IN THE DETECTING METHOD - A target substance is more accurately detected by recording a manufacturing condition specific to a probe-immobilized carrier that influences a measurement result for the detection of the target substance, and correcting the measurement result obtained from the detection of the target substance by use of the probe-immobilized carrier on the basis of the recorded manufacturing condition. The influence of variations in the immobilization states of the probe onto the solid phase carrier on the measurement result of the target substance can be eliminated. | 2010-02-18 |
20100041166 | Method and system for detecting a target within a polupation of molecules | 2010-02-18 |
20100041167 | DRUG FOR DIAGNOSING LARGE INTESTINAL CANCER AND/OR POLYP, OBSERVING POSTOPERATIVE COURSE AND MONITORING RECURRENCE - The present invention is directed to a method for diagnosing large intestinal cancer and/or polyp and a method for observing postoperative course or monitoring recurrence thereof, wherein each method includes detecting cystatin SN protein by use of an anti-cystatin SN antibody. The present invention is able to provide a kit for assaying cystatin SN, which can be used, in a simple manner, in a diagnosis performed prior to conventional barium enema examination and endoscopic examination which impose burdens on patients; as an indicator of metastasis and recurrence; and in the evaluation of therapeutic effects. The present invention provides a method for diagnosing or monitoring large intestinal cancer and/or polyp which can be performed in a simple manner, and thus can allow to design a new regimen rapidly. | 2010-02-18 |
20100041168 | METHODS OF FABRICATING MAGNETIC MEMORY DEVICES WITH THIN CONDUCTIVE BRIDGES - A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described. | 2010-02-18 |
20100041169 | Method of forming a resin cover lens of LED assembly - A method of forming the resin cover lens of LED assembly uses transparent materials, such as plastics, PP (Polypropylene), PET (Polyethylene teraphthalate), PC (Polycarbonate), PE (Polyethylene) or glass to produce the mold for making lens; and uses liquid transparent resin that can be quickly cured under EB (electron-beam) radiation, such as PU (Polyurethane), epoxy, silicon, acrylic resin or its copolymer et al., or the above resin added with photo initiator and curable under UV radiation; and fills in the mold cavity with the resin; and selects EB or UV to cure the liquid transparent resin inside the cavity to form lens. The new process in the invention is to reduce the curing time for making lens that helps LED assembly achieve high throughput rate and mass production. | 2010-02-18 |
20100041170 | Package-Integrated Thin Film LED - LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features. There is very little absorption of light by the thinned epitaxial layer, there is high thermal conductivity to the package because the LED layers are directly bonded to the package substrate without any support substrate therebetween, and there is little electrical resistance between the package and the LED layers so efficiency (light output vs. power input) is high. The light extraction features of the LED layer further improves efficiency. | 2010-02-18 |
20100041171 | LIGHT-EMITTING DEVICE - To provide a light-emitting device which can emit light with high luminance and high efficiency, and is excellent in durability. The light-emitting device includes an organic compound layer containing a phenanthroline compound represented by the general formula [I] and a carbonate. | 2010-02-18 |
20100041172 | METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - The present invention provides a method for fabricating a flip chip semiconductor light-emitting device which includes a substrate and a semiconductor multi-layer structure. The method of the invention includes the steps of: (a) forming a semiconductor multi-layer structure on a first substrate; (b) flip-chip bonding the semiconductor multi-layer structure on a second substrate; (c) removing the first substrate, so as to expose a first surface of the semiconductor multi-layer structure; and (d) forming a plurality of protrusions, arranged periodically, on the first surface. Particularly, the protrusions comprise a first protrusion and a second protrusion adjacent to the first protrusion, the first protrusion and the second protrusion both having a peak, and the second surface having a bottom, wherein the ratio of the vertical distance between one of the peaks and the bottom and the horizontal distance between the two peaks is in between 0.01 and 10. | 2010-02-18 |
20100041173 | METHOD OF FABRICATING LIGHT EMITING DIODE CHIP - The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination. As the directional angle of the light emitting diode chip is wider, when a white light emitting device is fabricated using the light emitting diode chip and a phosphor, light uniformity can be adjusted even though the phosphor is not concentrated at the center of the device. Thus, the overall light emitting efficiency can be enhanced by reducing a light blocking phenomenon caused by the increased amount of the phosphor distributed at the center portion. | 2010-02-18 |
20100041174 | LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - An LCD panel and a method for manufacturing the same is disclosed, in which light leakage is prevented from occurring by forming a dummy pattern in an array peripheral region. The LCD panel includes a first substrate having an array region and an array peripheral region, a gate line on the first substrate, a gate insulating film on the entire surface of the first substrate including the gate line, a data line arranged to cross the gate line for defining a pixel region on the array region, a light leakage prevention film formed between the gate and/or data lines of the array peripheral region for preventing light leakage in the panel, and a TFT and a pixel electrode formed in each pixel region. | 2010-02-18 |
20100041175 | METHOD OF PURIFYING A CRYSTALLINE SILICON SUBSTRATE AND PROCESS FOR PRODUCING A PHOTOVOLTAIC CELL - The invention relates to a method of purifying a crystalline silicon substrate and to a process for producing a photovoltaic cell. The method of purifying a crystalline silicon substrate according to the invention is of the type that includes a step of extracting impurities by external gettering and which includes, before said step of extracting the impurities by external gettering, at least one step of rapidly annealing the substrate at a temperature of between 750° C. and 1000° C. inclusive for a time of between 1 second and 10 minutes inclusive. The invention is particularly applicable in the photovoltaic cell field. | 2010-02-18 |
20100041176 | PATTERNED ASSEMBLY FOR MANUFACTURING A SOLAR CELL AND A METHOD THEREOF - Apparatuses and methods for manufacturing a solar cell are disclosed. In a particular embodiment, the solar cell may be manufactured by disposing a solar cell in a chamber having a particle source; disposing a patterned assembly comprising an aperture and an assembly segment between the particle source and the solar cell; and selectively implanting first type dopants traveling through the aperture into a first region of the solar cell while minimizing introduction of the first type dopants into a region outside of the first region. | 2010-02-18 |
20100041177 | CONTROLLED GROWTH OF LARGER HETEROJUNCTION INTERFACE AREA FOR ORGANIC PHOTOSENSITIVE DEVICES - An optoelectronic device and a method of fabricating a photosensitive optoelectronic device includes depositing a first organic semiconductor material on a first electrode to form a continuous first layer having protrusions, a side of the first layer opposite the first electrode having a surface area at least three times greater than an underlying lateral cross-sectional area; depositing a second organic semiconductor material directly on the first layer to form a discontinuous second layer, portions of the first layer remaining exposed; depositing a third organic semiconductor material directly on the second layer to form a discontinuous third layer, portions of at least the second layer remaining exposed; depositing a fourth organic semiconductor material on the third layer to form a continuous fourth layer, filling any exposed gaps and recesses in the first, second, and third layers; and depositing a second electrode on the fourth layer, wherein at least one of the first electrode and the second electrode is transparent, and the first and third organic semiconductor materials are both of a donor-type or an acceptor-type relative to second and fourth organic semiconductor materials, which are of the other material type. | 2010-02-18 |
20100041178 | Demounting of Inverted Metamorphic Multijunction Solar Cells - A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; attaching a surrogate second substrate over the third solar subcell and removing the first substrate; and etching a first trough around the periphery of the solar cell to the surrogate second substrate so as to form a mesa structure on the surrogate second substrate and facilitate the removal of said solar cell from the surrogate second substrate. | 2010-02-18 |
20100041179 | Forming Substrate Structure by Filling Recesses with Deposition Material - A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure. | 2010-02-18 |
20100041180 | Methods of Forming Semiconductor Constructions and Assemblies - The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies. | 2010-02-18 |
20100041181 | HEAT DISSIPATING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure. | 2010-02-18 |
20100041182 | METHOD, SYSTEM, AND APPARATUS FOR A SECURE BUS ON A PRINTED CIRCUIT BOARD - A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area. | 2010-02-18 |
20100041183 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, in which a size reduction may be attempted. The device includes a semiconductor chip, an external connection terminal pad electrically connected to the semiconductor chip, and an encapsulation resin encapsulating the semiconductor chip, wherein a wiring pattern on which the external connection terminal pad is formed is provided between the semiconductor chip and the external connection terminal pad, and the semiconductor chip is flip-chip bonded to the wiring pattern. | 2010-02-18 |
20100041184 | Molding apparatus for manufacturing a semiconductor device and method using the same - A molding apparatus including an upper half having a substrate mounting plate; and a lower half coupled with the upper half to form a cavity there between, wherein the substrate mounting plate faces the cavity, wherein the lower half includes a projecting part which has a top surface which faces the cavity and which projects from the bottom surface of the lower half toward a substantial center point of the substrate mounting plate, wherein the substrate mounting plate is adjustably mounted on the upper half and movable toward the lower half, and wherein the upper half includes a clamp mounted thereon which surrounds the projecting part when the upper and lower halves are coupled with each other. | 2010-02-18 |
20100041185 | METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT - A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer is formed on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation. A first buried oxide layer is formed between the substrate and the first layer. Micro-cavities are formed in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer. A first field effect transistor of a first conductivity type is formed in or on the first layer. A second field effect transistor of a second conductivity type is formed in or on the second layer. | 2010-02-18 |
20100041186 | IMPACT IONISATION MOSFET METHOD - A method of manufacturing an I-MOS device includes forming a semiconductor layer ( | 2010-02-18 |
20100041187 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 μm or less in width, and allowing the metal to react with silicon. | 2010-02-18 |
20100041188 | ROBUST TRANSISTORS WITH FLUORINE TREATMENT - A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region. | 2010-02-18 |
20100041189 | SELECTIVE REMOVAL OF A SILICON OXIDE LAYER - A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains. | 2010-02-18 |
20100041190 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel TFT is to be formed; thus, a source region and a drain region are formed in a semiconductor film of the other one of the p-channel TFT and the n-channel TFT by adding first impurity ions using the second resist mask and the third resist mask. After that, the first resist mask, the second resist mask, and the third resist mask are removed, and a source region and a drain region are formed in a semiconductor film of the one of the p-channel TFT and the n-channel TFT by adding second impurity ions using a fourth resist mask. | 2010-02-18 |
20100041191 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE - A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor at a first end of the fin; and forming a back-gate at a lateral side of the fin. The back-gate is in electrical contact with the conductive region and is structured and arranged to influence a threshold voltage of the fin. | 2010-02-18 |
20100041192 | Method For Preparing Multi-Level Flash Memory Structure - A method for preparing a multi-level flash memory structure comprises the steps of forming a protrusion in a semiconductor substrate, forming a plurality of storage structures at the sides of the protrusion, forming a dielectric layer overlying the storage structures and the protrusion of the semiconductor substrate, forming a gate structure on the dielectric layer, and forming a plurality of diffusion regions at the sides of the protrusion. Each of the storage structures includes a charge-trapping site and an insulation structure isolating the charge-trapping site from the semiconductor substrate. | 2010-02-18 |
20100041193 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds. | 2010-02-18 |
20100041194 | SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF - A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell. | 2010-02-18 |
20100041195 | METHOD OF MANUFACTURING SILICON CARBIDE SELF-ALIGNED EPITAXIAL MOSFET FOR HIGH POWERED DEVICE APPLICATIONS - A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer. | 2010-02-18 |
20100041196 | Method for Fabricating a Transistor having a Recess Gate Structure - A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate. | 2010-02-18 |
20100041197 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING RECESSED-CHANNEL-ARRAY MOSFET HAVING A HIGHER OPERATIONAL SPEED - A semiconductor device includes a recessed-channel-array MOSFET including a gate electrode having a portion received in a recess. The gate insulting film has a first portion made of silicon oxide in contact with the sidewall of the recess and a second portion made of silicon oxynitride in contact with the bottom of the recess. The first portion has an equivalent oxide thickness larger than the equivalent oxide thickness of the second portion to reduce the parasitic capacitance of the gate electrode. | 2010-02-18 |
20100041198 | TRIPLE GATE AND DOUBLE GATE FINFETS WITH DIFFERENT VERTICAL DIMENSION FINS - A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs. | 2010-02-18 |
20100041199 | FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs. | 2010-02-18 |
20100041200 | Semiconductor transistor device and method for manufacturing the same - A semiconductor transistor device and a method for manufacturing the same are provided. The method includes forming a silicon epitaxial layer having a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate and forming a source and drain junction by ion implantation and rapid annealing in the silicon semiconductor substrate in which the silicon epitaxial layer is formed. The semiconductor transistor device includes a silicon epitaxial layer formed to have a predetermined thickness in source and drain diffusion regions of a silicon semiconductor substrate. Thus, since a salicide layer is used without increase of leakage current, the transistor device having low power and high performance can be manufactured. | 2010-02-18 |
20100041201 | Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions - Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques. | 2010-02-18 |
20100041202 | Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures - In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines. | 2010-02-18 |
20100041203 | Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors - A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate. | 2010-02-18 |
20100041204 | Methods Of Making Capacitors, DRAM Arrays and Electronic Systems - Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems. | 2010-02-18 |
20100041205 | METHOD FOR SIMULTANEOUSLY TENSILE AND COMPRESSIVE STRAINING THE CHANNELS OF NMOS AND PMOS TRANSISTORS RESPECTIVELY - A method of forming a microelectronic device comprising, on a same support: at least one semi-conductor zone strained according to a first strain, and at least one semi-conductor zone strained according to a second strain, different to the first strain, comprising: the formation of semi-conductor zones above a pre-strained layer, then trenches extending through the thickness of the pre-strained layer, the dimensions and the layout of the semi-conductor zones as a function of the layout and the dimensions of the trenches being so as to obtain semi-conductor zones having a strain of the same type as that of the pre-strained layer and semi-conductor zones having a strain of a different type to that of the pre-strained layer. | 2010-02-18 |
20100041206 | METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to a method of manufacturing a MONOS nonvolatile semiconductor memory device, a tunnel insulating film, a charge storage layer, a block insulating film containing a metal oxide and a control gate electrode are stacked on a semiconductor substrate. Heat treatment is carried out in an atmosphere containing an oxidizing gas after the tunnel insulating film, the charge storage layer and the block insulating film are stacked on the semiconductor substrate. Thereafter, the control gate electrode is formed on the block insulating film. | 2010-02-18 |
20100041207 | HIGH DENSITY PLASMA GAPFILL DEPOSITION-ETCH-DEPOSITION PROCESS USING FLUOROCARBON ETCHANT - A high density plasma dep/etch/dep method of depositing a dielectric film into a gap between adjacent raised structures on a substrate disposed in a substrate processing chamber. The method deposits a first portion of the dielectric film within the gap by forming a high density plasma from a first gaseous mixture flown into the process chamber, etches the deposited first portion of the dielectric film by flowing an etchant gas comprising C | 2010-02-18 |
20100041208 | SEMICONDUCTOR DEVICE MANUFACTURED WITH A DOUBLE SHALLOW TRENCH ISOLATION PROCESS - A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area. | 2010-02-18 |
20100041209 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: bringing a first major surface of a first substrate into close contact with a second major surface of a second substrate being different in thermal expansion coefficient from the first substrate at a first temperature higher than room temperature; and bonding the first substrate and the second substrate by heating the first substrate and the second substrate to a second temperature higher than the first temperature with the first major surface being in close contact with the second major surface. | 2010-02-18 |
20100041210 | METHOD OF PROCESSING OPTICAL DEVICE WAFER - A method of dividing an optical device wafer includes: a laser beam processing step of performing laser beam processing on the face side of an optical device wafer so as to form breakage starting points along streets; a protective plate bonding step of bonding the face side of the optical device wafer to a surface of a highly rigid protective plate with a bonding agent permitting peeling; a back side grinding step of grinding the back side of the optical device wafer so as to form the optical device wafer to a finished thickness of optical devices; a dicing tape adhering step of adhering the back-side surface of the optical device wafer to a dicing tape; a cut groove forming step of cutting the protective plate bonded to the optical device wafer along the streets so as to form cut grooves; and a wafer dividing step of exerting an external force on the optical device wafer through the protective plate, so as to break up the optical device wafer along the breakage starting points formed along the streets, thereby dividing the optical device wafer into the individual optical devices. | 2010-02-18 |
20100041211 | LAMINATE BODY, METHOD, AND APPARATUS FOR MANUFACTURING ULTRATHIN SUBSTRATE USING THE LAMINATE BODY - Provided is a laminated body comprising a substrate to be ground and a support, where the substrate is ground to a very small thickness and can then be separated from the support without damaging the substrate. One embodiment of the present invention is a laminated body comprising a substrate to be ground, a joining layer in contact with the substrate to be ground, a photothermal conversion layer comprising a light absorbing agent and a heat decomposable resin, and a light transmitting support. After grinding the substrate surface which is opposite that in contact with the joining layer, the laminated body is irradiated through the light transmitting layer and the photothermal conversion layer decomposes to separate the substrate and the light transmitting support. | 2010-02-18 |
20100041212 | FILM FORMING METHOD AND FILM FORMING APPARATUS - The present invention provides a film forming apparatus capable of removing a natural oxide film of a silicon substrate W at a very low temperature, as compared to the related art. The natural oxide film is removed at a low temperature by converting the natural oxide film on the silicon substrate W into a volatile material and evaporating the volatile material. The natural oxide film can be converted into volatile ammonium fluorosilicate by reaction with ammonium fluoride. A single crystal SiGe film can be grown on the silicon substrate W from which the natural oxide film is removed. The film forming apparatus includes an etching chamber, a SiGe growing chamber, and a substrate transport chamber that transports the silicon substrate in a controlled atmosphere. | 2010-02-18 |
20100041213 | Vapor Deposition Reactor For Forming Thin Film - A vapor deposition reactor includes a chamber filled with a first material, and at least one reaction module in the chamber. The reaction module may be configured to make a substrate pass the reaction module through a relative motion between the substrate and the reaction module. The reaction module may include an injection unit for injecting a second material to the substrate. A method for forming thin film includes positioning a substrate in a chamber, filling a first material in the chamber, moving the substrate relative to a reaction module in the chamber, and injecting a second material to the substrate while the substrate passes the reaction module. | 2010-02-18 |
20100041214 | Single crystal substrate and method of fabricating the same - A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or germanium seed layer on the portion of the substrate exposed through the window; depositing a silicon or germanium material layer, which are crystallization target material layers, on the epitaxial growth silicon 6r germanium seed layer and the insulator; and crystallizing the crystallization target material layer by melting and cooling the crystallization target material layer. | 2010-02-18 |
20100041215 | METHODS FOR PREPARATION OF HIGH-PURITY POLYSILICON RODS USING A METALLIC CORE MEANS - The present invention relates to a method for preparing a polysilicon rod using a metallic core means, comprising: installing a core means in an inner space of a deposition reactor used for preparing a silicon rod, wherein the core means is constituted by forming one or a plurality of separation layer(s) on the surface of a metallic core element and is connected to an electrode means; heating the core means by supplying electricity through the electrode means; and supplying a reaction gas into the inner space for silicon deposition, thereby forming a deposition output in an outward direction on the surface of the core means. According to the present invention, the deposition output and the core means can be separated easily from the silicon rod output obtained by the process of silicon deposition, and the contamination of the deposition output caused by impurities of the metallic core element can be minimized, thereby a high-purity silicon can be prepared in a more economic and convenient way. | 2010-02-18 |
20100041216 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures. | 2010-02-18 |
20100041217 | Method of synthesizing silicon wires - A method of synthesizing silicon wires is provided. A substrate is provided. A copper catalyst particle layer is formed on a top surface of the substrate. The reactive device is heated at a temperature of above 450° C. in a flowing protective gas. A mixture of a protective gas and a silicon-based reactive gas is introduced at a temperature above 450° C. at a pressure below 700 Torr to form the silicon wires on the substrate. | 2010-02-18 |
20100041218 | USJ TECHNIQUES WITH HELIUM-TREATED SUBSTRATES - A method of using helium to create ultra shallow junctions is disclosed. A pre-implantation amorphization using helium has significant advantages. For example, it has been shown that dopants will penetrate the substrate only to the amorphous-crystalline interface, and no further. Therefore, by properly determining the implant energy of helium, it is possible to exactly determine the junction depth. Increased doses of dopant simply reduce the substrate resistance with no effect on junction depth. Furthermore, the lateral straggle of helium is related to the implant energy and the dose rate of the helium PAI, therefore lateral diffusion can also be determined based on the implant energy and dose rate of the helium PAI. Thus, dopant may be precisely implanted beneath a sidewall spacer, or other obstruction. | 2010-02-18 |
20100041219 | USJ TECHNIQUES WITH HELIUM-TREATED SUBSTRATES - A method of using helium to create ultra shallow junctions is disclosed. A pre-implantation amorphization using helium has significant advantages. For example, it has been shown that dopants will penetrate the substrate only to the amorphous-crystalline interface, and no further. Therefore, by properly determining the implant energy of helium, it is possible to exactly determine the junction depth. Increased doses of dopant simply reduce the substrate resistance with no effect on junction depth. Furthermore, the lateral straggle of helium is related to the implant energy and the dose rate of the helium PAI, therefore lateral diffusion can also be determined based on the implant energy and dose rate of the helium PAI. Thus, dopant may be precisely implanted beneath a sidewall spacer, or other obstruction. | 2010-02-18 |
20100041220 | METHODS FOR UNIFORMLY OPTICALLY ANNEALING REGIONS OF A SEMICONDUCTOR SUBSTRATE - Methods for uniformly optically annealing regions of a semiconductor substrate and methods for fabricating semiconductor substrates using uniform optical annealing are provided. In accordance with an exemplary embodiment, a method for uniformly optically annealing a semiconductor substrate comprises the step of obtaining an optical reflectance of a first region of the semiconductor substrate. A second region of the semiconductor substrate is fabricated such that the optical reflectance of the second region is substantially equal to the optical reflectance of the first region, wherein the first region is not the second region. The semiconductor substrate is optically annealed. | 2010-02-18 |
20100041221 | HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME - The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention. | 2010-02-18 |
20100041222 | SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same - A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias. | 2010-02-18 |
20100041223 | METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function. | 2010-02-18 |
20100041224 | Non-volatile memory device and method of manufacturing the same - The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode. | 2010-02-18 |
20100041225 | STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE - A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal with a first work function in a central region and forming a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function. | 2010-02-18 |
20100041226 | Process For Through Silicon Via Filing - A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. Low copper concentration and high acidity electroplating solution is used for deposition copper into the through silicon vias. | 2010-02-18 |
20100041227 | METHODS FOR INCORPORATING HIGH DIELECTRIC MATERIALS FOR ENHANCED SRAM OPERATION AND STRUCTURES PRODUCED THEREBY - Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught. | 2010-02-18 |
20100041228 | Method of manufacturing a wiring board - In a method of manufacturing a wiring board, a basic circuit pattern is formed on an insulating plate, and a metal layer is formed on the basic circuit pattern by cold spraying to thereby form a built-up circuit pattern on the basic circuit pattern. | 2010-02-18 |
20100041229 | METHOD AND FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap. | 2010-02-18 |
20100041230 | METHODS FOR FORMING COPPER INTERCONNECTS FOR SEMICONDUCTOR DEVICES - Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed. | 2010-02-18 |
20100041231 | FUSI Integration Method Using SOG as a Sacrificial Planarization Layer - A method for making a transistor | 2010-02-18 |
20100041232 | Adjustable dummy fill - A method of placing a dummy fill layer on a substrate is disclosed (FIG. | 2010-02-18 |
20100041233 | FABRICATION METHODS FOR INTEGRATION CMOS AND BJT DEVICES - Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device. | 2010-02-18 |
20100041234 | Process For Restoring Dielectric Properties - A method for preparing an interlayer dielectric to minimize damage to the interlayer's dielectric properties, the method comprising the steps of: depositing a layer of a silicon-containing dielectric material onto a substrate, wherein the layer has a first dielectric constant and wherein the layer has at least one surface; providing an etched pattern in the layer by a method that includes at least one etch process and exposure to a wet chemical composition to provide an etched layer, wherein the etched layer has a second dielectric constant, and wherein the wet chemical composition contributes from 0 to 40% of the second dielectric constant; contacting the at least one surface of the layer with a silicon-containing fluid; optionally removing a first portion of the silicon-containing fluid such that a second portion of the silicon-containing fluid remains in contact with the at least one surface of the layer; and exposing the at least one surface of the layer to UV radiation and thermal energy, wherein the layer has a third dielectric constant that is restored to a value that is at least 90% restored relative to the second dielectric constant. | 2010-02-18 |
20100041235 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICES - A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x−890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5≦x≦22.1). | 2010-02-18 |
20100041236 | NOVEL METHOD TO INTEGRATE GATE ETCHING AS ALL-IN-ONE PROCESS FOR HIGH K METAL GATE - The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue. | 2010-02-18 |
20100041237 | METHOD FOR FORMING A FINE PATTERN USING ISOTROPIC ETCHING - A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer. | 2010-02-18 |
20100041238 | TUNABLE MULTI-ZONE GAS INJECTION SYSTEM - A tunable multi-zone injection system for a plasma processing system for plasma processing of substrates such as semiconductor wafers. The system includes a plasma processing chamber, a substrate support for supporting a substrate within the processing chamber, a dielectric member having an interior surface facing the substrate support, the dielectric member forming a wall of the processing chamber, a gas injector fixed to part of or removably mounted in an opening in the dielectric window, the gas injector including a plurality of gas outlets supplying process gas at adjustable flow rates to multiple zones of the chamber, and an RF energy source such as a planar or non-planar spiral coil which inductively couples RF energy through the dielectric member and into the chamber to energize the process gas into a plasma state. The injector can include an on-axis outlet supplying process gas at a first flow rate to a central zone and off-axis outlets supplying the same process gas at a second flow rate to an annular zone surrounding the central zone. The arrangement permits modification of gas delivery to meet the needs of a particular processing regime by allowing independent adjustment of the gas flow to multiple zones in the chamber. In addition, compared to consumable showerhead arrangements, a removably mounted gas injector can be replaced more easily and economically. | 2010-02-18 |
20100041239 | Diffractive Optical Element, Lithographic Apparatus and Semiconductor Device Manufacturing Method - A diffractive optical element, a lithographic apparatus including a diffractive optical element, and a semiconductor device manufacturing method diffract a radiation beam onto an output plane. The diffractive optical element has a plurality of unit cells each having a phase structure for adjusting a cross-sectional intensity distribution of an incoming radiation beam into a desired intensity distribution. The unit cells of the diffractive optical element have corresponding phase structures that are arranged adjacently and are mirrored or inverted with respect to each other. | 2010-02-18 |
20100041240 | FOCUS RING, PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A focus ring of a ring shape is disposed to surround a target substrate on a lower electrode on which the target substrate is mounted in a process chamber. The process chamber receives the target substrate and subjects the received target substrate to a plasma process. At the point of time when the focus ring is first used for the plasma process, a distance between a lower side of an edge portion of the target substrate and a portion of the focus ring facing the lower side of the edge portion of the target substrate is set to be equal to or greater than about 0.4 mm. | 2010-02-18 |
20100041241 | HIGH DENSITY PLASMA DIELECTRIC DESPOSITION FOR VOID FREE GAP FILL - A process for void free deposition of dielectric films over high aspect ratio structures using HDP CVD. In a dielectric liner deposition step and the etch to deposition ratio is increased and the deposition pressure is reduced to reduce the aspect ratio of the gap and to deposit a dielectric sidewall on the gap with a significant slope. | 2010-02-18 |
20100041242 | Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme - A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal. | 2010-02-18 |
20100041243 | Precursors for Depositing Silicon-containing Films and Methods for Making and Using Same - Aminosilane precursors for depositing silicon-containing films, and methods for depositing silicon-containing films from these aminosilane precursors, are described herein. In one embodiment, there is provided an aminosilane precursor for depositing silicon-containing film comprising the following formula (I): | 2010-02-18 |
20100041244 | HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. | 2010-02-18 |
20100041245 | HDP-CVD PROCESS, FILLING-IN PROCESS UTILIZING HDP-CVD, AND HDP-CVD SYSTEM - An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step. | 2010-02-18 |
20100041246 | Cleaving Of Substrates - An improved process of substrate cleaving and a device to perform the cleaving are disclosed. In the traditional cleaving process, a layer of microbubbles is created within a substrate through the implantation of ions of a gaseous species, such as hydrogen or helium. The size and spatial distribution of these microbubbles is enhanced through the use of ultrasound energy. The ultrasound energy causes smaller microbubbles to join together and also reduces the straggle. An ultrasonic transducer is acoustically linked with the substrate to facilitate these effects. In some embodiments, the ultrasonic transducer is in communication with the platen, such that ultrasound energy can be applied during ion implantation and/or immediately thereafter. In other embodiments, the ultrasonic energy is applied to the substrate during a subsequent process, such as an anneal. | 2010-02-18 |
20100041247 | PROGRAM FOR CONTROLLING LASER APPARATUS AND RECORDING MEDIUM FOR RECORDING PROGRAM FOR CONTROLLING LASER APPARATUS AND CAPABLE OF BEING READ OUT BY COMPUTER - The object of the present invention is to solve problems of treatment time when using an SLS method or continuous-oscillation laser. An indispensable portion is scanned with a laser beam in order to crystallize a semiconductor film by driving a laser and so on in accordance with the positions of islands instead of scanning and irradiating the whole semiconductor film. The present invention makes it possible to omit the time for irradiating a portion to be removed through patterning after crystallizing the semiconductor film with a laser beam and greatly shorten the treatment time for one substrate. | 2010-02-18 |
20100041248 | MULTI-STEP SYSTEM AND METHOD FOR CURING A DIELECTRIC FILM - A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film. | 2010-02-18 |
20100041249 | SOCKET ASSEMBLY WITH PICK UP CAP - A socket assembly ( | 2010-02-18 |
20100041250 | ELECTRICAL CONTACT ARRANGEMENT FOR TELECOMMUNICATIONS AND DATA SYSTEMS TECHNOLOGY - The invention relates to an electrical contact arrangement ( | 2010-02-18 |
20100041251 | CONDUCTIVE CONTACT HOLDER AND CONDUCTIVE CONTACT UNIT - A conductive contact holder includes a holder substrate that is made of a conductive material. The holder substrate has a first opening section for holding conductive signal contacts, and a holding member that is made of an insulating material and that is arranged into the first opening section for holding at least one of the conductive signal contacts. The largest outer diameter of a surface of the holding member parallel to a surface of the conductive contact holder is larger than the smallest interval between longitudinal axes of the conductive contacts held in the conductive contact holder. | 2010-02-18 |
20100041252 | CONNECTOR, CONNECTOR MOUNTING STRUCTURE, AND METHOD OF MANUFACTURING CONNECTOR - A connector includes a wiring board; a lead configured to connect the wiring board electrically to an external board; a conductive layer configured to connect the lead to the wiring board; a guide part configured to guide the lead in directions in which the lead extends, when the conductive layer is melted; and a reinforcement member configured to reinforce a mechanical connection of the wiring board and the external board. | 2010-02-18 |
20100041253 | Contact and Electrical Connector - A contact includes a substantially rectangular base plate. A linking member extends from the base plate such that the linking member is perpendicular thereto. A first elastic contact arm extends obliquely upward from a tip end of the linking member. The first elastic contact arm has a contact member for electrically connecting the first elastic contact arm to an integrated circuit socket. A second elastic contact arm extends obliquely downward from a tip end of the linking member. The second elastic contact arm has a contact member for electrically connecting the second elastic contact arm to a circuit board. | 2010-02-18 |
20100041254 | SOCKET FOR BURN-IN TESTS - A socket adapted for interconnecting an IC package ( | 2010-02-18 |
20100041255 | Substrate Connector - A substrate connector includes a housing, a plurality of terminals which project from the housing and are connected to a substrate, and a guide plate which is secured to the housing for guiding at least some of the terminals. The guide plate includes a main part formed in a meandering shape, and end portions which are joined to opposite sides of the main part and are attached to guide plate attaching portions arranged on opposite sides of the housing. | 2010-02-18 |
20100041256 | Matched-Impedance Connector Footprints - Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system. | 2010-02-18 |
20100041257 | EMI SHIELDED ELECTRICAL CONNECTOR - An electrical connector including a receptacle having receptacle having at least one shielding member and at least one electrically conductive surface. The shielding member includes at least one grounding member and at least one latching member. The grounding member is in physical contact with the electrically conductive surface and the latching member is configured to detachably engage a latching feature of a mating receptacle. A connector system and a method for shielding a connector are also disclosed. | 2010-02-18 |
20100041258 | ROTARY RECEPTACLE ASSSEMBLY - A new rotary receptacle assembly comprises a frame assembly and a drum assembly journaled to the frame assembly so that the drum assembly may rotate relative to the frame assembly. Mounted to the drum assembly is at least one receptacle. A motor assembly may be mounted to one of the frame assembly and the drum assembly for imparting rotary motion to the drum assembly relative to the frame assembly. A clutch assembly disposed on one of the frame assembly or the drum assembly is coupled to the motor assembly. At least one sensor assembly is mounted on the drum assembly and operably coupled to the motor assembly via a rotation control circuit for preventing, among other things, the motor assembly from operating or changing the direction of rotation when an object obstructs the rotation of the drum assembly. | 2010-02-18 |
20100041259 | SAFETY RECEPTACLE WITH TAMPER RESISTANT SHUTTER - The disclosed embodiments are directed to a protective shutter assembly that includes a registration member having longitudinal and lateral axes, first and second shutter members slidably mounted in the registration member, each shutter member including a ramp member and a receptacle blocking member, the ramp member being configured to lie in a path of a first receptacle opening and the receptacle blocking member being configured to lie in a path of a second receptacle opening, spring members connected between the registration member and respective ones of the first and second shutter members, the spring members being configured to bias the first and second shutter members so that the ramp members lie in a path of a respective receptacle opening, and wherein the first and second shutter members are independently movable such that when an object exerts a force on only one ramp member, a respective shutter member moves relative to the other shutter member such that the one ramp member is longitudinally displaced allowing the object to contact the receptacle blocking member of the other shutter member. | 2010-02-18 |
20100041260 | Memory card connector - A memory card connector adapted for accommodating a memory card includes a dielectric housing, a plurality of terminals received in the dielectric housing, a primary ejector and a secondary ejector. The dielectric housing defines a recess for accommodating the memory card. The primary ejector is received in one lateral side of the dielectric housing for ejecting the memory card out of the dielectric housing. The secondary ejector is received in the other lateral side of the dielectric housing for cooperating with the primary ejector to push the memory card out of the dielectric housing. After the memory card is fully inserted in the recess, the primary ejector stores an elastic force therein but is controlled to provide a substantially zero pushing force to the memory card. At the same time, the secondary ejector is still elastically urged against the memory card by an elastic force stored therein. | 2010-02-18 |
20100041261 | Foldable electrical connector-housing system and method of manufacture thereof - A method of manufacture of a foldable electrical connector-housing system includes: providing a first end panel having an outer first end panel side with first end panel contacts that substantially span from one edge of the outer first end panel side to an opposite edge of the outer first end panel side; providing a second end panel having an outer second end panel side, the second end panel and the first end panel with the outer second end panel side facing away from the outer first end panel side and the first end panel contacts exposed in a folded configuration; mounting an electronic component between the outer first end panel side and the outer second end panel side; and connecting a conductor to the first end panel contacts and the electronic component. | 2010-02-18 |
20100041262 | Energy Saving Switch of Continuously Powered Transformers - An additional miniature switch or jumper switch to be integrated within the power connector of any device that is using transformer but that does not need to be connected to it all the time. The energy saving switch will disconnect the primary winding of the transformer from the voltage source when the device does not need to be powered. | 2010-02-18 |
20100041263 | Flexible Connector Assembly for a Load Control Device - A load control device has a modular assembly to allow for easy adjustment of the aesthetic and the color of the load control device after installation. The load control device comprises a user interface module and a base module. The user interface module includes an actuation member for receiving a user input and a visual display for providing feedback to the user. A connector of the base module is adapted to be coupled to a connector of the user interface module, such that the base module and the user interface module are electrically connected. The connector of the base module is adapted to move along a longitudinal axis and a lateral axis of the dimmer, such that the actuation member is easily aligned within an opening of a faceplate. | 2010-02-18 |