| 07th week of 2010 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20100038664 | Semiconductor Chip and Method for Producing a Semiconductor Chip - A semiconductor chip includes a carrier and a semiconductor body, which includes a semiconductor layer sequence having an active region provided for generating radiation. The carrier has a first carrier area facing the semiconductor body and a second carrier area remote from the semiconductor body. The semiconductor body is cohesively fixed to the carrier by means of a connection layer. A plurality of reflective or scattering elements are formed between the second carrier area and the active region. | 2010-02-18 |
| 20100038665 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device ( | 2010-02-18 |
| 20100038666 | Lens Arrangement and LED Display Device - A lens arrangement for an LED display device includes a lens. The lens has a first lens surface and an optical axis. The optical axis penetrates the first lens surface of the lens. Furthermore, the lens arrangement includes a transparent transition body, which is firmly coupled with the lens on the first lens surface, which is more temperature-resistant than the lens and which has an optical axis that is parallel to the optical axis of the lens. | 2010-02-18 |
| 20100038667 | Optoelectronic Semiconductor Chip and Method for Manufacturing a Contact Structure for Such a Chip - An optoelectronic semiconductor chip with a semiconductor body having a semiconductor layer sequence with an active region suitable for generating radiation is specified, wherein the semiconductor chip comprises a radiation-transmissive and electrically conductive contact layer arranged on a semiconductor body and electrically connected to an active region. The contact layer adjoins a barrier layer of the semiconductor layer sequence and a contact layer is applied to the semiconductor body having a structure. An electrode is arranged on the semiconductor body on a side of the active region facing away from the barrier layer and having a contact area, wherein the contact layer adjoins the barrier layer with its entire surface in a region of the barrier layer that is covered by the contact area of the electrode. | 2010-02-18 |
| 20100038668 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention is directed to providing a smaller semiconductor device with a lower manufacturing cost and higher reliability and a method of manufacturing the same. A light emitting element (a LED die | 2010-02-18 |
| 20100038669 | VERTICAL LIGHT EMITTING DIODES - A light emitting device (LED) employs one or more conductive multilayer reflector (CMR) structures. Each CMR is located between the light emitting region and a metal electrical contact region, thereby acting as low-loss, high-reflectivity region that masks the lossy metal contact regions away from the trapped waveguide modes. Improved optical light extraction via an upper surface is thereby achieved and a vertical conduction path is provided for current spreading in the device. In an example vertical, flip-chip type device, a CMR is employed between the metal bottom contact and the p-GaN flip chip layer. A complete light emitting module comprises the LED and encapsulant layers with a phosphor. Also provided is a method of manufacture of the LED and the module. | 2010-02-18 |
| 20100038670 | ILLUMINATION ASSEMBLY INCLUDING CHIP-SCALE PACKAGED LIGHT-EMITTING DEVICE - The embodiments described herein are drawn generally towards illumination assemblies including light emitting devices. In some embodiments, the illumination assemblies including chip-scale packaged light-emitting devices and optical elements. | 2010-02-18 |
| 20100038671 | LIGHT-EMITTING ELEMENT CHIP, EXPOSURE DEVICE AND IMAGE FORMING APPARATUS - The light-emitting element chip includes: a substrate; a light-emitting portion including plural light-emitting elements each having a first semiconductor layer that has a first conductivity type and that is stacked on the substrate, a second semiconductor layer that has a second conductivity type and that is stacked on the first semiconductor layer, the second conductivity type being a conductivity type different from the first conductivity type, a third semiconductor layer that has the first conductivity type and that is stacked on the second semiconductor layer, and a fourth semiconductor layer that has the second conductivity type and that is stacked on the third semiconductor layer; and a controller including a logical operation element that performs logical operation for causing the plural light-emitting elements to perform a light-emitting operation, the logical operation element being formed by combining some sequential layers of the first, second, third and fourth semiconductor layers. | 2010-02-18 |
| 20100038672 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a light emitting device. The light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, the second conductive semiconductor layer comprising a first area and a second area, a third conductive semiconductor layer on the second area of the second conductive semiconductor layer, a first electrode layer electrically connecting the first conductive semiconductor layer with the second conductive semiconductor layer of the second area, and a second electrode layer electrically connecting the second conductive semiconductor layer with the third conductive semiconductor layer. | 2010-02-18 |
| 20100038673 | Radiation-Emitting Chip Comprising at Least One Semiconductor Body - A chip includes at least one semiconductor body having a radiation-emitting region, and at least one first contact region which is provided for making electrical contact with the semiconductor body and is spaced apart laterally from the radiation-emitting region. An electrically conductive first contact layer which is transmissive to the emitted radiation and which connects a surface of the semiconductor body, is situated on the radiation exit side of the chip to the first contact region. The surface is free of the radiation-absorbing contact structures. | 2010-02-18 |
| 20100038674 | Light-Emitting Diode With Current-Spreading Region - A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer. | 2010-02-18 |
| 20100038675 | POWER SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n | 2010-02-18 |
| 20100038676 | Semiconductor Devices with a Field Shaping Region - A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region. | 2010-02-18 |
| 20100038677 | Semiconductor device for electrostatic discharge protection - A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly. | 2010-02-18 |
| 20100038678 | Photodiode with a Reduced Dark Current and Method for the Production Thereof - A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced. | 2010-02-18 |
| 20100038679 | FINFET WITH LONGITUDINAL STRESS IN A CHANNEL - At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin. | 2010-02-18 |
| 20100038680 | III-NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate ( | 2010-02-18 |
| 20100038681 | TRANSISTOR - An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway. | 2010-02-18 |
| 20100038682 | ELECTRONIC DEVICES WITH IMPROVED OHMIC CONTACT - In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s). | 2010-02-18 |
| 20100038683 | INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS - An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length). | 2010-02-18 |
| 20100038684 | Transistor layout for manufacturing process control - A symmetrical circuit is disclosed ( | 2010-02-18 |
| 20100038685 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 2010-02-18 |
| 20100038686 | SOI SUBSTRATES AND DEVICES ON SOI SUBSTRATES HAVING A SILICON NITRIDE DIFFUSION INHIBITION LAYER AND METHODS FOR FABRICATING - Semiconductor-on-insulator substrates and methods for fabricating semiconductor-on-insulator substrates are provided. One exemplary method comprises providing a first silicon-comprising substrate, providing a second silicon-comprising substrate, forming a first silicon nitride layer overlying the second silicon-comprising substrate, and coupling the first silicon-comprising substrate to the second silicon-comprising substrate such that the first silicon nitride layer is interposed between the two substrates. | 2010-02-18 |
| 20100038687 | Selective deposition of amorphous silicon films on metal gates - A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface. | 2010-02-18 |
| 20100038688 | CMOS image sensor, method of making the same, and method of suppressing dark leakage and crosstalk for CMOS image sensor - A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The implants can reside at the isolation structures or in the substrate under the isolation structures. Dark leakage and crosstalk are thus suppressed. | 2010-02-18 |
| 20100038689 | INTEGRATING FABRICATION OF PHOTODETECTOR WITH FABRICATION OF CMOS DEVICE ON A SILICON-ON-INSULATOR SUBSTRATE - A method and semiconductor device for integrating the fabrication of a photodetector with the fabrication of a CMOS device on a SOI substrate. The SOI substrate is divided into two regions, a CMOS region and an optical detecting region. After the CMOS device is fabricated in the CMOS region, the optical detecting region is patterned and etched through the top silicon layer and the buried oxide layer to the base silicon layer. The pattern is etched to a depth so that after a material of a photodetector is deposited in the etched pattern, the material grows to the surface level of the SOI substrate. After the formation of a photodetector structure in the optical detecting region, the metallization process is performed on the CMOS device and the photodetector. In this manner, the fabrication of a photodetector is integrated with the fabrication of a CMOS device on the SOI substrate. | 2010-02-18 |
| 20100038690 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - An image sensor can include a gate insulation layer, a gate electrode, a photodiode, and a floating diffusion region. The gate insulation layer can be formed on and/or over a semiconductor substrate for a transfer transistor. The gate insulation layer includes a first gate insulation layer having a central opening and a second gate insulation layer formed on and/or over an uppermost surface of the first gate insulation layer including the opening. The gate electrode can be formed on and/or over the gate insulation layer. The photodiode can be formed in the semiconductor substrate at one side of the gate electrode so as to generate an optical charge. The floating diffusion region can be formed in the semiconductor at the other side of the gate electrode opposite to the photodiode. The floating diffusion region can be electrically connected to the photodiode through a channel so as to store the optical charge generated from the photodiode. | 2010-02-18 |
| 20100038691 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench. | 2010-02-18 |
| 20100038692 | Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors - An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode. | 2010-02-18 |
| 20100038693 | SEMICONDUCTOR DEVICE - p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed. | 2010-02-18 |
| 20100038694 | SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE - A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at a first lateral side of the fin and in electrical contact with the conductive region. | 2010-02-18 |
| 20100038695 | Computing Apparatus Employing Dynamic Memory Cell Structures - A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing. | 2010-02-18 |
| 20100038696 | Semiconductor Device and Method for Making Same - One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material. | 2010-02-18 |
| 20100038697 | NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT - A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor. | 2010-02-18 |
| 20100038698 | HIGH DENSITY FLASH MEMORY DEVICE , CELL STRING FABRICATING METHOD THEREOF - A flash memory cell string and a method of fabricating the same are provided. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially laminated on the semiconductor substrate. In each cell device, a source/drain region is not formed. The switching device does not include a source or drain region in a side connected to the cell devices. The switching device includes a source or drain region in the other side that is not connected to the cell devices. The source or drain region does or does not overlap the control electrode. Accordingly, it is possible to improve a miniaturization property and performance of NAND flash memory cell devices. If necessary, it is possible to electrically connect cells or cell strings by inducing an inversion layer through a fringing electric field from a control electrode. | 2010-02-18 |
| 20100038699 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A stacked body is formed on a silicon substrate by stacking a plurality of insulating films and a plurality of electrode films alternately and through-holes are formed to extend in the stacking direction. Next, gaps are formed between the electrode films using etching the insulating films via the through-holes. Charge storage layers are formed along side faces of the through-holes and inner faces of the gaps, and silicon pillars are filled into the through-holes. Thereby, a nonvolatile semiconductor memory device is manufactured. | 2010-02-18 |
| 20100038700 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 2010-02-18 |
| 20100038701 | INTEGRATED TWO DEVICE NON-VOLATILE MEMORY - The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed threshold element by a tunnel insulator over the substrate, a charge trapping layer over the tunnel insulator, a charge blocking layer over the trapping layer, and a control gate, having a nitride layer, over the charge blocking layer. In one embodiment, the gate insulator, tunnel insulator and charge trapping layers are all SiON with thicknesses that depend on the designed programming voltage. The control gate can be formed overlapping the access gate or the access gate can be formed overlapping the control gate. | 2010-02-18 |
| 20100038702 | Nonvolatile memory device and methods of forming the same - Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase. | 2010-02-18 |
| 20100038703 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction. | 2010-02-18 |
| 20100038704 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE SUPPRESSING FLUCTUATION IN THRESHOLD VOLTAGE - First and second memory cell transistors are isolated by an element isolation insulating film. A barrier insulating film covers the element isolation insulating film. The first memory cell transistor includes a first tunnel insulating film, a first charge storage layer made of an insulating film, a first block insulating film, and a first gate electrode. The second memory cell transistor includes a second tunnel insulating film, a second charge storage layer made of an insulating film, a second block insulating film, and a second gate electrode. The barrier insulating film is in contact with the first and second charge storage layers, and has a film thickness smaller than that of the first and second charge storage layers. | 2010-02-18 |
| 20100038705 | FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION - A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method. | 2010-02-18 |
| 20100038706 | SEMICONDUCTOR DEVICE - Provided is an ESD protection element, in which: LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to easily satisfy a function required for the ESD protection element, the function of being constantly in an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again. | 2010-02-18 |
| 20100038707 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor substrate; a first main electrode provided on a first main surface of said semiconductor substrate; a second main electrode provided on a second main surface of said semiconductor substrate, wherein a main current flows in a thickness direction of said semiconductor substrate; a trench that extends from the first main surface of said semiconductor substrate towards the second main surface; a gate insulating film covering an inner surface of said trench; and a gate electrode buried in said trench and surrounded by said gate insulating film. | 2010-02-18 |
| 20100038708 | Method and Structure for Forming a Shielded Gate Field Effect Transistor - A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type. | 2010-02-18 |
| 20100038709 | VERTICAL TRANSISTOR AND ARRAY WITH VERTICAL TRANSISTORS - A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates. | 2010-02-18 |
| 20100038710 | Vertical power MOSFET semiconductor apparatus having separate base regions and manufacturing method thereof - A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region, a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region, a first high concentration base region, a second high concentration base region provided below and separated from the first concentration base region, and a third high concentration base region of the second conductive type included inside the low concentration base region, provided below and separated from the second high concentration base region. | 2010-02-18 |
| 20100038711 | TRENCHED MOSFET WITH GUARD RING AND CHANNEL STOP - A trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a guard ring and a channel stop, including: a substrate including an epi layer region on the top thereof; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate structure filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a guard ring wrapping around the metal layer corresponding to the gate region at the termination; and a channel stop which is a heavier N-type doping region aside the guard ring at the termination; Wherein the contact plugs connecting to the top metal layer are corresponding to the source and the body regions. | 2010-02-18 |
| 20100038712 | POWER SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=N | 2010-02-18 |
| 20100038713 | Self-aligned tunneling pocket in field-effect transistors and processes to form same - A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body. | 2010-02-18 |
| 20100038714 | DEVICE AND PROCESS INVOLVING PINHOLE UNDERCUT AREA - An electronic device fabrication method including: (a) providing a dielectric region and a lower electrically conductive region, wherein the dielectric region includes a plurality of pinholes each with an entry and an exit; and (b) depositing an etchant for the lower electrically conductive region into the pinholes that undercuts the pinholes to create for a number of the pinholes an overhanging surface of the dielectric region around the exit facing an undercut area of the lower electrically conductive region wider than the exit. | 2010-02-18 |
| 20100038715 | THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS - A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxide layer. A hard mask on top of the gate stack is formed. An off-set spacer is formed surrounding the gate stack. A raised source/drain region is epitaxially formed adjacent to the off-set spacer. The raised source/drain region is grown slightly about a height of the gate stack including the hard mask. The raised source/drain region forms borderless self-aligned contact. | 2010-02-18 |
| 20100038716 | CRYSTALLINE SEMICONDUCTOR THIN FILM, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME - There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained. | 2010-02-18 |
| 20100038717 | Semiconductor on Insulator Apparatus - A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers. | 2010-02-18 |
| 20100038718 | ELECTRO-STATIC DISCHARGE AND LATCHUP RESISTANT SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region, which includes a voltage input terminal. The isolation layer is located between the backgate region and the substrate layer and has a doping type opposite that of the backgate region. The diode includes a first terminal connected to the isolation layer and a second terminal coupled to an isolation voltage source. | 2010-02-18 |
| 20100038719 | Semiconductor apparatuses and methods of manufacturing the same - Disclosed are semiconductor apparatuses and methods of fabricating the same. According to the methods, the number of operations for fabricating the semiconductor apparatuses having a plurality of layers may be the same as the number of operations for fabricating a semiconductor apparatus having one layer. The semiconductor apparatuses may include first active regions extending in the same direction, in parallel, separated from each other and including first and second impurity doped regions on opposite ends of the first active regions from each other. The semiconductor apparatuses may further include second active regions on a layer above the first active regions, extending in the same direction as the first active regions, separated from each other, in parallel, and including first and second impurity doped regions on opposite ends of the second active regions from each other. | 2010-02-18 |
| 20100038720 | STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE - A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The multi-work function metal gate structure comprises a first type of metal with a first work function in a central region and a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function. | 2010-02-18 |
| 20100038721 | METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function. | 2010-02-18 |
| 20100038722 | MIS TRANSISTOR AND CMOS TRANSISTOR - A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate ( | 2010-02-18 |
| 20100038723 | SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION - A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact. | 2010-02-18 |
| 20100038724 | Metal-Gate High-K Reference Structure - Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V. Also disclosed are method embodiments for forming the integrated circuit structure. | 2010-02-18 |
| 20100038725 | CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION - Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region. | 2010-02-18 |
| 20100038726 | RADIATION HARDENED DEVICE - A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance. | 2010-02-18 |
| 20100038727 | Carbon-Doped Epitaxial SiGe - A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor gate stack, and source/drain extensions. The PMOS transistor also includes carbon-doped epitaxial SiGe source/drain regions. | 2010-02-18 |
| 20100038728 | FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs. | 2010-02-18 |
| 20100038729 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO | 2010-02-18 |
| 20100038730 | SEMICONDUCTOR STRUCTURES INCLUDING A MOVABLE SWITCHING ELEMENT, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive contact via an electrical field, establishing electrical contact between the conductive pad and the conductive contact. Various methods may be used to form such semiconductor structures, and switching devices including such semiconductor structures. Memory devices and electronic systems include such switching devices. | 2010-02-18 |
| 20100038731 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever ( | 2010-02-18 |
| 20100038732 | MICRO MOVABLE DEVICE - A micro movable device includes a protection cap for protecting a movable unit arranged above a semiconductor substrate and the movable unit, signal line for transmitting a high-frequency signal formed above the semiconductor substrate, and insulation layer that has projection formed to project upward from the semiconductor substrate and coated surfaces with the signal line. | 2010-02-18 |
| 20100038733 | MICROELECTROMICHANICAL SYSTEM PACKAGE WITH STRAIN RELIEF BRIDGE - A strain absorption bridge for use in a MEMS package includes a first substrate that is configured to be attachable to a circuit board. A first elastically deformable element is coupled to the first substrate and the first elastically deformable element is configured to be attachable to a MEMS device. Alternatively, the MEMS device may be attached to the first substrate. The elastically deformable element at least partially absorbs and dissipates mechanical strain communicated from the circuit board before the mechanical strain can reach the MEMS device. | 2010-02-18 |
| 20100038734 | VIBRATION SENSOR AND METHOD FOR MANUFACTURING THE VIBRATION SENSOR - A method for manufacturing a vibration sensor including forming a sacrifice layer at one part of a front surface of a semiconductor substrate of monocrystalline silicon with a material isotropically etched by an etchant for etching the semiconductor substrate, forming a thin film protective film with a material having resistance to the etchant on the sacrifice layer and the front surface of the semiconductor substrate at a periphery of the sacrifice layer, forming a thin film of monocrystalline silicon, polycrystalline silicon, or amorphous silicon on an upper side of the sacrifice layer, opening a backside etching window in a back surface protective film having resistance to the etchant for etching the semiconductor substrate formed on a back surface of the semiconductor substrate, forming a through-hole in the semiconductor substrate by etching the semiconductor substrate anisotropically by using crystal-oriented etching by applying the etchant from the back surface window, then etching the sacrifice layer isotropically by the etchant after the etchant reaches the front surface of the semiconductor substrate, and then etching the semiconductor substrate anisotropically by using crystal-oriented etching from a front side by the etchant spread to a space formed after the sacrifice layer is removed, and forming a holder for supporting the thin film on an upper surface of the semiconductor substrate by removing the thin film protective film partially. | 2010-02-18 |
| 20100038735 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 2010-02-18 |
| 20100038736 | SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE - A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized. | 2010-02-18 |
| 20100038737 | PLASTIC IMAGE SENSOR PACKAGING FOR IMAGE SENSORS - A package for an image sensor includes a lead frame having a first surface and a second surface opposite the first surface; an image sensor mounted on the first surface of the lead frame; an optical cover spanning the first surface; and a plastic, optically transparent window in the optical cover and aligned with the image sensor. | 2010-02-18 |
| 20100038738 | Capacitive Bypass - An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance. | 2010-02-18 |
| 20100038739 | SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A semiconductor device that includes a circuit portion, a first light-shielding film and plural second light-shielding films. In the circuit portion, a plurality of wiring layers that include circuit elements are laminated. The first light-shielding film covers an uppermost layer of the wiring layers and light-shields light that is illuminated at the circuit portion. The second light-shielding films are covered by the first light shielding film and formed so as to respectively encircle the wiring layers in ring forms. Outer peripheries of the plural second light-shielding films are formed to be successively smaller from an upper to a lower layer, so as to be at the inner side relative to the outer periphery of the second light-shielding film of the upper layer. | 2010-02-18 |
| 20100038740 | COLOR IMAGE SENSOR WITH IMPROVED OPTICAL CROSSTALK - The invention relates to image sensors produced on a thinned silicon substrate. To limit the optical crosstalk between adjacent filters and, notably filters of different colors, the invention proposes positioning, between the adjacent filters of different colors (FR, FB, FV), a wall ( | 2010-02-18 |
| 20100038741 | SEMICONDUCTOR APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS, AND CAMERA MODULE - A semiconductor apparatus includes, a semiconductor substrate having first and second main surfaces and a thought hole connecting the first and second main surfaces; a first insulation layer arranged on the first main surface, and having an opening corresponding to the thought hole; a first conductive layer arranged on the first insulation layer, and covering the thought hole; a second insulation layer arranged on an inner wall of the thought hole and the second surface; a second conductive layer arranged in the thought hole and on the second insulation layer, the second conductive layer contacting the first conductive layer; and a filling member arranged on the second conductive layer in the through hole, and having a gap between the second conductive layer on the first main surface side. | 2010-02-18 |
| 20100038742 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer | 2010-02-18 |
| 20100038743 | INFORMATION STORAGE SYSTEM WHICH INCLUDES A BONDED SEMICONDUCTOR STRUCTURE - An information storage system includes a bonded semiconductor structure having a memory circuit region carried by an interconnect region. The memory circuit region includes a memory control device region having a vertically oriented memory control device. The memory circuit region includes a memory device region in communication with the memory control device region. The memory device region includes a memory device whose operation is controlled by the vertically oriented memory control device. | 2010-02-18 |
| 20100038744 | Shallow Trench Isolation - Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench. | 2010-02-18 |
| 20100038745 | INTEGRATED CIRCUIT STRUCTURE HAVING BOTTLE-SHAPED ISOLATION - An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region. | 2010-02-18 |
| 20100038746 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING ISOLATION STRUCTURE THEREIN - A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well as a first undercut and a second undercut on opposite sides of the shallow trench isolation. Later, the first deep trench and the second deep trench are partially filled with Si. Afterwards, the first deep trench and the second deep trench are filled with an isolation material to form the isolation structure. | 2010-02-18 |
| 20100038747 | ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD - An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet. | 2010-02-18 |
| 20100038748 | ELECTRIC FUSE CIRCUIT AND ELECTRONIC COMPONENT - An electric fuse circuit is provided which has a capacitor that forms an electric fuse; a write circuit for breaking an insulating film of the capacitor, by applying a voltage to a terminal of the capacitor in response to a write signal; and at least two transistors, including a first transistor and a second transistor, which are connected in series between the capacitor and the write circuit. | 2010-02-18 |
| 20100038749 | Contact and VIA Interconnects Using Metal Around Dielectric Pillars - An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect. | 2010-02-18 |
| 20100038750 | Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors - A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench. | 2010-02-18 |
| 20100038751 | STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE - A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node. | 2010-02-18 |
| 20100038752 | MODULAR & SCALABLE INTRA-METAL CAPACITORS - An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell. | 2010-02-18 |
| 20100038753 | Variable capacitor employing MEMS technology - When a positive voltage of V | 2010-02-18 |
| 20100038754 | Back-End-of-Line Resistive Semiconductor Structures - In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines. | 2010-02-18 |
| 20100038755 | SILICON WAFER WITH CONTROLLED DISTRIBUTION OF EMBRYOS THAT BECOME OXYGEN PRECIPITATES BY SUCCEEDING ANNEALING AND ITS MANUFACTURING METHOD - A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility. | 2010-02-18 |
| 20100038756 | (110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES COMPRISING SAID (110) ORIENTED SILICON SUBSTRATE - The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.15 nm RMS in a 2×2 μm | 2010-02-18 |
| 20100038757 | SILICON WAFER, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR HEAT-TREATING THE SAME - A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T | 2010-02-18 |
| 20100038758 | SEMICONDUCTOR MODULE WITH TWO COOLING SURFACES AND METHOD - A semiconductor module with two cooling surfaces and method. One embodiment includes a first carrier with a first cooling surface and a second carrier with a second cooling surface. The first cooling surface is arranged in a first plane, the second cooling surface is arranged in a second plane, at an angle different from 0° relative to the first plane. | 2010-02-18 |
| 20100038759 | Leadless Package with Internally Extended Package Leads - A DFN package includes internally extended package leads. One or more package pads are physically and electrically extended from a first edge of the package to a second, opposite edge of the package. These extended package leads can terminate at the edges of the leadframe. The package pads and the extended package leads where the IC die is attached can have full leadframe thickness. Other extended package lead features can have a reduced leadframe thickness (e.g., about half the leadframe thickness). Leadframe features can be physically and electrically connected to a tie-bar feature which can be an integral part of a leadframe matrix. The tie-bar can stabilize the leadframe features during assembly. The tie-bar can also provide electrical connectivity for post assembly leadframe plating. The tie-bar can be removed during package singulation by sawing or punching techniques to free the leadframe features both physically and electrically. | 2010-02-18 |
| 20100038760 | Metal Leadframe Package with Secure Feature - A fabrication method for a BGA or LGA package includes a low-cost metal leadframe with internally extended leads. I/O attach lands can be placed at any location on the metal leadframe, including the center of the package. An I/O attach land can be fabricated at any position upon an extended lead (e.g., near the center of the package). During fabrication of the package, an isolation saw cut to the bottom of the package can be used to electrically disconnect the leadframe circuit from the peripheral extension traces to prevent tampering with the IC die by probing the edge metal traces. | 2010-02-18 |
| 20100038761 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes: mounting a first integrated circuit over a carrier; mounting an interposer, having an opening, over the first integrated circuit and the carrier with the interposer having an overhang over the carrier; connecting an internal interconnect, through the opening, between the carrier and the interposer; and forming an encapsulation over the first integrated circuit, the internal interconnect, and the carrier. | 2010-02-18 |
| 20100038762 | CIRCUIT BOARD MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS, CIRCUIT BOARD AND SEMICONDUCTOR DEVICE - There is provided a circuit board manufacturing method that makes it possible to manufacture a next-generation semiconductor device in a stable manner and improve the yield during secondary mounting processing. A circuit board | 2010-02-18 |
| 20100038763 | Semiconductor structure with communication element - In one embodiment, a structure includes a semiconductor chip including a communication element for performing a wireless communication function where the communication element has a communication core occupying a region of the semiconductor chip, a plurality of chip pads with two of the chip pads electrically connected to the communication core; a chip carrier for carrying the semiconductor chip where the chip carrier includes a plurality of carrier pads with two of the carrier pads connected to the two chip pads; and an antenna connected to the carrier pads and electrically connected to the chip pads and to the communication core. | 2010-02-18 |
