07th week of 2022 patent applcation highlights part 51 |
Patent application number | Title | Published |
20220051852 | COMPONENT BUILT-IN SUBSTRATE - A component built-in substrate includes a multilayer body and a substrate including a multilayer ceramic electronic component embedded therein. The multilayer ceramic electronic component includes a first connection portion that protrudes from the first external electrode, and a second connection portion that protrudes from the second external electrode. The substrate includes a core material. The multilayer ceramic electronic component including the first connection portion and the second connection portion includes a surface covered by the core material and embedded in the substrate. The first connection portion protrudes toward a surface of the substrate, and is not exposed at the surface of the substrate. The second connection portion protrudes toward the surface of the substrate, and is not exposed at the surface of the substrate. | 2022-02-17 |
20220051853 | MULTILAYER ELECTRONIC COMPONENT - A multilayer electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode including an electrode layer disposed on the body and connected to the internal electrode and a conductive resin layer disposed on the electrode layer, and the conductive resin layer includes a metal wire, a conductive metal, and a base resin. | 2022-02-17 |
20220051854 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and first and second internal electrodes with the dielectric layer interposed therebetween, the dielectric layer and the first and second internal electrodes arranged to be stacked, and a first cover portion disposed on the capacitance portion, and a second cover portion disposed on the capacitance portion, a first external electrode connected to the first internal electrode, and a second external electrode connected to the second internal electrode. The first cover portion and the second cover portion include a cover reinforcing layer including graphene. | 2022-02-17 |
20220051855 | CAPACITOR COMPONENT FOR AN ELECTRIC MOTOR OR GENERATOR - A capacitor component comprising a first busbar, a second busbar, one or more capacitor elements and a housing, the housing having a first portion and a second portion, wherein the first portion and the second portion are arranged to extend around an aperture, the first portion includes a section for housing the one or more capacitor elements, with the second portion extending between a first end and a second end of the first portion, wherein the first busbar and the second busbar are arranged to extend around the first portion and the second portion of the housing, a first power supply terminal is formed at the first end of the first portion and a second power supply terminal is formed at the second end of the first portion, wherein the first power supply terminal is coupled to the first busbar and the second power supply terminal is coupled to the second busbar, wherein a first conductive layer of the one or more capacitor elements is coupled to the first busbar and a second conductive layer of the one or more capacitor elements is coupled to the second busbar. | 2022-02-17 |
20220051856 | SYSTEMS AND METHODS FOR ENHANCING ELECTRICAL ENERGY STORAGE - An electrical energy storage device comprises a housing having a first end, a second end, a first side, and a second side; a first electrode disposed in the housing adjacent the first side; a second electrode disposed in the housing adjacent the second side; and an electrolyte mixture disposed between the first electrode and the second electrode, the electrolyte mixture containing a plurality of ions. In an implementation, a channel disposed in the housing permits ions to flow adjacent to the first end and a barrier in the housing prevents ions from flowing adjacent to the second end. In another implementation, some of the ions are magnetic. In a further implementation, some of the ions have a greater density than other ions. Charging of the electrical energy storage device is enhanced by applying a magnetic field to the electrical energy storage device or rotating the device. | 2022-02-17 |
20220051857 | SWITCHING TERMINAL - Disclosed are example embodiments of a switching terminal that can be rotated with minimal parts. The switching terminal can include: an inner portion configured to be securely or loosely attached to an external conductor element; and an outer portion configured to be rotatably affixed to the inner portion when then inner portion is loosely attached to the external conductor and to be tightly affixed to the inner portion when then inner portion is tightly attached to the external conductor. | 2022-02-17 |
20220051858 | LIGHT-GUIDE PLANAR STRUCTURE OF BACKLIGHT MODULE - The invention discloses a light-guide planar structure of a backlight module, comprising a backlight module including a luminescent lamp source, a reflecting plate, a light guide plate and a light shading plate with a plurality of preset key caps thereon, which are sequentially arranged, and a light guide structure which is arranged on the surface of the light guide plate, is planar and is a surface consisting of three or more circular or rectangular mesh points. The light-guide planar structure is simple in structure, has the effect of gathering and centralizing the light source, is stable in light guide effect, reduces light source waste and reduces module cost. | 2022-02-17 |
20220051859 | ROLLER INPUT DEVICE - A roller input device includes a casing and a roller. A roller seat and an encoder are disposed in the casing. The roller is pivotally disposed on the roller seat. The body of the roller includes a shaft portion, a first side, and a second side. The first side and the second side are at opposite sides of the body. The first shaft and the second shaft of the roller are connected to the shaft portion and respectively extend from the first side and the second side. An end portion of the first shaft and an end portion of the second shaft away from the shaft portion respectively have a first connection portion and a second connection portion. A structural strength of the first connection portion is greater than a structural strength of the second connection portion, and the first connection portion is connected to the encoder. | 2022-02-17 |
20220051860 | Earbud With Rotary Switch - An earbud device having a user interface that incorporates a rotary switch is described. The rotary switch is part of a stem that extends from the main body of the earbud, and can provide file selection and/or volume control functions. The interface can include a pressure switch, which can provide switching between on, off, and sleep modes. The pressure switch can also be positioned on the stem, and in some embodiments the rotary switch can also act as the pressure switch when pressed. In some embodiments the user interface can utilize a combination of rotary switch and pressure switch inputs. | 2022-02-17 |
20220051861 | Rotational Push Switch - A rotational push switch includes a bottom shell having a first and a second conductive terminals connected to a power supply, and a third conductive terminal connected to the conductive elastic piece. The conductive elastic piece is mounted in the bottom shell. A switch assembly is mounted on a top shell mounted on the bottom shell. The switch assembly is switched to connect or detach the conductive elastic piece and the second conductive terminal. A cap is mounted on the switch assembly. When the conductive elastic piece is connected to or departed from the second conductive terminal, ON/OFF symbols can be correspondingly seen in a display window of the cap, and a user can recognize an ON/OFF state of the rotational push switch. | 2022-02-17 |
20220051862 | RELAY - The disclosure relates to an electromagnetic relay that comprises a yoke and an armature. The armature may be swivellably arranged on the yoke, have an open position and a contact position in relation to the yoke, and configured to be attracted by a magnetic field out of the open position into the contact position. The armature may include a first branch circuit having a first capacitor and a first exciter coil connected in series with the first capacitor, a second branch circuit having a second capacitor and a second exciter coil connected in series with the second capacitor, and a switch element arranged between the first branch circuit and the second branch circuit and having a first switch state and a second switch state. The first exciter coil and the second exciter coil may provide the magnetic field for attracting and retaining the armature. | 2022-02-17 |
20220051863 | ELECTROMAGNETIC RELAY - An electromagnetic relay includes a pair of fixed terminals, a movable contact piece, and a magnet portion. The pair of fixed terminals includes fixed contact. The movable contact piece that includes a movable contact disposed facing the fixed contact and that is movable in a first direction in which the movable contact contacts the fixed contact and in a second direction in which the movable contact separates from fixed contact. The magnet portion generating a magnetic field for extending an arc generated between the fixed contact and the movable contact. At least one of a corner portion in the first direction side of the fixed terminal located in an arc extension direction in which the arc is extended or a corner portion in the second direction side of the movable contact piece located in the arc extension direction has a chamfered shape in a range where the arc passes through. | 2022-02-17 |
20220051864 | Breaker Plug, Network Systems and Methods - A device with “plug-in” receptacle that mounts in a breaker panel. The plug receptacle receives a power cord inserted by the operator. The device includes a multifunction circuit interrupt that offers overload, thermal, and ground fault (GFCI) protection for the operator in hazardous environments such as garages, shops and spider boxes at construction sites. The devices may include a networkable node or port and onboard comm circuitry that is compatible with a wired or wireless TOT network. In another embodiment, a dummy breaker body includes a plug receptacle with a GFCI interrupt circuit but no direct electrical connection to the hot bus bar, and is wired in series with a conventional circuit breaker module in a breaker panel. Using solid state electronics, the GFCI panel-mounted devices may be configured to perform an automatic fault test prior to each use. Network systems using smart breaker devices are described. | 2022-02-17 |
20220051865 | HIGH-VOLTAGE FUSING APPARATUS - A high-voltage fusing apparatus includes a current fuse, a temperature fuse, and a current-carrying fuse. The current fuse is connected in series with the temperature fuse, and a series branch of the current fuse and the temperature fuse is connected in parallel with the current-carrying fuse. A resistance value of the current-carrying fuse is less than a resistance value of the current fuse, and a fusing temperature of the current-carrying fuse is lower than a fusing temperature of the temperature fuse. The high-voltage fusing apparatus can cut off a high-voltage circuit quickly, and effectively protect the high-voltage heating circuit from overheating. | 2022-02-17 |
20220051866 | ELECTRON GUN DEVICE - An electron gun device that emits an electron beam by heating to a high temperature in a vacuum. The surface of a material, which emits an electron beam, is a hydrogenated metal that is melted and in a liquid state during a high-temperature operation. The liquid hydrogenated metal is contained in a hollow cover tube container, which is in a solid state during the high-temperature operation, in the form of a hydrogenated liquid metal or in the form of a liquid metal before hydrogenation, and heated together with the cover tube container to a high temperature. The hydrogenated liquid metal is exposed from the cover tube container and forms a liquid surface where gravity, the electric field and the surface tension of the liquid surface are balanced; and an electron beam is emitted from the exposed surface of the hydrogenated liquid metal. | 2022-02-17 |
20220051867 | REDUCING A TEMPERATURE DIFFERENCE BETWEEN A SAMPLE AND A CHUCK OF AN ELECTRON BEAM TOOL - A method, a non-transitory computer readable medium and a system for reducing a temperature difference between a sample and a chuck of an electron beam tool. The method may include determining a target temperature of samples located at the load port of the electron beam tool; setting a temperature of the samples, located at the load port, to the target temperature; moving the sample from the load port to the chuck, the chuck is located within a vacuum chamber, the sample belongs to the samples; and positioning the sample on the chuck, wherein when positioned on the chuck, a temperature of the sample substantially equals a temperature of the chuck. | 2022-02-17 |
20220051868 | Electron Beam Observation Device, Electron Beam Observation System, and Image Correcting Method and Method for Calculating Correction Factor for Image Correction in Electron Beam Observation Device - The objective of the present invention is to reduce differences between individual electron beam observation devices accurately by means of image correction. This method for calculating a correction factor for correcting images between a plurality of electron beam observation devices; in electron beam observation devices which generate images by scanning an electron beam across a specimen, is characterized by including: a step in which a first electron beam observation device generates a first image by scanning a first electron beam across first and second patterns, on either a specimen including the first pattern and the second pattern, having a different shape or size to the first pattern, or a first specimen including the first pattern and a second specimen including the second pattern; a step in which a second electron beam observation device generates a second image by scanning a second electron beam across the first and second patterns; and a step in which the first or second electron beam observation device calculates a correction factor at a peak frequency extracted selectively from first and second frequency characteristics calculated on the basis of the first and second images. | 2022-02-17 |
20220051869 | Charged Particle Beam Drawing Device and Method of Controlling Charged Particle Beam Drawing Device - A charged particle beam drawing device includes: a storage unit that stores a pattern generation program for generating pattern data, the pattern generation program being a program in which an instruction for specifying a type of a figure and an instruction for specifying a regular arrangement of the figure are described; an execution unit that executes the pattern generation program stored in the storage unit; and a control unit that performs drawing control based on the pattern data generated by the executed pattern generation program. | 2022-02-17 |
20220051870 | Ion Milling Apparatus and Sample Holder - An ion milling apparatus has: a sample holder including a shield member for shielding the sample except for a portion to be milled; and a sample locking member cooperating with the shield member such that the sample is sandwiched and held therebetween. The shield member has an edge portion that determines a milling position on or in the sample. The sample locking member is disposed downstream of the edge portion in the direction of irradiation by the ion beam and has a support portion cooperating with the edge portion to support the milled portion therebetween. The support portion has a first surface making contact with the sample and a second surface making a given angle to the first surface. The given angle is equal to or less than 90°. | 2022-02-17 |
20220051871 | PATTERN FORMATION METHOD AND TEMPLATE MANUFACTURING METHOD - According to one embodiment, a pattern formation method includes placing an imprint resist film on a substrate, then imprinting a pattern in the imprint resist film. The pattern has a first loop section in a first end portion and a second loop section in a second end portion. After the imprint resist film has been patterned, it is selectively irradiated between the first loop section and the second loop section. The imprint resist film is then etched under conditions leaving the selectively irradiated portion of the imprint resist film and removing the unirradiated portion of the imprint resist film. | 2022-02-17 |
20220051872 | ATOMIC LAYER ETCHING PROCESSES - Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant. | 2022-02-17 |
20220051873 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a chamber; a support member in the chamber; a window plate at an upper portion of the chamber and including a window plate body and a fastening hole, wherein the fastening hole includes a lower fastening hole portion and an upper fastening hole portion. and a gas injector including a first body having a plurality of distribution nozzles and a second body having an accommodating groove to which the first body is fastened and a plurality of injection nozzles. The second body includes a first portion disposed inside the upper fastening hole portion, a second portion disposed inside the lower fastening hole portion, and a third portion disposed below the window plate. The second portion of the second body includes a gas hole extending from the accommodating groove to an external side surface of the second portion of the second body. | 2022-02-17 |
20220051874 | PLASMA PROCESSING APPARATUS AND POWER SUPPLY METHOD - A plasma processing apparatus includes a process chamber; a mounting stage; first and second electrodes; first and second high frequency power sources;, wherein the first power source supplies a waveform of one of a first pulse wave having high and low levels of first high frequency power or a continuous wave in the first period, supplies a waveform of the other in the second period, and stepwise or continuously changes the low level of the first pulse wave in the transition period, wherein the second power source supplies a waveform of one of a second pulse wave having high and low levels of second high frequency power or a continuous wave in the first period, supplies a waveform of the other in the second period, and stepwise or continuously changes the low level of the second pulse wave in the transition period. | 2022-02-17 |
20220051875 | Ion Stratification Using Bias Pulses of Short Duration - A plasma processing apparatus includes a plasma processing chamber configured to contain a plasma comprising a plasma sheath, ions of a first species, and ions of a second species, a substrate disposed in the plasma processing chamber, and a short pulse generator coupled to the substrate, the short pulse generator configured to generate a pulse train of negative bias pulses. Each of the negative bias pulses has a pulse duration less than 10 μs. A pulse delay between successive negative bias pulses is at least five times the pulse duration. The first species has a first mass and the second species has a second mass less than the first mass. The pulse train spatially stratifies the ions of the first species and the ions of the second species in the plasma sheath. | 2022-02-17 |
20220051876 | VACUUM PROCESSING APPARATUS AND METHOD FOR CONTROLLING VACUUM PROCESSING APPARATUS - The present disclosure relates to a vacuum processing apparatus. The vacuum processing apparatus includes a processing container capable of maintaining an inside thereof in a vacuum atmosphere, a stage provided in the processing container and on which a substrate is placed, a support member passing through an opening formed at a bottom of the processing container to support the stage from below, a holder part located outside the processing container, a flange part arranged around the opening on the outside of the processing container, and a sealing part configured to be expandable and contractible and provided inside the spherical bearing along the circumferential direction of the opening so as to airtightly seal at least a space between the flange part and the holder part. | 2022-02-17 |
20220051877 | UPPER ELECTRODE AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME - An upper electrode used for a substrate processing apparatus using plasma is provided. The upper electrode includes a bottom surface including a center region and an edge region having a ring shape and surrounding the center region, a first protrusion portion protruding toward plasma from the edge region and having a ring shape, wherein the first protrusion portion includes a first apex corresponding to a radial local maximum point toward the plasma, and a first distance, which is a radial-direction distance between the first apex and a center axis of the upper electrode, is greater than a radius of a substrate. | 2022-02-17 |
20220051878 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a balun having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, a vacuum container, a first electrode electrically connected to the first output terminal, a second electrode electrically connected to the second output terminal, and a connection unit configured to electrically connect the vacuum container and ground, the connection unit including an inductor. | 2022-02-17 |
20220051879 | ELECTRODE ARRANGEMENT FOR A PLASMA SOURCE FOR PERFORMING PLASMA TREATMENTS - In order to improve the etch depth and/or the etch homogeneity of a substrate, a plasma source with one or more evaporators and two or more electrodes according to the invention is proposed. The use of more than one electrode allows the use of different currents at the electrodes and a time-selective application of the currents, so that an improved control of the plasma generation is enabled. | 2022-02-17 |
20220051880 | APPARATUS AND TECHNIQUES FOR ANGLED ETCHING USING MULTIELECTRODE EXTRACTION SOURCE - A plasma source may include a plasma chamber, where the plasma chamber has a first side, defining a first plane and an extraction assembly, disposed adjacent to the side of the plasma chamber, where the extraction assembly includes at least two electrodes. A first electrode may be disposed immediately adjacent the side of the plasma chamber, wherein a second electrode defines a vertical displacement from the first electrode along a first direction, perpendicular to the first plane, wherein the first electrode comprises a first aperture, and the second electrode comprises a second aperture. The first aperture may define a lateral displacement from the second aperture along a second direction, parallel to the first plane, wherein the vertical displacement and the lateral displacement define a non-zero angle of inclination with respect to a perpendicular to the first plane. | 2022-02-17 |
20220051881 | Plasma Etching Apparatus and Method - A plasma etching apparatus for etching a semiconductor substrate comprises: a plasma chamber; a plasma generation device for sustaining a plasma within the plasma chamber; a substrate support disposed within the plasma chamber for supporting the semiconductor substrate, the substrate support comprising an electrically conductive structure; a power supply for providing an RF electrical signal having an RF power to the electrically conductive structure; and an annular dielectric ring structure comprising a backside surface, the backside surface comprising an electrically conductive coating; wherein the electrically conductive structure is spaced apart from and extends under the electrically conductive coating so that when RF power is provided to the electrically conductive structure the RF power couples to the electrically conductive coating. Associated methods are also disclosed. | 2022-02-17 |
20220051882 | A MAGNET ARRANGEMENT FOR A PLASMA SOURCE FOR PERFORMING PLASMA TREATMENTS - In order to improve the etching depth and/or the etching homogeneity at a substrate, a plasma source with one or more single electrodes or one or more magnets is proposed. The magnet generates a magnetic field in the vicinity of the electrodes, which may be rear-side or front-side. | 2022-02-17 |
20220051883 | SPUTTERING EQUIPMENT AND OPERATION METHOD THEREOF - A sputtering equipment is adapted for sputtering substrates, where each of the substrates includes two opposite main surfaces and side surfaces connecting the two main surfaces. The sputtering equipment includes a cavity, at least one target set and a carrier box. The at least one target set is disposed in the cavity, the target set includes targets, and the targets are staggered at both side surfaces of an axis. The carrier box is movably disposed so as to enter and exit the cavity, and includes substrate accommodating grooves. The substrates are adapted for being placed in the substrate accommodating grooves of the carrier box, and at least one side surface of each of the substrates is located outside the carrier box and protrudes toward the at least one target set. | 2022-02-17 |
20220051884 | IMAGING MASS SPECTROMETER - An imaging mass spectrometer includes: a storage configured to acquire and store data constituting a first imaging graphic indicating an ion intensity distribution in a specific one or plurality of m/z or m/z ranges based on data obtained by mass spectrometry for a sample; a Raman imaging data acquisition unit configured to acquire and store data constituting one or plurality of second imaging graphics obtained by Raman analysis that is a type different from mass spectrometry for the sample; a signal intensity normalization processor configured to perform data conversion processing of normalizing signal intensity in one or plurality of first and second imaging graphics; an adjustment processor configured to perform data processing of aligning spatial resolutions of the one or plurality of first and second imaging graphics; and a statistical analysis processor configured to execute statistical analysis processing on images and to classify the first and second imaging graphics. | 2022-02-17 |
20220051885 | METHOD FOR EVALUATING MASS SPECTROMETRY DEVICE, METHOD FOR CALIBRATING MASS SPECTROMETRY DEVICE, ANALYSIS METHOD, MASS SPECTROMETRY DEVICE, AND MASS SPECTROMETRY REAGENT - A method for evaluating a mass spectrometry device includes: by a mass spectrometry device, performing mass spectrometry of an ester of phthalic acid and detecting a plurality of types of ions produced by dissociation of the ester of phthalic acid; and obtaining information concerning whether the mass spectrometry device is in a state suitable for analysis, based on a ratio of intensities of the plurality of types of ions detected. | 2022-02-17 |
20220051886 | TIME-OF-FLIGHT MASS SPECTROMETER AND METHOD FOR IMPROVING MASS AND SPATIAL RESOLUTION OF AN IMAGE - Disclosed embodiments include a time-of-flight mass spectrometer with a straight ion optical axis comprising: an ion gate is electrically insolated electrode on which applied voltages to reject/pass ions through ion gate, entrance module and exit module set in focus/mirror modes, and create ion optical image on image plane located in field view aperture, electrostatic object lens, entrance module in focus mode and, transport electrostatic lens, exit module in focus mode and projection lens focused and map ions from image plane of field view aperture to image plane of ion detector, projection lens configured to form ion optical image of sample holder on image plane of ion detector and ion optical components with corrected geometrical, chromatic and timed aberrations configured to compensate time arriving disturbance in image plane of ion detector and improve mass and spatial resolution of image on image plane of ion detector. | 2022-02-17 |
20220051887 | Ion Injection into an Electrostatic Linear Ion Trap Using Zeno Pulsing - An ion guide defining a guide axis receives ions. The ion guide applies a potential profile that includes a pseudopotential well to the ions using an ion control field. The ion control field includes a component for restraining movement of the ions normal to the guide axis and a component for controlling the movement of the ions parallel to the guide axis. The ion guide sequentially injects the ions with the same ion energy and in decreasing order of m/z value into an ELIT aligned along an ELIT axis to focus the ions irrespective of m/z value at the same location on the ELIT axis within the ELIT at the same time by varying a magnitude of the pseudopotential well. The ELIT can trap the focused ions using in-trap potential lift or mirror-switching ion capture. | 2022-02-17 |
20220051888 | METHOD FOR MANUFACTURING ALUMINUM NITRIDE-BASED TRANSISTOR - The present invention relates to a method of manufacturing an AlN-based transistor. An AlN-based high electron mobility transistor (HEMT) element according to the present invention may use an AlN buffer layer, and include an AlGaN composition change layer inserted into a GaN/AlN interface to remove or suppress a degree of generation of a two-dimensional hole gas (2DHG), thereby decreasing an influence of a coulomb drag on a two-dimensional electron gas (2DEG) layer and improving mobility of a two-dimensional electron gas (2DEG). | 2022-02-17 |
20220051889 | Method for Fabricating Field-Effect Transistor - A first semiconductor layer, a second semiconductor layer, a channel layer, a barrier layer, and a third semiconductor layer are crystal-grown in this order on a first substrate in the +c axis direction, a second substrate is bonded to the side of the barrier layer of the first substrate, and after that, the first substrate is removed, and the first semiconductor layer is selectively thermally decomposed by heating. | 2022-02-17 |
20220051890 | STEAM OXIDATION INITIATION FOR HIGH ASPECT RATIO CONFORMAL RADICAL OXIDATION - A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region. | 2022-02-17 |
20220051891 | Apparatus and Method of Forming a Semiconductor Layer - A method of forming a silicon layer includes introducing a source gas containing a precursor material and a carrier gas into a reactor, controlling a gas flow of the source gas through a first main flow controller unit in response to a change of a concentration of the precursor material in the source gas, introducing an auxiliary gas into the reactor, and controlling a gas flow of the auxiliary gas through a second main flow controller unit such that a total gas flow of the source gas and the auxiliary gas into the reactor is held constant when the gas flow of the source gas changes. | 2022-02-17 |
20220051892 | MANUFACTURING METHOD OF GALLIUM OXIDE THIN FILM FOR POWER SEMICONDUCTOR USING DOPANT ACTIVATION TECHNOLOGY - Disclosed is a method of manufacturing a gallium oxide thin film for a power semiconductor using a dopant activation technology that maximizes dopant activation effect and rearrangement effect of lattice in a grown epitaxial at the same time by performing in-situ annealing in a growth condition of a nitrogen atmosphere at the same time as the growth of a doped layer is finished. | 2022-02-17 |
20220051893 | NUCLEATION LAYER DEPOSITION METHOD - A nucleation layer comprised of group III and V elements is directly deposited onto the surface of a substrate made of a group IV element. Together with a first gaseous starting material containing a group III element, a second gaseous starting material containing a group V element is introduced at a process temperature of greater than 500° C. into a process chamber containing the substrate. It is essential that at least at the start of the deposition process of the nucleation layer, a third gaseous starting material containing a group IV element is fed into the process chamber, together with the first and second gaseous starting material. The third gaseous starting material develops an n-doping effect in the deposited III-V crystal, which causes a decrease in damping at a dopant concentration of less than 1×10 | 2022-02-17 |
20220051894 | CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME - Methods of making molybdenum sulfide (MoS | 2022-02-17 |
20220051895 | METHODS FOR DEPOSITING A TITANIUM ALUMINUM CARBIDE FILM STRUCTURE ON A SUBSTRATE AND RELATED SEMICONDUCTOR STRUCTURES - Methods for depositing a titanium aluminum carbide (TiAlC) film structure on a substrate are disclosed. The methods may include: depositing a first TiAlC film on a substrate utilizing a first cyclical deposition process, and depositing a second TiAlC film over the first TiAlC film utilizing a second cyclical deposition process. Semiconductor structures including titanium aluminum carbide (TiAlC) film structures deposited by the methods of the disclosure are also disclosed. | 2022-02-17 |
20220051896 | SELECTIVE METAL REMOVAL FOR CONDUCTIVE INTERCONNECTS IN INTEGRATED CIRCUITRY - Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided. | 2022-02-17 |
20220051897 | WAFER PROCESSING METHOD - A processing method for a wafer having a chamfered portion at a peripheral edge includes a holding step of holding the wafer by a holding table, and a chamfer removing step of rotating the holding table while causing a first cutting blade to cut into the peripheral edge of the wafer while supplying a cutting liquid from a first cutting liquid supply nozzle to cut the peripheral edge of the wafer. In the chamfer removing step, a second cutting unit is positioned at a position adjacent to the first cutting unit at such a height that a second cutting blade does not make contact with the wafer and on the side of the center of the wafer as compared to the first cutting unit, and the cutting liquid is supplied from a second cutting liquid supply nozzle. | 2022-02-17 |
20220051898 | ETCHING METHOD USING HALOGEN FLUORIDE AND METHOD FOR PRODUCING SEMICONDUCTOR - A method for precise plasma etching of micropatterns on a silicon substrate containing silicon or additionally having a silicon oxide film. An etching method for plasma-etching a silicon substrate having silicon or a silicon oxide film using a halogen fluoride having a nitrogen (N | 2022-02-17 |
20220051899 | ETCHING METHOD AND ETCHING APPARATUS - An etching method is provided that includes: (a) providing a substrate including an etching target film on a substrate support stage arranged in a process chamber; (b) setting a temperature of the substrate support stage; (c) generating plasma from an etching gas;(d) increasing the temperature of the substrate; (e) decreasing the temperature of the substrate; and (f) repeating (d) and (e) a predetermined number of times. | 2022-02-17 |
20220051900 | PATTERN FORMING METHOD - There is provided a pattern forming method for forming a pattern on a substrate. The method comprises preparing on a base a substrate in which a plurality of core materials arranged in a convex shape and in a line shape, and first and second line materials arranged in a convex shape and in a line shape on one side and the other side of each of the core materials, respectively, are formed, selectively forming a mask material on any one of the first and the second line materials by a process including anisotropic film formation, by a process including etching using a line mask having a line-shaped hole at a portion corresponding to a region where line cutting is performed, etching and removing the one on which the mask material is not formed among the first and the second line materials in the region, and removing the core material. | 2022-02-17 |
20220051901 | METHOD, DEVICE, AND SYSTEM FOR ETCHING SILICON OXIDE FILM - A method of etching silicon oxide on a surface of a substrate is provided. The method comprises alternately repeating heating the substrate to a heating temperature of 60° C. or higher, supplying hydrogen fluoride gas and ammonia gas onto the substrate to react with the silicon oxide, and modifying the silicon oxide to obtain a reaction product, and removing at least a portion of the reaction product from the substrate while stopping the supply of the above gases and continuing to heat the substrate at the heating temperature; and when a process gas that is at least one of the hydrogen fluoride gas and the ammonia gas is supplied, while continuing to supply the process gas from an upstream side of a flow path, closing a valve disposed in the flow path to pressurize the process gas in the flow path, and then opening the valve. | 2022-02-17 |
20220051902 | ETCHING METHOD AND PLASMA ETCHING APPARATUS - An etching method includes: (a) providing a substrate that contains silicon, on a support; (b) etching the substrate with plasma generated from a first gas that includes a fluorine-containing gas, to form an etching shape having a bottom; (c) generating plasma from a second gas that includes a hydrogen fluoride (HF) gas, to selectively form a condensed or solidified layer of HF at the bottom of the etching shape; and (d) etching the bottom with the plasma generated from the second gas, by supplying a bias power to the support. During (c) and (d), a temperature of the substrate is maintained to be 0° C. or lower. | 2022-02-17 |
20220051903 | PREPARATION METHOD FOR ACCURATE PATTERN OF INTEGRATED CIRCUIT - A method for preparing precise pattern of integrated circuits, which comprises the following steps: (S1) preparing a large pitch trench or circular through-hole structure with a hard mask in a first dielectric layer by lithography and etching; (S2) forming micro trench on the hard mask of the second dielectric layer at the bottom side wall of the trench or circular through-hole structure by plasma etching process; (S3) removing the first dielectric layer; (S4) opening the hard mask of the second dielectric layer at the micro trench formed on the hard mask of the second dielectric layer by plasma etching process; (S5) small pitch trench or circular through holes are prepared in the second dielectric layer. | 2022-02-17 |
20220051904 | ETCHING METHOD - An etching method including: (a) providing a workpiece including a first region made of a first material and a second region made of a second material defining a recess, the first region filling the recess of the second region while covering the second region; (b) generating plasma of a first fluorocarbon gas to etch the first region until before exposing the second region; (c) generating plasma of a second fluorocarbon gas to form fluorocarbon deposits on the first region; (d) generating plasma of an inert gas to etch the first region by fluorocarbon radicals contained in the fluorocarbon deposits; and (e) repeating step (c) and step (d) one or more times until after exposing the second region. An etching rate of the first material of the first region is higher than that of the second material of the second region with respect to the second fluorocarbon gas. | 2022-02-17 |
20220051905 | FORMATION OF LOW-TEMPERATURE AND HIGH-TEMPERATURE IN-SITU DOPED SOURCE AND DRAIN EPITAXY USING SELECTIVE HEATING FOR WRAP-AROUND CONTACT AND VERTICALLY STACKED DEVICE ARCHITECTURES - Techniques herein provide thermal processing solutions applicable to both existing FINFET applications, including wrap-around contacts, as well as 3D architectures such as transistor-on-transistor and gate-on-gate monolithic or heterogeneous CFET. Techniques include heating or annealing a first target material without heating or affecting performance of a second material or other materials. Techniques include using a first heating process to heat a substrate and materials provided thereon to a first temperature, and then using a wavelength/frequency tunable second heating process to increase temperature of the target material without increasing temperature of the second material or other materials. | 2022-02-17 |
20220051906 | Nitride-Containing STI Liner for SiGe Channel - A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers. | 2022-02-17 |
20220051907 | METHOD OF FABRICATING ELECTRONIC COMPONENT COOLING APPARATUS INCLUDING HEAT PIPES AND HEAT TRANSFER BLOCK - A method of fabricating an electronic component cooling apparatus. In the electronic component cooling apparatus, a cooling tower includes a plurality of heat dissipation plates stacked on each other, and heat pipes extend through portions of the heat dissipation plates in the top-bottom direction. A heat transfer block includes a base having grooves receiving the heat pipes and a cover covering the heat pipes is located on a top surface of an electronic component. The method includes locating the base above the heat pipes and pressing the base to the heat pipes using a press so that the grooves receive the heat pipes, dropping Cu dust produced from the pressing, realigning an assembly of the base and the heat pipes so that the base is located below, and a fourth step of locating the cover above the assembly and pressing the cover to the assembly using the press. | 2022-02-17 |
20220051908 | Fan-out Packaging Method and Fan-out Packaging Plate - A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole. | 2022-02-17 |
20220051909 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY - An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide methods of making an electronic device, and electronic devices made thereby, that comprise forming first and second encapsulating materials, followed by further processing and the removal of the entire second encapsulating material. | 2022-02-17 |
20220051910 | Showerhead With Interlaced Gas Feed And Removal And Methods Of Use - Gas distribution modules comprising a housing with an upper plenum and a lower plenum are described. One of the upper plenum and lower plenum is in fluid communication with an inlet and the other is in fluid communication with an outlet. A plurality of upper passages connects the upper plenum to the bottom of the housing to allow a flow of gas to pass through and be isolated from the first plenum. | 2022-02-17 |
20220051911 | ADJUSTABLE DEVICE AND AN ADJUSTABLE STORAGE BOX - The disclosure provides an adjustable device including plates and at least two adjustable modules connect with two adjacent of the plates. The adjustable module can stretch or shrink to change a distance between plates. The disclosure also provides an adjustable storage box including an upper cover and a lower cover. A storage space is formed by the upper cover and the lower cover and for the accommodating of the adjustable device. When the upper cover moves upward relative to the lower cover, the adjustable modules changes from a compression state to a stretch state and increase a distance between plates. Whereby, it is easy to pick and place object when a distance of two adjacent plates increases. The overall volume of the adjustable device is reduced when a distance of two adjacent plates decrease, thereby saving the working space. | 2022-02-17 |
20220051912 | GAS FLOW CONTROL DURING SEMICONDUCTOR FABRICATION - A method is provided. The method includes introducing a process gas into an interior space of a processing chamber through a gas inlet port, wherein a substrate is supported within the interior space. The process gas is evacuated from the interior space by a vacuum source through an exhaust port in fluid communication with the interior space of the process chamber. A flow of the process gas is controlled by supporting an exhaust baffle within a flow path of the process gas being evacuated from the interior space through the exhaust port. | 2022-02-17 |
20220051913 | TEMPERATURE MEASUREMENT UNIT, HEAT TREATMENT APPARATUS, AND TEMPERATURE MEASUREMENT METHOD - A temperature measurement unit includes a measurement substrate on which a sensor configured to measure a temperature is mounted, an information processor configured to acquire a result of detection by the sensor, and a cable connecting the sensor and the information processor to each other. The information processor is configured to be detachably installed on an installation part facing a heating area provided with a hot plate, with a cooling area interposed therebetween. The cable is configured to be able to follow movement of the measurement substrate when a cooling plate on which the measurement substrate is placed is moved from the cooling area to the heating area and the measurement substrate is placed on the hot plate in a state in which the information processor is installed on the installation part. | 2022-02-17 |
20220051914 | Wafer Susceptor - A wafer susceptor includes a plurality of grooves and a convex structure disposed in one groove of the plurality of grooves. The convex structure is asymmetrical, and a convex part of the convex structure is far away from a circle center of a wafer susceptor. The surface temperature of a portion of a substrate far away from the circle center of the wafer susceptor is increased. That is, the temperature of the convex position is basically the same as that of other positions on the substrate, the surface of the entire substrate is heated more uniformly, and thus the wavelength of an epitaxial wafer formed on the substrate is also more uniform, and the quality of the epitaxial wafer is promoted. | 2022-02-17 |
20220051915 | LIGHT IRRADIATION TYPE HEAT TREATMENT APPARATUS - A light diffusion plate made of quartz and provided with a plurality of recessed spherical surfaces is placed on an upper chamber window so as to be in opposed relation to a central portion of a semiconductor wafer. Flashes of light emitted from flash lamps and passing by the side of the light diffusion plate impinge upon a peripheral portion of the semiconductor wafer. On the other hand, flashes of light emitted from the flash lamps and entering the light diffusion plate are diverged by the recessed spherical surfaces. Part of the light entering the light diffusion plate is diffused toward the peripheral portion of the semiconductor wafer. As a result, this increases the amount of light impinging upon the peripheral portion of the semiconductor wafer, and decreases the amount of light impinging upon the central portion of the semiconductor wafer. | 2022-02-17 |
20220051916 | APPARATUS FOR TRANSFERRING MICRODEVICE AND METHOD FOR TRANSFERRING MICRODEVICE - This invention provides an apparatus for transferring at least one microdevice and a method for transferring at least one microdevice, which is characterized by utilizing the apparatus for transferring at least one microdevice having a magnetic attracting substrate with at least one magnetic attracting head or magnetic attracting position hole to attract at least one microdevice having at least one magnetic layer disposed on a temporary substrate, and transfer the at least one microdevice to the conductive bonding layer of the at least one microdevice bonding region on a target substrate thereafter. | 2022-02-17 |
20220051917 | OPERATION METHOD OF VACUUM PROCESSING DEVICE - According to one embodiment, a vacuum processing device is provided which is capable of being controlled to create the most suitable gas flow under the situation where the device is placed by allowing a plurality of vacuum transfer chambers to communicate with each other via the intermediate chamber in an operation method of the vacuum processing device including the plurality of vacuum transfer chambers connected to each other via the intermediate chamber and a plurality of vacuum processing chambers respectively connected to the vacuum transfer chambers. | 2022-02-17 |
20220051918 | TRANSFER CHAMBER WITH INTEGRATED SUBSTRATE PRE-PROCESS CHAMBER - A transfer chamber includes a monolithic chamber body, a transfer robot configured to pass substrates between a factory interface and a processing module in a substrate processing system, a load lock chamber station, a shutter station, a pre-clean chamber station, and a process chamber station integrated within the monolithic chamber body, and a plurality of slit valves integrated within the monolithic chamber body. The plurality of slit valves are configured to open and close the load lock chamber station, the pre-clean chamber station, and the process chamber station each from the shutter station such that the load lock chamber station, the pre-clean chamber station, and the process chamber station maintain respective vacuum pressures. | 2022-02-17 |
20220051919 | CONTROL OF WAFER BOW IN MULTIPLE STATIONS - A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing. | 2022-02-17 |
20220051920 | FUME-REMOVING DEVICE - The present invention relates to an apparatus for removing fume which includes, a wafer cassette for stacking wafers; and an exhaust for exhausting the fume of the wafers stacked in the wafer cassette, wherein the wafer cassette includes stacking shelves provided at both sides for stacking wafers; and a front opening for incoming and outgoing of the wafers which are being stacked in the stacking shelf, wherein the stacking shelves include multiple inclined ramp portions which are slanted towards the wafers stacked in the stacking shelves as they travel towards the front opening, wherein a purge gas outlet is provided in the inclined ramp portion for supplying purge gas for the wafers stacked in the stacking shelves. According to the present invention, the residual process gases on wafers can be removed efficiently. | 2022-02-17 |
20220051921 | METHOD FOR MASK AND SUBSTRATE ALIGNMENT - Methods and apparatuses for aligning masks with substrates are provided. A method can include receiving a carrier having a substrate disposed thereon at an alignment stage of an alignment module, transferring a mask from a mask cassette of a mask stocker of the alignment module to a position over the alignment stage, and positioning the mask on the carrier. The method also includes acquiring one or more images of the mask and the substrate, where the mask contains one or more alignment holes passing through the mask and the substrate contains one or more alignment elements disposed on an upper surface of the substrate, analyzing the one or more images to determine one or more differences between one or more alignment holes of the mask and one or more alignment elements of the substrate, and aligning the mask with the substrate based on the differences. | 2022-02-17 |
20220051922 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSFER METHOD - An apparatus for processing a substrate includes a housing having a processing space therein, a transfer robot that loads the substrate into the processing space or unloads the substrate from the processing space, a support unit including a chuck that supports the substrate in the processing space and a lift pin that moves the substrate in an up-down direction, a dielectric plate having a lower surface disposed to face an upper surface of the chuck, and a gap measurement unit that measures a gap between the dielectric plate and the substrate supported by the lift pin or a gap between the dielectric plate and the chuck. | 2022-02-17 |
20220051923 | ELECTROSTATIC CHUCK AND REACTION CHAMBER - The present disclosure provides an electrostatic chuck and a reaction chamber. The electrostatic chuck includes an insulation layer and a heating body arranged at a bottom of the insulation layer. The electrostatic chuck further includes a cooling pipeline. The cooling pipeline is arranged under the heating body, spaced apart from the heating body, and configured to transfer cooling liquid to absorb heat radiated by the heating body. The electrostatic chuck further includes a thin-wall structure respectively connected to the heating body and the cooling pipeline. The thin-wall structure is configured to reduce heat dissipation efficiency between the heating body and the cooling pipeline. The electrostatic chuck provided by the present disclosure may realize stable temperature control for the heating body during a processing process to effectively reduce whisker defects and to improve the product yield. | 2022-02-17 |
20220051924 | METHOD OF ALIGNING MICRO LIGHT EMITTING ELEMENT AND DISPLAY TRANSFERRING STRUCTURE - A method of aligning micro light emitting elements includes supplying the plurality of micro light emitting elements on a substrate including a plurality of grooves having different shapes, the plurality of micro light emitting elements being configured to be inserted exclusively and respectively into the plurality of grooves; respectively inserting the plurality of micro light emitting elements into the plurality of grooves; and aligning the plurality of micro light emitting elements, wherein at least one groove of the plurality of grooves has a shape that is different from a shape of a respective micro light emitting element inserted into the at least one groove. | 2022-02-17 |
20220051925 | MICRO DEVICE TRANSFER APPARATUS AND METHOD - A micro device transfer apparatus and a micro device transfer method are provided. The micro device transfer apparatus comprises a stage unit including a stage where a target substrate is to be disposed, a plurality of transfer head units disposed above the stage, and a transfer head unit moving part configured to move the plurality of transfer head units, wherein, the transfer head unit comprises a carrier substrate fastening part configured to fasten a carrier substrate where a plurality of micro devices are disposed, a mask unit disposed above the carrier substrate fastening part, the mask unit comprising a mask including an opening part and a shielding part, a light emitting part disposed on the mask unit, and a housing formed around the carrier substrate fastening part, the mask unit, and the light emitting part. | 2022-02-17 |
20220051926 | SUBSTRATE TRANSPORT APPARATUS, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE TRANSPORT METHOD - A substrate transport apparatus includes transport hands that clamp substrates by vacuum pressures, respectively, and that are located at different heights, a vacuum pressure supply unit that supplies the vacuum pressures to the transport hands, and a controller that controls the vacuum pressure supply unit to supply the vacuum pressures to the transport hands or interrupt the supply of the vacuum pressures to the transport hands. The controller controls the vacuum pressure supply unit such that the vacuum pressures of the transport hands are turned off at the same height from a substrate support member. | 2022-02-17 |
20220051927 | SUBSTRATE HOLDER FOR USE IN A LITHOGRAPHIC APPARATUS - A substrate holder for use in a lithographic apparatus and configured to support a substrate, the substrate holder having a main body having a main body surface, a plurality of main burls projecting from the main body surface, wherein each main burl has a distal end surface configured to support the substrate, a first seal member projecting from the main body surface and having an upper surface, the first seal member surrounding the plurality of main burls and configured to restrict the passage of liquid between the substrate and the main body surface radially inward past the first seal member, and a plurality of minor burls projecting from the upper surface of the first seal member, wherein each minor burl has a distal end surface configured to support the substrate. | 2022-02-17 |
20220051928 | TRANSFER DEVICE, TRANSFER SYSTEM, AND END EFFECTOR - A transfer device for simultaneously or separately transferring a wafer and a consumable part having a circular shape is disclosed. The consumable part is disposed in a wafer processing module, and the outer diameter of the consumable part is larger than the outer diameter of the wafer. The transfer device comprises an end effector configured to place the wafer and the consumable part thereon simultaneously or separately, an arm configured to move the end effector, and a controller configured to control the arm, to place the consumable part on the end effector such that the center of gravity of the consumable part coincides with a first position when transferring the consumable part, and to place the wafer on the end effector such that the center of gravity of the wafer coincides with a second position between the first position and front ends of the end effector when transferring the wafer. | 2022-02-17 |
20220051929 | BULK SEMICONDUCTOR STRUCTURE WITH A MULTI-LEVEL POLYCRYSTALLINE SEMICONDUCTOR REGION AND METHOD - Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module). | 2022-02-17 |
20220051930 | METHODS OF FORMING APPARATUSES INCLUDING AIR GAPS BETWEEN CONDUCTIVE LINES AND RELATED APPARATUSES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed. | 2022-02-17 |
20220051931 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench. | 2022-02-17 |
20220051932 | FINFET DEVICE AND METHOD OF FORMING SAME - A semiconductor device a method of forming the same are provided. The semiconductor device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure. | 2022-02-17 |
20220051933 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures. | 2022-02-17 |
20220051934 | METHOD FOR PRODUCING AN ADVANCED SUBSTRATE FOR HYBRID INTEGRATION - A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer. | 2022-02-17 |
20220051935 | SUBSTRATE PROCESSING METHOD - A substrate processing method capable of filling a gap structure without forming voids or seams in a gap while minimizing damage to the gap structure includes: forming a first thin film on a structure by performing a first cycle a plurality of times, the first cycle including supplying a first reaction gas onto the structure including a gap and purging a residue, forming a second thin film by changing a chemical composition of the first thin film, and forming a third thin film having the same component as that of the second thin film on the second thin film while filling the gap. | 2022-02-17 |
20220051936 | SEMICONDUCTOR DEVICE WITH GRAPHENE CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer. | 2022-02-17 |
20220051937 | SEMICONDUCTOR DEVICE WITH GRAPHENE-BASED ELEMENT AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate, a buried dielectric layer inwardly positioned in the first substrate, a buried conductive layer including a lower portion positioned on the buried dielectric layer and an upper portion positioned on the lower portion, a buried capping layer positioned on the upper portion, and buried covering layers positioned between the buried capping layer and the buried dielectric layer and between the upper portion of the buried conductive layer and the buried dielectric layer. The buried conductive layer includes graphene. | 2022-02-17 |
20220051938 | FILM STACK SIMPLIFICATION FOR HIGH ASPECT RATIO PATTERNING AND VERTICAL SCALING - Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon. | 2022-02-17 |
20220051939 | TRANSISTOR WITH REDUCED GATE RESISTANCE AND IMPROVED PROCESS MARGIN OF FORMING SELF-ALIGNED CONTACT - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes two gate structures, a first conductor, a barrier, a second conductor and a plurality of air gaps. The two gate structures are located on a surface of a semiconductor material substrate. The first conductor is disposed between the two gates structures. The barrier is disposed between the first conductor and the gate structure. The second conductor is disposed on the first conductor. The air gaps are disposed at two sides of the second conductor. A width of the second conductor is greater than a width of the first conductor. | 2022-02-17 |
20220051940 | CONTACT PLUG - The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer. | 2022-02-17 |
20220051941 | Methods Of Forming Metal Chalcogenide Pillars - Methods of producing a self-aligned structure comprising a metal chalcogenide are described. Some methods comprise forming a metal-containing film in a substrate feature and exposing the metal-containing film to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise forming a metal-containing film in a substrate feature, expanding the metal-containing film to form a pillar and exposing the pillar to a chalogen precursor to form a self-aligned structure comprising a metal chalcogenide. Some methods comprise directly forming a metal chalcogenide pillar in a substrate feature to form a self-aligned structure comprising a metal chalcogenide. Methods of forming self-aligned vias are also described. | 2022-02-17 |
20220051942 | FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE/DRAIN CONTACTS AND GATE CONTACTS POSITIONED OVER ACTIVE TRANSISTORS - A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner. | 2022-02-17 |
20220051943 | METHOD OF PROCESSING WAFER - A method of processing a wafer having a plurality of intersecting streets on a face side thereof with protrusions on the streets includes a holding step of holding a protective sheet of a wafer unit on a holding table, an upper surface heightwise position detecting step of detecting a heightwise position of an upper surface of a reverse side of the wafer along the streets, and a laser beam applying step of applying a laser beam having a wavelength transmittable through the wafer to the wafer from the reverse side thereof along the streets while positioning a focused point of the laser beam within the wafer on the basis of the heightwise position, to thereby form modified layers in the wafer along the streets. | 2022-02-17 |
20220051944 | METHOD FOR MANUFACTURING A MEMORY DEVICE AND MEMORY DEVICE MANUFACTURED THROUGH THE SAME METHOD - A method for manufacturing a 3D vertical array of memory cells is disclosed. The method comprises:
| 2022-02-17 |
20220051945 | Embedded Stressors in Epitaxy Source/Drain Regions - A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin. | 2022-02-17 |
20220051946 | INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE - Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC). | 2022-02-17 |
20220051947 | Different Source/Drain Profiles for N-type FinFETs and P-type FinFETs - A method includes etching a first and a second semiconductor fin to form a first and a second recesses, epitaxially growing an n-type source/drain region comprising a first portion and a second portion from the first and the second recesses, and a first middle portion in between and having a concave top surface. A first contact opening is formed extending into the n-type source/drain region and having a first V-shaped bottom. The method further includes etching a third and a fourth semiconductor fin to form a third and a fourth recesses, and forming a p-type source/drain region including a third portion and a third portion grown from the third and the fourth recesses, and a second middle portion in between and having a convex top surface. A second contact opening is formed and has a second V-shaped bottom, with a tip of the second V-shaped bottom being downwardly pointing. | 2022-02-17 |
20220051948 | Asymmetric Epitaxy Regions for Landing Contact Plug - A method includes forming isolation regions extending into a semiconductor substrate, and forming a first plurality of protruding fins and a second protruding fin over the isolation regions. The first plurality of protruding fins include an outer fin farthest from the second protruding fin, and an inner fin closest to the second protruding fin. The method further includes etching the first plurality of protruding fins to form first recesses, growing first epitaxy regions from the first recesses, wherein the first epitaxy regions are merged to form a merged epitaxy region, etching the second protruding fin to form a second recess, and growing a second epitaxy region from the second recess. A top surface of the merged epitaxy region is lower on a side facing toward the second epitaxy region than on a side facing away from the second epitaxy region. | 2022-02-17 |
20220051949 | Semiconductor Device and Method - An embodiment device includes: first fins protruding from an isolation region; second fins protruding from the isolation region; a first fin spacer on a first sidewall of one of the first fins, the first fin spacer disposed on the isolation region, the first fin spacer having a first spacer height; a second fin spacer on a second sidewall of one of the second fins, the second fin spacer disposed on the isolation region, the second fin spacer having a second spacer height, the first spacer height greater than the second spacer height; a first epitaxial source/drain region on the first fin spacer and in the first fins, the first epitaxial source/drain region having a first width; and a second epitaxial source/drain region on the second fin spacer and in the second fins, the second epitaxial source/drain region having a second width, the first width greater than the second width. | 2022-02-17 |
20220051950 | GAPFILL STRUCTURE AND MANUFACTURING METHODS THEREOF - A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench. | 2022-02-17 |
20220051951 | METHOD FOR PRODUCING OVERLAY RESULTS WITH ABSOLUTE REFERENCE FOR SEMICONDUCTOR MANUFACTURING - A method of processing a wafer is provided. The method includes providing a reference pattern for patterning a wafer. The reference pattern is independent of a working surface of the wafer. A placement of a first pattern on the working surface of the wafer is determined by identifying the reference pattern to align the first pattern. The first pattern is formed on the working surface of the wafer based on the placement. | 2022-02-17 |