07th week of 2011 patent applcation highlights part 10 |
Patent application number | Title | Published |
20110037431 | BATTERY CHARGER FOR A PORTABLE RADIO - A battery charger for a portable radio having a cradle which holds and charges a radio with a battery attached, or optionally holds and charges the battery alone. The cradle is typically mounted in a vehicle. A lock element is provided in the cradle to engage the battery and is operated by a lock actuator and a release actuator. The lock actuator is displaced when the radio or battery is pushed into the cradle by a user. The release actuator may be displaced by the user to disengage the lock from the battery. | 2011-02-17 |
20110037432 | BATTERY STATE MONITORING CIRCUIT AND BATTERY DEVICE - Provided are a battery state monitoring circuit and a battery device which can be readily adapted to variation in number of batteries, and has low withstand voltage and a simple circuit configuration. The battery state monitoring circuit includes: a first voltage monitoring terminal; a second voltage monitoring terminal; a first transmitting terminal; a second transmitting terminal; a first receiving terminal; a second receiving terminal; a control terminal; an overcharge detector circuit for detecting whether a battery is in an overcharged state or not based on a voltage between the first voltage monitoring terminal and the second voltage monitoring terminal and outputting an overcharge detection signal indicating the detection result; and an overcharge information communication circuit for transmitting an overcharge signal indicative of an overcharged state to an external from the first transmitting terminal when at least one of an overcharge signal indicating whether another battery is in the overcharged state or not, which has been received through the first receiving terminal, and the overcharge detection signal, is indicative of the overcharged state. | 2011-02-17 |
20110037433 | CELL BALANCING CIRCUIT AND SECONDARY BATTERY WITH CELL BALANCING CIRCUIT - A cell balancing circuit with a self-balancing function and a secondary battery with the cell balancing circuit, the cell balancing circuit includes a balancing unit provided for every two adjacent unit cells among the unit cells. The balancing unit includes a discharge unit and a voltage-dividing unit. The discharge unit sets a discharge path to discharge only the unit cell with the higher voltage among the two adjacent unit cells. The voltage-dividing unit uses the voltages of the two adjacent unit cells to provide an enable signal to the discharge unit. | 2011-02-17 |
20110037434 | METHOD OF CONTROLLING BATTERY CHARGE LEVEL OF HYBRID ELECTRIC VEHICLE - A method of controlling a battery charge level of a hybrid electric vehicle includes: monitoring a quantity of current accumulated for a predetermined time based on a battery charge/discharge current value; calculating a regenerative charge derating constant; calculating a correction coefficient based on the quantity of current accumulated and a battery state of charge; multiplying the regenerative charge derating constant by the correction coefficient to calculate a final regenerative charge derating constant; and multiplying the final regenerative charge derating constant by a charge power to calculate a final charge power, and selectively restricting the battery charge level based on the final charge power. | 2011-02-17 |
20110037435 | POWER TOOL - A power tool | 2011-02-17 |
20110037436 | MULTI-MODAL BATTERY PACK - At least one embodiment of the invention provides a multi-modal rechargeable battery pack that can switch between charging algorithms dynamically. This dynamic switching can be accomplished in a wide variety of ways, for example via external command or automatically. At least one embodiment of the invention provides a system that can switch a multi-modal rechargeable battery pack between one or more of a runtime mode, a lifespan mode, and a quick charge mode. | 2011-02-17 |
20110037437 | METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY - A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature. | 2011-02-17 |
20110037438 | MODULATED, TEMPERATURE-BASED MULTI-CC-CV CHARGING TECHNIQUE FOR LI-ION/LI-POLYMER BATTERIES - Some embodiments of the present invention provide a system that charges a battery. During operation, the system obtains a set of charging currents {I | 2011-02-17 |
20110037439 | INCREASING ENERGY DENSITY IN RECHARGEABLE LITHIUM BATTERY CELLS - Some embodiments of the present invention provide an improved rechargeable lithium battery. This rechargeable lithium battery includes a cathode current collector with a coating of cathode active material. It also includes an electrolyte separator, and an anode current collector with a coating of anode active material. Within this rechargeable battery, the thickness of the coating of cathode active material and the thickness of the coating of anode active material are selected so that the battery will charge in a predetermined maximum charging time with a predetermined minimum cycle life when the battery is charged using a multi-step constant-current constant-voltage (CC-CV) charging technique. Note that using the multi-step CC-CV charging technique instead of a conventional charging technique allows the thickness of the cathode active material and the thickness of the anode active material to be increased while maintaining the same predetermined maximum charging time and the same predetermined minimum cycle life. This increase in the thickness of the active materials effectively increases both the volumetric and gravimetric energy density of the battery cell. | 2011-02-17 |
20110037440 | Process for producing lithium secondary battery - A process for producing a lithium secondary battery employs a charging method where a positive electrode upon charging has a maximum achieved potential of 4.3 V (vs. Li/Li+) or lower. The process includes charging the lithium secondary battery to reach at least a region with relatively flat fluctuation of potential appearing in a positive electrode potential region exceeding 4.3 V (vs. Li/Li | 2011-02-17 |
20110037441 | SYSTEMS AND METHODS OF REDUCING A LOAD ON AN ENGINE - A system for reducing an alternator's load on an engine when the engine drives a second load. The system includes an alternator, a battery, a resistor, and a switch. The alternator includes a stator, a voltage regulator, a rectifier, and a field coil. The battery has a first terminal coupled to the alternator and a second terminal coupled to the alternator. The resistor has a first lead coupled to the first terminal and a second lead coupled to the field coil. The switch is coupled in parallel across the resistor, and is open when the engine drives the second load and closed when the engine is not driving the second load. | 2011-02-17 |
20110037442 | PERMANENT MAGNET GENERATOR CONTROL - A method of and a system for controlling a permanent magnet AC generator ( | 2011-02-17 |
20110037443 | PARALLEL CONNECTED PFC CONVERTER - A parallel PFC converter comprises a first PFC circuit, a second PFC circuit, and a voltage divider. The second PFC circuit is connected in parallel with the first PFC circuit for generating an output voltage of the parallel PFC converter. The voltage divider is coupled to receive the output voltage for generating a first feedback signal and a second feedback signal. The first feedback signal is higher than the second feedback signal. The first PFC circuit and the second PFC circuit respectively comprises a first switching control circuit and a second switching control circuit for regulating the output voltage. It is an object of the present invention to reduce the power loss for improving the efficiency of the PFC converter. | 2011-02-17 |
20110037444 | Bridgeless Boost PFC Circuits and Systems With Reduced Common Mode EMI - According to one example embodiment, a bridgeless boost power factor correction (PFC) system includes a first input for connection to a first line of an alternating current (AC) source and a second input for connection to a second line of the AC source. The PFC system includes an output for delivering an output of the bridgeless boost PFC system, a first boost choke coupled to the first input and a second boost choke coupled to the second input. A common mode choke is coupled between the first and second input and the first and second boost choke. A first X capacitor is coupled between the first input and the output and a second X capacitor coupled between the second input and the output. | 2011-02-17 |
20110037445 | POWER CONTROL CIRCUIT FOR WIRE COMPENSATION AND COMPENSATION METHOD OF THE SAME - A power control circuit with wire compensation is provided. The power control circuit is applied in a power converter, which has an output coupled to a load through a power wire. The power control circuit has an adaptive sensing circuit and a controller. The adaptive sensing circuit is utilized for detecting an output voltage of the power converter and a current on the power wire and generating a feedback signal according to the output voltage and the current on the power wire. The controller is utilized for adjusting a level of the output voltage according to the feedback signal. | 2011-02-17 |
20110037446 | SWITCH MODE POWER SUPPLY WITH DYNAMIC TOPOLOGY - A power supply system has an inductive device, a plurality of switching devices for providing connection of the inductive device to input and output nodes and a ground node, and a switch driver circuit for driving the switching devices so as to enable the power supply to operate in a boost mode to increase the input voltage, in a buck mode to decrease the input voltage, and in a solid-state flyback mode to transfer between the boost mode and the buck mode. In the solid-state flyback mode, the switching devices are controlled to provide switching of the inductive device between an input state in which the inductive device is connected between the input node and the ground node, and an output state in which the inductive device is connected between the ground node and the output node. | 2011-02-17 |
20110037447 | Component Powered by HDMI Interface - A HDMI (High-Definition Multimedia Interface) transmitter component may be operated solely on power that is scavenged and converted from termination tail current received while the HDMI transmitter component is coupled to an HDMI compliant sink connector on a HDMI receiver component. The termination tail current is received at the transmitter component from a plurality of differential HDMI signals from terminators on a receiver component. A portion of the received tail current is converted to form a supply voltage Vdd source. Function logic on the transmitter component is operated using the Vdd voltage, and the function logic is configured to control the plurality of differential signals. | 2011-02-17 |
20110037448 | Switching regulator with transient control function and control circuit and method therefor - The present invention discloses a switching regulator with transient control function, and a control circuit and a method for controlling the switching regulator. The switching regulator with transient control function includes: a power conversion circuit for receiving an input voltage and converting the input voltage to an output voltage; a feedback circuit for detecting the output voltage and generating a feedback signal representing the output voltage; an output capacitor coupled to an output terminal of the power conversion circuit; and a control circuit for receiving the feedback signal and generating a control signal to control the conversion operation by the power conversion circuit accordingly, wherein the control circuit includes a voltage balancing circuit which discharges the output capacitor when the output voltage is higher than a first predetermined threshold, and charges the output capacitor when the output voltage is lower than a second predetermined threshold. | 2011-02-17 |
20110037449 | SEMICONDUCTOR DEVICE - A non-insulated DC-DC converter has a power MOS-FET for a highside switch and a power MOS-FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS-FET for the highside switch and the power MOS-FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS-FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other. | 2011-02-17 |
20110037450 | SEMICONDUCTOR DEVICE - In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided including a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p-channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOSFET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad. | 2011-02-17 |
20110037451 | BANDGAP VOLTAGE REFERENCE CIRCUIT - A bandgap voltage reference circuit comprising: a first P-N junction circuit generating a first voltage which changes according to a first characteristic; a second P-N junction circuit generating a second voltage which changes according to a second characteristic different from the first characteristic; an amplifier receiving the first and second voltages at a pair of input terminals and changing the amount of an output current provided from a high-voltage power supply to an output terminal according to a difference voltage between the first and second voltages, wherein an output voltage at the output terminal is provided to the first and second P-N junction circuits; and an output current controller causing the amplifier to provide the output current to the output terminal regardless of the difference voltage when the output voltage equals to or is smaller than a threshold voltage. | 2011-02-17 |
20110037452 | DETECTION OF GROUND-LAID WIRE USING ULTRAVIOLET C-BAND RADIATION - A system for tracing wire includes an electrical exciter adapted to apply a voltage to a ground-laid wire to generate a corona at an outer surface of the ground laid wire, at least a portion of the corona including ultraviolet c-band radiation, and an ultraviolet c-band detector to detect the ultraviolet c-band radiation to trace at least a portion of the path of the ground-laid wire. | 2011-02-17 |
20110037453 | DETECTOR DEVICE - A high-frequency detector device ( | 2011-02-17 |
20110037454 | CdSe QUANTUM DOTS DOPED OPTICAL FIBER AND A CURRENT SENSOR USING THE SAME - Disclosed is an optical fiber for a current sensor, the optical fiber comprising a core doped with CdSe quantum dots and a current sensor using the same. | 2011-02-17 |
20110037455 | SYSTEM FOR MEASURING ELECTRICAL POWER - The claimed subject matter discloses a system for measuring power consumption of an electrical appliance. The system comprises a sensing module for sensing physical phenomenon, located externally to the electrical appliance. The system further comprises a transmitter for transmitting information representing the physical phenomenon sensed by the sensing module and a power device. The physical phenomenon sensed by the sensing module provides indication on whether the electrical appliance is ON or OFF and whether the power consumption of the electrical appliance increased or decreased. In some cases, the indication is one or more scalars representing the sensed physical phenomena. | 2011-02-17 |
20110037456 | Measuring Transducer for Process Instrumentation, and Method for Monitoring the Condition of the Sensor Thereof - A measuring transducer for process instrumentation that comprises a sensor for sensing a physical or chemical variable, wherein the sensor includes at least one electrical element embedded in a substrate comprising semiconducting material and is electrically separated therefrom by a blocked PN junction during normal operation. In order to monitor the condition of the sensor, the PN junction is connected in the conducting direction in a test mode, and the electrical property of the PN junction, i.e., the forward voltage, is determined and used to monitor the sensor condition. Additionally, a temperature sensor mounted on the sensor can be monitored by determining, based on the dependence of the forward voltage on the temperature, a comparative value for the temperature sensed by the temperature sensor. If major differences occur, a conclusion can be reached that there is a failure of the sensor, and a corresponding error message can be output over a field bus. | 2011-02-17 |
20110037457 | READOUT APPARATUS FOR CURRENT TYPE TOUCH PANEL - A readout apparatus for a current type touch panel is provided. The readout apparatus includes a current-to-voltage converter, a voltage gain unit and an analog-to-digital converter (ADC). The current-to-voltage converter converts a sensing current of the current type touch panel to a sensing voltage. An input end of the voltage gain unit is coupled to an output end of the current-to-voltage converter for receiving the sensing voltage. An input end of the ADC is coupled to an output end of the voltage gain unit. An output end of the ADC generates a digital code. | 2011-02-17 |
20110037458 | Open loop magneto-resistive magnetic field sensor - An apparatus and a general method to measure a magnetic field using magneto-resistive sensors in an open-loop configuration are disclosed. A key feature is the regular in-situ normalization of the sensors to compensate for the effects of sensor aging. | 2011-02-17 |
20110037459 | ROTATION-ANGLE-DETECTING APPARATUS - A rotation-angle-detecting apparatus comprising a magnet rotor, a magnetic sensor detecting the direction of magnetic flux from the magnet rotor, a correction circuit, and an angle-calculating circuit, the magnetic sensor having bridge circuits X and Y each comprising four connected magnetoresistive devices, each magnetoresistive device comprising a spin-valve, giant-magnetoresistive film, the correction circuit calculating difference (Vx−Vy) and sum (Vx+Vy) from the output voltage Vx of the bridge circuit X and the output voltage Vy of the bridge circuit Y, and making their amplitudes equal to each other, and the angle-calculating circuit determining the rotation angle of the rotor by arctangent calculation from a signal (Vx−Vy)′ and a signal (Vx+Vy)′ supplied with the same amplitude from the correction circuit. | 2011-02-17 |
20110037460 | Multiple receiver coil dual mode electromagnetic detector - An electromagnetic detection system comprising: a transmitter loop for generating a primary magnetic field, and a first pair of spaced apart receiver coils and second pair of spaced apart receiver coils for measuring a secondary magnetic field generated in response to the primary magnetic field. The transmitter loop drives the transmitter to generate the primary magnetic field. The system automatically switches between a first signal measuring mode and a second signal measuring mode, wherein in the first signal measuring mode a difference between signals induced in the receiver coils of the first pair is measured to provide a first receiver coil pair difference signal and a difference between the signals induced in the receiver coils of the second pair is measured to provide a second receiver coil pair difference signal, and in the second signal measuring mode a sum of the signals induced in the receiver coils of the first pair is measured to provide a first receiver coil pair sum signal and a sum of the signals induced in the receiver coils of the second pair is measured to provide a second receiver coil pair sum signal, and the difference between the first receiver coil pair signal and the second receiver coil pair signal is determined. | 2011-02-17 |
20110037461 | METHOD AND DEVICE FOR DETECTING NEAR-SURFACE DEFECTS BY MEANS OF MAGNETIC LEAKAGE FLUX MEASUREMENT - In a method for detecting near-surface defects in a test sample consisting at least partly of a ferromagnetic material, a test volume of the test sample is magnetized and scanned for the detection of magnetic leakage fields caused by defects. The test volume is magnetized by means of a magnetic constant field and simultaneously by means of a magnetic alternating field superposed on the constant field. Leakage field test devices suitable for carrying out the method are described. | 2011-02-17 |
20110037462 | Multiple Receiver Coil Dual Mode Electromagnetic Detector - An electromagnetic detection system comprising: a transmitter loop for generating a primary magnetic field, and spaced apart receiver coils for measuring a secondary magnetic field generated in response to the primary magnetic field. | 2011-02-17 |
20110037463 | SPINTRONIC MAGNETIC NANOPARTICLE SENSORS WITH AN ACTIVE AREA LOCATED ON A MAGNETIC DOMAIN WALL - A sensor is described for detecting the presence of a magnetic nanoparticle (N). The sensor is arranged on a support ( | 2011-02-17 |
20110037464 | TUNABLE GRAPHENE MAGNETIC FIELD SENSOR - A magnetic field sensor employing a graphene sense layer, wherein the Lorentz force acting on charge carriers traveling through the sense layer causes a change in path of charge carriers traveling through the graphene layer. This change in path can be detected indicating the presence of a magnetic field. The sensor includes one or more gate electrodes that are separated from the graphene layer by a non-magnetic, electrically insulating material. The application of a gate voltage to the gate electrode alters the electrical resistance of the graphene layer and can be used to control the sensitivity and speed of the sensor. | 2011-02-17 |
20110037465 | COMPOSITE PULSE DESIGN METHOD FOR LARGE-TIP-ANGLE EXCITATION IN HIGH FIELD MAGNETIC RESONANCE IMAGING - A magnetic resonance imaging apparatus having a static magnetic field source, a plurality of radio frequency magnetic field sources and a plurality of gradient magnetic field sources for generating a gradient magnetic field is provided. The static magnetic field source generates a static magnetic field for aligning a spin vector of an object in a direction of the magnetic field and plurality of radio frequency magnetic field sources generate a radio frequency magnetic field for rotating the spin vector by an angle. The apparatus further includes a processor for generating a plurality of radio frequency excitation pulses for the plurality of radio frequency magnetic field sources and a plurality of gradient excitation pulses for the plurality of gradient magnetic field sources. The second half of each of the plurality of radio frequency excitation pulses comprises a time-reversed first half of a respective one of the plurality of radio frequency excitation pulses and the second half of each of the plurality of gradient excitation comprises a time-reversed and sign-reversed first half of a respective one of the plurality of gradient excitation pulses. The average value of each of the plurality of gradient excitation pulses is zero. | 2011-02-17 |
20110037466 | Magnetic resonance imaging apparatus and magnetic resonance imaging method - A magnetic resonance imaging apparatus includes an imaging unit which applies a labeling pulse to invert a spin included in a labeling region within part of a imaging region and then collects a echo signal from a time point when an inversion time has passed from the application of the labeling pulse, and a control unit, the control unit controlling the imaging unit so that the echo signal in the imaging region is collected a plurality of times with variations in the inversion time, the control unit also controlling the imaging unit so that a time ranging from a reference time point within a biological signal obtained from a subject to the application of the labeling pulse is a time determined in accordance with the inversion time. | 2011-02-17 |
20110037467 | MAGNETIC RESONANCE IMAGING APPARATUS - A magnetic resonance imaging apparatus includes: a pair of static magnetic field generators separately disposed at the top and bottom of an imaging space in which a subject is placed; a shim magnetic material, disposed on the imaging-space side of each of the pair of static magnetic field generators, for generating a magnetic field to adjust the static magnetic field; a gradient magnetic field generator; a high-frequency magnetic field generator; a temperature sensor for directly or indirectly measuring the temperature of the shim magnetic material; and a controller for controlling the gradient magnetic field generator and the high-frequency magnetic field generator to execute an imaging pulse sequence. The controller determines the inhomogeneity of the static magnetic field from the output of the temperature sensor, considering the change in a magnetic field adjustment parameter due to the temperature change of the shim magnetic material, and causes a warning message to be presented if the determined static magnetic field inhomogeneity has exceeded a predetermined allowable value. | 2011-02-17 |
20110037468 | OPTIMIZED MRI STRIP ARRAY DETECTORS AND APPARATUS, SYSTEMS AND METHODS RELATED THERETO - Featured is a device for NMR or MRI signals from excited nuclei as well as related apparatus, systems and methods. The device includes a strip array antenna including one or more conductor and N reactive tuning components, where N is an integer≧1 at least one of the N reactive components is electrically coupled to each of the one or more conductors as well as to ground/virtual ground. The apparent electrical length of the conductors is tuned with the reactive tuning components so it is equal to be about nλ/4, where n is an integer≧1 and λ is the wavelength of the signal to be detected. The length of the strip also is such as to be substantially in the approximate range of 1.3 times the depth of interest. The strip conductors are also combined with loop coils to form quadrature detectors. | 2011-02-17 |
20110037469 | Electromagnet Device and Magnetic Resonance Imaging Device - An electromagnet device which generates magnetic field in the direction perpendicular to the inserting direction of an inspection subject is reduced in size and weight by removing unnecessary arrangement as much as possible. A magnetic resonance imaging device is also provided. The electromagnet device comprises a first coil ( | 2011-02-17 |
20110037470 | MAGNETIC RESONANCE SURFACE COIL - A plug block module for a surface coil for a magnetic resonance tomography apparatus has a plug block body with contacts for connection lines that can be connected with a magnetic resonance tomography apparatus, an adapter plug that can be inserted into an adapter plug of the surface coil, a surface coil connector device that fixes the plug block module to the surface coil, and a connection between the plug block and the adapter plug. | 2011-02-17 |
20110037471 | MAGNETIC RESONANCE IMAGING APPARATUS - In a magnetic resonance imaging apparatus according to an embodiment, a transmitting coil applies a radio-frequency magnetic field to a subject placed in a static magnetic field. A receiving coil receives a magnetic resonance signal emitted from the subject owing to an application of the radio-frequency magnetic field. A balun is connected to the receiving coil, and suppresses an unbalanced current induced in the receiving coil. An overheat protection circuit indicates that the balun is abnormal when a temperature of the balun exceeds a temperature threshold. An imaging control unit stops imaging when the overheat protection circuit indicates an abnormality of the balun. | 2011-02-17 |
20110037472 | Omnidirectional Sonde and Line Locator - At least one antenna array including three mutually orthogonal antennas each sharing a common center point senses an electromagnetic signal emitted by a buried object such as a utility line, pipe or sonde. A circuit at least partially mounted in a housing is connected to the array and determines a location of the buried object by measuring signal strength and field angles in three dimensions without having to align the antenna array relative to the buried object while eliminating nulls and false peaks. A graphical user interface (GUI) has user-friendly icons, symbols, menus, numbers and graphical and auditory representation of signal strength. A SEARCH view indicates signal strength by showing a rotating strength indicator, a trace mode MAP view in which line location is shown by a line that moves side-to-side, and a sonde mode MAP view in which sonde location is shown by a moving line, pole and equator. | 2011-02-17 |
20110037473 | Data acquisition method with a three dimensional small bin electromagnetic consecutive array - Disclosed herein is a three dimensional small bin electromagnetic consecutive array data acquisition method used in oil exploration comprising the steps of recording data using small bin lattices on execution of arrangement electrodes, each acquisition station (E | 2011-02-17 |
20110037474 | METHOD AND SYSTEM FOR MEASURING RESISTIVITY ANISOTROPY OF LAYERED ROCK SAMPLES - A method and apparatus for measuring the resistivity anisotropy of cylindrical rock samples is disclosed. The measurement setup includes two pairs of electrodes that contact the sample surface. The ring electrodes of the first pair are disposed on the cylindrical surface of the sample. The cap electrodes of the second pair are mounted at the sample ends. Two differences in potentials are measured. One of the cap electrodes and the nearest ring electrode are used to measure the first difference that results from current injected through the remaining cap and ring electrodes. The second difference is measured between the two ring electrodes, while current is injected through the first and second end cap electrodes. These two differences are inverted for the anisotropy coefficient, horizontal and vertical resistivity. | 2011-02-17 |
20110037475 | Battery Capacity Estimation by DCIR - A method of battery capacity measurement is actualized by battery internal resistance. This method establishes a controlled discharge path inside the battery module. The battery discharge current is a constant value despite of the variation of system loading current. The internal resistance measured by establishing this constant battery current can be used to obtain the battery capacity precisely. | 2011-02-17 |
20110037476 | METHOD AND APPARATUS FOR DETECTING ABNORMALITY OF CURRENT SENSOR IN BATTERY PACK - Disclosed are a method and an apparatus for detecting abnormality of a current sensor operative to measure a charge or discharge current of a battery pack. The method comprises measuring current and voltage of the battery pack; and detecting abnormality of the current sensor by comparing variations in current and voltage over a predetermined time with a current reference value and a voltage reference value, respectively. | 2011-02-17 |
20110037477 | TEST STRUCTURE FOR HIGHLY ACCELERATED ELECTROMIGRATION TESTS FOR THICK METALLIZATION SYSTEMS OF SOLID INTEGRATED CIRCUITS - A test structure and a process for the electromigration test of integrated circuits is suggested, in which metallization planes consisting of strip conductors of a usual thickness ( | 2011-02-17 |
20110037478 | FIELD DEVICE - Disclosed is a field device which determines whether or not an abnormality which was detected is the type of abnormality which may not allow the output of a burn-out H signal, and sets a signal output for the abnormality to a burn-out L signal when the type of abnormality was one which may not allow the output of a burn-out H signal. For example, an abnormality in the D/A converter or the power supply. Therefore, a burn-out L signal is always output for an abnormality judged likely not to be able to output a burn-out H signal, and the certainty of reporting an abnormality when burn-out H is set is enhanced. | 2011-02-17 |
20110037479 | Method for Fault Monitoring at a Lighting Output of a Motor Vehicle - A method for fault monitoring at a lighting output of a motor vehicle. Reference current values are first measured and calculated at various reference voltages. During operation of the lighting output, operating current values and operating voltages are measured. If the operating current value at the measured operating voltage deviates from the reference current value at the corresponding reference voltage, then a fault message is output. The method is suitable for detecting a fault even for unknown lamps at the lighting output. | 2011-02-17 |
20110037480 | METHOD FOR FAULT LOCATION IN UNCOMPENSATED POWER LINES WITH TWO-END UNSYNCHRONIZED MEASUREMENT - A method is provided for fault location in uncompensated power lines with two-end unsynchronized measurement, finding an application in the power industry and for overhead and overhead-cable transmission or distribution lines. The method according to the invention includes measuring the voltage and currents at both ends (A) and (B) of the section, obtaining the phasor of the positive sequence voltages (V | 2011-02-17 |
20110037481 | Method Of Testing Substrate - Disclosed herein is a method of testing a substrate. In the method, a first test terminal is connected to a first external circuit layer coupled to a first connection pad of a first active element included in a substrate, and a second test terminal is connected to a second external circuit layer coupled to a second connection pad of the first active element. Static electricity is applied through the first test terminal and a voltage drop of an electrostatic discharge protection circuit of the first active element is measured at the second test terminal, thus testing a status of a connection between the first active element and the external circuit layers. In the method, status of a connection of a connection circuit layer, a connection of an external circuit layer, a connection of a surface mount element, and a normal operation of the substrate is further tested. | 2011-02-17 |
20110037482 | Nondestructive inspection method of insulator using frequency resonance function - A nondestructive inspection method of testing insulators using frequency resonance function that can inspect an anomaly of an insulator by vibrating the insulator with a force having the characteristic of white noise, measuring the change in motion of the insulator according to the vibration and calculating the frequency resonance function of the insulator is disclosed. | 2011-02-17 |
20110037483 | MESS-SENSOR - The invention relates to a sensor having a conductor arrangement and an intervening dielectric to detect local sensor impedances in response to external forces. The conductor arrangement comprises elongate conductor strips between which the intervening dielectric is arranged as a compressible insulating medium. | 2011-02-17 |
20110037484 | System and Method for Augmented Impedance Sensing - An impedance monitoring circuit for an electrosurgical generator is disclosed. The monitoring circuit includes an isolation transformer coupled to at least one of an active terminal and a return terminal of an electrosurgical generator, wherein the isolation transformer includes a primary winding coupled to a reference resistor and a secondary winding coupled to a load. The monitoring circuit also includes a driver configured to transmit a sensor signal to the reference resistor and the load, a primary converter coupled to the reference resistor and the load and configured to detect a primary converted signal as a function of the sensor signal passing through the reference resistor and the load. The monitoring circuit further includes a secondary converter coupled to the driver and configured to detect a secondary converted signal as a function of the sensor signal prior to passing through the reference resistor and the load and a controller configured to determine a fault condition based on the primary and secondary converted signals. | 2011-02-17 |
20110037485 | COVERING AND SEALING FILM FOR A PACK AND A METHOD FOR DETERMINING THE OPENING STATE OF A PACK - The invention concerns a covering and/or sealing film for a pack, in particular a blister pack, configured to seal at least one filling product chamber and allow opening access to the filling product chamber by separation and/or tearing, wherein the film, in particular in the area of the filling product chamber, has a predetermined electrical conductance property (C | 2011-02-17 |
20110037486 | NUCLEOTIDE CAPACITANCE MEASUREMENT FOR LOW COST DNA SEQUENCING - High frequency capacitance measurement on a single strand of deoxyribonucleic acid (DNA) or a ribonucleic acid (RNA) is employed to provide identification of the nucleotides in the strand. Effect of variations in the capacitance of nucleotides can be minimized by employing statistical quantities generated from multiple measurement values on a strand of DNA or RNA nucleotides, or by employing a program that positively identifies a large capacitance nucleotide upon detection of a large capacitance. Capacitance data on a DNA strand can be used as a criterion for identifying the DNA sequence in conjunction with other methods for identifying the DNA sequence. | 2011-02-17 |
20110037487 | METHOD FOR DETECTING PRESSURE ON TOUCH SENSING ELEMENT AND ELECTRONIC DEVICE USING THE SAME - A method for detecting pressure on a touch sensing element includes the steps of: providing a first potential difference to two electrodes of a first film; charging a capacitor with a division voltage of the first potential difference; sampling a charged voltage of the capacitor to obtain a plurality of first voltage values and calculating a first voltage variation according to the plurality of first voltage values; comparing the first voltage variation with a threshold value; and post-processing at least one of the first voltage values when the first voltage variation is smaller than the threshold value. The present disclosure further provides an electronic device. | 2011-02-17 |
20110037488 | FLEXURAL MECHANISM FOR PASSIVE ANGLE ALIGNMENT AND LOCKING - A passive alignment structure is provided that includes at least one rigid post being coupled to a top surface and a bottom surface. At least one in-plane clamp is associated with a respective at least one rigid post. The at least one in-plane clamp receives a clamping force to lock the respective at least one rigid post. A plurality of pins allows the top surface to align to the bottom surface. | 2011-02-17 |
20110037489 | SILICON CHICKLET PEDESTAL - A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another. | 2011-02-17 |
20110037490 | Dielectric Film and Layer Testing - A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line. | 2011-02-17 |
20110037491 | Circuit Board Having Bypass Pad - An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. | 2011-02-17 |
20110037492 | WAFER PROBE TEST AND INSPECTION SYSTEM - An apparatus for electrically testing a semiconductor device is herein disclosed. The apparatus includes carriers for a semiconductor device and a probe card ( | 2011-02-17 |
20110037493 | PROBE-ABLE VOLTAGE CONTRAST TEST STRUCTURES - Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices. | 2011-02-17 |
20110037494 | Method for Wafer-Level Testing of Integrated Circuits - A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal. | 2011-02-17 |
20110037495 | METHOD FOR FAULT DETECTION IN CONTROLLING A ROTARY FIELD MOTOR - The invention specifies a method for fault identification when driving a polyphase motor by means of a frequency converter, wherein, in a rest state, the frequency converter controls the phase voltages of the polyphase motor and the phase currents of the polyphase motor are measured. In this case, provision is made for, then in the rest state, the phase currents or current variables derived therefrom to be adjusted by closed-loop control to a predetermined setpoint current variable, for the frequency converter to be controlled so as to output an interference voltage variable for the phase voltages, for the response of the adjustment by closed-loop control to the interference voltage variable to be observed, and for a conclusion to be drawn regarding a fault of the frequency converter and/or the phases of the polyphase motor from the response of the closed-loop control. The cited method allows for largely loss-free detection of faults in the drive system of a polyphase motor. In the event of field-oriented closed-loop control, no additional complexity is required in the measuring device. | 2011-02-17 |
20110037496 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND IMPEDANCE ADJUSTMENT METHOD - It is desired to reduce the current consumption of an autonomous impedance adjustment circuit. The semiconductor integrated circuit according to the present invention stops the change in the drive capability of a driver correspondingly to the output (count data) of a comparator which is sequentially outputted for changing the drive capability of a replica driver and an output driver. | 2011-02-17 |
20110037497 | Method for Fabrication of a Semiconductor Device and Structure - A novel method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the antifuse. | 2011-02-17 |
20110037498 | VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS - In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. | 2011-02-17 |
20110037499 | COMPARATOR FOR TECHNOLOGIES WITH TRANSIENT VARIATIONS OF TRANSISTOR PARAMETERS - This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters. | 2011-02-17 |
20110037500 | INTEGRATED CIRCUIT COMPARATOR OR AMPLIFIER - An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit. | 2011-02-17 |
20110037501 | High agility frequency synthesizer phase-locked loop - A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved. | 2011-02-17 |
20110037502 | DIGITAL HIGH-FREQUENCY GENERATOR CIRCUIT - A high-frequency generator circuit comprises a signal generating circuit, a delay unit, a selector, a synthesizer circuit, and a controller. The signal generating circuit generates a signal having the same frequency as an output signal. The delay unit includes a plurality of delay circuits, and delays the signal generated by the signal generating circuit. The selector selects an output signal of the delay circuits. The synthesizer circuit synthesizes the signal selected by the selector, and outputs the output signal. The controller controls the selector based on data for setting a waveform of the output signal and a control signal for setting at least amplitude, phase and frequency of the output signal. | 2011-02-17 |
20110037503 | Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof - A method for increasing responding speed and lifespan of a buffer includes detecting an edge of an input signal of the buffer, triggering a pulse signal with a predetermined period according to the detected edge, and driving the buffer for generating an output signal according to the pulse signal and the input signal. | 2011-02-17 |
20110037504 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables. | 2011-02-17 |
20110037505 | TRANSCEIVER AND OPERATING METHOD THEREOF - A semiconductor chip area is reduced and the possibility of malfunction in generation of reproduction data and a reproduction clock is reduced. A transceiver comprises a clock data recovery circuit, a deserializer, a serializer, a PLL circuit, and a frequency detector. The clock data recovery circuit extracts a reproduction clock and reproduction data in response to a receive signal and a clock signal generated by the PLL circuit. The deserializer generates parallel receive data from the reproduction clock and the reproduction data, and the serializer generates a serial transmit signal from parallel transmit data and the clock signal. The detector detects a difference in frequency of the receive signal and the clock signal, and generates a frequency control signal. In response to the frequency control signal, the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency. | 2011-02-17 |
20110037506 | DC OFFSET CALIBRATION FOR COMPLEX FILTERS - Exemplary techniques for DC offset calibration for complex filters are disclosed. A complex filter is provided having a first calibration path circuit and a second calibration path circuit, each including a first and a second set of switches, respectively. The first set of switches is enabled during calibration mode and the second set of switches is enabled during normal operation mode such that the network characteristics of each calibration path circuit are substantially the same during both modes of operation. In one embodiment, the complex filter is a low pass filter. | 2011-02-17 |
20110037507 | MIXER WITH DIFFERENTIAL DC OFFSET CANCELLATION FUNCTION - A mixer with a differential DC offset cancellation function includes: a load unit including a first load unit and a second load unit; a mixing unit biased by current transferred from the load unit to mix inputs signal and oscillation signals; a first output voltage detection unit detecting an output voltage of the first output terminal; a second output voltage detection unit detecting an output voltage of the second output terminal; a first injection/extraction circuit unit injecting current into the first load unit or extracting current from the first load unit according to the size of a first detection voltage; a second injection/extraction circuit unit injecting current into the second load unit or extracting current from the second load unit according to the size of a second detection voltage; and a current regulation unit regulating an overall current flowing across the first and second injection/extraction circuit units. | 2011-02-17 |
20110037508 | REGISTERS WITH REDUCED VOLTAGE CLOCKS - A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level. | 2011-02-17 |
20110037509 | APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT - An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element. | 2011-02-17 |
20110037510 | MIXER CIRCUIT - In a mixer circuit, addition of analog signals by capacitive coupling is used and square-law characteristics of the drain current of a MOS transistor operating in a saturated region are used. With this configuration, the voltage and power of the mixer circuit can be reduced. | 2011-02-17 |
20110037511 | MULTIPLE SIGNAL SWITCHING CIRCUIT, CURRENT SWITCHING CELL CIRCUIT, LATCH CIRCUIT, CURRENT STEERING TYPE DAC, SEMICONDUCTOR INTEGRATED CIRCUIT, VIDEO DEVICE, AND COMMUNICATION DEVICE - In a multiple signal switching circuit using four input signals IN | 2011-02-17 |
20110037512 | DEVICE AND METHOD FOR MANIPULATING DIRECTION OF MOTION OF CURRENT CARRIERS - A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current carriers: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity. The device may also be configured and operable to allow emission of the current carriers from a diffusive region at one side of the region of inhomogeneity to a ballistic region at the opposite side of the region of inhomogeneity to provide the current carriers propagation in multiple directions in the ballistic region with a wide angular range of these directions. | 2011-02-17 |
20110037513 | Controlling Bias Current for an Analog to Digital Converter - A converter includes an analog to digital converter having a bias current input, a control input, and an analog input to provide a digital output as a function of the analog input. A bias module is coupled to the bias current input to provide bias current to the analog to digital converter. A controller is coupled to the bias module and to the control input of the analog to digital converter. The controller controls the analog to digital converter to sample an analog input and controls the bias module to provide an operating bias current during sampling of the analog input and an idle bias current when not sampling the analog input. | 2011-02-17 |
20110037514 | Method for the Elimination of Ringing of Power Line Interference Filter - The present invention discloses a method for the removal of power line interference (PLI) to the signal parts of which are abrupt. First, to the non-abrupt part of the original input signal, we pass it to the notch filter, and get the output as the system output. Then, to the abrupt part, we subtract previous output from the original input signal; and add a straight line, connecting the starting and end of previous output, to the result of the subtraction to get the input of the notch filter. After processing of the notch filter, we add previous output to current output of the notch filter; and subtract the straight line as before from the sum to get the output of this step. We repeat this processing several times. During the detection of electrocardiogram (ECG), 50/60 Hz power line interference conceals the subtle changes in the original ECG, which affects the diagnosis. When the linear time-invariant (LTI) notch filter is used to the suppression of PLI, it usually causes ringing after the QRS complex, which affects the measurement of the Ventricular Late Potential and so on. The present invention uses the starting and end points of the QRS complex to process the input and output signal of the notch filter, so it is able to suppress PLI as well as to avoid the generation of the ringing. | 2011-02-17 |
20110037515 | Op-R, a solid state filter - The device described herein proposes an electronic active filter void of capacitors and inductors. The circuit utilizes only operational amplifiers (OP-Amp) and resistors, hence the name Op-R. Although capable of being constructed of lumped circuit elements this filter is intended for integrated circuit (IC) applications. Filtering of signals can be accommodated from dc through the UHF frequency range depending on the selected op-amp ICs. Low pass, band pass, high pass, as well as band reject frequency responses are achievable. Although the circuits described herein are single input-single output, multiple inputs and outputs present no difficulty, being limited only chip space. Temperature and production spread variations are also considered within the realm of tunability. | 2011-02-17 |
20110037516 | MULTI-STAGE IMPEDANCE MATCHING - Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches. | 2011-02-17 |
20110037517 | Concept, method and apparatus of improved distortion switched-mode amplifier - Systems and methods for switched-mode amplifiers having improved harmonic distortion are disclosed. High order in-band filtering is enabled without undue trade-off of distortion due to intermodulation/aliasing. A pre-modulation block is introduced, deployed between a loop filter block and a pulse-width modulation block, performing uniform pulse-width modulation. The pre-modulation block attenuates/removes amplitude dependent high frequency ripples before pulse-width modulation. The pre-modulation block in conjunction with the pulse-width modulation block performs double sampling of the input signals. | 2011-02-17 |
20110037518 | AMPLIFIERS WITH IMPROVED LINEARITY AND NOISE PERFORMANCE - Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor receives an input signal and provides an amplified signal. The second transistor receives the amplified signal and provides signal drive for an output signal. The third transistor receives the input signal and provides an intermediate signal. The fourth transistor provides bias for the third transistor in a high linearity mode. The fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor generates distortion component used to cancel distortion component from the first transistor. | 2011-02-17 |
20110037519 | AMPLIFIER WITH VARIABLE MATCHING CIRCUIT TO IMPROVE LINEARITY - Techniques for reducing distortion and improving linearity of amplifiers are described. In an exemplary design, an apparatus includes a driver amplifier, a variable matching circuit, and a power amplifier. The driver amplifier amplifies a first RF signal and provides a second RF signal. The variable matching circuit receives the second RF signal and provides a third RF signal. The power amplifier amplifies the third RF signal and provides a fourth RF signal. The variable matching circuit matches a fixed impedance at the output of the driver amplifier to a variable impedance at the input of the power amplifier in order to improve the linearity of the amplifiers. In an exemplary design, the power amplifier includes a first transistor (e.g., an NMOS transistor) of a first type, and the variable matching circuit includes a second transistor (e.g., a PMOS transistor) of a second type that is different from the first type. | 2011-02-17 |
20110037520 | MULTISTAGE AMPLIFYING CIRCUIT - A multistage amplifying circuit includes a first amplifying circuit that either samples a first analog voltage input or amplifies a difference between the first analog voltage and a first digital voltage converted from the first analog voltage, in response to a control signal. A second amplifying circuit either samples a second analog voltage input or amplifies a difference between the second analog voltage and a second digital voltage converted from the second analog voltage, in response to the control signal. A common amplifier receives output voltages of the first amplifying circuit and the second amplifying circuit and either resets the output voltage of the first amplifying circuit and determines an output voltage by using the second amplifying circuit, or resets the output voltage of the second amplifying circuit and determines an output voltage by using the first amplifying circuit, in response to the control signal. | 2011-02-17 |
20110037521 | POWER AMPLIFIER HAVING DEPLETION MODE HIGH ELECTRON MOBILITY TRANSISTOR - Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor. | 2011-02-17 |
20110037522 | ACTIVE BALUN WITH STACKED STRUCTURE - An active balun with a stacked structure includes: a first amplification unit including a first transistor having a first terminal connected with a first input terminal, a second terminal connected with a power voltage terminal, and a third terminal connected with an output terminal; a second amplification unit including a second transistor having a first terminal connected with a second input terminal, a second terminal connected with the output terminal, and a third terminal connected with a ground; and a capacitance matching unit connected between the first terminal and the third terminal of the first transistor and having a pre-set matching capacitance. | 2011-02-17 |
20110037523 | CHARGE PUMP LINEARIZATION FOR DELTA-SIGMA FRACTIONAL-N PHASE LOCKED LOOPS - A method and apparatus for linearizing a phase locked loop (PLL) are provided. To accomplish this, three separate signal (two feedback/one reference or two reference/one feedback) are applied to two phase/frequency detectors (PFDs). Either an edge of the one reference signal or one feedback signal is approximately equidistant between corresponding edges of the two feedback or two reference signals so that the PFDs can properly apply actuation signals to a charge pump that account for jitter. Thus, a more linear PLL is provided. | 2011-02-17 |
20110037524 | OSCILLATOR AMPLIFIER WITH INPUT CLOCK DETECTION AND METHOD THEREFOR - An oscillator circuit has a crystal oscillator amplifier having only two clock input terminals, one being an input terminal and the other being an output terminal. The input terminal allows a user of the integrated circuit to choose between connecting a first clock signal generated from a crystal or a second clock signal generated by a non-crystal source to the input terminal. Control circuitry has a capacitor coupled in parallel with a transistor. Both are coupled in series with a resistive device at an output of the control circuitry to provide a control signal. Clock generation circuitry coupled to the crystal oscillator amplifier provides an oscillating output signal in response to an enable signal. In one form a comparator circuit provides the oscillating output signal. The control signal is used to ensure that inputs to the comparator circuit repeatedly cross each other over time. | 2011-02-17 |
20110037525 | CRYSTAL OSCILLATOR - This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal. | 2011-02-17 |
20110037526 | OSCILLATOR - There is provided an oscillator using a high-frequency crystal resonator which can satisfy the drive level needed for the crystal resonator and expand a variable frequency range. An oscillator having an oscillation circuit CC for oscillating the resonator SS is provided with a limiter circuit LM | 2011-02-17 |
20110037527 | FAST START-UP CRYSTAL OSCILLATOR - An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations. | 2011-02-17 |
20110037528 | Wave Guiding Structures for Crosstalk Reduction - Various apparatus and methods of addressing crosstalk in a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first layer of a circuit board with a first signal trace and forming a second layer of the circuit board with a second signal trace. A first guard trace is formed on the first layer and offset laterally from the first signal trace but at least partially overlapping the second signal trace and a second guard trace is formed on the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace. | 2011-02-17 |
20110037529 | NON-RECIPROCAL CIRCUIT AND NON-RECIPROCAL CIRCUIT DEVICE, AND CENTRAL CONDUCTOR ASSEMBLY USED THEREIN - A central conductor assembly for use in a non-reciprocal circuit comprising a first inductance element between a first input/output port and a second input/output port, and a second inductance element between the second input/output port and a ground port, a magnetic substrate being integrally provided with a first central conductor constituting the first inductance element and a second central conductor constituting the second inductance element; and the second central conductor being crossing the first central conductor on a main surface side of the substrate via a magnetic layer or a dielectric layer, with at least one end portion thereof bent such that high-frequency current flows therethrough in the same direction as or in an opposite direction to that of high-frequency current flowing through the first central conductor. | 2011-02-17 |
20110037530 | STRIPLINE TO WAVEGUIDE PERPENDICULAR TRANSITION - A stripline to waveguide transition is provided that includes a shielded stripline having a transmission line in a dielectric, between two ground planes. The transition includes a stripline patch electrically coupled to the transmission line within an opening of the first ground plane and a stripline impedance matching transformer. The transition further includes a waveguide comprising a waveguide wall defining a waveguide opening. The waveguide is arranged substantially perpendicular to the patch, and the waveguide opening is aligned with an opening in the first ground plane. The electric field of the stripline transitions to a transverse electric propagation in the waveguide. The transition may be integrated with a transceiver and antenna. | 2011-02-17 |