07th week of 2019 patent applcation highlights part 66 |
Patent application number | Title | Published |
20190052213 | Regenerative energy system for ground transportation vehicles - Present example embodiments relate generally to a ground transportation system for interacting with one or more vehicles, the vehicle comprising at least one magnetic element fixedly attached to the vehicle, each magnetic element operable to generate a magnetic field having a first magnitude and a first direction, the system comprising a magnetic coil assembly fixedly positioned near an area traversable by the vehicle and comprising a core and a magnetic wire coil wrapped around the core, the magnetic coil assembly operable to generate a magnetic field having a second magnitude and a second direction; and an energy storage unit operable to release energy to and store energy from the magnetic coil assembly. | 2019-02-14 |
20190052214 | Motor Control System - The invention is directed to omit an adjustment work of a motor control system and increase versatility. Provided is a motor control system including: an inverter which outputs a voltage to a motor based on a voltage command; a current detecting unit which outputs a current detection value based on a current flowing through the motor of a state quantity detecting unit; a voltage command calculating unit which outputs the voltage command of the state quantity detecting unit based on the high-order command and the current detection value of the state quantity detecting unit; a storage unit which outputs a data set of the quantity of state of the state quantity detecting unit based on the quantity of state of a driving target of the motor of the state quantity detecting unit; an abnormality degree calculation equation updating unit which outputs an abnormality degree calculation equation for computing the abnormality degree of the driving target of the state quantity detecting unit based on the data set of the state quantity detecting unit; an abnormality degree calculating unit which outputs the abnormality degree based on the quantity of state of the state quantity detecting unit and the abnormality degree calculation equation of the state quantity detecting unit; and a voltage adjusting unit which outputs an adjustment voltage for adjusting the voltage command of the state quantity detecting unit based on the abnormality degree of the state quantity detecting unit. | 2019-02-14 |
20190052215 | CONTROL SYSTEM FOR A THREE-PHASE AC MOTOR - A method for controlling a three-phase AC motor, wherein the three-phase AC motor has a rotatably mounted rotor and a stator including a first group of coils and a second group of coils. Each of the coils generates an oscillating magnetic field upon actuation using an alternating current. The phases of the alternating currents are selected such that the superposition of the magnetic fields of the first group of coils generates a magnetic rotating field that rotates with a direction of rotation and the superposition of the magnetic fields of the second group of coils generates a magnetic rotating field that rotates counter to the direction of rotation. A system composed of a three-phase AC motor and an inverter for carrying out the control method is also described. | 2019-02-14 |
20190052216 | MOTOR CONTROL DEVICE AND MACHINE TOOL SYSTEM FOR CONTROLLING MOTOR IN ACCORDANCE WITH AMOUNT OF DROP IN POWER SUPPLY VOLTAGE - A motor control device includes a rectifier which converts AC power into DC power and outputs it to a DC link, an inverter which converts the DC power of the DC link into AC power for each motor and outputs it, an AC voltage detection unit which detects an AC voltage value on the AC input side of the rectifier, a state determination unit which determines that a voltage dropped state has been set when the AC voltage value is smaller than a certain specified voltage and that a normal state has been set when the AC voltage value is equal to or larger than the specified voltage, and an output control unit which controls each motor in accordance with the amount of voltage drop with respect to the specified voltage of the AC voltage value when the state determination unit determines that the voltage dropped state has been set. | 2019-02-14 |
20190052217 | THREE-PHASE MOTOR CONTROL CIRCUIT AND THREE-PHASE MOTOR CONTROL METHOD - The present disclosure relates to a three-phase motor control circuit including an inverter circuit configured to convert input power into three-phase power, a relay switch configured to determine whether the three-phase power is input to a three-phase motor on the basis of a control signal of an operational level, an operation circuit configured to calculate the three-phase power and the input power to generate the operational level, and an amplification circuit configured to amplify a control signal of an initial level, which is generated by a controller for operating the relay switch, to be a control signal of the operational level on the basis of the generated operational level. | 2019-02-14 |
20190052218 | Motor Driving Device - Disclosed is a motor driving device for driving a motor having coil sets that includes energization systems each including a drive circuit, the drive circuits being one-to-one connected to the coil sets; first semiconductor switches disposed in the energization systems in a one-to-one correspondence, each first semiconductor switch lying between a power supply and the corresponding one of the drive circuits; and a second semiconductor switch which connects the power supply and each of the first semiconductor switches in series. Each of the first semiconductor switches includes a parasitic diode of which a forward direction is from the corresponding drive circuit to the second semiconductor switch, and the second semiconductor switch includes a parasitic diode of which a forward direction is from the power supply to the first semiconductor switches. | 2019-02-14 |
20190052219 | MOTOR CONTROL DEVICE, BLOWING DEVICE, AND CLEANER - A motor control device of a motor includes voltage acquisition circuitry that acquires a drive voltage of the motor; rotational speed acquisition circuitry that acquires a rotational speed of the motor; setting circuitry that sets a rotational speed instruction value of the motor; calculation circuitry that calculates a rotational speed threshold value of the motor; change circuitry that changes the rotational speed instruction value; and storage circuitry that stores reference data. The reference data includes at least three types of reference value sets each including a reference drive voltage value, a reference rotational speed instruction value, and a reference rotational speed threshold value. The calculation circuitry performs a proportional calculation, a current rotational speed instruction value, and the reference value set to calculate the rotational speed threshold value. | 2019-02-14 |
20190052220 | Systems and Methods for an Identification Protocol between a Local Controller of a Solar Module and a Master Controller - Systems and methods for local and master management units in a photovoltaic energy system. In one embodiment, a method implemented in a computer system includes sending a first identification code from a local management unit to a master management unit. The first identification code is associated with the first local management unit, and the local management unit controls a solar module. An authentication of the first identification code is received from the master management unit. In response to receiving the authentication, active operation of the local management unit is continued (e.g., for a set time period). | 2019-02-14 |
20190052221 | RAIL-LESS ROOF MOUNTING SYSTEM - A roof mounting system for the attachment of an article to a roof, the system comprising a plurality of PV modules each having at least one corner and a frame member, a flashing member having a top surface; an upstanding sleeve attached to the top surface of the flashing member; an elevated water seal having a borehole formed therethrough, the elevated water seal further comprising at least one screw for providing a waterproof seal between the article and the roof structure; and whereby the plurality of PV modules are interlocked in a way to provide a corner-to-corner coupling arrangement supported above the roof through the frame members of the plurality of PV modules. | 2019-02-14 |
20190052222 | RAIL-LESS ROOF MOUNTING SYSTEM - A roof mounting system for the attachment of an article to a roof, the system comprising a plurality of PV modules each having at least one corner and a frame member, a flashing member having a top surface; an upstanding sleeve attached to the top surface of the flashing member; an elevated water seal having a borehole formed therethrough, the elevated water seal further comprising at least one screw for providing a waterproof seal between the article and the roof structure; and whereby the plurality of PV modules are interlocked in a way to provide a corner-to-corner coupling arrangement supported above the roof through the frame members of the plurality of PV modules. | 2019-02-14 |
20190052223 | IN-PLANE ROTATION SUN-TRACKING FOR CONCENTRATED PHOTOVOLTAIC PANEL - A method for controlling a two-dimensional array of photovoltaic cells having a plurality of rows, each row having a pivot axis parallel to the row. Each cell has a lens which has a front surface configured to concentrate light normal to the front surface onto the photovoltaic element. The photovoltaic array further includes a rotational actuator, coupled to the array of photovoltaic cells configured to rotate the array of photovoltaic cells about an axis perpendicular to a plane defined by the array of photovoltaic elements and a tilt actuator, coupled to each of the rows of photovoltaic elements configured to pivot the rows of photovoltaic elements about their pivot axes. The method includes rotating the array of photovoltaic cells about an axis perpendicular to a plane defined by the array of photovoltaic elements, and tilting the rows of photovoltaic elements to pivot about their pivot axes. | 2019-02-14 |
20190052224 | SOLAR PANEL SUPPORT AND DRIVE SYSTEM - A solar panel support apparatus comprising: a support frame for holding the solar panel; a support post pivotally connected to the support frame at a post pivot connection and anchored to an adjacent supporting surface, the support post for positioning the support frame above the supporting surface; and a linear actuator coupled at a proximal end to the support post by a support pivot connection and at a distal end by a frame pivot connection with the support frame, the post pivot connection and the frame pivot connection spaced apart from one another on the support frame; wherein a change in a length of the linear actuator results in pivoting of the support frame about the post pivot connection. | 2019-02-14 |
20190052225 | INTELLIGENT SOLAR CELL CARRIER SYSTEM FOR FLIGHT AND LABORATORY MEASUREMENT APPLICATIONS - An apparatus for carrying, retrieving, and characterizing temperature and current-voltage properties of a solar cell may include a metal core printed circuit board (PCB). The metal core PCB includes current-voltage and temperature measurement electronics operated by a remote device via a communication unit. The solar cell is embedded onto the metal core PCB by way of a thermally- and electrically-conducting adhesive material. The current-voltage and temperature electronics and the solar cell are thermally connected to the PCB, and are electrically isolated from each other, while residing on the same plane. | 2019-02-14 |
20190052226 | METHOD AND APPARATUS FOR DETERMINING A CLOCK FREQUENCY FOR AN ELECTRONIC PROCESSOR - Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency. | 2019-02-14 |
20190052227 | METHOD FOR THE FREQUENCY CORRECTION OF AN OSCILLATOR OF A SENSOR NODE OF A WIRELESS SENSOR NETWORK - The invention relates to a method for the frequency error correction of an oscillator of a sensor node in a sensor network, comprising the following steps: receiving a transmission signal of a transmitter, the signal being modulated by orthogonal frequency division multiplexing (OFDM); determining the frequency deviation of the oscillator using the received transmission signal; determining a correction signal for correcting the frequency deviation of the oscillator and correcting the frequency of the oscillator by means of the correction signal. | 2019-02-14 |
20190052228 | Rail-To-Rail Source Follower - A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level. | 2019-02-14 |
20190052229 | SIGNAL PROCESSING SYSTEM AND METHOD THEREOF - A signal processing system and method is disclosed, applicable to environment providing voltage to Class-H driver. When using the signal processing system, the first is to detect the volume change of inputted voice and use the detection result as a power source to generate an expectation value for the circuit; the input end of the power generation circuit also adds a voltage offset in addition to the expectation value, so that the output voltage from the output end of the power generator provided to the Class-H driver is higher than a fixed value. The signal processing system and method of the present invention can adjust automatically and rapidly the output voltage signal for the power voltage provided to the Class-H driver by using negative feedback controller (such as, negative feedback loop, voltage offset and proportional integral differential (PID)) based on the detected volume change of inputted voice. | 2019-02-14 |
20190052230 | DIFFERENTIAL AMPLIFIER CIRCUIT - A differential amplifier circuit includes a differential pair including a first field-effect transistor (FET) and a second FET, a first current source that generates a current which flows in the first FET and the second FET, and an output circuit that outputs an output voltage corresponding to a difference between a gate voltage of the first FET and a gate voltage of the second FET in accordance with an operation of the differential pair. A back gate of the first FET is connected to a gate of the first FET, and a back gate of the second FET is connected to a gate of the second FET. A first feedback voltage corresponding to the output voltage is input to the gate of the second FET. | 2019-02-14 |
20190052231 | DIFFERENTIAL CIRCUIT - A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor. | 2019-02-14 |
20190052232 | POWER MANAGEMENT CIRCUIT AND RELATED RADIO FREQUENCY FRONT-END CIRCUIT - A power management circuit and related radio frequency (RF) front-end circuit are provided. In examples discussed herein, a power management circuit can be incorporated into an RF front-end circuit to support RF beamforming in millimeter wave spectrum(s). In this regard, the power management circuit is configured to generate multiple output voltages to drive multiple power amplifier subarrays in the RF front-end circuit. More specifically, the power management circuit is configured to generate the output voltages based on a voltage scaling factor(s) such that each of the output voltages corresponds proportionally to a battery voltage received by the power management circuit. As such, the output voltages can be dynamically controlled based on the voltage scaling factor(s) to maximize operating efficiency of the power amplifier subarrays. As a result, it is possible to reduce heat dissipation of the power amplifier subarrays and improve overall thermal performance of the RF front-end circuit. | 2019-02-14 |
20190052233 | POWER AMPLIFICATION MODULE - A power amplification module includes: a first bipolar transistor in which a radio frequency signal is input to a base and an amplified signal is output from a collector; a second bipolar transistor that is thermally coupled with the first bipolar transistor and that imitates operation of the first bipolar transistor; a third bipolar transistor in which a first control voltage is supplied to a base and a first bias current is output from an emitter; a first resistor that generates a third control voltage corresponding to a collector current of the second bipolar transistor at a second terminal; and a fourth bipolar transistor in which a power supply voltage is supplied to a collector, the third control voltage is supplied to a base, and a second bias current is output from an emitter. | 2019-02-14 |
20190052234 | METHODS AND APPARATUSES FOR DIGITAL PRE-DISTORTION - A method is provided. The method, comprises: power amplifying, with at least two parallel power amplifiers, at least two pre-distorted signals each corresponding to a unique transmit band, wherein each power amplifier operates in a unique transmit band; and pre-distorting, with a single pre-distortion system, at least two signals in different transmit bands, where the pre-distortion of each of the at least two signals is based upon a portion of a corresponding power amplified, pre-distorted signal, and where the pre-distortion diminishes certain IMD products in the corresponding power amplified, pre-distorted signal. | 2019-02-14 |
20190052235 | MULTI-PATH COMMUNICATION DEVICE FOR SHARING FEEDBACK PATH FOR DIGITAL PRE-DISTORTION - The present invention, which relates to a multi-path communication device for sharing a feedback path for digital pre-distortion, includes: a DPD processing unit configured to output a plurality of pre-distorted signals by respectively pre-distorting a plurality of input signals, to output an n | 2019-02-14 |
20190052236 | VARIABLE GAIN CIRCUIT AND TRANSIMPEDANCE AMPLIFIER USING THE SAME - A transimpedance amplifier includes a variable gain circuit configured to generate a pair of complementary signals in accordance with an input signal and a reference signal. A first differential circuit of the variable gain circuit includes a first transistor including a control terminal to receive the input signal, a second transistor including a control terminal to receive the reference signal, and a variable resistance circuit including a first field effect transistor (FET) and a second FET. A first timing when a voltage of a first linearity adjustment signal input to the first FET reaches a first threshold voltage of the first FET and a second timing when a voltage of a second linearity adjustment signal input to the second FET reaches a second threshold voltage of the second FET are different from each other. | 2019-02-14 |
20190052237 | AMPLIFIER CIRCUIT AND METHOD - The present invention provides an amplifier circuit for amplifying an incoming signal, the amplifier circuit comprising at least two signal paths configured to amplify signals of different overlapping frequency bands, a signal splitter comprising an input port configured to receive the incoming signal, the signal splitter being coupled to an input side of the signal paths and configured to split the incoming signal into split signals for the signal paths, and a diplexer coupled to an output side of the signal paths and configured to combine the amplified signals and provide a combined amplified signal. Further, the present invention provides a respective method. | 2019-02-14 |
20190052238 | CIRCUIT MODULE HAVING DUAL-MODE WIDEBAND POWER AMPLIFIER ARCHITECTURE - A circuit module includes a power amplifier, a switch, and a bypass capacitor. The power amplifier has a signal input node coupled to an input signal, a signal output node to generate an output signal, and a power input node coupled to a supply output signal of a supply modulator. The switch is coupled between the power input node of the power amplifier and the bypass capacitor. The bypass capacitor is an equivalently removable bypass capacitor coupled between the switch and a ground level. | 2019-02-14 |
20190052239 | DIFFERENTIAL CIRCUIT AND OPERATIONAL AMPLIFIER - A differential circuit including: a first MOS transistor and a second MOS transistor that constitute a differential pair; a determination unit to determine a level of a determination target signal that is based on at least one of differential inputs being input to gate of the first MOS transistor and a gate of the second MOS transistor; and a voltage changing unit to change a back gate voltage that is supplied to both back gates of the first MOS transistor and the second MOS transistor according to a determination result of the determination unit, and an OP-amp will be provided. | 2019-02-14 |
20190052240 | METHOD FOR AMPLIFYING AUDIO SIGNAL BASED ON ITS AMPLITUDE AND ELECTRONIC DEVICE SUPPORTING THE SAME - An electronic device includes a processor. The processor is configured to examine the sound level of an audio signal obtained from an external object for a preset time; change, if the frequency with which the sound level becomes higher than or equal to a specified level satisfies a preset condition, a reference level, at which the gain value for audio signal amplification is changed in accordance with the amplitude change of the audio signal, for at least one section of the audio signal satisfying the preset condition; and amplify the at least one section of the audio signal according to the changed reference level. | 2019-02-14 |
20190052241 | HIGH-FREQUENCY MODULE AND COMMUNICATION APPARATUS - A high-frequency module includes a plurality of filters, a switch that commonly connects a plurality of paths, and a low noise amplifier that amplifies a high-frequency signal input from the plurality of filters with the switch interposed therebetween, wherein paths in which first and second filters are respectively provided among the plurality of paths connect the respective filters and the switch without connecting impedance elements, and each of the first and second filters has an output impedance located in a matching region between a NF matching impedance at which an NF of the low noise amplifier is minimum and a gain matching impedance at which a gain of the low noise amplifier is maximum in its respective pass band thereof on a Smith chart. | 2019-02-14 |
20190052242 | SURFACE ACOUSTIC WAVE DEVICE - A surface acoustic wave device includes a piezoelectric substrate, an IDT electrode, support layers, and a cover layer. A distance from a first end of a first partition-support layer to one of the outer-periphery-frame support layers closest to the first end is smaller than a distance from a second end of the first partition-support layer to one of the outer-periphery-frame support layers closest to the second end, and a distance from a first end of a second partition-support layer to one of the outer-periphery-frame support layers closest to the first end is larger than a distance from a second end of the second partition-support layer to one of the outer-periphery-frame support layers closest to the second end. | 2019-02-14 |
20190052243 | Multi-Function Frequency Control Device - A single frequency control device incorporating a high frequency resonator, a low frequency resonator and a temperature sensing element, the latter thermally coupled closely to the said resonators to facilitate temperature sensing with higher resolution and accuracy. Additional benefits offered by the structure include smaller size and lower cost. | 2019-02-14 |
20190052244 | ELASTIC WAVE DEVICE, RADIO-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE - An elastic wave device includes a first filter including an elastic wave resonator and a second filter connected to an antenna common terminal via a common node. When a first pass band of the first filter and second pass bands of the second filters are F | 2019-02-14 |
20190052245 | QUARTZ CRYSTAL DEVICE - A quartz crystal device includes a crystal element, a container, a conductive adhesive having flexibility, first pillow portions, and a second pillow portion. The first pillow portions hold the crystal element floated from an inner bottom surface of the container at the proximities of the two positions. The second pillow portion opposes the crystal element at a proximity of a second side. The second side opposes the first side of the crystal element. A height of the first pillow portion is represented as h and a length of the first pillow portion in a direction perpendicular to the first side is represented as X | 2019-02-14 |
20190052246 | RESONATOR AND RESONANCE DEVICE - The resonator includes a vibrating portion that has three or more vibrating arms each having a fixed end and an open end and at least two vibrating arms undergoing out-of-plane bending in different phases. Moreover, the resonator includes a first base portion having a first front end connected to the fixed ends and a first rear end facing the first front end, a second base portion having a second front end facing the first rear end and a second rear end facing the second front end, and a connecting portion connected between a vicinity of a center of the first rear end and a vicinity of a center of the second front end, a holding portion that is provided in at least a part of a periphery of the vibrating portion, and a holding arm that is provided between the vibrating portion and the holding portion. | 2019-02-14 |
20190052247 | UNRELEASED PLANE ACOUSTIC WAVE RESONATORS - Unreleased plane acoustic wave (PAW) resonators are disclosed. An example unreleased PAW resonator includes a substrate, a first acoustic reflector disposed on the substrate, and a piezoelectric layer disposed on the first acoustic reflector, wherein the first acoustic reflector and the piezoelectric layer are unreleased from the substrate. | 2019-02-14 |
20190052248 | MULTIPLEXER, TRANSMISSION APPARATUS, AND RECEPTION APPARATUS - A multiplexer includes filters and a common terminal connected to an antenna element by a connection path, a first inductance element being connected between the connection path and a reference terminal. A terminal closer to the antenna element among an input terminal and an output terminal of one filter among the filters is connected to a parallel resonator and is connected to the common terminal with a second inductance element interposed therebetween. A terminal closer to the antenna element among an input terminal and an output terminal of each of other filters other than the one filter among the filters is connected to the common terminal and a series resonator. | 2019-02-14 |
20190052249 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal. | 2019-02-14 |
20190052250 | SEMICONDUCTOR DEVICE - To provide an asynchronous circuit capable of power gating, a semiconductor device is configured with first to third terminals, a latch circuit, and a memory circuit. The third terminal outputs “false” when “false” is input to the first terminal and the second terminal. The third terminal outputs “true” when “true” is input to the first terminal and the second terminal. The third terminal outputs a truth value that is the same as the previous output, when “true” is input to one of the first terminal and the second terminal and “false” is input to the other of the first terminal and the second terminal. The memory circuit is capable of storing data stored in the latch circuit, while supply of a power supply voltage is stopped. The memory circuit includes a transistor that contains a metal oxide in a channel formation region. | 2019-02-14 |
20190052251 | APPARATUS AND METHOD FOR SIGNAL PROCESSING BY CONVERTING AMPLIFIED DIFFERENCE SIGNAL - A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal. | 2019-02-14 |
20190052252 | PULSE SHIFT CIRCUIT AND FREQUENCY SYNTHESIZER - A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal. | 2019-02-14 |
20190052253 | HIGH-SPEED PHASE INTERPOLATOR - The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well. | 2019-02-14 |
20190052254 | SUPPLY TRACKING DELAY ELEMENT IN MULTIPLE POWER DOMAIN DESIGNS - An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current. | 2019-02-14 |
20190052255 | SEMI-CONTROLLABLE DEVICE DRIVING METHOD AND APPARATUS, AND HYBRID DEVICE - A semi-controllable device driving method and apparatus and a hybrid device of the present disclosure belong to the electrical field, and are particularly a driving method, with no driving dead zone or with an extremely small driving dead zone, that is applicable to a semi-controllable device such as a thyristor; a semi-controllable driving apparatus, with no conduction dead zone or with an extremely small conduction dead zone, that is applicable to a driving loop of a semi-controllable device such as a thyristor; and a hybrid device with no conduction dead zone or with an extremely small conduction dead zone. In the semi-controllable device driving method, a voltage detection switch is used; an input end of the voltage detection switch is connected to two ends of a semi-controllable device that needs to be driven; the voltage detection switch is connected, in series, in a driving loop of the semi-controllable device; the voltage detection switch is turned on when a potential difference at the two ends of the semi-controllable device is not greater than an on-state voltage of the semi-controllable device; and the voltage detection switch is turned off after detecting that the semi-controllable device is turned on. The present disclosure has an advantage of no driving dead zone or an extremely small driving dead zone. | 2019-02-14 |
20190052256 | Radio Frequency Switch with Low Oxide Stress - A RF switch circuit includes a voltage divider circuit and a semiconductor device. The semiconductor device has an activated state and a deactivated state. The voltage divider circuit has an input terminal connected to a first line and an output terminal connected to a second line. The first line is connected to a power source. A gate terminal of the semiconductor device is connected to the second line. In the activated state, a source terminal and a drain terminal of the semiconductor device are each selectively connected to ground. In the deactivated state, the source terminal and the drain terminal of the semiconductor device are each selectively connected to the power source. | 2019-02-14 |
20190052257 | APPARATUS AND METHOD FOR PROTECTING MOSFET RELAY BY USING VOLTAGE DETECTOR AND SIGNAL FUSE - The present invention relates to an apparatus and a method for protecting a MOSFET relay by using a voltage detector and a signal fuse, which calculate a detection voltage value through a voltage detector from an electrically conducted current value of a MOSFET relay provided in a battery main circuit for a vehicle and pre-block current applied to the MOSFET relay by operating a signal fuse when the calculated voltage value is more than a predetermined threshold to protect the MOSFET relay from being burned. | 2019-02-14 |
20190052258 | GLITCH COMPENSATION IN ELECTRONIC CIRCUITS - A supply circuit for providing pulses of current has a current source, a reference voltage source for controlling magnitude of the current, and a current switch for controlling whether or not the current passes through a load. Also, there is a switch control signal terminal for controlling the current switch, and glitch compensation elements including at least one capacitance circuit and associated capacitor drive circuit for feeding a variable correcting voltage back to the reference voltage, and a controller to control said variable voltage. | 2019-02-14 |
20190052259 | SEMICONDUCTOR INTEGRATED CIRCUIT - In order to provide a power supply switch circuit using only low-breakdown voltage transistors and eliminate the need for a special through-current preventing circuit, the switch control circuits output a signal ranging from a ground voltage level to a second power supply voltage level when a first power supply voltage (0 V/3.3 V) is in off-state and a second power supply voltage (0 V/1.8 V) is in on-state, and a signal ranging from the second power supply voltage level to a first power supply voltage level when the first and second power supply voltages are in on-state, thereby allowing a PMOS transistor and an NMOS transistor to turn on or off. | 2019-02-14 |
20190052260 | CIRCUIT AND METHOD FOR PROVIDING AN OUTPUT SIGNAL - An output circuit including an output transistor configured to provide an output signal; and a gate switch configured to decouple a gate of the output transistor from other components of the output circuit when there is a decrease in a supply voltage of the output circuit, wherein when the gate of the output transistor is decoupled, a charge at the gate is maintained in a capacitor inherent within the gate of the output transistor. | 2019-02-14 |
20190052261 | Adaptive Body Biasing In CMOS Circuits To Extend The Input Common Mode Operating Range - In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition. | 2019-02-14 |
20190052262 | CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC - Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. | 2019-02-14 |
20190052263 | CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC - Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. | 2019-02-14 |
20190052264 | TRIAXIAL PHOTOCONDUCTIVE SWITCH MODULE - Methods, systems, and devices describe triaxial photoconductive switch modules that include a center conductor, an inner conductor, an outer conductor, a high voltage capacitor that is formed between the center conductor and the inner conductor, and a photoconductive switch that is formed between the center conductor and a section of the outer conductor. The disclosed triaxial photoconductive switch modules include low inductance current paths that lead to high current efficiencies. Furthermore, the disclosed triaxial photoconductive switch modules eliminate or reduce parasitic capacitance problems of existing systems. | 2019-02-14 |
20190052265 | TOUCH PANEL SWITCH DEVICE - A touch panel switch device includes a display panel, a touch panel placed correspondingly to the display panel, a storage part and a control part. The storage part stores switch image information according to respective operation functions, code information according to the respective operation functions and placement information for display designating placement of switch images to be displayed on the display panel. The control part is configured to make the display panel display the switch images according to the switch image information and the placement information for display, and, in accordance with a touch operation onto the touch panel, read out from the storage part the code information corresponding to the switch image displayed at a location of the touch operation, perform output control of the code information, and also perform a rewrite process of the placement information for display based on received information. | 2019-02-14 |
20190052266 | Key assembly in optical mechanical keyboard - A key assembly in an optical mechanical keyboard, comprising a base plate (10), a circuit board ( | 2019-02-14 |
20190052267 | KEY INPUT APPARATUS - A key input apparatus includes a key top capable of moving up and down through a pressing operation; a first substrate, which includes a first surface, which is positioned on the key top side, and a second surface, which is opposite to the first surface, and the first substrate supports the key top and is provided to be movable up and down along with the key top; a second substrate, which is provided between the key top and the first substrate in the direction of the up-and-down movement of the key top, and the second substrate includes a first surface, which is positioned on the first substrate side, and a second surface, which is opposite to the first surface; a magnetic field generation unit; a magnetic sensor unit, which includes a magnetic detection element that detects a magnetic field generated from the magnetic field generation unit; and an adhesion unit, which includes a soft magnetic material capable of adhering to the magnetic field generation unit. The magnetic sensor unit and the adhesion unit are provided on one of the first surface of the first substrate and the first surface of the second substrate, and the magnetic field generation unit is provided on the other of the first surface of the first substrate and the first surface of the second substrate, opposite to the adhesion unit. | 2019-02-14 |
20190052268 | MEMORY MODULES, MEMORY SYSTEMS INCLUDING THE SAME, AND METHODS OF CALIBRATING MULTI-DIE IMPEDANCE OF THE MEMORY MODULES - A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation. | 2019-02-14 |
20190052269 | ON-DIE TERMINATION CONTROL - A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs. | 2019-02-14 |
20190052270 | MAINTAINING SLEW RATE WHILE LOADING FLASH MEMORY DIES - Systems and methods for maintaining a slew rate while loading flash memory dies are described. In one embodiment, the systems and methods may include placing one or more comparator circuits connectively between one or more channel controllers and a plurality of flash memory dies and maintaining a slew rate in relation to the one or more channel controllers writing data to a plurality of flash memory dies inside the solid state drive. In some cases, a hardware controller of a solid state drive may include the one or more channel controllers. In some cases, the plurality of flash memory dies may include at least one NAND die. | 2019-02-14 |
20190052271 | METHOD FOR MULTIPLEXING BETWEEN POWER SUPPLY SIGNALS FOR VOLTAGE LIMITED CIRCUITS - In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node. | 2019-02-14 |
20190052272 | PULSE-WIDTH MODULATION (PWM) CONTROL LOOP FOR POWER APPLICATION - A method includes: receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD); looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and generating a compensated output signal using the matching pre-calculated data to drive a switch of the power regulator. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper. | 2019-02-14 |
20190052273 | PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND CHARACTERIZATION METHOD - An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell. | 2019-02-14 |
20190052274 | Programmable Logic Device Virtualization - A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time. | 2019-02-14 |
20190052275 | COMPENSATION MEMORY (CM) FOR POWER APPLICATION - A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper. | 2019-02-14 |
20190052276 | FREQUENCY COMPENSATOR, ELECTRONIC DEVICE AND FREQUENCY COMPENSATION METHOD - A frequency compensator, an electronic device, and a frequency compensation method are disclosed. The frequency compensator includes a control circuit and a frequency compensation circuit. The control circuit is configured to generate a frequency control word according to an initial frequency and an target frequency. The frequency compensation circuit is configured to receive an input signal of an initial frequency, and to generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency. | 2019-02-14 |
20190052277 | FUNCTIONAL SAFETY CLOCKING FRAMEWORK FOR REAL TIME SYSTEMS - Methods and apparatus relating to functional safety clocking framework for real time systems are described. In an embodiment, clock monitoring logic circuitry monitors a plurality of clock signals. Safety island logic circuitry receives an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals. Safety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals. Other embodiments are also disclosed and claimed. | 2019-02-14 |
20190052278 | APPARATUS AND METHOD FOR FREQUENCY CALIBRATION OF VOLTAGE CONTROLLED OSCILLATOR (VCO) INCLUDING DETERMINING VCO FREQUENCY RANGE - A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal. | 2019-02-14 |
20190052279 | CIRCUIT, APPARATUS, DIGITAL PHASE LOCKED LOOP, RECEIVER, TRANSCEIVER, MOBILE DEVICE, METHOD AND COMPUTER PROGRAM TO REDUCE NOISE IN A PHASE SIGNAL - A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude. | 2019-02-14 |
20190052280 | REFERENCE-LOCKED CLOCK GENERATOR - Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer. | 2019-02-14 |
20190052281 | JITTER REDUCTION TECHNIQUES WHEN USING DIGITAL PLLS WITH ADCS AND DACS - This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal. | 2019-02-14 |
20190052282 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED CONTROL METHOD - A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result. | 2019-02-14 |
20190052283 | DIGITAL/ANALOG CONVERTER CIRCUIT, SOURCE DRIVER, DISPLAY APPARATUS, ELECTRONIC APPARATUS, AND METHOD OF DRIVING A DIGITAL/ANALOG CONVERTER CIRCUIT - A digital/analog converter circuit includes: a decoding unit that performs decoding processing on a bit signal in a predetermined part of a digital signal; and a selector circuit that selects and outputs a voltage depending on an output of the decoding unit, in which a switching device is disposed on at least one of inside of the decoding unit and an output unit side of the decoding unit, the switching device being controlled by a control signal different from the hit signal as a target for the decoding processing. | 2019-02-14 |
20190052284 | DATA COMPRESSION APPARATUS, DATA DECOMPRESSION APPARATUS, DATA COMPRESSION PROGRAM, DATA DECOMPRESSION PROGRAM, DATA COMPRESSION METHOD, AND DATA DECOMPRESSION METHOD - An apparatus includes a processor that detects a match sequence that matches with a preceding partial sequence in input data, a relative position of the match sequence with respect to the partial sequence, and a match length which is a length of the match sequence; retains the relative position encoded lastly; selects one of a plurality of encoding formats based on closeness indicated by the relative position, the encoding formats being set such that the number of bits to be allocated to the relative position varies among the encoding formats; and encodes the input data by arranging codes in byte unit and omitting, depending on the encoding format selected, the relative position when the relative position is the same as the relative position encoded lastly and retained by the processor. | 2019-02-14 |
20190052285 | KEYBOARD APPARATUS - A keyboard apparatus including a key module and a detection circuit is provided. The key module includes a plurality of keys, a plurality of scan lines, and a plurality of return lines. The scan lines and the return lines are crossed to each other and coupled to the keys respectively. The detection circuit is coupled to the return lines and configured to detect a current flowing through each of the return lines and indicate that a switch of each of the keys is in an on state or in an off state according to a value of the current. | 2019-02-14 |
20190052286 | ERROR DETECTOR AND/OR CORRECTOR CHECKER METHOD AND APPARATUS - In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum. | 2019-02-14 |
20190052287 | METHOD OF CHANNEL CODING FOR COMMUNICATION SYSTEMS AND APPARATUS USING THE SAME - Disclosed herein are a channel coding/decoding method in which a parity check matrix is transformed and an apparatus using the same. The channel-coding method includes loading a first exponent matrix, transforming the first exponent matrix into a second exponent matrix, creating a parity check matrix corresponding to a required block size using the second exponent matrix, and performing LDPC encoding using the parity check matrix. | 2019-02-14 |
20190052288 | Low Density Parity Check Decoder - A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order. | 2019-02-14 |
20190052289 | METHOD AND DEVICE FOR TURBO DEMODULATION, ITERATIVE DEMAPPING AND ITERATIVE DECODING - The present invention concerns a method and device for demodulating received symbols using a turbo-demodulation scheme comprising an iterative de-mapping and wherein an iterative channel decoder is used in the turbo-demodulation scheme, characterized in that the iterative channel decoder performs a first iterative process named iterative decoding process, the turbo-demodulation performing a second iterative process named iterative demodulation and decoding process, at each iteration of the second iterative process, the iterative channel decoder executing plural iterations in order to decode bits from which symbols are derived from, and wherein the iterative channel decoder: memorizes at the end of the iterations of the first iterative process, the variables used internally by the iterative channel decoder, reads the memorized variables at the following iteration of the second iterative process. | 2019-02-14 |
20190052290 | Rate Matching Methods for LDPC Codes - A method of producing a set of coded bits from a set of information bits for transmission between a first node ( | 2019-02-14 |
20190052291 | METHODS FOR RE-USING FILTERS FOR UPLINK CARRIER AGGREGATION - Disclosed herein are systems, circuits, architectures and methods related to front-end architectures for wireless devices configured for uplink carrier aggregation. The disclosed methods dynamically route signals from a filter-less module to one of two modules with filters for filtering. The re-use of filters reduces the size of the filter-less module relative to a module that utilizes its own filters, thereby reducing costs, reducing size, and/or providing additional space for other modules or other functionality to be included in a wireless device. | 2019-02-14 |
20190052292 | METHOD AND ELECTRONIC DEVICE FOR DYNAMICALLY CHANGING GROUND POINTS OF A PLURALITY OF ANTENNAS OF THE ELECTRONIC DEVICE - An electronic device is provided and includes a housing, a support member including a first ground region, a printed circuit board including a second ground region, a plurality of switches electrically connecting the first ground region and the second ground region, a first antenna element including at least a portion of a first edge of the housing and electrically connected with the first ground region of the support member, a second antenna element including at least a portion of a second edge of the housing and electrically connected with the second ground region of the printed circuit board, and a wireless communication circuit configured to transmit/receive in a first frequency band based on a first electrical path, transmit/receive in a second frequency band based on a second electrical path, set ON/OF states of the plurality of switches to a first arrangement and a second arrangement, wherein at least one switch of the plurality of switches is set to an ON state in each of the first arrangement and the second arrangement. | 2019-02-14 |
20190052293 | CROSSTALK-CORRECTION IN DIGITIZERS USING COUPLING COEFFICIENTS - In a system, known digitizer signals (known analog signals or digital representations of known analog signals) are generated. The known digitizer signals are input into digitizers (analog-to-digital converter (ADCs) or digital-to-analog converter (DACs)) to output generated digitizer signals (generated digital representations or generated analog signals). The generated digitizer signals are analyzed in relation to the known digitizer signals to generate coupling coefficients, which can be either scalar quantities or finite-impulse-response (FIR) filter functions. Subsequent digitizer signals are generated. The subsequent digitizer signals are modified using the coupling coefficients to generate modified digitizer signals according to formulae. The modified digitizer signals are used directly as digital representations, or are input to the DACs to output modified analog signals that substantially match subsequent analog signals. | 2019-02-14 |
20190052294 | METHOD AND APPARATUS FOR DETECTING AND ANALYZING PASSIVE INTERMODULATION INTERFERENCE IN A COMMUNICATION SYSTEM - A system that incorporates aspects of the subject disclosure may perform operations including, for example, receiving, via an antenna, a signal generated by a communication device, detecting passive intermodulation interference in the signal, the interference generated by one or more transmitters unassociated with the communication device, and the interference determined from signal characteristics associated with a signaling protocol used by the one or more transmitters. Other embodiments are disclosed. | 2019-02-14 |
20190052295 | POLAR RECEIVER SYSTEM AND METHOD FOR BLUETOOTH COMMUNICATIONS - Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit. | 2019-02-14 |
20190052296 | Method for Transmitting a Value Measured by a Sensor, Method for Receiving the Measured Value, Sensor, Control Device - A method for transmitting a value measured by a sensor. The measured value is copied onto a data word by a function in order to be transmitted. | 2019-02-14 |
20190052297 | DEVICE COVER FOR ACCESSORY ATTACHMENT - Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided. | 2019-02-14 |
20190052298 | DEVICE COVER FOR ACCESSORY ATTACHMENT - Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided. | 2019-02-14 |
20190052299 | DEVICE COVER FOR ACCESSORY ATTACHMENT - Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided. | 2019-02-14 |
20190052300 | Transmitter/Receiver Module for Millimeter Wave 5G MIMO Communication Systems - A transmit/receive module includes a control circuit including multiple pairs of I/O terminals, each pair including a TX output terminal and an RX input terminal, a plurality of transmit/receive circuits connected to the control circuit, each of the transmit/receive circuits including a TX input terminal connected to the TX output terminal of one of the pairs of I/O terminals, an RX output terminal connected to the RX input terminal from the one of the pairs of I/O terminals, and a power amplifier connected to the TX input terminal. DC biasing terminals of each power amplifier of the transmit/receive circuits are independently connected to and controllable by the control circuit. | 2019-02-14 |
20190052301 | RADIO FREQUENCY SHIELDING WITHIN A SEMICONDUCTOR PACKAGE - Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip. | 2019-02-14 |
20190052302 | COEXISTENCE OVER A SHARED BAND WITH DUAL ANTENNA SHARING - This disclosure provides techniques for managing antenna sharing on a multi-mode wireless device between coexisting cellular and WLAN modems operating on the same band. One of the modems can communicate a WLAN scanning parameter to another one of the modems, and the distribution of shared antennas between the cellular modem and the WLAN modem may be modified based at least in part on the communicated scanning parameter to accommodate a WLAN scan on channels in the shared band. The distribution of the shared antennas between the modems for the WLAN scan may additionally or alternatively be selected based at least in part on the source of a detected WLAN scanning trigger (e.g., whether the scan is triggered by an application of the wireless device or the WLAN modem of the wireless device). | 2019-02-14 |
20190052303 | SIGNAL TRANSCEIVER DEVICE AND CALIBRATION METHOD THEREOF - A signal transceiver device includes a transceiver circuit, a switching circuit, a compensation circuit, and a calibration circuit. The transceiver circuit includes a transmitter and a receiver. The switching circuit has a first configuration and a second configuration, in which the transmitter is coupled to the receiver via the switching circuit. The compensation circuit analyzes an output of the receiver to obtain a first analyzed result and a second analyzed result, and generates first compensation coefficients and second compensation coefficients, in which the first analyzed result is corresponding to the first configuration, and the second analyzed result is corresponding to the second configuration. The calibration circuit calibrates the transmitter according to the first compensation coefficients, and calibrates the receiver according to the second compensation coefficients. | 2019-02-14 |
20190052304 | SELF-INTERFERENCE SIGNAL CANCELLATION DEVICE AND METHOD - A self-interference signal cancellation device and method are disclosed. A power divider divides a signal source into two paths, with one being connected to a transmit antenna and the other being connected to an input end of a self-interference signal reconstruction circuit. An output end of the self-interference signal reconstruction circuit is connected to a first input end of a combiner. An output end of a receive antenna is connected to a second input end of the combiner and a feedback regulating end of the self-interference signal reconstruction circuit, respectively. The transmit antenna and the receive antenna are arranged at different positions. According to the self-interference signal cancellation device of the present invention, by means of polarization isolation and separate arrangement between the transmit antenna and the receive antenna, high isolation between the antennas can be achieved, thereby reducing requirements for simulation elimination. | 2019-02-14 |
20190052305 | TWO-PHASE TRANSMISSION FOR MACHINE-TYPE COMMUNICATION - A two-phase approach to machine-type communications is provided. In a first phase, for activity detection, at least one symbol is transmitted using a long signature. During a second phase, for data transmission, information-carrying symbols are transmitted using a short spreading signature. Activity detection performance is enhanced through the use of a longer spreading signature. | 2019-02-14 |
20190052306 | Spread-Spectrum Modulated Clock Signal - A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal. | 2019-02-14 |
20190052307 | EXTRA-CHANNEL TRANSMISSION LIMITING SWITCH - A signal transmission system comprising a power amplifier, configured to amplify a signal; an antenna port, controllably connectable by a switch in series to an output of the power amplifier, and configured to be coupled to an antenna; a load component, controllably connectable by the switch in series to the output of the power amplifier; wherein the switch is disposed between the power amplifier and the antenna port and the load, to selectively connect the load component or the antenna port to the power amplifier according to a first operational mode and a second operational mode, and wherein the first operational mode is a mode in which the power amplifier is electrically connected to the antenna port and disconnected from the load component, and the second operational mode is a mode in which the power amplifier is electrically connected to the load component and disconnected from the antenna port. | 2019-02-14 |
20190052308 | DESIGN OF FREQUENCY HOPPING PATTERN FOR UNLICENSED INTERNET-OF-THINGS SYSTEM - The disclosure provides design of a frequency hopping sequence for an unlicensed IoT system operating in unlicensed spectrum. According to some embodiments, an apparatus for generating a frequency hopping sequence in an unlicensed Internet-of-Things (IoT) system includes baseband circuitry to generate a frequency hopping sequence by conducting a permutation operation based on a physical cell identifier (PCI) and a system frame number (SFN), and to select a channel within an unlicensed spectrum according to the frequency hopping sequence. In some embodiments, the input of the permutation operation is obtained from the SFN or from the SFN and the PCI. In some embodiments, the control of the permutation operation is a function of the PCI and/or the SFN. In some embodiments, the control of the permutation operation is generated using a pseudorandom number generator with the PCI as a seed. | 2019-02-14 |
20190052309 | NON-ORTHOGONAL MULTIPLE ACCESS SIGNALLING IN LTE - The present invention provides a method of operating a non-orthogonal multiple access, NOMA, communications network, the method comprising receiving from each of a plurality of user equipment, UE, devices at least one radio resource measurement report; processing the radio resource measurement reports to select a group of UE devices of the plurality of UE devices as a NOMA group; for the UE devices in the NOMA group determining a set of control parameters for the UE devices; informing the NOMA group UE devices a of the control parameters, wherein the control parameters are transmitted to the NOMA group UE devices using a downlink control information message having a format specific for NOMA messaging. | 2019-02-14 |
20190052310 | SYNCHRONIZED MULTI-CHANNEL ACCESS SYSTEM - Systems and methods are provided for synchronizing multiple channels in an access network, where the multiple channels are neighboring channels such that a guard band between them or use of a diplexer to prevent inter-channel interference is not required. Synchronization is achieved by defining channel MAP (media access plan) cycle structures such that all channels work in the same direction (upstream US or downstream DS) at any given time. Moreover, the network controller of channel may send out a beacon to allow new nodes to join. A long MAP cycle ( | 2019-02-14 |
20190052311 | FULL DUPLEX TRANSCEIVERS HAVING DIGITAL DISTORTION COMPENSATION AND METHODS OF THEREOF - In an example embodiment, a full duplex transceiver includes an analog-to-digital converter (ADC), at least one processor, a first digital-to-analog converter (DAC) and an amplifier. The ADC is configured to convert an analog first signal to a digital first signal, the analog first signal being based on a transmitted signal from the transceiver and a received signal from a far-end transceiver. The at least one processor is configured to determine pre-distortion compensation coefficients using the digital first signal and a first input signal and generate a pre-distorted compensated input signal based on the pre-distortion compensation coefficients. The first DAC is configured to convert the pre-distortion compensated input signal to an analog input signal. The amplifier is configured to amplify the analog input signal to a subsequent transmit signal. | 2019-02-14 |
20190052312 | MONITORING AND MITIGATING CONDITIONS IN A COMMUNICATION NETWORK - Aspects of the subject disclosure may include, for example, a system for receiving telemetry information from an apparatus that induces electromagnetic waves on a wire surface of a wire of a power grid for delivery of communication signals to a recipient communication device coupled to the power grid, and detecting a condition from the telemetry information that is adverse to a delivery of the communication signals to the recipient communication device. Other embodiments are disclosed. | 2019-02-14 |