07th week of 2019 patent applcation highlights part 59 |
Patent application number | Title | Published |
20190051510 | LAMP COMPRISING MULTIPLE COMPONENT DESIGNS AND CONSTRUCTIONS - The present invention provides a bulb ( | 2019-02-14 |
20190051511 | METHOD FOR DEPOSITING A SILICON NITRIDE FILM AND FILM DEPOSITION APPARATUS - A method for depositing a silicon nitride film is provided. In the method, an adsorption blocking region is formed such that a chlorine-containing gas conformally adsorbs on a surface of a substrate by adsorbing chlorine radicals on the surface of the substrate. A source gas that contains silicon and chlorine is adsorbed on the adsorption blocking region adsorbed on the surface of the substrate. A silicon nitride film is deposited on the surface of the substrate by supplying a nitriding gas activated by plasma to the source gas adsorbed on the surface of the substrate. | 2019-02-14 |
20190051512 | METHOD FOR DEPOSITING A SILICON NITRIDE FILM AND FILM DEPOSITION APPARATUS - A method for depositing a silicon nitride film is provided to fill a recessed pattern formed in a surface of a substrate with a silicon nitride film. In the method, a first silicon nitride film is deposited in the recessed pattern formed in the surface of the substrate. The first silicon nitride film has a V-shaped cross section decreasing its film thickness upward from a bottom portion of the recessed pattern. A second silicon nitride film conformal to a surface shape of the first silicon nitride film is deposited. | 2019-02-14 |
20190051513 | METHOD FOR DEPOSITING A SILICON NITRIDE FILM AND FILM DEPOSITION APPARATUS - A method for depositing a silicon nitride film is provided to fill a recessed pattern formed in a surface of a substrate. In the method, a first adsorption blocking region is formed by adsorbing first chlorine radicals such that an amount of adsorption increases upward from a bottom portion of the recessed pattern. A source gas that contains silicon and chlorine adsorbs on an adsorption site where the first adsorption site is not formed. A molecular layer of a silicon nitride film is deposited so as to have a V-shaped cross section. A second adsorption blocking region is formed by adsorbing second chlorine radicals on the molecular layer of the silicon nitride film. The molecular layer of the silicon nitride film is modified by nitriding the molecular layer while removing the second adsorption blocking region. | 2019-02-14 |
20190051514 | METHOD AND DEVICE FOR ETCHING PATTERNS INSIDE OBJECTS - Systems and methods for etching complex patterns on an interior surface of a hollow object are disclosed. A method generally includes positioning a laser system within the hollow object with a focal point of the laser focused on the interior surface, and operating the laser system to form the complex pattern on the interior surface. Motion of the laser system and the hollow object is controlled by a motion control system configured to provide rotation and/or translation about a longitudinal axis of one or both of the hollow object and the laser system based on the complex pattern, and change a positional relationship between a reflector and a focusing lens of the laser system to accommodate a change in distance between the reflector and the interior surface of the hollow object. | 2019-02-14 |
20190051515 | SEMICONDUCTOR BASE AND SEMICONDUCTOR DEVICE - Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of second material is decreased gradually upward, first composition graded layer is thicker than second composition graded layer. | 2019-02-14 |
20190051516 | FABRICATION OF A DEVICE ON A CARRIER SUBSTRATE - A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate. | 2019-02-14 |
20190051517 | Crystalline Semiconductor Growth On Amorphous And Poly-Crystalline Substrates - A multilayer semiconductor structure including at least in part a substrate and an III-N film layer. The substrate's constant of thermal expansion being substantially matched to the III-N film's constant of thermal expansion. The multilayer semiconductor structure may also include a crystal matching layer that has a lattice constant that substantially matches the lattice of constant of the III-N film. By not relying on the substrate for lattice matching the III-N film, the multilayer structure allows greater flexibility in the selection of an applicable substrate. | 2019-02-14 |
20190051518 | PLANARIZATION METHOD FOR A SEMICONDUCTOR SUBSTRATE USING A SILICON-CONTAINING COMPOSITION - A method for flatly covering a semiconductor substrate using a silicon-containing composition. A method for producing a polysiloxane-coated substrate, including a first step for forming a first polysiloxane coating film by applying a first polysiloxane composition for coating to a stepped substrate and firing the composition thereon and a second step for forming a second film by applying a second polysiloxane composition for coating to the first film and firing the composition thereon. The second film has an Iso-dense bias of 50 nm or less; the first polysiloxane contains a hydrolysis-condensation product of a hydrolyzable silane starting material containing a first hydrolyzable silane having four hydrolyzable groups in each molecule at a ratio of 0-100% by mole in all the silanes; and the second polysiloxane contains silanol groups at a ratio of 30% by mole or less relative to Si atoms, while having a weight average molecular weight of 1,000-50,000. | 2019-02-14 |
20190051519 | SUBSTRATE PROCESSING METHOD, RECORDING MEDIUM AND SUBSTRATE PROCESSING SYSTEM - In a substrate processing method, as a liquid film forming process, a liquid film of a processing liquid covering a surface of a substrate W is formed by supplying the processing liquid onto the surface of the substrate W while rotating the substrate W at a first rotation number. After the liquid film forming process, as a supply stopping process, a rotation number of the substrate W is set to be of a value equal to or less than the first rotation number and a supply of the processing liquid onto the substrate W is stopped. After the supply stopping process, as a liquid amount adjusting process, a liquid amount of the processing liquid forming the liquid film is reduced by setting the rotation number of the substrate W to a rotation number larger than the first rotation number. | 2019-02-14 |
20190051520 | METHOD FOR FORMING METAL OXIDE LAYER, AND PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION DEVICE - A method and a device for forming a highly dielectric metal oxide layer. The method includes repeatedly causing a plasma-off period and a plasma-on period while an organic metal compound and an oxidizing agent are continuously injected into a chamber. One cycle includes one plasma-off period and one plasma-on period. During the plasma-off period, a physical and chemical adsorption layer including an organic metal compound and a plurality of atomic layers is formed on a substrate. During the plasma-on period, a metal oxide layer that is thicker than two atomic layers is formed by a chemical reaction of metal atoms in the physical and chemical adsorption layer and oxygen atoms in the oxidizing agent. | 2019-02-14 |
20190051521 | SELECTIVE FILM DEPOSITION USING HALOGEN DEACTIVATION - Embodiments of the invention provide selective film deposition in a recessed feature of a substrate using halogen deactivation. A substrate processing method includes a) providing a substrate containing a field area and a recessed feature having a sidewall and a bottom, b) exposing the substrate to a first precursor gas to form a first precursor layer on the substrate, c) exposing the substrate to a plasma-excited halogen-containing gas to deactivate or at least partially remove the first precursor layer on the field area of the substrate and the bottom of the recessed feature, and d) exposing the substrate to a second precursor gas that reacts with the first precursor layer to form a material layer on the sidewall of the recessed feature but not on the field area and the bottom of the recessed feature that has been deactivated by the plasma-excited halogen-containing gas. | 2019-02-14 |
20190051522 | SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a base, a buffer layer, a mask layer and a first GaN layer. The buffer layer is disposed on the base, wherein doped regions are disposed in a portion of the surface of the buffer layer. The mask layer is disposed on the buffer layer and located on the doped regions. The first GaN layer is disposed on the buffer layer and covers the mask layer. | 2019-02-14 |
20190051523 | CUT FIRST SELF-ALIGNED LITHO-ETCH PATTERNING - The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer. | 2019-02-14 |
20190051524 | WAFER BONDING METHOD AND STRUCTURE THEREOF - Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers. | 2019-02-14 |
20190051525 | METHOD FOR MANUFACTURING COMPOSITE WAFER PROVIDED WITH OXIDE SINGLE CRYSTAL THIN FILM - A composite wafer includes an oxide single crystal thin film of lithium tantalate or lithium niobate transferred onto the entire face of a support wafer and is free from cracking or peeling on a bonding interface between the support wafer and the oxide single crystal thin film. A method for manufacturing a composite wafer at least includes a step of forming an ion-implanted layer in an oxide single crystal wafer, a step of subjecting at least one of the ion-implanted surface of the oxide single crystal wafer and a surface of a support wafer to a surface activation treatment, a step of bonding the ion-implanted surface of the oxide single crystal wafer to the surface of the support wafer to form a laminate, a step of subjecting the laminate to a first heat treatment at a temperature not less than 90° C. and not causing cracking, a step of applying a mechanical impact to the ion-implanted layer, and a step of subjecting the support wafer having the transferred oxide single crystal thin film to a second heat treatment at 250° C. to 600° C. to yield a composite wafer. | 2019-02-14 |
20190051526 | METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE - An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern. | 2019-02-14 |
20190051527 | METHODS FOR FORMING A PHOTO-MASK AND A SEMICONDUCTOR DEVICE - A method for forming a photo-mask includes providing a first pattern, wherein the first pattern includes a first light-transmitting region and a first light-shielding region; transforming the first pattern into a second pattern, wherein the second pattern includes a second light-transmitting region and a second light-shielding region, the second light-transmitting region is located within range of the first light-transmitting region, and the second light-transmitting region has an area which is smaller than that of the first light-transmitting region, the second light-shielding region includes the entire region of the first light-shielding region, and the second light-shielding region has an area which is greater than that of the first light-shielding region; and forming the second pattern on a photo-mask substrate to form a photo-mask, wherein the photo-mask is used in an ion implantation process of a material layer. | 2019-02-14 |
20190051528 | Phase Change Memory with Diodes Embedded in Substrate - An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type. | 2019-02-14 |
20190051529 | Method for Producing a Superjunction Device - Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer. | 2019-02-14 |
20190051530 | MANUFACTURING METHOD OF INTEGRATED CIRCUIT - A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate. | 2019-02-14 |
20190051531 | CONTACT INTEGRATION AND SELECTIVE SILICIDE FORMATION METHODS - Methods for selective silicide formation are described herein. The methods are generally utilized in conjunction with contact structure integration schemes and provide for improved silicide formation characteristics. In one implementation, a silicide material is selectively formed on source/drain (S/D) regions at a temperature less than about 550° C. The resulting silicide is believed to exhibit desirable contact resistance and applicability in advanced contact integration schemes. | 2019-02-14 |
20190051532 | CUTTING APPARATUS AND WAFER PROCESSING METHOD - A cutting apparatus includes a line sensor unit that applies a laser beam in a band shape elongated in a radial direction of a wafer to a region inclusive of a peripheral portion of the wafer held on a chuck table, and detects reflected light, and an information calculation section that calculates the position of the wafer and the height of the front surface of the wafer from the reflected light of the laser beam detected by the line sensor unit in a state in which the chuck table is rotated before the wafer is cut to form a stepped portion, and that calculates the width and the height of the stepped portion from the reflected light of the laser beam detected by the line sensor unit after the wafer is cut to form the stepped portion. | 2019-02-14 |
20190051533 | METHOD OF MANUFACTURING SUBSTRATE AND SEMICONDUCTOR DEVICE - To provide dummy openings having at least one of arrangement and shape determined depending on the shape of a non-effective region. | 2019-02-14 |
20190051534 | METHOD FOR THE VAPOUR PHASE ETCHING OF A SEMICONDUCTOR WAFER FOR TRACE METAL ANALYSIS - The surface layer of a semiconductor wafer lying on a rotatable plate within an etching chamber is etched by a process whereby homogeneous etching of the surface is obtained by introducing an etching gas into the etching chamber in such a way that the flow of the etching gas is not directed directly to the wafer but is allowed first to distribute within the etching chamber before coming into contact with the surface of the semiconductor wafer to be etched. | 2019-02-14 |
20190051535 | Stacked Nanowires - Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided. | 2019-02-14 |
20190051536 | DOUBLE PATTERNING METHOD - In some embodiments, the disclosure relates to an integrated circuit structure. The integrated circuit structure has a substrate and a first hard mask layer over the substrate. An island of a second hard mask layer is arranged on the first hard mask layer and is set back from sidewalls of the first hard mask layer. A sacrificial mask is disposed over the island of the second hard mask layer. The sacrificial mask has sidewalls that define an opening exposing upper surfaces of the first hard mask layer and the island of the second hard mask layer. The island of the second hard mask layer extends from below the sacrificial mask to laterally past the sidewalls of the sacrificial mask. | 2019-02-14 |
20190051537 | CHEMICAL MECHANICAL POLISHING METHOD FOR TUNGSTEN - A process for chemical mechanical polishing a substrate containing tungsten to at least reduce dishing of tungsten features of 100 μm or less. The process includes providing a substrate containing tungsten features of 100 μm or less; providing a polishing composition, containing, as initial components: water; an oxidizing agent; arginine or salts thereof; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally, a pH adjusting agent; and, optionally, a surfactant; and, optionally, a biocide; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten is polished away from the substrate and yet at least reducing dishing of the tungsten features of 100 μm or less. | 2019-02-14 |
20190051538 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - In a semiconductor device including a crystalline nitride layer, in which diamond is used for heat dissipation thereof, it is an object of the present invention to suppress cracking of the crystalline nitride layer. The semiconductor device includes a layered body and a heat dissipation layer. The layered body includes a crystalline nitride layer and a composite layer. The composite layer includes a non-inhibiting portion which does not inhibit diamond growth on a surface thereof and an inhibiting portion which inhibits the diamond growth on the surface. A layered body main surface of the layered body has a first region in which the non-inhibiting portion is exposed and a second region in which the inhibiting portion is exposed. The heat dissipation layer is made of diamond, opposed to the main surface, adhered to the first region, and separated from the second region with a void interposed therebetween. | 2019-02-14 |
20190051539 | METHOD FOR MANUFACTURING RESIN-SEALED POWER SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a method for manufacturing a resin-sealed power semiconductor device that facilitates the separation of a suspension lead from a mold resin and a lead frame. A method for manufacturing a resin-sealed power semiconductor device according to the present invention includes the following steps: (a) sealing a semiconductor element and a lead frame, to prepare a sealed body in which a terminal lead and a suspension lead that are included in the lead frame project outward from a side of the mold resin; (b) punching a portion of the suspension lead, the portion projecting from the mold resin, with a first punch in a first direction, to separate the suspension lead from the mold resin; and (c) punching the projecting portion of the suspension lead with a second punch in a second direction. | 2019-02-14 |
20190051540 | SYSTEMS AND METHODS FOR PLASMA-LESS DE-HALOGENATION - A substrate processing system to remove residual halogen species from a substrate includes a processing chamber and a substrate support arranged in the processing chamber to support a substrate. The substrate includes residual halogen species. A heater heats the substrate to a temperature in a predetermined temperature range from 100° C. to 700° C. during a processing period. A chamber pressure controller controls pressure inside the processing chamber in a predetermined pressure range greater than 10 Torr and less than 800 Torr during the processing period. A vapor generator supplies water vapor at least one of in the processing chamber or to the processing chamber during the processing period. | 2019-02-14 |
20190051541 | SPIN CHUCK WITH CONCENTRATED CENTER AND RADIAL HEATING - A substrate processing system to treat a substrate includes a spin chuck configured to hold and rotate a substrate. A heating assembly is configured to heat an opposite surface of the substrate and includes a main heater assembly and a nozzle stack cap. The main heater assembly includes a first plurality of light emitting diodes (LEDs) arranged on a first printed circuit board (PCB) in a first plane that is spaced from and parallel to a second plane including the substrate. The nozzle stack cap assembly includes at least one nozzle to dispense liquid onto a center of a first surface of the substrate. A radiant heat source is arranged closer to the substrate than the first plane and is configured to heat the center of the first surface of the substrate. | 2019-02-14 |
20190051542 | FLUORINE CONTAMINATION CONTROL IN SEMICONDUCTOR MANUFACTURING PROCESS - A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance. | 2019-02-14 |
20190051543 | WAFER HOLDER - A wafer holder includes a mounting table that has a mounting surface for a workpiece at a top, a supporting member that supports the mounting table from a lower side, a first cylindrical member one end of which is joined hermetically to a lower surface of the mounting table, and a second cylindrical member that is provided inside the first cylindrical member and one end of which is joined hermetically to the lower surface of the mounting table. | 2019-02-14 |
20190051544 | RADIATION SHIELD - A radiation shield and an assembly and a reactor including the radiation shield are disclosed. The radiation shield can be used to control heat flux from a susceptor heater assembly and thereby enable better control of temperatures across a surface of a substrate placed on a surface of the susceptor heater assembly. | 2019-02-14 |
20190051545 | SEMICONDUCTOR PROCESSING STATION - A semiconductor processing station including a central transfer chamber, a load lock chamber disposed adjacent to the central transfer chamber, and a cooling stage disposed adjacent to the load lock chamber and the central transfer chamber is provided. The load lock chamber is adapted to contain a wafer carrier including a plurality of wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer of the plurality of wafers between the cooling stage and the load lock chamber. | 2019-02-14 |
20190051546 | EFEM ROBOT AUTO TEACHING METHODOLOGY - The present disclosure relates to a method of automatically re-programming an EFEM to account for positional changes of the EFEM robot. In some embodiments, the method is performed by determining an initial position of an EFEM robot within an EFEM chamber. The EFEM robot at the initial position moves along a first plurality of steps defined relative to the initial position and that extend along a path between a first position and a second position. Positional parameters are determined, which describe a change between an initial position and a new position of the EFEM robot that is different than the initial position. A second plurality of steps are determined based upon the positional parameters. The EFEM robot at the new position moves along the second plurality of steps defined relative to the new position and that extend along the path between the first position and the second position. | 2019-02-14 |
20190051547 | PROCESS MANAGEMENT METHOD AND APPARATUS - Provided is a method of managing a target process. The method performed by a process management apparatus includes: generating a reference pattern indicating a normal state based on reference observed data on a process factor measured while the target process is maintained in the normal state; obtaining observed data on the process factor measured for a specified observation period; calculating a dissimilarity between the reference pattern and the observed data; and constructing a regression tree for the target process by using the observed data and the dissimilarity, wherein the process factor is set as an independent variable of the regression tree, and the dissimilarity is set as a dependent variable of the regression tree. | 2019-02-14 |
20190051548 | CASSETTE HOLDER ASSEMBLY FOR A SUBSTRATE CASSETTE AND HOLDING MEMBER FOR USE IN SUCH ASSEMBLY - The invention relates to a cassette holder assembly for holding a cassette for storing at least one semiconductor material substrate in an interior space accessible from a front end of the cassette. The cassette holder assembly may have a base plate for receiving the cassette. Two holding members supported by the base plate may be positioning the cassette on the plate in the assembly. The holding members may be substantially identical to each other. | 2019-02-14 |
20190051549 | METHOD AND SYSTEM OF MEASURING AIR-TIGHTNESS AND CONTAINER MEASURED THEREBY - A method and a system of measuring air-tightness and a container measured thereby are provided. In the method, a first cover having a first contact surface and a first base having a second contact surface are provided. The two contact surfaces are used for engaging with each other to form an air-tight state. Further, a first contour curve relating to the first contact surface and a second contour curve relating to the second contact surface are acquired. Then, the two contour curves are brought into contact with each other, and the area of a first gap between the two curves is determined. When the area of the first gap is equal to or smaller than a threshold, the first cover and the first base are paired as a first combination of acceptable air-tightness so as to form the container. | 2019-02-14 |
20190051550 | MOUNTING MEMBER - Provided is a mounting member that is excellent in low dusting property and hardly contaminates an object to be mounted while being excellent in gripping force and heat resistance. The mounting member of the present invention includes an aggregate of carbon nanotubes for forming a mounting surface, wherein a ratio of a plan view area of recessed portions occurring in a carbon nanotube aggregate-side surface of the mounting member to a total area of the carbon nanotube aggregate-side surface is 5% or less. | 2019-02-14 |
20190051551 | SUBSTRATE SUPPORT WITH SYMMETRICAL FEED STRUCTURE - Apparatus for processing a substrate is disclosed herein. In some embodiments, a substrate support may include a substrate support having a support surface for supporting a substrate the substrate support having a central axis; a first electrode disposed within the substrate support to provide RF power to a substrate when disposed on the support surface; an inner conductor coupled to the first electrode about a center of a surface of the first electrode opposing the support surface, wherein the inner conductor is tubular and extends from the first electrode parallel to and about the central axis in a direction away from the support surface of the substrate support; an outer conductor disposed about the inner conductor; and an outer dielectric layer disposed between the inner and outer conductors, the outer dielectric layer electrically isolating the outer conductor from the inner conductor. The outer conductor may be coupled to electrical ground. | 2019-02-14 |
20190051552 | MULTI-LEVEL MICRO-DEVICE TETHERS - An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor. | 2019-02-14 |
20190051553 | Methods of Transferring a Graphene Monolayer via a Stacked Structure and Devices Fabricated Thereby - A method of fabricating a graphene device generally involving depositing a graphene monolayer from a carbon source on a metal catalyst layer; depositing a transfer substrate on the graphene monolayer by way of casting, thereby forming a transfer-substrate/graphene/metal-catalyst structure; annealing the transfer-substrate/graphene/metal-catalyst structure, thereby forming an annealed transfer-substrate/graphene/metal-catalyst structure; coupling a thermal adhesive with the transfer-substrate/graphene/metal-catalyst structure; moving the annealed transfer-substrate/graphene/metal-catalyst structure to a target area of a target device, by using a probe assembly or the like, thereby forming an annealed transfer-substrate/graphene/metal-catalyst/thermal-adhesive/target-device structure; releasing the slip of thermal adhesive from the annealed transfer-substrate/graphene/metal-catalyst thermal-adhesive/target-device structure by applying heat, thereby forming an annealed transfer-substrate/graphene/metal-catalyst/target-device structure; etching away the metal catalyst layer from the annealed transfer-substrate/graphene/metal-catalyst/target-device structure in an etching solution, thereby forming a graphene/transfer-substrate/target-device structure; rinsing the graphene/transfer-substrate/target-device structure with DI water, thereby removing any excess etching solution; and drying the graphene/transfer-substrate/target-device structure, thereby providing the graphene device. | 2019-02-14 |
20190051554 | Wafer Support Assembly Including Ion Implantation Mask Structure - A wafer support assembly can include a wafer chuck including a first surface and a second surface, where the first surface can have a central region that is configured to hold a wafer during ion implantation into the wafer, and an edge region surrounding the central region beyond an edge of the wafer when held in the central region, and the second surface opposing the first surface. An edge mask structure can cover at least a portion of the edge region of the first surface, where the edge mask structure can have a mask body with an inclined side surface facing the central region. | 2019-02-14 |
20190051555 | SUBSTRATE LIFT MECHANISM AND REACTOR INCLUDING SAME - A substrate support assembly suitable for use in a reactor including a common processing and substrate transfer region is disclosed. The substrate support assembly includes a susceptor and one or more lift pins that can be used to lower a substrate onto a surface of the susceptor and raise the substrate from the surface, to allow transfer of the substrate from the processing region, without raising or lowering the susceptor. | 2019-02-14 |
20190051556 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of short-circuit prevention-regions of a second conductivity type at an upper portion of the semiconductor substrate, a first insulating film on a top surface of the semiconductor substrate, a strip-shaped fuse on a top surface of the first insulating film spanning over the short-circuit prevention-regions, a second insulating film on a top surface of the fuse, and a passivation film on a top surface of the second insulating film and having an opening for laser trimming. The opening exposes the second insulating film above an area including the short-circuit prevention-regions. | 2019-02-14 |
20190051557 | SEAM-HEALING METHOD UPON SUPRA-ATMOSPHERIC PROCESS IN DIFFUSION PROMOTING AMBIENT - Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere. | 2019-02-14 |
20190051558 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 2019-02-14 |
20190051559 | INTERCONNECT STRUCTURE FOR STACKED DEVICE - A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers. | 2019-02-14 |
20190051560 | PROCESSING METHOD FOR SUBSTRATE HAVING METAL EXPOSED - A processing method for a substrate having a metal exposed and having cutting lines of a predetermined width set thereon includes: a structural body disposing step of disposing two structural bodies on the metal along respective edges in regard of the width direction of the cutting line, with a gap corresponding to the width therebetween; and a cutting step of causing a cutting blade to cut into the substrate from between the two structural bodies to cut the substrate along the cutting lines, after the structural body disposing step is carried out. | 2019-02-14 |
20190051561 | WORKPIECE DIVIDING METHOD - A workpiece dividing method includes: a laser processing step of forming along each street a plurality of minute holes extending in a pulsed laser beam application direction; and a dividing step of pressing the streets by a pressing member to divide a wafer along the streets. The minute hole has one end opening at least one of a front surface and a back surface of the wafer and is decreased in diameter from the one end toward the other end. In the dividing step, the pressing member is pressed against that surface of the front surface and the back surface of the wafer at which the one end of the minute hole is not opening. | 2019-02-14 |
20190051562 | GALLIUM NITRIDE NMOS ON SI (111) CO-INTEGRATED WITH A SILICON PMOS - This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island. | 2019-02-14 |
20190051563 | METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF A VERTICAL TRANSISTOR - A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process. | 2019-02-14 |
20190051564 | Method of Making a FinFET Device - A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space. | 2019-02-14 |
20190051565 | CMOS DEVICES AND MANUFACTURING METHOD THEREOF - A method of manufacturing a complementary metal-oxide-semiconductor (CMOS) device comprising an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region is provided, that comprises: depositing a raised source and drain (RSD) layer of a first type in the NMOS region and the PMOS region at the same time; selectively removing the RSD layer of the first type in one of the NMOS region and the PMOS region; and depositing an RSD layer of a second type in the one of the NMOS region and the PMOS region. | 2019-02-14 |
20190051566 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer. | 2019-02-14 |
20190051567 | TEST KEY LAYOUT AND METHOD OF MONITORING PATTERN MISALIGNMENTS USING TEST KEYS - A set of test key layout including multiple test keys and method of monitoring layout pattern misalignments using the test keys is provided. Each test key is composed of a testing electrode, an operating voltage (V | 2019-02-14 |
20190051568 | SYSTEM AND METHOD FOR TEMPERATURE CONTROL IN PLASMA PROCESSING SYSTEM - Techniques herein include systems and methods for fine control of temperature distribution across a substrate. Such techniques can be used to provide uniform spatial temperature distribution, or a biased spatial temperature distribution to improve plasma processing of substrates and/or correct characteristics of a given substrate. Embodiments include a plasma processing system with temperature control. Temperature control systems herein include a primary heating mechanism to heat a substrate, and a secondary heating mechanism that precisely modifies spatial temperature distribution across a substrate being processed. At least one heating mechanism includes a digital projection system configured to project a pattern of electromagnetic radiation onto or into a substrate, or through the substrate and onto a substrate support assembly. The digital projection system is configured to spatially and dynamically adjust the pattern of electromagnetic radiation and selectively augment heating of the substrate by each projected point location. | 2019-02-14 |
20190051569 | METHODS FOR FORMING INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS - An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad. | 2019-02-14 |
20190051570 | MULTIPLE BARRIER LAYER ENCAPSULATION STACK - A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack. | 2019-02-14 |
20190051571 | MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF - Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package. | 2019-02-14 |
20190051572 | SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 2019-02-14 |
20190051573 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film on a semiconductor substrate; a fuse on the first insulating film, including first second terminal pads, a blowing strip having a width smaller than the first and second terminal pads, extending from the first terminal pad to the second terminal pad, a first connecting portion connecting the first terminal pad and the blowing strip, and a second connecting portion connecting the second terminal pad and the blowing strip, and a second insulating film covering the first insulating film and the fuse. The first and second connecting portions are asymmetric with respect to a reference plane passing through the middle point of the blowing strip, orthogonal to the extending direction of the blowing strip and normal to the principal surface of the semiconductor substrate. | 2019-02-14 |
20190051574 | Chip Package Structure, Terminal Device, and Method - A chip package apparatus includes a substrate, a chip on the substrate, and a filling layer on the substrate and surrounding a portion of the chip. The filling layer is made of epoxy molding compound (EMC) and the EMC is white. An electronic device with the chip package apparatus and a method for manufacturing the chip apparatus structure are provided. | 2019-02-14 |
20190051575 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first substrate having connection parts at a first surface; a second substrate bonded with the first substrate having through-holes in a stacking direction of the first and second substrates for respectively exposing the connection parts; through-electrodes respectively arranged at through-holes and electrically connected with the connection parts; and a protective film for integrally covering the through-electrodes. Frame-shaped slits are formed to respectively surround the through-holes when viewed in a normal direction with respect to the first surface of the first substrate. The protective film is separated by the slit into a region inside the slit and a region outside the slit. | 2019-02-14 |
20190051576 | METHOD AND APPARATUS FOR PROVIDING THERMAL WEAR LEVELING - Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory. | 2019-02-14 |
20190051577 | ELECTRONIC DEVICE - An electronic device has a substrate | 2019-02-14 |
20190051578 | SEMICONDUCTOR DEVICE PACKAGES WITH DIRECT ELECTRICAL CONNECTIONS AND RELATED METHODS - Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate. | 2019-02-14 |
20190051579 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor chip including a substrate and an element region on the substrate, a heat transfer body made of diamond, and a metal layer between the semiconductor chip and the heat transfer body, wherein the substrate includes an amorphous region on a back surface thereof, the amorphous region and the metal layer are bonded to each other, and the metal layer and the heat transfer body are bonded to each other. | 2019-02-14 |
20190051580 | Clamping Mechanism For Heat Sink and Electronic Device Assembly Including the Same - A clamping mechanism adapted to clamp a heat sink on a housing of an electronic device comprises a frame, a plurality of mounting legs connected on the frame, and a plurality of elastic tabs obliquely extending from the frame towards the heat sink. The frame has a rectangular shape and includes a first arm adapted to be connected to a front end of the housing, a second arm adapted to be connected to a rear end of the housing, and a pair of third arms connected between the first arm and the second arm. The mounting legs are configured to mount the frame on the housing. The elastic tabs press the heat sink against the housing. Each of the third arms has at least one of the elastic tabs. | 2019-02-14 |
20190051581 | SEMICONDUCTOR DEVICE - According to the present invention, a semiconductor device includes a first metal plate, a second metal plate provided above the first metal plate, a third metal plate provided above the second metal plate, a first semiconductor chip provided between the first metal plate and the second metal plate, a second semiconductor chip provided between the second metal plate and the third metal plate and a cooling member, wherein the first metal plate has a first cooling portion that is in contact with the cooling member, the second metal plate has a second cooling portion that is in contact with the cooling member, and the third metal plate has a third cooling portion that is in contact with the cooling member. | 2019-02-14 |
20190051582 | SUBSTRATE-FREE SYSTEM IN PACKAGE DESIGN - Apparatuses and processes are disclosed for a substrate-free system in package that includes a through mold via Embodiments may include providing a circuit trace layer on top of a first side of a carrier, coupling a first set of one or more surface mount components to a first side of the circuit trace layer opposite the carrier, embedding the first set of the one or more surface mount components in a molding compound, exposing a second side of the circuit trace layer opposite the first side of the circuit trace layer, and coupling one or more electrical interconnects to serve as TMVs to the second side of the circuit trace layer. Embodiments may also include exposing the second side of the circuit trace layer by grinding the carrier. Other embodiments may be described and/or claimed. | 2019-02-14 |
20190051583 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device PKG includes a semiconductor chip CP, a lead LD | 2019-02-14 |
20190051584 | Side-Solderable Leadless Package - A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer. | 2019-02-14 |
20190051585 | THERMALLY ENHANCED LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF - Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate. | 2019-02-14 |
20190051586 | POWER MODULE AND POWER CONVERSION SYSTEM INCLUDING SAME - A power module includes an upper substrate comprising a plurality of circuit pattern areas made of a metal and a dielectric area disposed between each of the plurality of circuit pattern areas; a lower substrate including a plurality of circuit pattern areas made of a metal and a dielectric area disposed between each of the plurality of circuit pattern areas; and a semiconductor element having an upper terminal and a lower terminal, the upper terminal and the lower terminal being bonded to a lower surface of the upper substrate and an upper surface of the lower substrate, respectively. | 2019-02-14 |
20190051587 | IC PACKAGE - Aspects of the disclosure provide an integrated circuit (IC) package. The IC package includes a package substrate configured to have a first surface and a second surface that is opposite to the first surface. An IC chip is interconnected with the package substrate. The IC package includes a first plurality of contact structures disposed on the first surface to electrically couple the IC package (e.g., a first plurality of input/output (I/O) pads on the IC chip) to traces on a printed circuit board (PCB). The IC package includes a second plurality of contact structures disposed on the second surface. The second plurality of contact structures is configured to electrically couple the IC package (e.g., a second plurality of I/O pads on the IC chip) to another device via a connective structure that is independent of the PCB. | 2019-02-14 |
20190051588 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE PROVIDED WITH SAME - A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group. | 2019-02-14 |
20190051589 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, electrical conductors and a passivation layer. Each of the electrical conductors includes a first portion through the substrate, and a second portion over the surface of the substrate and connected to the first portion. The passivation layer is over the surface of the substrate, wherein the passivation layer partially covers an edge of the second portion of each of the electrical conductors. | 2019-02-14 |
20190051590 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer. | 2019-02-14 |
20190051591 | INTERPOSER WITH A NANOSTRUCTURE ENERGY STORAGE DEVICE - An interposer device comprising an interposer substrate; a plurality of conducting vias extending through the interposer substrate; a conductor pattern on the interposer substrate, and a nanostructure energy storage device. The nanostructure energy storage device comprises at least a first plurality of conductive nanostructures formed on the interposer substrate; a conduction controlling material embedding each nanostructure in the first plurality of conductive nanostructures; a first electrode connected to each nanostructure in the first plurality of nanostructures; and a second electrode separated from each nanostructure in the first plurality of nanostructures by the conduction controlling material, wherein the first electrode and the second electrode are configured to allow electrical connection of the nanostructure energy storage device to the integrated circuit. | 2019-02-14 |
20190051592 | SEMICONDUCTOR PACKAGE HAVING A CIRCUIT PATTERN - A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first installation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions. | 2019-02-14 |
20190051593 | DISPLAY DEVICE - According to one embodiment, a display device includes a first signal wiring disposed on an insulating substrate, a base substrate, a first connection wiring on the base substrate and a conductive adhesive member which electrically connects the first signal wiring and the first connection wiring, wherein the base substrate includes a first end surface overlapping the first signal wiring, the insulating substrate includes a second end surface overlapping the first connection wiring, the first connection wiring has a first width in a position overlapping the first end surface and a second width in a position overlapping the second end surface, and the first width is less than the second width. | 2019-02-14 |
20190051594 | MODULE - A module with high reliability is provided by inhibiting occurrences of air bubbles caused with rise in flow resistance of resin when a sealing resin layer is formed using a die. A module includes a wiring board, components mounted over an upper face of the wiring board, and a sealing resin layer laminated over the upper face. On the upper face, the sealing resin layer includes a high-level region with a long distance from the upper face of the wiring board, a low-level region with a short distance from the upper face, and a level difference region. In a portion included in the wiring board and corresponding to the low-level region and the level difference region, a thin portion is formed so as to be thinner than the remaining portion and overlaps the low-level region at least partially in a plan view. | 2019-02-14 |
20190051595 | Advanced Metal Connection With Metal Cut - Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. | 2019-02-14 |
20190051596 | METHOD OF INCREASING EMBEDDED 3D METAL-INSULATOR-METAL (MIM) CAPACITOR CAPACITANCE DENSITY FOR WAFER LEVEL PACKAGING - Methods of processing a substrate include providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer; depositing a plurality of polymer layers atop the substrate; patterning the plurality of polymer layers to form at least one via that extends from a top surface of an uppermost polymer layer to a top surface of the metal layer; and forming a three-dimensional metal-insulator-metal (3D MIM) capacitance stack in the at least one via and over a portion of the metal layer and the plurality of polymer layers. | 2019-02-14 |
20190051597 | CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A capacitor structure includes a substrate including an electrode pad and a ground pad, a plurality of dielectric layers on the substrate, the plurality of dielectric layers being at different levels on the substrate, a plurality of conductive pattern layers in at least two dielectric layers of the plurality of dielectric layers, the at least two dielectric layers of the plurality of dielectric layers being first dielectric layers, a plurality of via plugs connecting the plurality of conductive pattern layers to each other, and at least one contact layer in at least one second dielectric layer of the plurality of dielectric layers, the at least one second dielectric layer being different from the at least two first dielectric layers, and the at least one contact layer electrically connecting the plurality of conductive pattern layers to the electrode pad and the ground pad. | 2019-02-14 |
20190051598 | CIRCUIT BOARD, METHOD FOR MANUFACTURING CIRCUIT BOARD, AND ELECTRONIC DEVICE - A circuit board includes an insulating layer, a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias. | 2019-02-14 |
20190051599 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug. | 2019-02-14 |
20190051600 | SEMICONDUCTOR DEVICE INCLUDING DUMMY CONTACT - A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection. | 2019-02-14 |
20190051601 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed herein is a semiconductor integrated circuit device which can ensure sufficient power supply ability and ESD protection capability for an I/O cell without increasing the area of the semiconductor integrated circuit. In-row power supply interconnects ( | 2019-02-14 |
20190051602 | THROUGH-HOLES OF A SEMICONDUCTOR CHIP - One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate. | 2019-02-14 |
20190051603 | HIGH-DENSITY INTERCONNECTING ADHESIVE TAPE - A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes. | 2019-02-14 |
20190051604 | INTEGRATED FAN-OUT PACKAGE AND METHOD FOR FABRICATING THE SAME - An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided. | 2019-02-14 |
20190051605 | HIGH-DENSITY INTERCONNECTING ADHESIVE TAPE - A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes. | 2019-02-14 |
20190051606 | SEMICONDUCTOR MODULE - A semiconductor module according to one embodiment includes a circuit substrate and first and second transistors for upper and lower arms of a power conversion circuit. The circuit substrate includes a substrate having first and second insulating parts and a conductive layer disposed therebetween, first and second input interconnection patterns coupled to the first and second input terminals, and an output interconnection pattern coupled to an output terminal. The first and second transistors are electrically coupled to the first and second input terminals through the first and second input interconnection patterns, respectively. The conductive layer has a first area situated opposite the first input interconnection pattern and a second area electrically coupled to the first area. The second area is electrically coupled to the second input interconnection pattern. The conductive layer is insulated from the first input interconnection pattern and the output interconnection pattern by the second insulating part. | 2019-02-14 |
20190051607 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved. | 2019-02-14 |
20190051608 | SEMICONDUCTOR MODULE - A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component. | 2019-02-14 |
20190051609 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure. | 2019-02-14 |