07th week of 2009 patent applcation highlights part 28 |
Patent application number | Title | Published |
20090040747 | KEYBOARD WITH LIGHTING CIRCUIT - An exemplary keyboard includes at least one lighting circuit and a keypad mounted on the keyboard. The lighting circuit comprises a power source, at least one light emitting diode (LED), and a regulating resistor. The regulating resistor includes an adjustment terminal connected to the power source and a connection terminal connected to the anode of the LED. The cathode of the LED is grounded. The keypad is illuminated by the lighting circuit arranged therein. Therefore, users can adjust illumination of different parts of the keyboard by adjusting the regulating resistors of the lighting circuits arranged therein. | 2009-02-12 |
20090040748 | ACTIVE ENCLOSURE FOR COMPUTING DEVICE - A computing device is disclosed. The computing device includes a housing having an illuminable portion. The computing device also includes a light emitting device disposed inside the housing. The light emitting device is configured to produce a light effect that alters the ornamental appearance of the computing device. | 2009-02-12 |
20090040749 | RETRACTABLE LIGHT APPARATUS - A retractable light is provided with a light to extend and retract in a housing. A motor for driving a sprocket is mounted in the housing or light assembly and a gear rack is mounted in the other. The gear rack has a series of apertures so that debris is conveyed into the apertures. Another embodiment provides a housing with a first guide member, connected to a light assembly by a second guide member. A motor and a gear are mounted in one of the housing and light assembly. A gear rack is mounted in the other of the housing and the light assembly. In another embodiment, a rechargeable battery is powered by a solar cell with a first circuit for powering the motor with a first voltage and a second circuit for powering the light source with a second voltage that is less than the first voltage. | 2009-02-12 |
20090040750 | SOLAR-POWERED LIGHT POLE AND LED LIGHT FIXTURE - A solar-powered lighting system includes a flexible, wrap-around, preferably self-stick panel of photovoltaic laminate applied to the outside surface of a light pole. An LED light fixture is connected preferably at or near the top of the pole and has the same or similar diameter as the pole. The LED light fixture has multiple columns and rows of LEDs and an interior axial space for air flow to cool the LEDs. The pole preferably also has vents and axial passage(s) for creating a natural updraft through at least a portion of the pole and the light fixture, for cooling of the photovoltaic panel interior surface, the LEDs, and/or other equipment inside the fixture or pole, and batteries that may be provided inside the pole or pole base. A purely or mainly decorative additional fixture, which emulates conventional outdoor light fixtures, may be provided on the lighting system, wherein the decorative additional fixture includes no, or only a minimal, light source. The lighting system has a sleek profile with few or no protrusions from the sides of the pole and from the LED light fixture, except for the optional decorative fixture that provides a conventional street light appearance even though the main light source is the LED fixture. | 2009-02-12 |
20090040751 | Light Attachment For Inspection Tool - A light attachment for an inspection tool having a mirror, the attachment having: a mounting bracket configured for releasable attachment to the mirror; a light member attached to the mounting bracket; and a power source for the light member. | 2009-02-12 |
20090040752 | MULTI BATTERY TYPE FLASHLIGHT - The invention relates to a portable lighting device including a body having a battery compartment, a head coupled to the body, a light source coupled to the head, the light source requiring a first voltage, and a circuit coupled to the light source. The battery compartment is configured to selectively receive batteries of different sizes. The circuit converts voltages of different magnitudes to the first voltage. | 2009-02-12 |
20090040753 | ILLUMINATION DEVICE AND PROJECTION DISPLAY DEVICE - An illumination device comprises: a plurality of laser light sources arranged so as to be identical in a direction of light emission; an optical element for converting laser light emitted from the laser light sources into parallel light at least in one direction; and a fly-eye lens into which the laser light converted into parallel light is entered. Placement of the laser light sources is adjusted in such a manner that incident regions of the laser light on the fly-eye lens are mutually shifted in a row or column direction of lens cells disposed in the fly-eye lens. | 2009-02-12 |
20090040754 | LIGHT EMITTING DIODE ILLUMINATION SYSTEM - In various embodiments of the invention, a unique construction for Light Emitting Diodes (LEDs) with at least one luminescent rod and extracting optical elements is used to generate a variety of high brightness light sources with different emission spectra. In an embodiment of the invention, forced air cooling is used to cool the luminescent rod. In an embodiment of the invention, totally internal reflected light can be redirected outward and refocused. In another embodiment of the invention, light emitted by the luminescent rod is out-coupled for use in a variety of applications. In various embodiments of the invention, a plurality of independent narrow band colors can be coaxially combined. | 2009-02-12 |
20090040755 | Light-Emitting Device With Chromatic Control - The light-emitting device includes a base substrate and preferably three light-emitting diodes respectively associated with three primary colors and emitting a part of their signal in the direction of the base substrate. The device includes three chromatic photodetectors formed in the base substrate constituting a semiconducting substrate, and each arranged under an associated light-emitting diode. Each chromatic photodetector includes superposed first, second and third layers. The first layer and third layer have a first type of conductivity and the second layer has a second type of conductivity. The device includes a control component connected to the chromatic photodetectors and to the light-emitting diodes to control the global color of the light emitted by the device. | 2009-02-12 |
20090040756 | Flameless Candle with Multimedia Capabilities - A flameless candle having speaker and lighting capability is provided. Multiple of such flameless candles can be used in a system to generate stereo or surround sound, as well as various lighting modes. The flameless candle or flameless candle system can have AM/FM radio functions, clock functions, alarm functions, etc., and can be used as an audio monitor. In addition, the flameless candle or candle system may be equipped with video capability. | 2009-02-12 |
20090040757 | MIXED LIGHT APPARATUS - A mixed light apparatus for mixing light emitted from a first light source and a second light source includes a body, a first light reflecting element and a second light reflecting element. The body has a light emitting surface. A first reflecting element extends from the light emitting surface. The first light reflecting element has a first emanating point and a first focal point. The first light source is disposed at the first focal point. A second reflecting element extends from the light emitting surface. The second light reflecting element has a second emanating point and a second focal point. The second light source is disposed at the second focal point. The first emanating point and the second emanating point overlaps and are disposed on the light emitting surface. | 2009-02-12 |
20090040758 | Lighting assembly - A lighting assembly is adapted to be connected to at least one conductive connection hole of an illumination device. The lighting assembly comprises at least one lighting cell and connection mechanism, wherein the lighting cell comprises a base, at least one electrical connector and a lighting unit. The electrical connector and the lighting unit are connected to the base, and electrically connected with each other. The lighting unit has a plurality of lighting circuits linearly arranged thereon, and one end of the connection mechanism is electrically connected to the electrical connector. When the lighting assembly only comprises one lighting cell, the other end of the connection mechanism is connected to the electrode connection hole; while when the lighting assembly comprises a plurality of said lighting cells, the other end of the connection mechanism is selectively connected to the conductive connection hole and the other electrical connector of the neighbor lighting cell. | 2009-02-12 |
20090040759 | LED LAMP WITH A HEAT SINK ASSEMBLY - An LED lamp includes a hollow first heat sink ( | 2009-02-12 |
20090040760 | ILLUMINATION DEVICE HAVING UNIDIRECTIONAL HEAT-DISSIPATING ROUTE - An illumination device having an unidirectional heat-dissipating route, includes a heat sink and a LED light module. The heat sink includes a heat plate, a heat pipe and a heat-dissipating body. The heat pipe has a heat absorbing portion and a heat dissipating portion with a horizontal position different to that of the heat absorbing portion. The heat absorbing portion is connected to the heat plate, and a plurality of grooves is formed in the heat pipe to be communicated with the heat absorbing portion and the heat dissipating portion. The heat absorbing portion is lower than the heat dissipating portion. The heat-dissipating body is connected to the heat dissipating portion. The LED light module is connected to the heat plate. Thus the LEDs are protected and prevented from being destroyed by the heat, and the working life thereof is increased greatly. | 2009-02-12 |
20090040761 | Acoustic wave induced light emitting golf ball - A light emitting golf ball is provided that includes a spherical housing, a fixing container, a light emitting device, a first fitting portion, and a second fitting portion. The light emitting device is disposed in the fixing container and includes an acoustic wave sensor, a controller, one or more light emitting elements and an electricity supplier. When the acoustic wave sensor receives an external acoustic wave signal higher than a predetermined value, it sends out an activating signal to the controller so that at least one light emitting element emits light. This invention is irrelevant to the hitting direction. It has an extremely low defective rate. Furthermore, the product life can be prolonged. | 2009-02-12 |
20090040762 | Rotating Light-Emitting Structure for a Shower Head - A rotating light-emitting structure for a shower head comprises a housing provided for accommodation of a coverture and a light-emitting device. The coverture integrally encloses the light-emitting device. The coverture and the light-emitting device are coaxially pivoted in the housing. The liquid flows in the housing and sprays from the housing to impact the coverture, so as to make the coverture and the light-emitting device rotate coaxially. The light-emitting device rotates to generate electricity for illumination. By such arrangements, when the power is cut off, the rotating light-emitting structure for a shower can emit light for illumination without using batteries or other power sources. | 2009-02-12 |
20090040763 | Light Source - A light source for fluorescence microscopy is designed to provide relatively constant illumination (lumens) of the specimen over the useful life of the light generator, such as the bulb, arc, or filament. In another aspect, the present invention provides for a light source for fluorescence microscopy designed to reduce heat transmission to optical components from the light generator, while providing adequate transmission of the required excitation wavelengths of light. | 2009-02-12 |
20090040764 | METHOD AND APPARATUS FOR INDUCING DAZZLE - There is disclosed a method and apparatus for successively and repeatedly illuminating a number of remote areas collectively defining a larger area with light in the form of a beam or beams to induce a physiological blink response or optical blink reflex in the illuminated eye of an animal (e.g., a human) within the area being illuminated. Each area being intermittently illuminated long enough to induce a blink response from an animal (e.g. human) subject there, after which another area(s) is illuminated in the meantime while illumination of the initial area is not required since the subject(s) there would still be recovering from their blink response. | 2009-02-12 |
20090040765 | LAMP ASSEMBLY COMPRISING A HIGH-PRESSURE GAS DISCHARGE LAMP - A lamp assembly comprising a high-pressure gas discharge lamp ( | 2009-02-12 |
20090040766 | Light Module - A light module has at least one light source mounted on a base, especially an LED, a housing to accommodate the base, an electrical connection element for power supply of at least one light source. An outer line of the connection element is formed by the housing, and an inner line, especially center line, of the connection element, which is at least partially enclosed by the outer line, contacts the base. | 2009-02-12 |
20090040767 | Recognition Module - A recognition module is applied in recognizing counterfeit of a card or a face of the card. The recognition module includes a sealed space, a light emitter, a light receiver and a transparent dustproof plate. The sealed space has two corresponding side inclinations and a transparent cover surface which covers two side inclinations. The light emitter and the light receiver are disposed to the side inclinations respectively. Moreover, the transparent dustproof plate is disposed on the light emitter and the light receiver, and is also disposed under the transparent cover surface. Accordingly, the light emitter and/or the light receiver may not be covered by dust and mists to influence the light-transmitting/receiving efficiency. The recognition rate regarding counterfeit of the card or the face of the card may not be influenced either. | 2009-02-12 |
20090040768 | LIGHT GUIDE PLATE AND DIRECT-TYPE BACKLIGHT MODULE WITH SAME - An exemplary backlight module includes a light guide plate and light sources. The light guide plate includes a block body and the recessed parts. The block body has a top light output surface and a bottom surface. The recessed parts are provided at the bottom surface. The light sources are disposed at least partly in or adjacent to the recessed parts. | 2009-02-12 |
20090040769 | Free-Form Lenses for Rectangular Illumination Zones - A light source emits light into a solid angle exceeding pi steradians with a known intensity distribution. An illumination lens has a first surface that receives at least 90% of the light of the known intensity distribution and has a shape that transforms the known intensity distribution into an intermediate intensity distribution within the transparent material of the lens. A second surface receives the intermediate intensity distribution and is shaped to transform the intermediate intensity distribution into a final intensity distribution that produces a prescribed illumination distribution upon a rectangular target zone. At least one of the shapes of the first and second surfaces is non-rotationally symmetric and is approximated by a super-ellipsoid. | 2009-02-12 |
20090040770 | Light Source Reflector - A light source reflector includes a conical reflective surface, and a flat reflective surface formed on a rim of the conical reflective surface. The conical reflective surface has a plurality of unit curved surfaces with convex surfaces or concave surfaces. Also, the flat reflective surface is provided with a plurality of refraction protrusions, to improve the optical efficiency and light-mixing effect of the light source reflector. | 2009-02-12 |
20090040771 | Thin light guiding plate and methods of manufacturing - The present invention provides a composite light guiding plate comprising a light guiding layer comprising an incident face for receiving light from at least one light source, a light guiding output surface that is also generally orthogonal to the incident face, a featured surface, opposite the light-guiding output surface and generally orthogonal to the input face for redirecting light through the light guiding output surface. Further, the featured surface comprises a plurality of rows of linear prismatic structures extended in a length direction that is substantially perpendicular to the incident face and having height and width dimensions of 10 to 200 microns and wherein the length-to-width aspect ratio of the linear prismatic structures is greater than 100:1 the thickness of the light guiding layer is less than 1 mm. Further, the plate is formed from polymeric materials comprising polyesters, amorphous polyesters, polyarylates, polycarbonates, polyamides, polyether-amides, polyamide-imides, polyimides, polyetherimides, cyclic olefin polymers, impact-modified polymethacrylates, polyacrylates, polyacrylonitrile, polystyrenes, polyethers, cellulosics, sulfur-containing polymers and blends or alloys of two or more polymers or copolymers thereof. Additionally, the plate comprises a light extraction layer comprising an input surface having a plurality of protruding light extraction features that have tips that are bonded to the light-guiding output surface of the light guiding layer and provide optical contact between the light guiding and light extraction layers and an illumination output surface for providing light output from the composite illumination plate. Further, the thickness of the light extraction layer is less than 1 mm and wherein one or more channels of air or other gas are sandwiched between the light guiding layer and the light extraction layer. | 2009-02-12 |
20090040772 | Optical element comprising restrained asymmetrical diffuser - The present invention provides an optical element having an optical film, the optical element comprising a support frame having a shaft therein, the support frame being provided around a perimeter of the optical element and the optical film having slots on a periphery thereon, the periphery of the optical film being provided on the support frame. The invention further provides a pin provided in each of the slots and protruding into the support frame and slidable on the shaft by a controlled tensile force and a spring mechanism that is slidable on the shaft for providing the controlled tensile force to the optical film, wherein the optical film is an asymmetric diffuser. | 2009-02-12 |
20090040773 | Lamp housing, particularly spotlight housing - A lamp housing which contains an accommodating apparatus for a burner or a lamp with a glass vessel, a lamp base and contact pins for supplying current, and a lampholder with sockets for connection to the contact pins, is provided. The accommodating apparatus containing clamping jaws, which can be connected to the lamp base in a force-fitting and/or interlocking manner, engage at least partially around the lamp base, are articulated, via lever arms, on the lamp housing or a lampholder mount, which is fixed to the housing and is connected to the lamp housing, and can be adjusted by means of an adjusting device, which has at least one adjusting element, which is arranged between the lever arms and pushes the lever arms apart from one another for opening the clamping jaws into an opening position, in which the lamp base is released, and brings the lever arms together for closing the clamping jaws into a locking position, in which the lamp base is fixed. | 2009-02-12 |
20090040774 | LIGHTING FIXTURE - A lighting fixture has a modular design. A plurality of interconnecting components fit together to impart to the lighting fixture multiple degrees of rotation. This enables the installer or user to effectively move, change, or adjust the area of illumination over time without constraints. A lamp housing is supported by a plurality of tubular arms that have a threaded connection at one end and a slip-fit connection at the other end. These connections enable the arms to be rotated independently of each other. The result is a lighting fixture having multiple degrees of rotation. An enclosed path through the tubular arms and a hinge leads from a J-box to the lamp housing. The enclosed path accommodates electrical wiring to power the lighting fixture, while the hinge enables the lamp housing to rotate about an axis parallel to the mounting surface. | 2009-02-12 |
20090040775 | ENCLOSURE FOR HOUSING A PLURALITY OF PIXELS OF A GRAPHICAL DISPLAY - An enclosure is provided for housing pixels of a graphical display. The enclosure provides one or more laminar structures at a first surface of the enclosure. The laminar structure may be made up of a first material of a predetermined thickness at the first surface and a second material in sufficiently close proximity with the first material to allow heat conduction. The second material preferably has a thermal conductivity greater than the thermal conductivity of the first material. Thermal conductors are provided in or attached to the second material in the laminar structure to conduct heat to a second surface of the enclosure. The first material may be, for example, a polymer. The second material may be, for example, a heat wick, a metal mesh or heat pipes. The second surface may be cooled by an air stream, which may also reduce humidity at the surface. | 2009-02-12 |
20090040776 | LED LAMP WITH A HEAT DISSIPATION DEVICE - An LED lamp includes a heat sink ( | 2009-02-12 |
20090040777 | PHOSPHORESCENT CHARGING SYSTEM FOR WHEELED VEHICLES HAVING PHOSPHORESCENT WHEELS - Various phosphorescence charging systems are provided for charging a phosphorescent wheel. The wheel is attached to the frame of a vehicle with nighttime or low light operation capability. The phosphorescence charging system directs electromagnetic radiation, such as ultraviolet light, onto phosphorescent portions of the wheel so as to cause subsequent phosphorescent emission therefrom. | 2009-02-12 |
20090040778 | IMAGE PICKUP DEVICE-EQUIPPED REAR-VIEW MIRROR - The present invention is intended to provide an image pickup device-equipped rear view mirror with improved image pickup performance, glare prevention and appearance (design) in addition to improved performance as a vehicle mirror. A mirror element is formed by forming a reflecting film consisting of high refractive index material films and a low refractive index material film on a back surface of a transparent glass substrate. The integrating sphere reflectance of the mirror element in the visible range is 40% to 60% and the near-infrared transmittance is no less than 70% for the whole or part of the band belonging to the near-infrared range within the entire sensitive wavelength range of the near-infrared camera. A black mask member is attached to an entire back surface of the reflecting film. The near-infrared camera is arranged behind the black mask member. The region corresponding to the area for the image-pickup by the near-infrared camera within the entire region of the black mask member is formed of a visible-light absorption and near-infrared transmission filter. The near-infrared transmittance of the visible-light absorption and near-infrared transmission filter is no less than 70% for the whole or part of the band belonging to the near-infrared range within the entire sensitive wavelength range of the near-infrared camera. | 2009-02-12 |
20090040779 | Headlight Unit and Straddle-Type Vehicle - A headlight unit includes a reflector that is concave in shape and has left and right reflection surfaces for reflecting light emitted by a headlight bulb in a desired direction. Protection covers cover outer edge sections of the reflector and have a color different from that of the left and right reflection surfaces. | 2009-02-12 |
20090040780 | Independent Lighting Energy Interruption System With Energy Subdivisioning And Method - An auxiliary lighting energy interruption system for use with snow plows and like front-mounted vehicle accessories is disclosed which facilitates the interconnection of such systems to the lighting system of a vehicle upon which the vehicle accessory is mounted to provide power to and to control the auxiliary lights with the lighting system of the vehicle. The system provides first and second harness portions for respective installation on the vehicle and the vehicle accessory, with the first harness portion having a first configuration when it is not connected to the second harness portion and a second configuration when it is connected to the second harness portion. The first configuration allow the headlights on the vehicle to operate, while the second configuration allows only the headlights on the vehicle accessory to operate, with changes between the first and second configurations being accomplished without the need for a switch or a relay. Resistors may be used to provide an electrical connection between the vehicle lights and the vehicle lighting system even if they are not to be illuminated by the system. | 2009-02-12 |
20090040781 | OPTICAL FIBER LIGHTING APPARATUS - An optical fiber lighting apparatus includes an exciting light source, a first optical fiber, a second optical fiber, and a wavelength conversion unit. The first optical fiber guides the exciting light emitted from the exciting light source. The wavelength conversion unit receives the exciting light exiting from the first optical fiber to generate a wavelength-converted light having a wavelength different from that of the exciting light. The second optical fiber guides at least part of the wavelength-converted light generated by the wavelength conversion unit. | 2009-02-12 |
20090040782 | LED LIGHTING DEVICE - An LED lighting device includes a light pipe and a support portion. The light pipe includes a light emitting diode module inside and two first fastening portions on an outer wall thereof. A support portion secures the light pipe and provides a rotatable function for the light pipe. The support portion further includes a clamp and a base member. A clamp has two second fastening portions at opposite sides thereof. The second fastening portions engage with the first fastening portions. The clamp further includes a strip hollow slot. A base member includes a pair of positioning portions for holding an outer wall of the clamp, wherein a fastener is led through the strip hollow slot and fastened on the base member. The clamp slides relative to the base member along the strip hollow slot such that the light pipe rotates relative to the base member. | 2009-02-12 |
20090040783 | Compact, high efficiency, high power solid state light source using a single solid state light-emitting device - A compact, high-efficiency, high-power, solid state light source, comprising a high-power solid state light-emitting device, a light guide having a proximal light-receiving end proximate the light-emitting device and a distal light-transmitting end spaced farther from the light-emitting device, and a mechanical light guide fixing device coupled to the light guide near its proximal end, to hold the proximal end of the light guide in position near the light-emitting device. | 2009-02-12 |
20090040784 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE - A light guide plate (LGP) adapted to a backlight module having a light emitting surface, a bottom surface opposite to the light emitting surface, and at least one light incident surface contacting with the light emitting surface and the bottom surface is provided. The bottom surface has a plurality of flat surfaces and a plurality of groove groups. The groove groups and the flat surfaces are arranged in an alternating fashion. Each of the groove groups has at least two grooves. Each of the grooves has a first slanted surface, a peak, and a second slanted surface intersecting with the first slanted surface at the peak. In each of the grooves, a first side of the first slanted surface away from the peak is at a first distance from a second side of the second slanted surface away from the peak. The luminance efficiency of the LGP is better. | 2009-02-12 |
20090040785 | Spread illuminating apparatus - A transparent resin plate includes a plurality of slits formed intermittently and located along the border line between a housing frame portion and a light conductor plate portion, the slits includes either or both of respective first optical path converting portions and a second optical path converting portion, and flap portions of a reflector are inserted at least in the first optical path converting portions. Also, the second optical path converting portion of the plurality of slits is arranged to meet at least part of optical paths of hypothetical optical paths which are emitted forward from a light source in the forward direction, reach directly the housing frame portion and which do not cross the first optical path converting portion. | 2009-02-12 |
20090040786 | SURFACE LIGHT SOURCE APPARATUS AND DISPLAY APPARATUS - An object is to provide a surface light source apparatus excellent in uniformity of brightness and chromaticity without being affected by variations in performance between point light sources, or a display apparatus using the surface light source apparatus. A surface light source apparatus according to the present invention includes a plurality of point light sources, a first light guide body that propagates light received from the plurality of point light sources and emits the same from an outgoing surface, and a second light guide body that receives the light emitted from the outgoing surface of the first light guide body at an incident surface to propagate, and emits the same from an outgoing surface substantially perpendicular to the incident surface, wherein at least some of the plurality of point light sources are arrayed in a direction substantially perpendicular to the outgoing surface of the first light guide body. | 2009-02-12 |
20090040787 | PLANAR ILLUMINATION DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME - A thin planar illumination device with a high light utilization efficiency is provided. In a planar illumination device | 2009-02-12 |
20090040788 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE USING THE SAME - A light guide plate has a bottom surface including flat surfaces (FSs) and a plurality of prism patterns (PPs) disposed alternately with the FSs, a light emitting surface (LES) and a light incident surface (LIS). Each FS is at a first distance respectively from the LES and the first distances gradually decrease along a direction away from the LIS. Each PP has a first slanted surface (FSS) and at least a groove having a second slanted surface (SSS) and a third slanted surface (TSS). The two opposite sides of the FSS are spaced out a second distance apart. The two opposite sides of the SSS are spaced out a third distance apart. The specific value of dividing a first orthogonal projection of the second distance on an axis perpendicular to the FSs by a second orthogonal projection of the third distance on the axis is between 0.5 and 1.5. | 2009-02-12 |
20090040789 | LIGHTING DEVICE - In the lighting device, cylindrical lenses are provided on a reflection surface side of a light guide plate, and the adjacent cylindrical lenses are connected by a concaved curved surface. | 2009-02-12 |
20090040790 | SIDE CURED LIGHT-TRANSMISSIVE DISPLAY SYSTEM - An invisible, light-transmissive display system with a light resistant material is provided. The light resistant material has a first side and a second side. Substantially invisible holes penetrate between the first surface and the second surface in a predetermined light-transmissive display pattern. The second surface is exposed to a side curing light that is substantially parallel to the second surface at the invisible holes thereadjacent. A light-conducting curable filler is applied into the invisible holes from the first surface. Surfaces of the light-conducting curable filler are cured in the invisible holes at the second surface with the side curing light. The remaining curable filler in the invisible holes is cured. | 2009-02-12 |
20090040791 | ENHANCEMENT OF POWER CONVERSION EFFICIENCY USING DYNAMIC LOAD DETECTING AND TRACKING - A switching mode power converter may include a modulation circuit to dynamically control a variable switching frequency of the power converter based on an error voltage of the power converter. The power converter may also include a control circuit connected to the modulation circuit and arranged to dynamically limit an inductor current in the power converter while the switching frequency of the power converter changes. A variable limit on the inductor current may be based on the error voltage of the power converter, a load current of the power converter, or information from a power manager of a system in which the power converter resides. In some implementations, the power converter may also include a disabling circuit to control the modulation circuit to disable the variable switching frequency when a sufficiently large load transient is detected. | 2009-02-12 |
20090040792 | SYNCHRONOUS RECTIFYING CIRCUIT FOR RESONANT POWER CONVERTERS - A synchronous rectifying circuit is provided for resonant power converter. An integrated synchronous rectifier comprises a rectifying terminal, a ground terminal a first input terminal and a second input terminal. The rectifying terminal is coupled to the secondary side of a power transformer. The ground terminal is coupled to the output of the power converter. A power transistor is connected between the rectifying terminal and the ground terminal. The first input terminal and the second input terminal are coupled to receive a pulse signal for turning on/off the power transistor. A pulse-signal generation circuit includes an input circuit coupled to receive the switching signal for switching the power transformer of the power converter. | 2009-02-12 |
20090040793 | Start-up time reduction in switching regulators - A start-up time accelerator is described for a switch controller that controls turning on or off a switch in a switching regulator. The start-up time accelerator uses the switch as a current amplifier and provides the amplified current to a capacitor using a current amplification path. In one example, the capacitor provides the bias voltage to a switch controller for the switch. Providing an amplified current to the capacitor accelerates the rate at which the bias voltage increases and reduces the time until the bias voltage reaches the turn-on threshold voltage of the switch controller. After the turn-on threshold voltage of the switch controller is reached, a second path is enabled for current to and from the capacitor and the capacitor provides the bias voltage to the switch controller until a voltage from an output voltage terminal is sufficiently high to provide the bias voltage for the switch controller through an auxiliary winding of a transformer. | 2009-02-12 |
20090040794 | Time-Multiplexed Multi-Output DC/DC Converters and Voltage Regulators - A boost switching converter with multiple outputs includes an inductor is connected between an input supply (typically a battery) and a node V | 2009-02-12 |
20090040795 | METHOD AND APPARATUS FOR INCREASING THE POWER CAPABILITY OF A POWER SUPPLY - Techniques are disclosed to extend an on time period of switch to regulate a transfer of energy from an input of a power supply to an output of a power supply. One example integrated circuit includes an energy transfer element coupled between an input and an output of the power supply. A switch is coupled to the input of the energy transfer element. A controller is coupled to the switch to control switching of the switch to regulate a transfer of energy from the input of the power supply to the output of the power supply in response to a feedback signal received from the output of the power supply. The controller is coupled to limit a maximum on time period of the switch a first maximum on time period in response to a first range of power supply operating conditions and to a second maximum on time period for a second range of power supply operating conditions. | 2009-02-12 |
20090040796 | BIPOLAR TRANSISTOR DRIVERS - We describe a switching power converter comprising a bipolar switching device (BJT or IGBT) switching an inductive load, and including a closed-loop control system. The control system comprises a voltage sensing system to sense a voltage on a collector terminal of the switching device and provide a voltage sense signal; a controller; and a drive modulation system coupled to an output of the controller for modulating a drive to the control terminal of said bipolar switching device responsive to a controller control signal; wherein said controller is configured to monitor changes in the sensed voltage during a period when said switching device is switched on and to control said drive modulation system to control the degree of saturation of said bipolar switching device when the device is switched on and hence improve turn-off times. | 2009-02-12 |
20090040797 | Pulse Width Modulation Method for a Power Converter - A pulse width modulation method has the steps of operating a second instruction signal so that each of the differences between two or three arbitrary instruction signals in three first instruction signals may become more than the predetermined value, and modulating in pulse width based on the second instruction signal. | 2009-02-12 |
20090040798 | SWITCHING MODE POWER SUPPLY APPARATUS AND POWER SUPPLY METHOD THEREOF - A switching mode power supply apparatus includes a conversion unit to convert input power into output power having a predetermined voltage by performing a switching operation; a light emitting unit to emit light if the voltage of the output power exceeds a predetermined threshold voltage; a light receiving unit to receive the light emitted from the light emitting unit and output a signal indicative of the voltage of the output power; a switching controller to control the switching operation of the conversion unit according to the voltage of the output power indicated by the signal output from the light receiving unit; and a disconnection unit to disconnect power applied to the light receiving unit if a voltage of the power applied to the light receiving unit exceeds a predetermined trigger voltage. | 2009-02-12 |
20090040799 | Universal Energy Supply System - A universal energy supply system for at least one electrical consumer comprises at least one AC voltage source and a cable connection connecting the source with the electrical consumer, wherein an AC/DC converting means is assigned to the AC voltage source for converting the AC voltage into DC voltage which DC voltage can be supplied to the electrical consumer via the cable connection. To improve such a universal energy supply system in that with small constructional efforts and with low costs, the energy supply to an electrical consumer is guaranteed also over great distances and the corresponding voltage supply is stabilized, the efficiency being relatively high at the same time and the system being redundant, the AC/DC conversion means comprises a number of AC/DC converting units which are connected in parallel with the AC voltage source on the input side and are serially connected to the electric consumer on the output side, each converting unit being constructed as a blocked switch mode power supply. | 2009-02-12 |
20090040800 | Three phase rectifier and rectification method - A method for converting a three-phase AC voltage to a regulated DC voltage using a three-phase rectifier is disclosed. Both the positive and negative DC currents are controlled, but the inner phase is not controlled. In one embodiment, the AC to DC converter utilizes a three-phase rectifier with low-speed diodes, three low-speed bidirectional switches, two high-speed diodes, two high-speed unidirectional switches, three inductors on the AC side, and two capacitors connected in series. | 2009-02-12 |
20090040801 | Content Addressable Memory - A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance. | 2009-02-12 |
20090040802 | SEMICONDUCTOR MEMORY DEVICE, MEMORY-MOUNTED LSI AND FABRICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes a memory cell array block having one or more stages of memory cell arrays stacked one on another, each memory cell array including a plurality of memory cells placed in a matrix at respective intersections of a plurality of word lines and a plurality of bit lines. A plurality of MOS transistor blocks are provided which are same in the configuration of circuit elements and include MOS transistors as one kind of the circuit elements. In part of the plurality MOS transistor blocks, the MOS transistors are used for drive of the word lines or the bit lines, while in at least part of the remaining MOS transistor blocks, the MOS transistors are used as MOS capacitors. | 2009-02-12 |
20090040803 | Semiconductor Memory and Method for Operating a Semiconductor Memory - A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields. | 2009-02-12 |
20090040804 | FUSE CIRCUIT - A fuse circuit in accordance with one embodiment of the present invention includes a first power supply liner a second power supply liner a current source connected between the first power supply line and an output terminal, a first transistor having a drain or a collector connected to the output terminal, the first transistor having a current supply capability or a current draw capability larger than that of the current source for the output terminal, a second transistor having a gate or a base connected in common with the gate or the base of the first transistor, a first resistive element and a fuse connected in series between the source or the emitter of either one of the first or second transistor and the second power supply line, and a second resistive element connected between the source or the emitter of the other one of the first or second transistor and the second power supply line. | 2009-02-12 |
20090040805 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation. | 2009-02-12 |
20090040806 | Reading circuit and method in a data-storage system - A reading circuit for reading a datum stored in a storage material. In the reading circuit, a generating stage generates a read electrical quantity to be applied to the storage material, and a sensing stage is configured to generate an output electrical quantity that is indicative of a charge variation associated to the datum stored, and that occurs in the storage material due to application of the read electrical quantity; in particular, the sensing stage uses a charge-sensing amplifier electrically connected to the storage material. | 2009-02-12 |
20090040807 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading. | 2009-02-12 |
20090040808 | Nondestructive methods of reading information in ferroelectric memory elements - The method of nondestructive data reading from the ferroelectric memory cell supplied with the electrodes was developed. This method implies supply of reading electric voltage to the memory element electrodes with the view of generation of resilience in the ferroelectric memory cell and registration of the resilience by the field transistor with the floating gate and/or by the conductive channel made from the material with the piezoelectric properties, and according to the value of the current running through the transistor degree and character of ferroelectric cell polarization are identified. | 2009-02-12 |
20090040809 | STORAGE DEVICE - A storage device includes: a wiring including a first conductor with a first conductivity; and first, second and third contacts, each including a second conductor with a second conductivity and contacting the wiring. The storage device also includes: a write switching circuit controlling current for writing information that flows through the first contact, the wiring, and the second contact, and changing resistance values of the first contact to write information; and a read switching circuit controlling current for reading information that flows through the first contact, the wiring, and the third contact. | 2009-02-12 |
20090040810 | SWITCHED CAPACITOR DRAM SENSE AMPLIFIER WITH IMMUNITY TO MISMATCH AND OFFSETS - A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals. | 2009-02-12 |
20090040811 | PHASE CHANGE MEMORY DEVICE HAVING MULTIPLE RESET SIGNALS AND OPERATING METHOD THEREOF - A phase change memory device includes a cell array unit having a phase change resistance cell positioned at an intersection of a word line and a bit line. A write driving unit is configured to generate a single write voltage to the cell array unit when data to be written is a first data and is configured to generate a plurality of write voltages selectively when the data is a second data. | 2009-02-12 |
20090040812 | PHASE CHANGE MEMORY DEVICE HAVING WRITE DRIVING CONTROL SIGNAL CORRESPONDING TO SET/RESET WRITE TIME - A phase change memory device includes a phase change resistance cell configured to sense a crystallization state that changes in response to a current so that data corresponding to the crystallization state can be stored in the phase change resistance cell. A write driving control signal generating unit outputs a write enable signal and a precharge enable signal in response to a write control signal that corresponds to a heating period and a quenching period of the write data. A write driving unit is configured to supply a driving voltage corresponding to the write data to the phase change resistance cell in response to the write enable signal and the precharge enable signal. | 2009-02-12 |
20090040813 | PHASE CHANGE MEMORY DEVICE AND OPERATING METHOD THEREOF - A phase change memory device and operation is described where the phase change memory device includes a phase change resistance cell storing data corresponding to a sensed crystallization state. The phase change memory device operates by reading data of a selected phase change resistance cell when in a write mode. The data to be written is compared to the read data. If the read data is different from the data to be written, it is determined whether the data to be written is a first data. An operation writing and verifying the first data in the cell under a first operating condition when the is data to be written is the first data is then performed. After performing verification, if the read data is different from the first data, the first data is written and verified in the selected phase change resistance cell under a second operating condition. | 2009-02-12 |
20090040814 | METHOD FOR DRIVING MULTI-LEVEL DATA TO A PHASE CHANGE MEMORY DEVICE - A phase change memory device including a phase change resistor senses a crystallization state that is changed according to supplied currents to store data corresponding to the crystallization state. The phase change memory device may receive and store multi-level data. The multi-level data is driven to the phase change memory device by reading cell data of a selected cell. The cell data is compared to multi-level data to be written to the cell. A high resistance reset state is written to the phase change resistor by applying a write voltage that corresponds to a threshold voltage when the cell data is different from the multi-level data. The multi-level data is then written to the phase change resistor by writing and verifying a set state that corresponds to the multi-level data. | 2009-02-12 |
20090040815 | PHASE CHANGE MEMORY DEVICE USING A MULTIPLE LEVEL WRITE VOLTAGE - A phase change memory device using a multiple level write voltage is described. The phase change memory device includes a cell array unit including a phase change resistance cell positioned at an intersection of a word line and a bit line. A voltage selection adjusting unit is configured to select one of a plurality of multiple voltages in response to a voltage adjusting signal to output a driving voltage. A write driving unit is also configured to finely adjust the voltage level of the driving voltage in response to a voltage fine-adjusting signal to supply the driving voltage to the cell array unit. | 2009-02-12 |
20090040816 | METHOD FOR DRIVING A PHASE CHANGE MEMORY DEVICE USING VARIOUS WRITE CONDITIONS - A phase change memory device includes a phase change resistor configured to sense a change in crystallization state due to current flow in order to store data that corresponds to the crystallization state. The phase change memory device is driven by reading cell data of a selected unit cell using a reference current. The cell data is compared to write data and then it is determined whether the write data is set data or reset data if the cell data is different from the write data. The set or reset state is written to the cell and verified during a write and verification operation under various conditions to stably write the data. | 2009-02-12 |
20090040817 | METHOD FOR EFFICIENTLY DRIVING A PHASE CHANGE MEMORY DEVICE - A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing. The phase change memory device has a resistor configured to sense a crystallization state changed by currents so as to store data corresponding to the crystallization state. The writing operation writes data having a first state in a corresponding unit cell of the phase change memory device. The reading operation reads a cell data stored in the unit cell. The comparing operation compares the data having the first state with the cell data read from the unit cell to verify whether or not the data having the first state is the same as the cell data. The changing operation changes a write condition when the data having a first state is different from that of the cell data. | 2009-02-12 |
20090040818 | TIME EFFICIENT PHASE CHANGE MEMORY DATA STORAGE DEVICE - A phase change memory device is presented that includes a phase change resistance cell array and a cache register. The phase change resistance cell array includes a phase change resistor configured to sense crystallization changed depending on currents so as to store data corresponding to resistance change. The cache register is configured to store a plurality of data applied externally depending on a register write command and to simultaneously output the plurality of data to the phase change resistance cell array depending on a cell write command. | 2009-02-12 |
20090040819 | NONVOLATILE MEMORY DEVICE USING RESISTIVE ELEMENTS AND AN ASSOCIATED DRIVING METHOD - A nonvolatile memory device is configured to increase the reliability of a write operation by providing a sufficiently high write current while reducing current consumption in a read operation. The nonvolatile memory device includes a memory cell array having a plurality of nonvolatile memory cells. A global bit line and a local bit line coupled to a plurality of the nonvolatile memory cells. The local bit line has first and second nodes. First and second bit line selection circuits are included where the first bit line selection circuit is coupled to the first node of the local bit line and the second bit line selection circuit is coupled to the second node of the local bit line. The first and second bit line selection circuits operate during a first period to electrically connect the local bit line to the global bit line, and only one of the first and second bit line selection circuits operates during a second period to electrically connect the local bit line to the global bit line. | 2009-02-12 |
20090040820 | Phase Change Memory - A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units, is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least, one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result. | 2009-02-12 |
20090040821 | LOW POWER MULTIPLE BIT SENSE AMPLIFIER - A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data. | 2009-02-12 |
20090040822 | FLASH MEMORY DEVICE HAVING SINGLE PAGE BUFFER STRUCTURE AND RELATED PROGRAMMING OPERATIONS - A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided. | 2009-02-12 |
20090040823 | FLASH MEMORY - A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on. | 2009-02-12 |
20090040824 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of a word lines. The word lines have a set of odd word lines and a set of even word lines. The odd and the even word lines are located from a first end region to a second end region through the cell region located between the first and the second end regions. The odd word lines are divided in the first end region and the even word lines are divided in the second end region to form dummy word line portions. | 2009-02-12 |
20090040825 | NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY - Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time. | 2009-02-12 |
20090040826 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller. | 2009-02-12 |
20090040827 | Flash memory device for remapping bad blocks and bad block remapping method - Provided are a flash memory device and a bad block remapping method thereof. The flash memory device includes: an address storage block detecting whether a block address provided from the outside is identical to an already stored block address, and then generating a repair signal according to a detection result; and an encoder converting the repair signal into a block select signal in order to select the normal memory block. | 2009-02-12 |
20090040828 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second memory cell blocks, a block decoder, and first and second block switches. The first and second memory cell blocks have a plurality of memory cells connected in a string structure and are respectively disposed in neighboring planes. The block decoder outputs first and second block select signals in response to pre-decoded address signals and first and second plane select signals, which are respectively enabled according to an enable state of the planes. The first and second block switches connect global word lines to word lines of the first and second memory cell blocks in response to the first and second block select signals, respectively. | 2009-02-12 |
20090040829 | LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES - A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes. | 2009-02-12 |
20090040830 | BLOCK DECODER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal. | 2009-02-12 |
20090040831 | METHOD OF PROGRAMMING IN A FLASH MEMORY DEVICE - A method of programming in a flash memory device is disclosed. The method includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, verifying whether or not the first memory cell is programmed through a first verifying voltage, and programming the first memory cell using a program voltage increased in sequence by a step voltage than the first program voltage in case that the first memory cell is not programmed programming a second memory cell coupled to an odd bit line by applying the first program voltage to the word line, and verifying whether or not the second memory cell is programmed through a second verifying voltage higher than the first verifying voltage, and programming the second memory cell using a program voltage increased in sequence by the step voltage than the first program voltage in case that the second memory cell is not programmed. | 2009-02-12 |
20090040832 | SOFT PROGRAM METHOD IN A NON-VOLATILE MEMORY DEVICE - A soft program method in a non-volatile memory device for performing a soft program step so as to improve threshold voltage distribution of an erased cell is disclosed. The soft program method in a non-volatile memory device includes performing a soft program for increasing threshold voltages of memory cells by a given level, wherein an erase operation is performed about the memory cells, performing a verifying operation for verifying whether or not a cell programmed to a voltage more than a verifying voltage is existed in each of cell strings, and performing repeatedly the soft program until it is verified that whole cell strings have one or more cell programmed to the voltage more than the verifying voltage. | 2009-02-12 |
20090040833 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - Provided are a non-volatile memory device and a programming method. The programming method includes applying a program voltage to a selected word line, applying an elevated pass voltage to word lines adjacent to the selected word line in a plurality of word lines, and applying a pass voltage to remaining word lines in the plurality of word lines. | 2009-02-12 |
20090040834 | SEMICONDUCTOR MEMORY DEVICE - A memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of a bit line. A sense amplifier initially charges a bit line in each control area in the memory cell array with a charging voltage controlled by a respective individual bit-line control signal. Bit-line control signal generator circuits are provided plural in accordance with the control areas in the memory cell array. Each bit-line control signal generator circuit receives the potential on a cell source line in a corresponding control area, individually generates and provides the bit-line control signal in the each control area in accordance with the received voltage on the cell source line in each control area. | 2009-02-12 |
20090040835 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line, and a sense amplifier of the current sense type. The sense amplifier includes an initial charging circuit capable of initially charging the bit line with a suppressed value of current only for a certain starting period during an initial charging period. The sense amplifier detects a value of current flowing in the bit line to decide data read out of each of the memory cells. | 2009-02-12 |
20090040836 | NAND flash memory device and method of programming the same - Provided are a NAND flash memory device and a method of programming the same. The NAND flash memory device may include a cell array including a plurality of pages; a page buffer storing program data of the pages; a data storage circuit providing program verification data to the page buffer; and a control unit. The control unit may program the pages and verify the pages using the program verification data following the programming of at least two of the pages. | 2009-02-12 |
20090040837 | System and method for reducing pin-count of memory devices, and memory device testers for same - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 2009-02-12 |
20090040838 | DELAY LOCKED OPERATION IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer. | 2009-02-12 |
20090040839 | READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION - Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells of the multi-cell memory devices can be iteratively disabled to render state distributions of remaining, non-disabled memory cells, non-overlapped. System components can measure distributions rendered non-overlapped to uniquely identify states of such distributions. Identified state distributions can subsequently be disabled to render other state distributions non-overlapped, and therefore identifiable. In such a manner, read errors associated with overlapped bit states of multi-cell memory devices can be mitigated. | 2009-02-12 |
20090040840 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF COMPENSATING FOR SIGNAL INTERFERENCE THEREOF - A semiconductor memory device includes a memory cell array including a plurality of memory cell array blocks, a plurality of pairs of first data lines for transceiving data with corresponding memory cell array blocks, a plurality of column selection signal lines disposed in an orthogonal direction to the pairs of first data lines, and a plurality of pairs of second data lines to transceive data with corresponding pairs of first data lines of the pairs of first data lines. The memory cell array includes a signal interference compensator that shifts a voltage level of a second data line signal of one of the pair of second data lines interfered by a column selection signal line, to a voltage level of a first data line signal of other of the pair of second data lines not interfered so as to compensate for a signal interference. | 2009-02-12 |
20090040841 | Method of Operating an Integrated Circuit Having at Least One Memory Cell - Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state. | 2009-02-12 |
20090040842 | Enhanced write abort mechanism for non-volatile memory - In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal. | 2009-02-12 |
20090040843 | Enhanced write abort mechanism for non-volatile memory - In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal. | 2009-02-12 |
20090040844 | OUTPUT CONTROL DEVICE - An output controller includes a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe (CAS) latency, each of the output enable signals having information relating to a delay time from an activation timing of a CAS signal; and an output driving signal generator for receiving the plurality of output enable signals corresponding to the preset CAS latency and outputting rising and falling output driving signals for controlling an output timing of data. | 2009-02-12 |
20090040845 | Column Path Circuit - A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal. | 2009-02-12 |
20090040846 | Programmable Control Block For Dual Port SRAM Application - A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle. | 2009-02-12 |