07th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090039446 | Semiconductor device with a high-k gate dielectric and a metal gate electrode - A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer. | 2009-02-12 |
20090039447 | FET Device with Stabilized Threshold Modifying Material - A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures. | 2009-02-12 |
20090039448 | THIN FILM TRANSISTOR, PIXEL STRUCTURE AND LIQUID CRYSTAL DISPLAY PANEL - A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low. | 2009-02-12 |
20090039449 | FINGERPRINT SENSING DEVICE HAVING FLEXIBLE PRINTED CIRCUIT BOARD SERVING AS SIGNAL TRANSMISSION STRUCTURE AND THE METHOD OF MANUFACTURING THE SAME - A fingerprint sensing device includes a chip substrate, a plurality of first connecting pads and a flexible printed circuit board. The chip substrate has a plurality of fingerprint sensing cells. The first connecting pads are respectively disposed on the fingerprint sensing cells and exposed from a top surface of the chip substrate. The flexible printed circuit board is disposed above the chip substrate and has a plurality of signal transmission structures exposed from a bottom surface of the flexible printed circuit board. The fingerprint sensing cells are respectively electrically connected to the signal transmission structures, and a top surface of the flexible printed circuit board serves as a contact surface for a finger so that sensed fingerprint signals of the finger are transmitted to the fingerprint sensing cells through the signal transmission structures. A method of manufacturing the fingerprint sensing device is also disclosed. | 2009-02-12 |
20090039450 | STRUCTURE OF MAGNETIC MEMORY CELL AND MAGNETIC MEMORY DEVICE - A structure of magnetic memory cell including a first anti-ferromagnetic layer is provided. A first pinned layer is formed over the first anti-ferromagnetic layer. A tunneling barrier layer is formed over the first pinned layer. A free layer is formed over the tunneling barrier layer. A metal layer is formed over the free layer. A second pinned layer is formed over the metal layer. A second anti-ferromagnetic layer is formed over the second pinned layer. | 2009-02-12 |
20090039451 | METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE - A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer. | 2009-02-12 |
20090039452 | EMBEDDED BONDING PAD FOR IMAGE SENSORS - A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer. | 2009-02-12 |
20090039453 | SEMICONDUCTOR LIGHT RECEIVING DEVICE - The present invention provides a semiconductor light receiving device that prevents local heat generation, has high-speed, high-sensitivity characteristics even at the time of an intensive light input, and exhibits high resistance to light inputs. The semiconductor light receiving device includes light absorption layers ( | 2009-02-12 |
20090039454 | SOLID-STATE IMAGE PICKUP DEVICE AND FABRICATION METHOD THEREOF - Provided is a solid-state image pickup device capable of suppressing deterioration of characteristic caused due to an antireflection film itself absorbing a light. In the solid-state image pickup device of the present invention, a plurality of color filters | 2009-02-12 |
20090039455 | Image sensor package with trench insulator and fabrication method thereof - The invention provides an image sensor package and a method for fabricating thereof. The package comprises a substrate having an image sensor device electrically connected to a metal layer thereon and a covering plate disposed over the substrate. A plurality of trench insulators is formed in the substrate, whereby the each trench insulator surrounds an isolation region each. A via hole is formed in the substrate within the isolation region and electrically connects to the metal layer to a solder ball thereby transmitting a signal from the image sensor device to an exterior circuit. | 2009-02-12 |
20090039456 | Structures and methods for forming Schottky diodes on a P-substrate or a bottom anode Schottky diode - This invention discloses bottom-anode Schottky (BAS) device supported on a semiconductor substrate having a bottom surface functioning as an anode electrode with an epitaxial layer has a same doped conductivity as said anode electrode overlying the anode electrode. The BAS device further includes an Schottky contact metal disposed in a plurality of trenches and covering a top surface of the semiconductor substrate between the trenches. The BAS device further includes a plurality of doped JBS regions disposed on sidewalls and below a bottom surface of the trenches doped with an opposite conductivity type from the anode electrode constituting a junction barrier Schottky (JBS) with the epitaxial layer disposed between the plurality of doped JBS regions. The BAS device further includes an ultra-shallow Shannon implant layer disposed immediate below the Schottky contact metal in the epitaxial layer between the plurality of doped JBS regions. | 2009-02-12 |
20090039457 | LOW CROSSTALK SUBSTRATE FOR MIXED-SIGNAL INTEGRATED CIRCUITS - An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip. | 2009-02-12 |
20090039458 | INTEGRATED DEVICE - A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured and the first component release from the exposed surface region of the substrate. | 2009-02-12 |
20090039459 | ISOLATION FILM IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation film is thicker than an isolation film of the cell region so that a parasitic transistor is not generated and a leakage current can be prevented. | 2009-02-12 |
20090039460 | DEEP TRENCH ISOLATION STRUCTURES IN INTEGRATED SEMICONDUCTOR DEVICES - A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic. | 2009-02-12 |
20090039461 | FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS - The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer. | 2009-02-12 |
20090039462 | EFUSE DEVICES AND EFUSE ARRAYS THEREOF AND EFUSE BLOWING METHODS - An exemplary embodiment of an efuse device is provided and comprises a plurality of word lines, at least one bit line, a plurality of cells, a plurality of first selection devices, and at least one second selection device. The word lines are interlaced with the bit line. The cells are disposed in an array, and each corresponds to one set of the interlaced word line and bit line. Each first selection device is coupled to one of the word lines, and the second selection device is coupled to the bit line. | 2009-02-12 |
20090039463 | FUSE BOX AND METHOD FOR FABRICATING THE SAME AND METHOD FOR REPAIRING THE SAME IN SEMICONDUCTOR DEVICE - A fuse box in a semiconductor device having a fuse line formed in a fuse line region to form a conductive pattern; wherein the conductive pattern has an empty space in the center thereof and a phase change material pattern in the empty space, and an insulation pattern formed over the fuse line to expose the phase change material pattern. | 2009-02-12 |
20090039464 | SEMICONDUCTOR DEVICE - To protect an internal circuit against ESD breakdown which is caused by exposure of a cut-off portion of a fuse, a separate ESD protection circuit is not provided for each fuse as before, but the internal circuit is efficiently protected by a small number of ESD protection circuits by connecting the ESD protection circuit to a pad arranged for each unit lattice which is set in correspondence with a portion shared by a plurality of fuses, for example, a common wiring connected to the plurality of fuses, and which is set in correspondence with a size of a contact surface of a charged jig, or the like, with a semiconductor chip. | 2009-02-12 |
20090039465 | ON-CHIP DECOUPLING CAPACITOR STRUCTURES - The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor. | 2009-02-12 |
20090039466 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than the first recessed portion and having a second depth from the main surface, and a third recessed portion provided in at least one of the plurality of first recessed portions and having a third depth from the bottom portion of the first recessed portion. The second recessed portion and the third recessed portion have the same depth, and a decoupling condenser is provided so as to fill the at least one of the first recessed portion and the third recessed portion provided therein, and an isolation insulating layer is provided so as to fill the remaining first recessed portions, and the second recessed portion is filled with a gate electrode. | 2009-02-12 |
20090039467 | ON-CHIP DECOUPLING CAPACITOR STRUCTURES - The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region. | 2009-02-12 |
20090039468 | N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE - A semiconductor memory device that has an isolated area comprised of one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are comprised of the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells. | 2009-02-12 |
20090039469 | Low temperature impurity doping of silicon carbide - The method described herein enables the introduction of external impurities into Silicon Carbide (SiC) to be conducted at a temperature between 1150-1400° C. Advantages include: a) low temperature diffusion procedure with greater control of the doping process, b) prevent roughness of SiC surface, c) less surface defects and d) better device performance and higher yield. The method described herein involves depositing a ceramic layer that contains the desired impurity and a certain element such as oxygen (in the form of oxide), or other elements/compounds that draw out the silicon and carbon atoms from the surface region of the SiC leaving behind carbon and silicon vacancies which then allow the external impurity to diffuse into the SiC more easily. In another embodiment, the deposited layer also has carbon atoms that discourage carbon from escaping from the SiC, thus generating a surface region of excess carbon in addition to the silicon vacancies. | 2009-02-12 |
20090039470 | STRESS RELIEF OF A SEMICONDUCTOR DEVICE - A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die. | 2009-02-12 |
20090039471 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced apart from the first main surface in the central region of the semiconductor substrate; (c) a through dummy isolation structure formed within the peripheral region to extend from the first main surface of the semiconductor substrate to a third surface vertically spaced apart from the first main surface of the semiconductor substrate, the through dummy isolation structure surrounding the active electrical structure; (d) an insulating layer disbursed throughout the active electrical structure within the central region and around the through dummy isolation structure of the peripheral region, the insulating layer including top and opposed peripheral sides; and (e) a metal film located over the top and peripheral sides of the wiring insulating film and over the semiconductor substrate. | 2009-02-12 |
20090039472 | STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER - A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced. | 2009-02-12 |
20090039473 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes steps of forming a semiconductor device layer on an upper surface of a substrate including the upper surface, a lower surface and a dislocation concentrated region arranged so as to part a first side closer to the upper surface and a second side closer to the lower surface, exposing a portion where the dislocation concentrated region does not exist above on the lower surface by removing the substrate on the second side along with at least a part of the dislocation concentrated region, and forming an electrode on the portion. | 2009-02-12 |
20090039474 | Formation Method of Porous Insulating Film, Manufacturing Apparatus of Semiconductor Device, Manufacturing Method of Semiconductor Device, and Semiconductor Device - In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio of the organosiloxane and the inert gas to be supplied during deposition. Thus, the dielectric constant of the insulating film in the semiconductor device is reduced while the adhesion of the insulating film with other materials is improved. It is desirable that the organosiloxane be cyclic organosiloxane including at least silicon, oxygen, carbon, and hydrogen, and that the total pressure of the reaction chamber be constant during deposition. | 2009-02-12 |
20090039475 | Apparatus and Method for Manufacturing Semiconductor - To provide a semiconductor manufacturing apparatus which is able to improve insulation film. | 2009-02-12 |
20090039476 | Apparatus and method for selectively recessing spacers on multi-gate devices - Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. | 2009-02-12 |
20090039477 | SILICON NITRIDE SUBSTRATE, A MANUFACTURING METHOD OF THE SILICON NITRIDE SUBSTRATE, A SILICON NITRIDE WIRING BOARD USING THE SILICON NITRIDE SUBSTRATE, AND SEMICONDUCTOR MODULE - In the silicon nitride substrate concerning an embodiment of the invention, degree of in-plane orientation fa of β type silicon nitride is 0.4-0.8. Here, degree of in-plane orientation fa can be determined by the rate of the diffracted X-ray intensity in each lattice plane orientation in β type silicon nitride. As a result of research by the inventors, it turned out that both high fracture toughness and high thermal conductivity are acquired, when degree of in-plane orientation fa was 0.4-0.8. Along the thickness direction, both the fracture toughness of 6.0 MPa·m | 2009-02-12 |
20090039478 | Method For Utilizing Heavily Doped Silicon Feedstock To Produce Substrates For Photovoltaic Applications By Dopant Compensation During Crystal Growth - A method for using relatively low-cost silicon with low metal impurity concentration by adding a measured amount of dopant and or dopants before and/or during silicon crystal growth so as to nearly balance, or compensate, the p-type and n-type dopants in the crystal, thereby controlling the net doping concentration within an acceptable range for manufacturing high efficiency solar cells. | 2009-02-12 |
20090039479 | MODULE FOR INTEGRATING PERIPHERAL CIRCUIT AND A MANUFACTURING METHOD THEREOF - A module for integrating peripheral circuit includes a silicon chip substrate, at least one peripheral circuit unit, and at least one main circuit unit. The peripheral circuit unit is integrated in the silicon chip substrate via a semiconductor manufacturing process. The main circuit unit is mounted on the surface of the silicon chip substrate and is electrically connected with the peripheral circuit unit for transmitting the signal. Thereby, the dimension of the module is reduced. | 2009-02-12 |
20090039480 | SEMICONDUCTOR DEVICE AND METHODS OF FORMING THE SAME - The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively. | 2009-02-12 |
20090039481 | SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME AND THICKNESS AND CAPABLE OF HIGH SPEED OPERATION AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance. | 2009-02-12 |
20090039482 | Package Including a Microprocessor & Fourth Level Cache - A method, apparatus and system with a package including an integrated circuit disposed between die including a microprocessor and a die including a fourth level cache. | 2009-02-12 |
20090039483 | HEAT SLUG AND SEMICONDUCTOR PACKAGE - A heat slug includes a heat spreading member and a supporting member. The supporting member extends outwardly from the edge of the heat spreading member. The tips of the supporting member are formed with a plurality of contact portions, wherein each said contact portion has a bottom face inclined to the surface of the chip carrier at an angle of more than 5 degrees. The present invention further provides a semiconductor package. | 2009-02-12 |
20090039484 | Semiconductor device with semiconductor chip and method for producing it - A semiconductor chip has at least one first contact and one second contact on its top side and has connecting elements which are arranged jointly on a structure element and which connect the first contact and the second contact of the top side of the semiconductor chip to the external contacts. | 2009-02-12 |
20090039485 | THERMALLY ENHANCED BALL GRID ARRAY PACKAGE FORMED IN STRIP WITH ONE-PIECE DIE-ATTACHED EXPOSED HEAT SPREADER - Methods, systems, and apparatuses for integrated circuit packages, such as ball grid array packages, and processes for assembling the same, are provided. A first strip includes an array of package substrate sections. An IC die is mounted to each package substrate section of the first strip. A second strip includes an array of leadframe sections. The second strip is positioned adjacent to the first strip to couple a planar protruding area of each leadframe section to a corresponding IC die mounted to the first strip. An encapsulating material is applied to the adjacently positioned first and second strips to fill a space between the first and second strips and to fill a cavity in a top surface of each leadframe section. A planar region of the first strip surrounding each centrally located cavity is not covered by the encapsulating material. The adjacently positioned first and second strips are singulated into a plurality of IC packages. | 2009-02-12 |
20090039486 | CIRCUIT MEMBER, MANUFACTURING METHOD FOR CIRCUIT MEMBERS, SEMICONDUCTOR DEVICE, AND SURFACE LAMINATION STRUCTURE FOR CIRCUIT MEMBER - A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed. | 2009-02-12 |
20090039487 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a source frame having a die pad; a linear gate frame having a bonding pad; a semiconductor chip mounted on the die pad; wires which electrically connect a source terminal of the semiconductor chip to the die pad and electrically connect a gate terminal of the semiconductor chip to the bonding pad; and resin which seals the die pad, the bonding pad, the semiconductor chip, and the wires. The die pad is spaced from the bonding pad and diagonal to an extending direction of the gate frame, in the vicinity of the bonding pad. | 2009-02-12 |
20090039488 | Semiconductor package and method for fabricating the same - A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant. | 2009-02-12 |
20090039489 | METHOD OF PRODUCING OPTICAL MEMS - A method and apparatus for constructing MEMS devices is provided which employs a low cost molded housing that simultaneously provides precise and accurate alignment, mechanical protection, electrical connections and structural integrity for mounting optical and MEMS components. The package includes a MEMS die mounting surface, an optical component mounting surface and an optical imaging window monolithically fabricated with the MEMS die mounting surface in a predetermined orientation for providing alignment between the MEMS die and optical components. A MEMS adaptor plate is provided to facilitate connections of a MEMS die to external components. | 2009-02-12 |
20090039490 | Mounting assembly of semiconductor packages prevent soldering defects caused by substrate warpage - A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of the semiconductor package, the external terminals are divided into at least two different groups. In one of the embodiment, different groups of the external terminals are bumps with non-equal heights to achieve a uniform standoff plane to compensate the warpage of the substrate. The predicted substrate warpage can be compensated without causing any soldering defects. In another embodiment, a plurality of compensating bumps are selectively disposed on one group of the external terminals with larger stacking gaps. | 2009-02-12 |
20090039491 | SEMICONDUCTOR PACKAGE HAVING BURIED POST IN ENCAPSULANT AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip. | 2009-02-12 |
20090039492 | STACKED MEMORY DEVICE - A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips. | 2009-02-12 |
20090039493 | Packaging substrate and application thereof - A packaging substrate is disclosed in the present invention, which includes a substrate body having a first surface and an opposite second surface. The first surface has a first cavity, and the second surface has a second cavity. The first cavity corresponds to and is interlinked to the second cavity. In order to provide a space for disposing a chip, the dimension of the second cavity is larger than that of the first cavity, such that there is a step at the interlinking region between the first cavity and the second cavity. Additionally, a plurality of wire bonding pads are disposed on the first surface around the first cavity. A package structure comprising the packaging substrate and the application thereof are also provided in the present invention. | 2009-02-12 |
20090039494 | Power semiconductor module with sealing device for sealing to a substrate carrier and method for manufacturing it - A power semiconductor module comprising a housing of a first plastic, at least one substrate carrier with a circuit constructed thereon and electric terminating elements extending therefrom. The housing includes attachment means for its permanent connection with the substrate carrier. The housing has a permanently elastic sealing device of a second plastic which is formed integrally with the housing and encircles and is directed towards a first inner main surface of the substrate carrier. A method for constructing such a module includes the steps of constructing a housing of a first mechanically stable plastic and a sealing device of a second permanently elastic plastic; disposing the at least one substrate carrier on the housing; and permanently connecting the housing to the substrate carrier. | 2009-02-12 |
20090039495 | WIRING SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - An active matrix substrate includes a first substrate and a driving integrated circuit chip mounted on the first substrate. A support member is provided between the active matrix substrate and the driving IC chip so as to be in contact with both the active matrix substrate and the driving IC chip. | 2009-02-12 |
20090039496 | METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer. | 2009-02-12 |
20090039497 | SEMICONDUCTOR DEVICE PACKAGE HAVING A BACK SIDE PROTECTIVE SCHEME - The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation. | 2009-02-12 |
20090039498 | POWER SEMICONDUCTOR MODULE - A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers. | 2009-02-12 |
20090039499 | Heat Sink with Thermally Compliant Beams - A heat dissipating structure includes: a heat spreader; and a plurality of compliant beams attached to the heat spreader. The beams are formed of a high-conductive material such that a maximum stress of each beam is less than a fatigue stress of the high-conductive material; said beams are placed at an angle relative to a chip surface such that the beams are able to exert bending compliance in response to x, y, and z forces exerted upon them. The structure also includes a thermal material interface for bonding said structure to the chip surface. Both the heat spreader and the compliant beams can be machined from a copper block. An alternative heat dissipating structure includes compliant beams soldered to the chip surface. | 2009-02-12 |
20090039500 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base plate having first and second surfaces both facing in opposite directions, and a plurality of anisotropic heat conducting members disposed in the base plate and spaced away from each other. A semiconductor element having a heat generating unit is mounted on the first surface, and the second surface is supported on a supporting member having a thermal conductivity. Each anisotropic heat conducting member has a sheet shape intersecting with the first and second surfaces, and orientates a direction of higher thermal conductivity than the thermal conductivity of the base plate in a direction from the first surface toward the second surface. | 2009-02-12 |
20090039501 | INTEGRATED CIRCUIT WITH GALVANICALLY BONDED HEAT SINK - An integrated circuit includes a semiconductor substrate, a first electrical contact formed on the semiconductor substrate, and a first heat sink element bonded to the first electrical contact via a galvanic bond. | 2009-02-12 |
20090039502 | HEATSINK AND SEMICONDUCTOR DEVICE WITH HEATSINK - A heatsink carries a UV-ray light emitting diode. Flow passages for causing circulation of a fluid that cools the UV-ray light emitting diode are opened in the heatsink. Supply ports and discharge ports are opened in a mount surface of a header where supply and discharge of the fluid for cooling purpose to and from the heatsink are performed. A pair of circulation orifices corresponding to the supply port and the discharge port are opened in the contact surface that contacts the mount surface in the heatsink. Recesses are formed around the respective circulation orifices, and an annular sealing member that exhibits rubber elasticity and that is compressed between the heatsink and the header is disposed in each of the recesses. | 2009-02-12 |
20090039503 | SEMICONDUCTOR DEVICE - The invention provides a heat radiating structure which reduces a mechanical stress applied to an electronic part mounted on a printed circuit board including a semiconductor package. The heat radiating structure is constructed by a semiconductor package mounted on a printed circuit board, a thermal conduction sheet arranged on an upper surface of the semiconductor package, and a metal case provided with a heat radiating fin for receiving a heat transmitted form the thermal conduction sheet so as to discharge to an atmospheric air, and the metal case is provided with a concavo-convex structure in a contact portion with the thermal conduction sheet. | 2009-02-12 |
20090039504 | SEMICONDUCTOR DEVICE - The present invention is intended to obtain a semiconductor device that is reduced in size, weight, and cost and improved in performance stability and productivity. | 2009-02-12 |
20090039505 | Thermally insulating bonding pad structure for solder reflow connection - A thermally insulating bonding pad for solder reflow is described. The bonding pad includes a structure. The structure forms the bonding pad. The bonding pad further includes an insulator formed on the structure. The insulator is configured to be interposed between the structure and a substrate of a component onto which said bonding pad is to be disposed. The bonding pad provides thermal insulation for said substrate when said bonding pad is subject to a solder reflow process being performed thereon. | 2009-02-12 |
20090039506 | SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR CHIP WHICH IS MOUNTED SPANING A PLURALITY OF WIRING BOARDS AND MANUFACTURING METHOD THEREOF - The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode pads on one side thereof. The wiring board includes a plurality of connection pads on a semiconductor chip-mounting face, and a plurality of lands on the opposite side thereof. The land is electrically connected to a corresponding connection pad. An external terminal is formed on each of the lands. Further, the electrode pad formed in the semiconductor chip is electrically connected to the corresponding connection pad of the wiring board. Moreover, the semiconductor chip, the semiconductor chip mounting face of the wiring board, and the side faces of the wiring board are covered with the sealing part. | 2009-02-12 |
20090039507 | Electronic Element, Electronic Element Device Using the Same, and Manufacturing Method Thereof - An electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode. A bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the constituent element of the metal nanoparticles. | 2009-02-12 |
20090039508 | LARGER THAN DIE SIZE WAFER-LEVEL REDISTRIBUTION PACKAGING PROCESS - Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes an integrated circuit die, a layer of insulating material, a redistribution interconnect on the layer of insulating material, and a ball interconnect. The integrated circuit die has a plurality of terminals on a first surface. The insulating material covers the first surface of the die and fills a space adjacent to one or more sides of the die. The redistribution interconnect has a first portion coupled to a terminal of the die through the first layer, and a second portion that extends away from the first portion over the insulating material filling the space adjacent to the die. The ball interconnect is coupled to the second portion of the redistribution interconnect. | 2009-02-12 |
20090039509 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided which can prevent contacts between thin metal wires for electrically connecting the electrodes of a substrate with the electrodes of a semiconductor element. The semiconductor device of the present invention includes metal protrusions formed on the electrodes of the semiconductor element, the metal protrusions having lower hardness than the hardness of the thin metal wires. The metal protrusions are bonded to the thin metal wires. | 2009-02-12 |
20090039510 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor construct constructed by a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate. A lower insulating film is provided under and outside the semiconductor construct. A sealing film is provided on the lower insulating film to cover a periphery of the semiconductor construct. A plurality of lower wiring lines are provided under the lower insulating film and connected to the external connection electrodes of the semiconductor construct, respectively. | 2009-02-12 |
20090039511 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose an undercut region, filling the contact hole and the undercut region with a photosensitive material, removing the photosensitive material from the contact hole and then forming a drain contact in the contact hole. | 2009-02-12 |
20090039512 | ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE - A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line. | 2009-02-12 |
20090039513 | Contacting Method for Semiconductor Material and Semiconductor Device - A contact-making method for a semiconductor material contains the method steps of forming a diffusion barrier which promotes electrical contact and adhesion on at least one portion of a surface of a semiconductor and forming a metallization on the diffusion barrier. The diffusion barrier being formed by applying a metalliforous paste to at least one portion of the semiconductor surface or to at least one portion of a layer covering the semiconductor surface, and a semiconductor component with a diffusion barrier which is arranged in the surface of the semiconductor and which promotes electrical contact between the semiconductor material and a metallization. The metallization is applied to the diffusion barrier. The diffusion barrier is formed by a sintered metalliforous paste applied to at least one portion of the semiconductor surface. | 2009-02-12 |
20090039514 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed. | 2009-02-12 |
20090039515 | IONIZING RADIATION BLOCKING IN IC CHIP TO REDUCE SOFT ERRORS - Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip. | 2009-02-12 |
20090039516 | Power semiconductor component with metal contact layer and production method therefor - A power semiconductor component having a basic body and at least one contact area. At least one first thin metallic layer of a first material is arranged on the contact area. A second metallic layer—thicker than the first—of a second material is arranged on the first material by a pressure sintering connection of said material. The associated method has the following steps: producing a plurality of power semiconductor components in a wafer; applying at least one first thin metallic layer on at least one contact area of a respective power semiconductor component; arranging a pasty layer, composed of the second material and a solvent, on at least one of the first metallic layers for each power semiconductor component; pressurizing the pasty layer; and singulating the semiconductor components. | 2009-02-12 |
20090039517 | CHEMICAL VAPOR DEPOSITION OF TITANIUM - A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias. | 2009-02-12 |
20090039518 | Method for forming a damascene structure - A method of forming a damascene structure comprises preparing a film stack on the substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO | 2009-02-12 |
20090039519 | SEMICONDUCTOR DEVICE, PHOTOMASK, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND PATTERN LAYOUT METHOD - A semiconductor device according to an aspect of the invention includes plural line pattern and plural pad patterns. The line patterns are repeatedly disposed with a space pattern interposed therebetween. The pad pattern straddles plural columns of the line patterns. The pad pattern is connected to the line pattern located on one side of the pad pattern in one of the plural columns, the pad pattern is connected to the line pattern located on the other side of the pad pattern in another column of the plural columns, and the line pattern located on one side of the pad pattern includes an open-circuit portion in another column. Therefore, a semiconductor device in which an interconnection pattern including the fine line-and-space-shape line pattern and the pad pattern is accurately formed at low cost, a semiconductor device production method, and a photomask used to produce the semiconductor device can be provided. | 2009-02-12 |
20090039520 | SEMICONDUCTOR CIRCUIT DEVICE, WIRING METHOD FOR SEMICONDUCTOR CIRCUIT DEVICE AND DATA PROCESSING SYSTEM - Via multiplexing technology is provided which can contribute to high density wiring. For coupling wirings of different wiring layers, a multiple via cell section is used which has vias for electrically coupling wirings bent in an L-shape of different wiring layers on both sides with the L-shaped bent portion therebetween. The vias of the multiple via cell section are on a grid line in an X-direction and a grid line in a Y-direction defined with a minimum wiring pitch, and all or part of the vias of the multiple via cell section are deviated from an intersection of the grid line in the X-direction and the grid line in the Y-direction. The vias of the multiple via cell section are placed on each of the grid line in the X-direction and the grid line in the Y-direction, corresponding to the L-shape, so that there is not much difference between the spatial conditions in the X-direction and the spatial conditions in the Y-direction viewed from the multiple via cell section. Thus, the wirability in the X-direction becomes equivalent to that in the Y-direction. | 2009-02-12 |
20090039521 | Semiconductor structure and semiconductor manufacturing method - A semiconductor structure comprising a first signal layer, a second signal layer, a wiring layer and at least one via is provided. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal on the wiring layer. At least one via is used to conduct the first signal layer and the second signal layer. The at least one via is disposed adjacent to the first terminal and the second terminal. | 2009-02-12 |
20090039522 | BIPOLAR AND CMOS INTEGRATION WITH REDUCED CONTACT HEIGHT - Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer. | 2009-02-12 |
20090039523 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 2009-02-12 |
20090039524 | METHODS AND APPARATUS TO SUPPORT AN OVERHANGING REGION OF A STACKED DIE - Methods and apparatus to support an overhanging region of stacked die are disclosed. A disclosed method comprises bonding a first die onto a substrate, placing a support element on the substrate; and bonding a second die onto the first die, wherein the second die overhangs at least one edge of the first die and the support element is positioned to limit bending of the second die. | 2009-02-12 |
20090039525 | Method of Welding Together at Least Two Stacked Members - In this soldering method, a laser is directed onto an end face of the stack in such a manner that the laser heats the stack. At least one parameter of the laser is adjusted to a value that is the image by means of a mathematical model of at least one thermal characteristic of the stack. The parameter of the laser is a parameter selected from an irradiation duration, a surface area of the end face of the stack that is irradiated by the laser, and an irradiating power of the laser. | 2009-02-12 |
20090039526 | PACKAGE AND THE METHOD FOR MAKING THE SAME, AND A STACKED PACKAGE - The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement. | 2009-02-12 |
20090039527 | Sensor-type package and method for fabricating the same - A sensor-type package and a method for fabricating the same are provided. A wafer having a plurality of semiconductor chips is provided, wherein a plurality of holes are formed on a first surface of each of the semiconductor chips, and a plurality of metallic pillars formed in the holes and a plurality of bond pads connected to the metallic pillars form through silicon vias (TSVs). A groove is formed on a second surface of each of the semiconductor chips to expose the metallic pillars. A plurality of sensor chips having TSVs are stacked in the grooves of the semiconductor chips and electrically connected to the exposed metallic pillars. A transparent cover is mounted onto the second surfaces of the semiconductor chips to cover the grooves. A plurality of conductive components are implanted on the bond pads of the semiconductor chips. The wafer is cut along borders among the semiconductor chips. | 2009-02-12 |
20090039528 | Wafer level stacked packages with individual chip selection - A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads. | 2009-02-12 |
20090039529 | Integrated Circuit Having a Plurality of Connection Pads and Integrated Circuit Package - In accordance with an embodiment of the invention, an integrated circuit including a plurality of connection pads is provided, wherein a first connection pad is configured in accordance with a first contacting technology, and wherein a second connection pad is configured in accordance with a second contacting technology. The second contacting technology is different from the first contacting technology. | 2009-02-12 |
20090039530 | NEAR CHIP SCALE PACKAGE INTEGRATION PROCESS - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die. | 2009-02-12 |
20090039531 | Flip-chip package covered with tape - A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion. | 2009-02-12 |
20090039532 | SEMICONDUCTOR DEVICE PACKAGE HAVING A BACK SIDE PROTECTIVE SCHEME - The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation. | 2009-02-12 |
20090039533 | ADHESION STRUCTURE FOR A PACKAGE APPARATUS - A packaging apparatus is disclosed having a substrate with an interior area and a peripheral area. The substrate is configured to have an integrated circuit chip bonded to an adhesion structure located substantially within the interior area of the substrate. The substrate is further configured to have the integrated circuit chip electrically coupled to either the interior area on a distal surface of the substrate or the peripheral area on a proximate side of the substrate through a conductive structure. The adhesion structure includes a bonding area configured to accept an adhesive layer formed between the integrated circuit chip and the interior area of the substrate, and at least one protrusion structure being formed substantially within the bonding area of the substrate and configured to define a gap between the integrated circuit chip and the interior area of the substrate. | 2009-02-12 |
20090039534 | Apparatus for producing carbonated water and method for producing carbonated water using the same - This invention concerns an apparatus and a method for producing carbonated water capable of obtaining high concentration carbonated water effectively. Carbon dioxide gas is passed through a first carbon dioxide gas dissolver composed of a membrane module to be dissolved in water and the carbonated water passing through the first carbon dioxide gas dissolver is passed through a static mixer, which is a second carbon dioxide gas dissolver. Consequently, a high concentration carbonated water can be obtained remarkably, effectively and easily with a simpler structure than conventionally. | 2009-02-12 |
20090039535 | Extended Wear Ophthalmic Lens - A method for making a silicone hydrogel contact lens is provided. In one embodiment, a prepolymer mixture is polymerized in a lens mold in an atmosphere having less than about ppm oxygen to form a silicone hydrogel contact lens suitable for extended wear as characterized by producing less than 10% corneal swelling after a period of continuous wear of 7 days including normal sleep periods. In one embodiment, the prepolymer mixture comprises at least one oxyperm material containing hydrophilic groups, wherein the at least one oxyperm material is a siloxane-containing macromer or monomer, at least one ionperm material, and a cross-linking agent. In certain embodiments, the polymerization of the prepolymer mixture may be carried out in an atmosphere having less than about 1000 ppm oxygen. | 2009-02-12 |
20090039536 | Electrical Connections in Microelectromechanical Devices - A micromirror device and a method of making the same are disclosed herein. The micromirror device comprises a mirror plate, hinge, and post each having an electrically conductive layer. One of the hinge, mirror plate, and post further comprises an electrically insulating layer. To enable the electrical connections between the conducting layers of the hinge, mirror plate, and post, the insulating layer is patterned. | 2009-02-12 |
20090039537 | Method for the Production of Expandable Styrol Polymers Having Improved Expandability - A process for producing expandable styrene polymers (EPS) having improved expandability, wherein from 0.1 to 1% by weight, based on the styrene polymer, of a free-radical former is metered into a styrene polymer melt containing blowing agent at a melt temperature in the range from 150 to 220° C. and the melt is extruded through a die plate with subsequent underwater pelletization. | 2009-02-12 |
20090039538 | METHOD OF FORMING A THERMOPLASTIC ARTICLE - A method of forming a thermoplastic article, including the steps of (a) forming a workpiece of a thermoplastic material of a first colour by injection molding; (b) applying a second colour on the workpiece by over-molding part of the workpiece with the thermoplastic material of the second colour by injection molding; (c) raising the temperature of the workpiece to at least the forming temperature of the thermoplastic material; and (d) enlarging the workpiece by blow molding. | 2009-02-12 |
20090039539 | VACUUM FORMING APPARATUS AND VACUUM FORMING METHOD - A vacuum forming apparatus has a forming die, a plurality of holding devices, a pressing device and a pair of supplemental holding devices. The forming die has at least one suction hole for creating a vacuum. The holding devices hold a resin sheet that has been softened by heating. The pressing device moves relative to the forming die to close a space therebetween and form an airtight state therebetween. Each of the supplemental holding devices includes a clamp member and a support member. The supplemental holding devices are movably arranged to move toward each other. The clamp members clamp the resin sheet on two sides of a selected sag area where the resin sheet will be made to sag. The support members extend along two side portions of the selected sag area for supporting a bottom surface of the resin sheet where the resin sheet will be made to sag. | 2009-02-12 |
20090039540 | REINFORCED ELECTROLYTE MEMBRANE COMPRISING CATALYST FOR PREVENTING REACTANT CROSSOVER AND METHOD FOR MANUFACTURING THE SAME - An object of the present invention is to reduce the amount of hydrogen gas permeating an electrolyte membrane to inhibit cross leak, in which hydrogen reacts with oxygen to thermally degrade the membrane, while improving the mechanical strength of the fuel cell to increase its durability and lifetime. The present invention provides a fuel cell reinforcing electrolyte membrane reinforced by a porous membrane, wherein noble metal carrying carbon is present on a surface of and/or in pores in the porous membrane, said membrane being covered by electrolyte layers. | 2009-02-12 |
20090039541 | METHOD FOR PRODUCING COMPONENTS, ESPECIALLY STRUCTURAL PANELS, FROM SOLID WASTE - A method for manufacturing building elements, in particular building panels, from solid waste is described, in which the latter is provided, sorted according to category, in different fractions of a specified particle size. The different fractions are mixed in specified proportions with addition of water and binder. The resulting mixture is subjected to a continuous extrusion process, in which a strand-like preproduct is produced. Through a cutting operation, the desired dimensions of the building element in the extrusion direction are at least approximately produced. The building-element blanks are then dried and the binder present therein is set. This continuously working process is much more economical compared with the prior art and can be carried out on a large-scale industrial basis. | 2009-02-12 |
20090039542 | METHOD OF AND APPARATUS FOR MAKING PACKING TAPE - Packing tape is made by predrying polyethylene terephthalate and supplying it to an intake end of a chamber of an extruder where the polyethylene terephthalate is agglomerated and melted while being moved through the chamber in a travel direction. Negative pressure is applied to the chamber of the extruder and to degas the PET and thereby draw low-molecular-weight impurities from the polyethylene terephthalate therein, and extruding the melted polyethylene terephthalate as a strip from the extruder through a spinneret. | 2009-02-12 |
20090039543 | Polymer Composition Comprising Polyolefins And Amphiphilic Block Copolymers And Optionally Other Polymers And/Or Fillers And Method For Dying Compositions Of That Type Or Printing Thereon - Polymeric compositions comprising polyolefins, amphiphilic block copolymers composed of polyisobutene blocks and polyoxyalkylene blocks and also optionally other polymers and/or fillers. Processes for dyeing or for printing such compositions and the use of amphiphilic block copolymers as auxiliaries for dyeing and printing polyolefins. | 2009-02-12 |
20090039544 | AQUEOUS RELEASE AGENT AND ITS USE IN THE PRODUCTION OF POLYURETHANE MOLDING - The invention relates to aqueous release agent compositions which are characterized in that they comprise, as release-active agent, at least one metal soap and at least one polyalkylene glycol. | 2009-02-12 |
20090039545 | SEALING STRUCTURE OF TERMINAL AND SEALING MATERIAL THEREFOR - The present invention intends to provide a sealing structure of a terminal that is low in a processing temperature for sealing, easy in sealing operation and high in the productivity. In the invention, the thermal expansion coefficient of a sealing material is made equivalent to or more than the linear expansion coefficient of a metallic sealing case block by adding inorganic filler to a liquid thermosetting polymer. | 2009-02-12 |