06th week of 2016 patent applcation highlights part 54 |
Patent application number | Title | Published |
20160043014 | UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. | 2016-02-11 |
20160043015 | THERMAL INTERFACE MATERIAL ON PACKAGE - A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. | 2016-02-11 |
20160043016 | THERMAL INTERFACE MATERIAL ON PACKAGE - A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. | 2016-02-11 |
20160043017 | PRINTED CIRCUIT BOARD ASSEMBLY INCLUDING CONDUCTIVE HEAT TRANSFER - A printed circuit board assembly (PCBA) may include a printed circuit board (PCB), a socket mechanically and electrically coupled to the PCB, and an integrated circuit package electrically coupled to the socket. The PCBA also may include a thermal cover comprising a thermally conductive material and a thermal strap thermally coupled to the thermal cover. The thermal cover may be thermally coupled to the integrated circuit package and mechanically urge the integrated circuit package in contact with the socket, and the thermal strap may include a thermally conductive material. | 2016-02-11 |
20160043018 | SEMICONDCUTOR DEVICE, MANUFACTURING METHOD AND STACKING STRUCTURE THEREOF - A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided. | 2016-02-11 |
20160043019 | Composite Lead Frame Structure - The present invention relates to a structure of a composite lead frame generally having a die bonding layer and a solder layer and may further have an cohesive layer between the die bonding layer and the solder layer. The die bonding layer is made of flex substrate and the solder layer is made of traditional lead frame. Thus, the composite lead frame structure is suitable for the flip chip or wire bonding packaging process of LED and also suitable for semiconductor IC packaging process. It is good in electric and heat conductivity, and also with higher mechanical strength, resulting high pin counts and minimization of resulted IC. | 2016-02-11 |
20160043020 | Semiconductor Packaging Structure And Forming Method Therefor - The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins. By adopting the present invention, a transverse area occupied by the package structure is decreased, the volume of the entire package structure is correspondingly decreased, and the integration level of the package structure is improved. The present invention further provides a forming method of the semiconductor package structure. | 2016-02-11 |
20160043021 | Dual Power Converter Package - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 2016-02-11 |
20160043022 | Power Converter Package Using Driver IC - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 2016-02-11 |
20160043023 | SYSTEM AND METHOD FOR METAL MATRIX MOUNTING SCHEME - An integrated circuit assembly element formed via an additive manufacturing technique, such as mixing a conductive material with a memory metal to form a portion of a substrate in desired locations, such as along the footprint of die, are discussed herein. In operation (e.g. in response to thermal cycling of the assembly) the memory metal contracts while the conductive material expands. The result is an element having reduced thermal expansion, which can be net zero coefficient of thermal expansion and/or be catered to the coefficient of thermal expansion of a desired material, such as the silicon die. | 2016-02-11 |
20160043024 | PRINTED WIRING BOARD AND SEMICONDUCTOR PACKAGE - A printed wiring board includes a wiring conductor layer having first surface, conductor posts formed on second surface of the wiring layer, and an insulating layer embedding the wiring layer such that the first surface of the wiring layer is exposed on first surface of the insulating layer and covering side surfaces of the posts such that end surface of each conductor post is exposed from second surface of the insulating layer. The first surface of the wiring layer is recessed with respect to the first surface of the insulating layer and the end surface of each conductor post is recessed with respect to the second surface of the insulating layer such that distance between the end surface of each conductor post and the second surface of the insulating layer is greater than distance between the first surface of the wiring layer and the first surface of the insulating layer. | 2016-02-11 |
20160043025 | PACKAGE SUBSTRATE AND ITS FABRICATION METHOD - This disclosure provides a package substrate and its fabrication method. The package substrate includes: a carrier; a first wiring layer formed on the carrier; a conductive pillar layer having a plurality of metal pillars on the first wiring layer; a molding compound layer formed on the first wiring layer, covering all the first wiring layer and the metal pillars, and exposing one end face of each metal pillar; a second wiring layer formed on the molding compound layer and the exposed end faces of the metal pillars; and a protection layer formed on the second wiring layer. | 2016-02-11 |
20160043026 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate including connection pads, a first semiconductor, and conductive wires. The first semiconductor chip is stacked on the substrate and includes bonding pads, non-bonding pads, and a routing area that is provided adjacent a center of an edge of the first semiconductor chip. The conductive wires are connected to the bonding pads and the connection pads. The bonding pads are disposed to form at least one column in a direction extending along the edge of the first semiconductor chip and are not disposed in the routing area. The non-bonding pads are disposed to form a column different from the at least one column formed by the bonding pads. | 2016-02-11 |
20160043027 | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings. | 2016-02-11 |
20160043028 | PACKAGE-IN-SUBSTRATE, SEMICONDUCTOR DEVICE AND MODULE - A package-in-substrate includes an exposed pad having a surface that is capable of contacting the outside; a semiconductor chip arranged on a surface opposite to the surface of the exposed pad; a molding resin for molding the semiconductor chip; and a lead frame extending from a side surface of the molding resin and having a leading end portion with a machined shape. The leading end portion of the lead frame is cut to have a cutting angel that is an acute angle formed by an extended straight line of the lead frame with respect to a top surface of a package. | 2016-02-11 |
20160043029 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups. | 2016-02-11 |
20160043030 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, and a first metal plug structure, wherein a circuit element is disposed on the substrate. The first dielectric layer is disposed on the circuit element and on the substrate. The first metal plug structure, including a first barrier metal layer and a first metal interconnector, is embedded in the first dielectric layer. The first metal interconnector is in direct contact with the circuit element. The first barrier metal layer is disposed on the first metal interconnector; wherein the first barrier metal layer and the first metal interconnect have different metal materials. | 2016-02-11 |
20160043031 | SEMICONDUCTOR DEVICE - One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring. | 2016-02-11 |
20160043032 | MEMORY CIRCUIT STRUCTURE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME - A memory circuit structure includes a substrate, a plurality of word lines disposed and evenly-spaced on the substrate, wherein the width of said word lines is F, and a select gate adjacent to the word lines, wherein the width of the select gate is (7+4n)F, and n is zero or positive integer. | 2016-02-11 |
20160043033 | ELECTRONIC INTERCONNECTS AND DEVICES WITH TOPOLOGICAL SURFACE STATES AND METHODS FOR FABRICATING SAME - An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states. | 2016-02-11 |
20160043034 | DEVICE AND METHOD FOR MANUFACTURING A DEVICE - In various embodiments a method of forming a device is provided. The method includes forming a metal layer over a substrate and forming at least one barrier layer. The forming of the barrier layer includes depositing a solution comprising a metal complex over the substrate and at least partially decomposing of the ligand of the metal complex. | 2016-02-11 |
20160043035 | Contact Structure and Method of Forming - Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening. | 2016-02-11 |
20160043036 | SEMICONDUCTOR DEVICE - A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO | 2016-02-11 |
20160043037 | MARK, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER - According to one embodiment, there is provided a mark comprising a first mark pattern, a second mark pattern, and an opening pattern. The first mark pattern is arranged in a lower layer of a semiconductor wafer that includes a substrate, the lower layer, an intermediate layer, and an upper layer. The second mark pattern is arranged in the upper layer. The opening pattern exposes the first mark pattern. | 2016-02-11 |
20160043038 | MULTI-HEIGHT SEMICONDUCTOR STRUCTURES - Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region. | 2016-02-11 |
20160043039 | SEMICONDUCTOR DEVICE WITH AN ISOLATION STRUCTURE COUPLED TO A COVER OF THE SEMICONDUCTOR DEVICE - A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically. | 2016-02-11 |
20160043040 | INTEGRATED CIRCUIT STRESS RELEASING STRUCTURE - The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate. | 2016-02-11 |
20160043041 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate dudes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die. | 2016-02-11 |
20160043042 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion. | 2016-02-11 |
20160043043 | DEVICES AND METHODS FOR DETECTING COUNTERFEIT SEMICONDUCTOR DEVICES - Techniques for providing a tamper mechanism for semiconductor devices are disclosed herein. The techniques include, for example, providing at least one die and at least one strain gauge, orienting the at least one strain gauge to the die, forming an encapsulated semiconductor device by encapsulating the die and each strain gauge within a mold compound to maintain respective orientation, and measuring an initial strain value for the at least one strain gauge after forming the encapsulated semiconductor device. | 2016-02-11 |
20160043044 | EMI SHIELD FOR HIGH FREQUENCY LAYER TRANSFERRED DEVICES - Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor. | 2016-02-11 |
20160043045 | PAD STRUCTURE OF A SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE PAD STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE PAD STRUCTUR - A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection. | 2016-02-11 |
20160043046 | ETCHING OF UNDER BUMP METALLIZATION LAYER AND RESULTING DEVICE - Methods for wet etching a UBM layer and the resulting devices are disclosed. Embodiments may include patterning metal bumps on a wafer that has at least two metal layers thereon; exposing the wafer to a first acid solution to remove a portion of a first of the two metal layers exposed by the patterning of the metal bumps; and exposing the wafer to a second acid solution to remove a portion a second of the two metal layers exposed by the patterning of the metal bumps and the exposure of the wafer to the first acid solution, wherein an undercut below the metal bumps, formed by removal of the portions of the first and second metal layers, is less than 1.5 microns. | 2016-02-11 |
20160043047 | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package - A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package. | 2016-02-11 |
20160043048 | PREVENTING MISSHAPED SOLDER BALLS - “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer. | 2016-02-11 |
20160043049 | TALL SOLDERS FOR THROUGH-MOLD INTERCONNECT - Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate. | 2016-02-11 |
20160043050 | Metallization stack and chip arrangement - A metallization stack for a chip arrangement is provided, wherein the metallization stack comprises a first metallic layer; a plating layer comprising an alloy comprising nickel and zinc arranged over the first metallic structure; and a second metallic layer arranged over the plating layer. | 2016-02-11 |
20160043051 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof. | 2016-02-11 |
20160043052 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 2016-02-11 |
20160043053 | FLIP CHIP BONDER AND METHOD OF CORRECTING FLATNESS AND DEFORMATION AMOUNT OF BONDING STAGE - Provided is a flip chip bonder including: a base ( | 2016-02-11 |
20160043054 | Batch Process for Connecting Chips to a Carrier - Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier. | 2016-02-11 |
20160043055 | GOA Layout Method, Array Substrate and Display Device - A GOA layout method, an array substrate and a display device are provided. The array substrate includes a plurality of GOA unit groups, each of which includes two adjacent GOA units. The plurality of GOA unit groups includes a first GOA unit group, two GOA units of the first GOA unit group have an overlapping region with at least one via hole provided therein, and the two GOA units of the first GOA unit group are electrically connected through the at least one via hole. With the array substrate, the density of gate lines can be increased. | 2016-02-11 |
20160043056 | DIE ASSEMBLY ON THIN DIELECTRIC SHEET - A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer. | 2016-02-11 |
20160043057 | SEMICONDUCTOR PACKAGES INCLUDING GAP IN INTERCONNECTION TERMINALS AND METHODS OF MANUFACTURING THE SAME - A semiconductor package includes a lower package comprising a lower semiconductor chip mounted on a lower package substrate, an upper package comprising an upper package substrate stacked on the lower package and an upper semiconductor chip mounted on the upper package substrate, interconnection terminals electrically connecting the lower package substrate with the upper package substrate, and a lower molding film molding the lower semiconductor chip between the lower package substrate and the upper package substrate. The lower package substrate comprises a chip region on which the lower semiconductor chip is mounted, an interconnection region enclosing a portion of the chip region, and a mold injection region defined by the chip region and the interconnection region. The interconnection terminals are disposed on the lower package substrate of the interconnection region but not disposed on the lower package substrate of the mold injection region. | 2016-02-11 |
20160043058 | SEMICONDUCTOR COOLING STRUCTURE AND METHOD IN A MIXED BONDING PROCESS - The invention provides a semiconductor cooling structure and method in a mixed bonding process, and comprises: providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein; a heat dissipation layer is set in at least one of the wafer, the heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer; wherein material of each of the heat dissipation layers is good conductors of heat. The invention can make heat generated during bonding process transfer and distribute evenly. | 2016-02-11 |
20160043059 | MULTI-CHIP SEMICONDUCTOR APPARATUS - A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip. | 2016-02-11 |
20160043060 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element. | 2016-02-11 |
20160043061 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - The present disclosure relates to a display device, and more particularly, to a display device using a semiconductor light emitting device. Such a display device using a semiconductor light emitting device may include a first substrate comprising an electrode portion, a conductive adhesive layer located on the first substrate, and a plurality of semiconductor light emitting devices at least part of which are buried in an upper region of the conductive adhesive layer to constitute individual pixels electrically connected to the electrode portion. | 2016-02-11 |
20160043062 | LIGHT SOURCE DEVICE - A light source device including a substrate, a plurality of first light emitting diode (LED) chips, and at least one second LED chip is provided. The substrate has an upper surface. The plurality of first LED chips are disposed on the upper surface and electrically connected to the substrate. Each of the first LED chips includes a first chip substrate, a first semiconductor layer, and a plurality of first electrodes, and the first electrodes are disposed on the upper surface of the substrate. The second LED chip is disposed on the upper surface and electrically connected to the substrate. The second LED chip includes a second chip substrate, a second semiconductor layer, and a plurality of second electrodes. A thickness of the second chip substrate is different from than a thickness of the first chip substrate, and the second electrodes are disposed on the upper surface of the substrate. | 2016-02-11 |
20160043063 | LIGHT EMITTING DEVICE - The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance. | 2016-02-11 |
20160043064 | PROXIMITY SENSOR HAVING LIGHT-BLOCKING STRUCTURE IN LEADFRAME AND METHOD OF MAKING SAME - A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound and forms walls rising from the frame of fingers to create an enclosed cavity for the LED. The pads, leads, and fingers connected to a board using a layer of solder for attaching the proximity sensor. | 2016-02-11 |
20160043065 | SEMICONDUCTOR MULTI-PROJECT OR MULTI-PRODUCT WAFER PROCESS - The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group- | 2016-02-11 |
20160043066 | APPARATUS AND METHOD OF MANUFACTURING THE SAME - Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support layer includes a flow passage. The flow passage may seal working fluid therein. The flow passage may extend along a thickness direction of the support layer. | 2016-02-11 |
20160043067 | SEMICONDUCTOR DEVICE - In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p | 2016-02-11 |
20160043068 | INTERPOSER INTEGRATED WITH 3D PASSIVE DEVICES - An integrated interposer includes an interposer substrate including at least a first portion of a 3D passive device within an active region of the interposer substrate. The integrated interposer also includes an inter-conductive dielectric layer on an active surface of the active region of the interposer substrate, the inter-conductive dielectric layer including at least a second portion of the 3D passive device. The integrated interposer further includes a contact layer coupled to the 3D passive devices and configured to couple at least one die to the integrated interposer. The integrated interposer also includes at least one through via coupled to the contact layer and extending through the interposer substrate to a passive surface of the interposer substrate. The integrated interposer further includes an interconnect layer on the passive surface of the interposer substrate and coupled to the at least one through via. | 2016-02-11 |
20160043069 | SWITCH CELL - A radio-frequency (RF) switch circuit is configured to maintain a disconnection or a connection between a node and an antenna terminal. The RF switch circuit comprises one or more switch cells. A switch cell comprises one or more transistors. The switch cell comprises one or more gate-drain capacitors. The switch cell comprises one or more source-drain capacitors. A gate-drain capacitor is coupled between a gate of a transistor and a drain of the transistor. A source-drain capacitor is coupled between a source of a transistor and a drain of the transistor. | 2016-02-11 |
20160043070 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte. | 2016-02-11 |
20160043071 | INTEGRATED CIRCUITS WITH RESISTORS - An integrated circuit includes transistor and resistor. The transistor includes a gate stack. The gate stack includes a first dielectric layer, a first conductive layer over the first dielectric layer, a second conductive layer over the first conductive layer, and a second dielectric layer over the second conductive layer. The transistor also includes source/drain (S/D) regions adjacent to the gate stack. The resistor adjacent to the transistor, and includes a third dielectric layer. | 2016-02-11 |
20160043072 | SYSTEMS AND METHODS FOR INTEGRATING BOOTSTRAP CIRCUIT ELEMENTS IN POWER TRANSISTORS AND OTHER DEVICES - Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package. | 2016-02-11 |
20160043073 | SEMICONDUCTOR DEVICE - An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n | 2016-02-11 |
20160043074 | JUNCTIONLESS NANOWIRE TRANSISTORS FOR 3D MONOLITHIC INTEGRATION OF CMOS INVERTERS - The invention provides a three dimensional (3D) semi-conductor device comprising a first junctionless transistor doped with dopants of the same polarity; a second junctionless transistor doped with dopants of the same polarity; and the second junctionless transistor and the first junctionless transistor comprise an opposite dopant polarity are stacked in a vertical arrangement, where the first and second junctionless transistors are separated by an insulating layer. The invention makes use of the fact that the transistors are uniformly doped with the same polarity to provide a junctionless transistor. The junctionless concept provides that the junction is already formed, so there is no high temperature step associated with junction formation or junction regrowth. This is an important advantage in the junctionless concept in relation to 3D monolithic integration that allows for vertical stacking of the transistors to form a three dimensional CMOS inverter. | 2016-02-11 |
20160043075 | RAISED METAL SEMICONDUCTOR ALLOY FOR SELF-ALIGNED MIDDLE-OF-LINE CONTACT - A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions. | 2016-02-11 |
20160043076 | INTEGRATION OF ANALOG TRANSISTOR - An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose. | 2016-02-11 |
20160043077 | Static Discharge System - A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state. | 2016-02-11 |
20160043078 | SEMICONDUCTOR ELECTRONIC COMPONENTS WITH INTEGRATED CURRENT LIMITERS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor. | 2016-02-11 |
20160043079 | Semiconductor Device and Method of Manufacture - In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged. | 2016-02-11 |
20160043080 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH. | 2016-02-11 |
20160043081 | METHOD OF FORMING SEMICONDUCTOR FINS - Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed. | 2016-02-11 |
20160043082 | FINFET WITH CONSTRAINED SOURCE-DRAIN EPITAXIAL REGION - A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions. | 2016-02-11 |
20160043083 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 2016-02-11 |
20160043084 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region. | 2016-02-11 |
20160043085 | Semiconductor Device And Fabricating The Same - The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. | 2016-02-11 |
20160043086 | SEMICONDUCTOR STRUCTURE HAVING COMMON GATE - Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same. | 2016-02-11 |
20160043087 | SiGe and Si FinFET Structures and Methods for Making the Same - FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. | 2016-02-11 |
20160043088 | NON-VOLATILE MEMORY DEVICE EMPLOYING A DEEP TRENCH CAPACITOR - A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer. | 2016-02-11 |
20160043089 | MEMORY CELL SUPPORT LATTICE - Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask. | 2016-02-11 |
20160043090 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device in which a voltage does not need to be applied to an element-isolating region that self-aligns with word lines (WL). This method for manufacturing said semiconductor device has the following steps: a step in which provisional active regions that are shaped such that active regions ( | 2016-02-11 |
20160043091 | Semiconductor Device - A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions. | 2016-02-11 |
20160043092 | FIN FIELD-EFFECT TRANSISTOR STATIC RANDOM ACCESS MEMORY DEVICES WITH P-CHANNEL METAL-OXIDE-SEMICONDUCTOR PASS GATE TRANSISTORS - A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line. | 2016-02-11 |
20160043093 | THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF - A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses. | 2016-02-11 |
20160043094 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A method for manufacturing a semiconductor device may include the following steps: providing a composite structure that includes a gate material layer, a first mask material layer, and a sacrificial layer; partially removing, through a first mask, the sacrificial layer to form a sacrificial members; providing a second mask material layer on the sacrificial members; partially removing the second mask material layer to form mask units that contact sides of the sacrificial members; removing the sacrificial members; providing a third mask material layer between two of the mask units for forming a second mask; partially removing, through the second mask, the first mask material layer to form a third mask; and partially removing, through the third mask, the gate material layer to form a control gate and a select gate. | 2016-02-11 |
20160043095 | Split-Gate Flash Memory Cell With Improved Scaling Using Enhanced Lateral Control Gate To Floating Gate Coupling - A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate. | 2016-02-11 |
20160043096 | METHOD FOR MANUFACTURING A FLOATING GATE MEMORY ELEMENT - The disclosed technology generally relates to fabricating semiconductor devices and more particularly to fabricating a floating-gate based memory device. In one aspect, a method of fabricating a memory device comprises forming a stack of horizontal layers comprising alternating sacrificial layers of a first type and sacrificial layers of a second type; forming a vertical opening through the horizontal stack of layers; forming a first vertical dielectric layer on a sidewall of the vertical opening; forming a vertical floating gate layer on the first vertical dielectric layer; forming a second vertical dielectric layer on the vertical floating gate layer; filling the vertical opening with a channel material; forming cavities of a first type by removing the sacrificial layers of the second type to expose the first vertical dielectric layer; removing portions of the first vertical dielectric layer and the vertical floating gate layer at locations adjacent to the cavities of the first type, such that portions of the second vertical dielectric layer are exposed; filling the cavities of the first type with an isolating material; forming cavities of a second type by removing the sacrificial layers of the first type, wherein the cavities of the second type exposes portions of the first vertical dielectric layer; forming a third dielectric layer in the cavities of the second type, wherein the third dielectric layer is formed on the first vertical dielectric layer; and forming a conductive material in the cavities of the second type. | 2016-02-11 |
20160043097 | SELF-ALIGNED SPLIT GATE FLASH MEMORY - The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have flat upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced. | 2016-02-11 |
20160043098 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming n | 2016-02-11 |
20160043099 | WORDLINE 3D FLASH MEMORY AIR GAP - Methods of forming air gaps in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include selectively gas-phase etching tungsten deposited into the stack structure to separate the tungsten levels. Other metals than tungsten may be used. The methods also include selectively etching silicon oxide from between the tungsten levels to make room for vertically spaced air gaps. A nonconformal silicon oxide layer is then deposited to trap the air gaps. Both tungsten removal and silicon oxide removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The nonconformal silicon oxide may be deposited inside or outside the mainframe. | 2016-02-11 |
20160043100 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper. | 2016-02-11 |
20160043101 | ELECTRODE LEAD-OUT STRUCTURE, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present invention belongs to the field of display technology and particularly relates to an electrode lead-out structure, an array substrate and a display device. The electrode lead-out structure comprises a substrate electrode, an isolating layer and an lead-out electrode. The isolating layer covers the substrate electrode to expose a part of region of the substrate electrode through a via formed in the isolating layer, and the lead-out electrode is in contact with the exposed region of the substrate electrode, wherein the lead-out electrode covers the wall and bottom of the via of the isolating layer and extends from an upper edge of the via of the isolating layer along an upper surface of the isolating layer to overlap with the upper layer of the isolating layer. | 2016-02-11 |
20160043102 | Array Substrate and Method for Manufacturing the Same, and Display Device - The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and at least one driving electrode provided on the base substrate, and the thin film transistor includes a gate, and a source and a drain provided in the same layer, wherein the gate, the source or the drain is formed with the same material as the at least one driving electrode, and thickness thereof is larger than that of the at least one driving electrode. Regarding the array substrate, the manufacturing procedure of the array substrate is effectively simplified, cost for mask plate and material is reduced, equipment investment is reduced, production cost is saved, productivity is improved, and competitiveness of the display device is increased, while the transmittance requirement is met. | 2016-02-11 |
20160043103 | Array Substrate, Color Filter Substrate, and Manufacturing Methods Thereof, Display Panel and Display Device - The invention discloses an array substrate, a color substrate, and manufacturing methods thereof, a display panel and a display device. The array substrate includes a plurality of gate lines and a plurality of data lines provided on a first base substrate to be intersected with each other, the gate lines and the data lines define a plurality of pixel units and at least part of the pixel units each provided therein with a first electrode, when the plurality of gate lines are sequentially scanned, the first electrode is loaded with a first voltage signal and a region corresponding to the first electrode is in a transparent state, and when the plurality of gate lines are reversely scanned, the first electrode is loaded with a second voltage signal, and a region corresponding to the first electrode is in a non-transparent state. The invention realizes a high switchover efficiency. | 2016-02-11 |
20160043104 | DISPLAY PANEL - A display panel including first and second pixel structures and a light shielding pattern layer is provided. The first pixel structure includes a first pixel electrode including first pixel electrode bars, wherein a first maximum spacing is formed between any two adjacent first pixel electrode bars of the first pixel structure. The second pixel structure includes a second pixel electrode including second pixel electrode bars, wherein a second maximum spacing which is larger than the first maximum spacing is formed between two adjacent second pixel electrode bars of the second pixel structure. The light shielding pattern layer has first and second light shielding portions. The area of the second light shielding portion is larger than the area of the first light shielding portion. The first pixel electrode is close to the second light shielding portion and the second pixel electrode is away from the second light shielding portion. | 2016-02-11 |
20160043105 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same. | 2016-02-11 |
20160043106 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less. | 2016-02-11 |
20160043107 | DISPLAY DEVICE AND MANUFACTURING AND TESTING METHODS THEREOF - A display device is disclosed which includes: gate lines and data lines crossing each other to define unit pixel regions in a display area; a pixel electrode in each unit pixel region; a data shorting bar in a non-display area in substantially parallel with the gate lines; a gate shorting bar in the non-display area in substantially parallel with the data lines; gate link lines electrically connecting the gate lines to the gate shorting bar; data link lines electrically connecting the data lines to the data shorting bar; and shield electrodes on at least one of the gate link lines and the data link lines, the shield electrodes including a conductive material that has a higher melting temperature than that of the at least one of the gate link lines and the data link lines. | 2016-02-11 |
20160043108 | Semiconductor Structure with Multiple Active Layers in an SOI Wafer - An semiconductor on insulator wafer has an insulator layer between a substrate layer and a semiconductor layer. A first active layer is formed in and on the semiconductor layer. A second active layer is formed in and on the substrate layer. In some embodiments, a handle wafer is bonded to the semiconductor on insulator wafer, and the substrate layer is thinned before forming the second active layer. In some embodiments, a third active layer may be formed in the substrate of the handle wafer. In some embodiments, the first and second active layers include a MEMS device in one of these layers and a CMOS device in the other. | 2016-02-11 |
20160043109 | FLEXIBLE DISPLAY DEVIE AND METHOD OF MANUFACTURING THE SAME - A flexible display device is discussed. The flexible display device includes a substrate having multiple signal lines arranged on the substrate; a transistor disposed on the substrate, the transistor including a gate electrode, a source electrode, and a drain electrode; and a second electrode disposed to correspond to a first electrode connected to the source electrode or the drain electrode of the transistor, wherein at least one of the multiple signal lines, the gate electrode, the source electrode, the drain electrode, and the second electrode is formed of a conductor having a metal nanowire structure and a polymer substance, the metal nonwire structure being disposed in the polymer substance. Also discussed is a method of manufacturing the flexible display device. | 2016-02-11 |
20160043110 | Semiconductor Device - A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor. | 2016-02-11 |
20160043111 | DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND DRIVING METHOD THEREOF - An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor. | 2016-02-11 |
20160043112 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided in which ESD is less likely to occur in a manufacturing process thereof. In manufacture of a semiconductor device including a long lead wiring A, during steps with direct exposure to a plasma atmosphere, a plurality of island-shaped wirings is formed for the wiring A and then electrically connected to one another in series. Specifically, a plurality of island-shaped wirings is formed, covered with an insulating layer, and electrically connected to one another in series by a wiring formed over the insulating layer. The island-shaped wiring and the wiring formed over the insulating layer are electrically connected to each other through an opening formed in the insulating layer. | 2016-02-11 |
20160043113 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor (TFT) substrate and a display using the same. A TFT substrate includes: a substrate, a first TFT on the substrate, including: a polycrystalline semiconductor layer, a first gate electrode thereover, a first source electrode, and a first drain electrode, a second TFT on the substrate, including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer, on the first gate electrode, and an oxide layer covering the second gate electrode, on the intermediate insulating layer, on the oxide layer, and overlapping the second gate electrode, wherein the first source, first drain, and second gate electrodes are between the intermediate insulating layer and the oxide layer, and wherein the second source and the second drain electrodes are on the oxide semiconductor layer. | 2016-02-11 |